feat(tc): bind SMMU-700 with DPU on TC3
TC3 adds a new SMMU-700 specifically for the DPU. This is used as the
DPU SMMU instead of the existing SMMU used for the DPU. Update the
device tree to reflect this.
Change-Id: I865140f8f53bceaa8849f6583190b240eeee0539
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index 3449792..918c496 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -516,6 +516,18 @@
status = "disabled";
};
+ smmu_700_dpu: iommu@4002a00000 {
+ #iommu-cells = <1>;
+ compatible = "arm,smmu-v3";
+ reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>;
+ interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 482 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 483 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "cmdq-sync", "gerror";
+ dma-coherent;
+ status = "disabled";
+ };
+
dp0: display@DPU_ADDR {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index 64546b6..0354217 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -90,7 +90,18 @@
smmu_700: iommu@3f000000 {
status = "okay";
};
+
+ smmu_700_dpu: iommu@4002a00000 {
+ status = "okay";
+ };
+#endif
+
+ dp0: display@DPU_ADDR {
+#if TARGET_FLAVOUR_FVP
+ iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
+ <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
#endif
+ };
gpu: gpu@2d000000 {
#if TARGET_FLAVOUR_FVP