diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
index c54aca0..2e2f426 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
@@ -12,28 +12,34 @@
 #include "../qos_reg.h"
 #include "qos_init_h3_v20.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.21"
+#define RCAR_QOS_VERSION			"rev.0.21"
 
-#define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
+#define QOSWT_TIME_BANK0			20000000U	/* unit:ns */
 
-#define	QOSWT_WTEN_ENABLE				(0x1U)
+#define QOSWT_WTEN_ENABLE			0x1U
 
 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20	(SL_INIT_SSLOTCLK_H3_20 - 0x5U)
 
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT	(3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT	(9U)
-#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT		3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT		9U
+#define QOSWT_WTREF_SLOT0_EN				\
+	((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |	\
+	(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN				\
+	((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |	\
+	(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
 
-#define QOSWT_WTSET0_REQ_SSLOT0			(5U)
-#define WT_BASE_SUB_SLOT_NUM0			(12U)
-#define QOSWT_WTSET0_PERIOD0_H3_20		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
-#define QOSWT_WTSET0_SSLOT0				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 -1U)
+#define QOSWT_WTSET0_REQ_SSLOT0			5U
+#define WT_BASE_SUB_SLOT_NUM0			12U
+#define QOSWT_WTSET0_PERIOD0_H3_20			\
+	((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_20) - 1U)
+#define QOSWT_WTSET0_SSLOT0			(QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 - 1U)
 
-#define QOSWT_WTSET1_PERIOD1_H3_20		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
-#define QOSWT_WTSET1_SSLOT1				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET1_SLOTSLOT1			(WT_BASE_SUB_SLOT_NUM0 -1U)
+#define QOSWT_WTSET1_PERIOD1_H3_20			\
+	((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_20) - 1U)
+#define QOSWT_WTSET1_SSLOT1			(QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET1_SLOTSLOT1			(WT_BASE_SUB_SLOT_NUM0 - 1U)
 
 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
 
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
index 44b58cb..7147a9d 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
@@ -12,27 +12,32 @@
 #include "../qos_reg.h"
 #include "qos_init_h3_v30.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.11"
+#define	RCAR_QOS_VERSION			"rev.0.11"
 
-#define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
+#define QOSWT_TIME_BANK0			20000000U	/* unit:ns */
 
-#define	QOSWT_WTEN_ENABLE				(0x1U)
+#define	QOSWT_WTEN_ENABLE			0x1U
 
 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30	(SL_INIT_SSLOTCLK_H3_30 - 0x5U)
 
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT	(3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT	(9U)
-#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT		3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT		9U
+#define QOSWT_WTREF_SLOT0_EN				\
+	((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |	\
+	(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN				\
+	((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |	\
+	(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
 
-#define QOSWT_WTSET0_REQ_SSLOT0			(5U)
-#define WT_BASE_SUB_SLOT_NUM0			(12U)
-#define QOSWT_WTSET0_PERIOD0_H3_30		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_30)-1U)
-#define QOSWT_WTSET0_SSLOT0				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 -1U)
+#define QOSWT_WTSET0_REQ_SSLOT0			5U
+#define WT_BASE_SUB_SLOT_NUM0			12U
+#define QOSWT_WTSET0_PERIOD0_H3_30			\
+	((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_30) - 1U)
+#define QOSWT_WTSET0_SSLOT0			(QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 - 1U)
 
 #define QOSWT_WTSET1_PERIOD1_H3_30		(QOSWT_WTSET0_PERIOD0_H3_30)
-#define QOSWT_WTSET1_SSLOT1				(QOSWT_WTSET0_SSLOT0)
+#define QOSWT_WTSET1_SSLOT1			(QOSWT_WTSET0_SSLOT0)
 #define QOSWT_WTSET1_SLOTSLOT1			(QOSWT_WTSET0_SLOTSLOT0)
 
 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
@@ -108,6 +113,7 @@
 void qos_init_h3_v30(void)
 {
 	unsigned int split_area;
+
 	dbsc_setting();
 
 #if RCAR_DRAM_LPDDR4_MEMCONF == 0	/* 1GB */
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
index 80870fb..e9f900a 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
@@ -12,27 +12,32 @@
 #include "../qos_reg.h"
 #include "qos_init_h3n_v30.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.07"
+#define	RCAR_QOS_VERSION			"rev.0.07"
 
-#define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
+#define QOSWT_TIME_BANK0			20000000U	/* unit:ns */
 
-#define	QOSWT_WTEN_ENABLE				(0x1U)
+#define	QOSWT_WTEN_ENABLE			0x1U
 
 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N	(SL_INIT_SSLOTCLK_H3N - 0x5U)
 
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT	(3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT	(9U)
-#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT		3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT		9U
+#define QOSWT_WTREF_SLOT0_EN				\
+	((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |	\
+	(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN				\
+	((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |	\
+	(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
 
-#define QOSWT_WTSET0_REQ_SSLOT0			(5U)
-#define WT_BASE_SUB_SLOT_NUM0			(12U)
-#define QOSWT_WTSET0_PERIOD0_H3N		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3N)-1U)
-#define QOSWT_WTSET0_SSLOT0				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 -1U)
+#define QOSWT_WTSET0_REQ_SSLOT0			5U
+#define WT_BASE_SUB_SLOT_NUM0			12U
+#define QOSWT_WTSET0_PERIOD0_H3N			\
+	((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3N) - 1U)
+#define QOSWT_WTSET0_SSLOT0			(QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 - 1U)
 
 #define QOSWT_WTSET1_PERIOD1_H3N		(QOSWT_WTSET0_PERIOD0_H3N)
-#define QOSWT_WTSET1_SSLOT1				(QOSWT_WTSET0_SSLOT0)
+#define QOSWT_WTSET1_SSLOT1			(QOSWT_WTSET0_SSLOT0)
 #define QOSWT_WTSET1_SLOTSLOT1			(QOSWT_WTSET0_SLOTSLOT0)
 
 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
@@ -108,6 +113,7 @@
 void qos_init_h3n_v30(void)
 {
 	unsigned int split_area;
+
 	dbsc_setting();
 
 	/* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */