fix(cpus): workaround for Neoverse-V3 erratum 2970647
Neoverse V3 erratum 2970647 that applies to r0p0 and is fixed in r0p1.
In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
which register to return when reading the value of
MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively.
The workaround is to do an ISB prior to an MRS read to either
MPIDR_EL1 and MIDR_EL1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958/latest/
Change-Id: Iedf7d799451f0be58a5da1f93f7f5b6940f2bb35
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 0e5c7a0..208d7cf 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -580,6 +580,9 @@
For Neoverse V3, the following errata build flags are defined :
+- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3
+ CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
+
- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3
CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and
is still open.