Merge "plat/arm/rddaniel: enabled GICv4 extension" into integration
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index cbac84b..a90b2a5 100644
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,7 @@
#define ARCH_HELPERS_H
#include <cdefs.h>
+#include <stdbool.h>
#include <stdint.h>
#include <string.h>
@@ -178,6 +179,7 @@
void flush_dcache_range(uintptr_t addr, size_t size);
void clean_dcache_range(uintptr_t addr, size_t size);
void inv_dcache_range(uintptr_t addr, size_t size);
+bool is_dcache_enabled(void);
void dcsw_op_louis(u_register_t op_type);
void dcsw_op_all(u_register_t op_type);
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 7c30758..669a140 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -226,6 +226,7 @@
void flush_dcache_range(uintptr_t addr, size_t size);
void clean_dcache_range(uintptr_t addr, size_t size);
void inv_dcache_range(uintptr_t addr, size_t size);
+bool is_dcache_enabled(void);
void dcsw_op_louis(u_register_t op_type);
void dcsw_op_all(u_register_t op_type);
diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h
index 88212c3..dda3173 100644
--- a/include/lib/coreboot.h
+++ b/include/lib/coreboot.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,6 +19,27 @@
} coreboot_serial_t;
extern coreboot_serial_t coreboot_serial;
+#define COREBOOT_MAX_MEMRANGES 32 /* libpayload also uses this limit */
+
+typedef struct __packed {
+ uint64_t start;
+ uint64_t size;
+ uint32_t type;
+} coreboot_memrange_t;
+extern coreboot_memrange_t coreboot_memranges[COREBOOT_MAX_MEMRANGES];
+
+typedef enum {
+ CB_MEM_NONE = 0, /* coreboot will never report this */
+ CB_MEM_RAM = 1,
+ CB_MEM_RESERVED = 2,
+ CB_MEM_ACPI = 3,
+ CB_MEM_NVS = 4,
+ CB_MEM_UNUSABLE = 5,
+ CB_MEM_VENDOR_RSVD = 6,
+ CB_MEM_TABLE = 16,
+} coreboot_memory_t;
+
+coreboot_memory_t coreboot_get_memory_type(uintptr_t address);
void coreboot_table_setup(void *base);
#endif /* COREBOOT_H */
diff --git a/lib/coreboot/coreboot_table.c b/lib/coreboot/coreboot_table.c
index 253fac2..c4cd1d7 100644
--- a/lib/coreboot/coreboot_table.c
+++ b/lib/coreboot/coreboot_table.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,6 +29,7 @@
} cb_header_t;
typedef enum {
+ CB_TAG_MEMORY = 0x1,
CB_TAG_SERIAL = 0xf,
CB_TAG_CBMEM_CONSOLE = 0x17,
} cb_tag_t;
@@ -37,11 +38,13 @@
uint32_t tag;
uint32_t size;
union {
+ coreboot_memrange_t memranges[COREBOOT_MAX_MEMRANGES];
coreboot_serial_t serial;
uint64_t uint64;
};
} cb_entry_t;
+coreboot_memrange_t coreboot_memranges[COREBOOT_MAX_MEMRANGES];
coreboot_serial_t coreboot_serial;
/*
@@ -86,6 +89,23 @@
CONSOLE_FLAG_CRASH);
}
+coreboot_memory_t coreboot_get_memory_type(uintptr_t address)
+{
+ int i;
+
+ for (i = 0; i < COREBOOT_MAX_MEMRANGES; i++) {
+ coreboot_memrange_t *range = &coreboot_memranges[i];
+
+ if (range->type == CB_MEM_NONE)
+ break; /* end of table reached */
+ if (address >= range->start &&
+ address - range->start < range->size)
+ return range->type;
+ }
+
+ return CB_MEM_NONE;
+}
+
void coreboot_table_setup(void *base)
{
cb_header_t *header = base;
@@ -99,6 +119,7 @@
ptr = base + header->header_bytes;
for (i = 0; i < header->table_entries; i++) {
+ size_t size;
cb_entry_t *entry = ptr;
if (ptr - base >= header->header_bytes + header->table_bytes) {
@@ -107,6 +128,15 @@
}
switch (read_le32(&entry->tag)) {
+ case CB_TAG_MEMORY:
+ size = read_le32(&entry->size) -
+ offsetof(cb_entry_t, memranges);
+ if (size > sizeof(coreboot_memranges)) {
+ ERROR("Need to truncate coreboot memranges!\n");
+ size = sizeof(coreboot_memranges);
+ }
+ memcpy(&coreboot_memranges, &entry->memranges, size);
+ break;
case CB_TAG_SERIAL:
memcpy(&coreboot_serial, &entry->serial,
sizeof(coreboot_serial));
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 0605fce..7d35dea 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -84,7 +84,7 @@
/* Helper function to check if the lock is acquired */
static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info,
- int is_cached)
+ bool is_cached)
{
/*
* Even though lock data is updated only by the owning cpu and
@@ -99,7 +99,7 @@
}
static unsigned int bakery_get_ticket(bakery_lock_t *lock,
- unsigned int me, int is_cached)
+ unsigned int me, bool is_cached)
{
unsigned int my_ticket, their_ticket;
unsigned int they;
@@ -164,17 +164,14 @@
void bakery_lock_get(bakery_lock_t *lock)
{
- unsigned int they, me, is_cached;
+ unsigned int they, me;
unsigned int my_ticket, my_prio, their_ticket;
bakery_info_t *their_bakery_info;
unsigned int their_bakery_data;
+ bool is_cached;
me = plat_my_core_pos();
-#ifdef __aarch64__
- is_cached = read_sctlr_el3() & SCTLR_C_BIT;
-#else
- is_cached = read_sctlr() & SCTLR_C_BIT;
-#endif
+ is_cached = is_dcache_enabled();
/* Get a ticket */
my_ticket = bakery_get_ticket(lock, me, is_cached);
@@ -232,11 +229,7 @@
void bakery_lock_release(bakery_lock_t *lock)
{
bakery_info_t *my_bakery_info;
-#ifdef __aarch64__
- unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT;
-#else
- unsigned int is_cached = read_sctlr() & SCTLR_C_BIT;
-#endif
+ bool is_cached = is_dcache_enabled();
my_bakery_info = get_bakery_info(plat_my_core_pos(), lock);
diff --git a/lib/xlat_tables_v2/xlat_tables_private.h b/lib/xlat_tables_v2/xlat_tables_private.h
index 70ef395..863470c 100644
--- a/lib/xlat_tables_v2/xlat_tables_private.h
+++ b/lib/xlat_tables_v2/xlat_tables_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -99,9 +99,6 @@
*/
bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx);
-/* Returns true if the data cache is enabled at the current EL. */
-bool is_dcache_enabled(void);
-
/*
* Returns minimum virtual address space size supported by the architecture
*/
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 1f569c2..1ed3074 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -120,7 +120,7 @@
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION)
#else
-# define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION)
+# define PLAT_ARM_MAX_BL2_SIZE (UL(0x12000) - FVP_BL2_ROMLIB_OPTIMIZATION)
#endif
#if RESET_TO_BL31
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index b446395..43c267d 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -139,7 +139,7 @@
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#endif
#else
-# define PLAT_ARM_MAX_BL2_SIZE (UL(0xF000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
+# define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#endif
/*
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index 8c8b231..3b8d565 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -77,7 +77,7 @@
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x11000
+# define PLAT_ARM_MAX_BL2_SIZE 0x14000
#endif
/*
diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h
index 0ac0c2b..12fa07f 100644
--- a/plat/arm/css/sgm/include/sgm_base_platform_def.h
+++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h
@@ -187,7 +187,7 @@
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x11000
+# define PLAT_ARM_MAX_BL2_SIZE 0x12000
#endif
/*
diff --git a/plat/brcm/board/stingray/platform.mk b/plat/brcm/board/stingray/platform.mk
index 20ebcdd..c5509bb 100644
--- a/plat/brcm/board/stingray/platform.mk
+++ b/plat/brcm/board/stingray/platform.mk
@@ -70,7 +70,7 @@
endif
ifeq (${BOARD_CFG},)
-BOARD_CFG := bcm958742k
+BOARD_CFG := bcm958742t
endif
# Use PAXB