diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index bb9582c..652765c 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -353,8 +353,7 @@
 		paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
 		assert(paged_mem_params != NULL);
 		paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
-			(dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
-			 STM32MP_DDR_SHMEM_SIZE);
+			stm32mp_get_ddr_ns_size();
 		paged_mem_params->image_info.image_max_size =
 			STM32MP_DDR_S_SIZE;
 
diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c
index 61db2e7..3a29ba9 100644
--- a/plat/st/stm32mp1/stm32mp1_security.c
+++ b/plat/st/stm32mp1/stm32mp1_security.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -35,29 +35,30 @@
 {
 	unsigned long long region_base, region_top;
 	unsigned long long ddr_base = STM32MP_DDR_BASE;
-	unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
-	unsigned long long ddr_top = ddr_base + (ddr_size - 1U);
+	unsigned long long ddr_ns_size =
+		(unsigned long long)stm32mp_get_ddr_ns_size();
+	unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U);
 
 	tzc400_init(STM32MP1_TZC_BASE);
 
 	tzc400_disable_filters();
 
-#ifdef AARCH32_SP_OPTEE
 	/*
 	 * Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the
 	 * same configuration to all filters in the TZC.
 	 */
 	region_base = ddr_base;
-	region_top = ddr_top - STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE;
+	region_top = ddr_ns_top;
 	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
 				region_base,
 				region_top,
 				TZC_REGION_S_NONE,
 				TZC_REGION_NSEC_ALL_ACCESS_RDWR);
 
+#ifdef AARCH32_SP_OPTEE
 	/* Region 2 set to cover all secure DRAM. */
 	region_base = region_top + 1U;
-	region_top = ddr_top - STM32MP_DDR_SHMEM_SIZE;
+	region_top += STM32MP_DDR_S_SIZE;
 	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 2,
 				region_base,
 				region_top,
@@ -66,24 +67,12 @@
 
 	/* Region 3 set to cover non-secure shared memory DRAM. */
 	region_base = region_top + 1U;
-	region_top = ddr_top;
+	region_top += STM32MP_DDR_SHMEM_SIZE;
 	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 3,
 				region_base,
 				region_top,
 				TZC_REGION_S_NONE,
 				TZC_REGION_NSEC_ALL_ACCESS_RDWR);
-#else
-	/*
-	 * Region 1 set to cover all DRAM at 0xC000_0000. Apply the
-	 * same configuration to all filters in the TZC.
-	 */
-	region_base = ddr_base;
-	region_top = ddr_top;
-	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
-				region_base,
-				region_top,
-				TZC_REGION_S_NONE,
-				TZC_REGION_NSEC_ALL_ACCESS_RDWR);
 #endif
 
 	/* Raise an exception if a NS device tries to access secure memory */