diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 33ad56f..20356e4 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -47,7 +47,9 @@
 };
 #endif
 
+#if STM32MP15
 static struct stm32mp_auth_ops stm32mp1_auth_ops;
+#endif
 
 static void print_reset_reason(void)
 {
@@ -82,6 +84,7 @@
 		return;
 	}
 
+#if STM32MP15
 	if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
 		if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
 			INFO("  System reset generated by MCU (MCSYSRST)\n");
@@ -90,6 +93,7 @@
 		}
 		return;
 	}
+#endif
 
 	if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
 		INFO("  System reset generated by MPU (MPSYSRST)\n");
@@ -116,10 +120,12 @@
 		return;
 	}
 
+#if STM32MP15
 	if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
 		INFO("  MPU Processor 1 Reset\n");
 		return;
 	}
+#endif
 
 	if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
 		INFO("  Pad Reset from NRST\n");
@@ -171,6 +177,7 @@
 #endif /* STM32MP_USE_STM32IMAGE */
 }
 
+#if STM32MP15
 static void update_monotonic_counter(void)
 {
 	uint32_t version;
@@ -204,6 +211,7 @@
 		     version);
 	}
 }
+#endif
 
 void bl2_el3_plat_arch_setup(void)
 {
@@ -271,8 +279,10 @@
 		mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
 	}
 
+#if STM32MP15
 	/* Disable MCKPROT */
 	mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
+#endif
 
 	/*
 	 * Set minimum reset pulse duration to 31ms for discrete power
@@ -307,7 +317,7 @@
 	stm32_save_boot_interface(boot_context->boot_interface_selected,
 				  boot_context->boot_interface_instance);
 
-#if STM32MP_USB_PROGRAMMER
+#if STM32MP_USB_PROGRAMMER && STM32MP15
 	/* Deconfigure all UART RX pins configured by ROM code */
 	stm32mp1_deconfigure_uart_pins();
 #endif
@@ -359,6 +369,7 @@
 		}
 	}
 
+#if STM32MP15
 	if (stm32mp_is_auth_supported()) {
 		stm32mp1_auth_ops.check_key =
 			boot_context->bootrom_ecdsa_check_key;
@@ -367,12 +378,15 @@
 
 		stm32mp_init_auth(&stm32mp1_auth_ops);
 	}
+#endif
 
 	stm32mp1_arch_security_setup();
 
 	print_reset_reason();
 
+#if STM32MP15
 	update_monotonic_counter();
+#endif
 
 	stm32mp1_syscfg_enable_io_compensation_finish();
 
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 6b8b712..735a58f 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -303,9 +303,13 @@
 				drivers/io/io_mtd.c					\
 				drivers/io/io_storage.c					\
 				drivers/st/crypto/stm32_hash.c				\
-				plat/st/common/stm32mp_auth.c				\
 				plat/st/stm32mp1/bl2_plat_setup.c
 
+
+ifeq ($(STM32MP15),1)
+BL2_SOURCES		+=	plat/st/common/stm32mp_auth.c
+endif
+
 ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
 BL2_SOURCES		+=	drivers/mmc/mmc.c					\
 				drivers/partition/gpt.c					\
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 1d55807..0946936 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -182,9 +182,11 @@
 #define GPIOG_BASE			U(0x50008000)
 #define GPIOH_BASE			U(0x50009000)
 #define GPIOI_BASE			U(0x5000A000)
+#if STM32MP15
 #define GPIOJ_BASE			U(0x5000B000)
 #define GPIOK_BASE			U(0x5000C000)
 #define GPIOZ_BASE			U(0x54004000)
+#endif
 #define GPIO_BANK_OFFSET		U(0x1000)
 
 /* Bank IDs used in GPIO driver API */
@@ -197,11 +199,13 @@
 #define GPIO_BANK_G			U(6)
 #define GPIO_BANK_H			U(7)
 #define GPIO_BANK_I			U(8)
+#if STM32MP15
 #define GPIO_BANK_J			U(9)
 #define GPIO_BANK_K			U(10)
 #define GPIO_BANK_Z			U(25)
 
 #define STM32MP_GPIOZ_PIN_MAX_COUNT	8
+#endif
 
 /*******************************************************************************
  * STM32MP1 UART
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 1125a69..8c27af2 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -111,42 +111,62 @@
 
 uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
 {
+#if STM32MP13
+	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
+#endif
+#if STM32MP15
 	if (bank == GPIO_BANK_Z) {
 		return GPIOZ_BASE;
 	}
 
 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+#endif
 
 	return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
 }
 
 uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
 {
+#if STM32MP13
+	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
+#endif
+#if STM32MP15
 	if (bank == GPIO_BANK_Z) {
 		return 0;
 	}
 
 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+#endif
 
 	return bank * GPIO_BANK_OFFSET;
 }
 
 bool stm32_gpio_is_secure_at_reset(unsigned int bank)
 {
+#if STM32MP13
+	return true;
+#endif
+#if STM32MP15
 	if (bank == GPIO_BANK_Z) {
 		return true;
 	}
 
 	return false;
+#endif
 }
 
 unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
 {
+#if STM32MP13
+	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
+#endif
+#if STM32MP15
 	if (bank == GPIO_BANK_Z) {
 		return GPIOZ;
 	}
 
 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+#endif
 
 	return GPIOA + (bank - GPIO_BANK_A);
 }
@@ -163,11 +183,15 @@
 	case GPIO_BANK_G:
 	case GPIO_BANK_H:
 	case GPIO_BANK_I:
+#if STM32MP15
 	case GPIO_BANK_J:
 	case GPIO_BANK_K:
+#endif
 		return fdt_path_offset(fdt, "/soc/pin-controller");
+#if STM32MP15
 	case GPIO_BANK_Z:
 		return fdt_path_offset(fdt, "/soc/pin-controller-z");
+#endif
 	default:
 		panic();
 	}
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index 3f34af1..6d24b0e 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -19,8 +19,10 @@
  * SYSCFG REGISTER OFFSET (base relative)
  */
 #define SYSCFG_BOOTR				0x00U
+#if STM32MP15
 #define SYSCFG_IOCTRLSETR			0x18U
 #define SYSCFG_ICNR				0x1CU
+#endif
 #define SYSCFG_CMPCR				0x20U
 #define SYSCFG_CMPENSETR			0x24U
 #define SYSCFG_CMPENCLRR			0x28U
@@ -32,8 +34,11 @@
  * SYSCFG_BOOTR Register
  */
 #define SYSCFG_BOOTR_BOOT_MASK			GENMASK(2, 0)
+#if STM32MP15
 #define SYSCFG_BOOTR_BOOTPD_MASK		GENMASK(6, 4)
 #define SYSCFG_BOOTR_BOOTPD_SHIFT		4
+#endif
+
 /*
  * SYSCFG_IOCTRLSETR Register
  */
@@ -106,12 +111,14 @@
 
 static void enable_high_speed_mode_low_voltage(void)
 {
+#if STM32MP15
 	mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
 		      SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
 		      SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
 		      SYSCFG_IOCTRLSETR_HSLVEN_ETH |
 		      SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
 		      SYSCFG_IOCTRLSETR_HSLVEN_SPI);
+#endif
 }
 
 static void stm32mp1_syscfg_set_hslv(void)
@@ -165,6 +172,7 @@
 
 void stm32mp1_syscfg_init(void)
 {
+#if STM32MP15
 	uint32_t bootr;
 
 	/*
@@ -178,6 +186,7 @@
 		SYSCFG_BOOTR_BOOT_MASK;
 	mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
 			   bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
+#endif
 
 	stm32mp1_syscfg_set_hslv();