feat(ast2700): set up CPU clock frequency by SCU
Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL
2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL
Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
diff --git a/plat/aspeed/ast2700/include/platform_def.h b/plat/aspeed/ast2700/include/platform_def.h
index 8be26c3..e668115 100644
--- a/plat/aspeed/ast2700/include/platform_def.h
+++ b/plat/aspeed/ast2700/include/platform_def.h
@@ -21,9 +21,6 @@
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER)
-/* arch timer */
-#define PLAT_SYSCNT_CLKIN_HZ U(1600000000)
-
/* power domain */
#define PLAT_MAX_PWR_LVL U(1)
#define PLAT_NUM_PWR_DOMAINS U(5)
@@ -55,4 +52,12 @@
#define CONSOLE_UART_CLKIN_HZ U(1846153)
#define CONSOLE_UART_BAUDRATE U(115200)
+/* CLK information */
+#define CLKIN_25M UL(25000000)
+
+#define PLAT_CLK_GATE_NUM U(29)
+#define PLAT_CLK_HPLL (PLAT_CLK_GATE_NUM + 5)
+#define PLAT_CLK_DPLL (PLAT_CLK_GATE_NUM + 6)
+#define PLAT_CLK_MPLL (PLAT_CLK_GATE_NUM + 7)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/aspeed/ast2700/include/platform_reg.h b/plat/aspeed/ast2700/include/platform_reg.h
index 7f26865..3c164a4 100644
--- a/plat/aspeed/ast2700/include/platform_reg.h
+++ b/plat/aspeed/ast2700/include/platform_reg.h
@@ -19,6 +19,10 @@
/* CPU-die SCU */
#define SCU_CPU_BASE U(0x12c02000)
+#define SCU_CPU_HW_STRAP1 (SCU_CPU_BASE + 0x010)
+#define SCU_CPU_HPLL (SCU_CPU_BASE + 0x300)
+#define SCU_CPU_DPLL (SCU_CPU_BASE + 0x308)
+#define SCU_CPU_MPLL (SCU_CPU_BASE + 0x310)
#define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780)
#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788)
#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790)