Tegra: SoC specific SiP handlers
This patch converts the common SiP handler to SoC specific SiP
handler. T210 and T132 have different SiP SMCs and so it makes
sense to move the SiP handler to soc/t132 and soc/t210 folders.
Change-Id: Idfe48384d63641137d74a095432df4724986b241
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index 2b4a247..220e206 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -60,5 +60,4 @@
${COMMON_DIR}/tegra_delay_timer.c \
${COMMON_DIR}/tegra_gic.c \
${COMMON_DIR}/tegra_pm.c \
- ${COMMON_DIR}/tegra_sip_calls.c \
${COMMON_DIR}/tegra_topology.c
diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/soc/t132/plat_sip_calls.c
similarity index 97%
rename from plat/nvidia/tegra/common/tegra_sip_calls.c
rename to plat/nvidia/tegra/soc/t132/plat_sip_calls.c
index de36a3c..450e1dd 100644
--- a/plat/nvidia/tegra/common/tegra_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t132/plat_sip_calls.c
@@ -43,7 +43,7 @@
#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT)
/*******************************************************************************
- * Tegra SiP SMCs
+ * Tegra132 SiP SMCs
******************************************************************************/
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
#define TEGRA_SIP_AARCH_SWITCH 0x82000004
@@ -58,7 +58,7 @@
/*******************************************************************************
* This function is responsible for handling all SiP calls from the NS world
******************************************************************************/
-uint64_t tegra_sip_handler(uint32_t smc_fid,
+uint64_t tegra132_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
@@ -138,11 +138,11 @@
/* Define a runtime service descriptor for fast SMC calls */
DECLARE_RT_SVC(
- tegra_sip_fast,
+ tegra132_sip_fast,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
NULL,
- tegra_sip_handler
+ tegra132_sip_handler
);
diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index 64db8c0..2364a22 100644
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -43,5 +43,6 @@
BL31_SOURCES += lib/cpus/aarch64/denver.S \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
${SOC_DIR}/plat_psci_handlers.c \
+ ${SOC_DIR}/plat_sip_calls.c \
${SOC_DIR}/plat_setup.c \
${SOC_DIR}/plat_secondary.c
diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c
similarity index 74%
copy from plat/nvidia/tegra/common/tegra_sip_calls.c
copy to plat/nvidia/tegra/soc/t210/plat_sip_calls.c
index de36a3c..7d9838a 100644
--- a/plat/nvidia/tegra/common/tegra_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c
@@ -39,26 +39,15 @@
#include <runtime_svc.h>
#include <tegra_private.h>
-#define NS_SWITCH_AARCH32 1
-#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT)
-
/*******************************************************************************
- * Tegra SiP SMCs
+ * Tegra210 SiP SMCs
******************************************************************************/
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
-#define TEGRA_SIP_AARCH_SWITCH 0x82000004
-
-/*******************************************************************************
- * SPSR settings for AARCH32/AARCH64 modes
- ******************************************************************************/
-#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \
- DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT)
-#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
/*******************************************************************************
* This function is responsible for handling all SiP calls from the NS world
******************************************************************************/
-uint64_t tegra_sip_handler(uint32_t smc_fid,
+uint64_t tegra210_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
@@ -102,29 +91,6 @@
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, x2);
- SMC_RET1(handle, 0);
- break;
-
- case TEGRA_SIP_AARCH_SWITCH:
-
- /* clean up the high bits */
- x1 = (uint32_t)x1;
- x2 = (uint32_t)x2;
-
- if (!x1 || x2 > NS_SWITCH_AARCH32) {
- ERROR("%s: invalid parameters\n", __func__);
- SMC_RET1(handle, SMC_UNK);
- }
-
- /* x1 = ns entry point */
- cm_set_elr_spsr_el3(NON_SECURE, x1,
- (x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64);
-
- /* switch NS world mode */
- cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2);
-
- INFO("CPU switched to AARCH%s mode\n",
- (x2 == NS_SWITCH_AARCH32) ? "32" : "64");
SMC_RET1(handle, 0);
break;
@@ -138,11 +104,11 @@
/* Define a runtime service descriptor for fast SMC calls */
DECLARE_RT_SVC(
- tegra_sip_fast,
+ tegra210_sip_fast,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
NULL,
- tegra_sip_handler
+ tegra210_sip_handler
);
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index f58baaf..bb6424d 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -56,6 +56,7 @@
lib/cpus/aarch64/cortex_a57.S \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
${SOC_DIR}/plat_psci_handlers.c \
+ ${SOC_DIR}/plat_sip_calls.c \
${SOC_DIR}/plat_setup.c \
${SOC_DIR}/plat_secondary.c