tree 2da4ef2c29e9767e078e5754b39918bf580b8d82
parent d37210e95f21bfb162358bdc8874d7bab9c855be
author Alexei Fedorov <Alexei.Fedorov@arm.com> 1618228194 +0100
committer Alexei Fedorov <Alexei.Fedorov@arm.com> 1619008695 +0200

Plat FVP: Fix Generic Timer interrupt types

The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:

Arm Cortex-A76 Core:
"Each timer provides an active-LOW interrupt output to the SoC."

Arm Cortex-A53 MPCore Processor:
"It generates timer events as active-LOW interrupt outputs and
event streams."

The following files in fdts\

fvp-base-gicv3-psci-common.dtsi
fvp-base-gicv3-psci-aarch32-common.dtsi
fvp-base-gicv2-psci-aarch32.dts
fvp-base-gicv2-psci.dts
fvp-foundation-gicv2-psci.dts
fvp-foundation-gicv3-psci.dts

describe interrupt types as edge rising
IRQ_TYPE_EDGE_RISING = 0x01:

interrupts = <1 13 0xff01>,
             <1 14 0xff01>,
             <1 11 0xff01>,
             <1 10 0xff01>;

, see include\dt-bindings\interrupt-controller\arm-gic.h:

which causes Linux to generate the warnings below:
arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low
arch_timer: WARNING: Please fix your firmware

This patch adds GIC_CPU_MASK_RAW macro definition to
include\dt-bindings\interrupt-controller\arm-gic.h,
modifies interrupt type to IRQ_TYPE_LEVEL_LOW and
makes use of type definitions in arm-gic.h.

Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>