diff --git a/drivers/rpi3/rng/rpi3_rng.c b/drivers/rpi3/rng/rpi3_rng.c
index b6bf005..16733e1 100644
--- a/drivers/rpi3/rng/rpi3_rng.c
+++ b/drivers/rpi3/rng/rpi3_rng.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,19 @@
 
 #include <rpi_hw.h>
 
+#define RPI3_RNG_CTRL_OFFSET		ULL(0x00000000)
+#define RPI3_RNG_STATUS_OFFSET		ULL(0x00000004)
+#define RPI3_RNG_DATA_OFFSET		ULL(0x00000008)
+#define RPI3_RNG_INT_MASK_OFFSET	ULL(0x00000010)
+/* Enable/disable RNG */
+#define RPI3_RNG_CTRL_ENABLE		U(0x1)
+#define RPI3_RNG_CTRL_DISABLE		U(0x0)
+/* Number of currently available words */
+#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT	U(24)
+#define RPI3_RNG_STATUS_NUM_WORDS_MASK	U(0xFF)
+/* Value to mask interrupts caused by the RNG */
+#define RPI3_RNG_INT_MASK_DISABLE	U(0x1)
+
 /* Initial amount of values to discard */
 #define RNG_WARMUP_COUNT	U(0x40000)
 
diff --git a/include/drivers/rpi3/mailbox/rpi3_mbox.h b/include/drivers/rpi3/mailbox/rpi3_mbox.h
index c107440..33458e3 100644
--- a/include/drivers/rpi3/mailbox/rpi3_mbox.h
+++ b/include/drivers/rpi3/mailbox/rpi3_mbox.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,6 +16,22 @@
 	uint32_t	tags[0];
 } rpi3_mbox_request_t;
 
+/* VideoCore -> ARM */
+#define RPI3_MBOX0_READ_OFFSET		ULL(0x00000000)
+#define RPI3_MBOX0_PEEK_OFFSET		ULL(0x00000010)
+#define RPI3_MBOX0_SENDER_OFFSET	ULL(0x00000014)
+#define RPI3_MBOX0_STATUS_OFFSET	ULL(0x00000018)
+#define RPI3_MBOX0_CONFIG_OFFSET	ULL(0x0000001C)
+/* ARM -> VideoCore */
+#define RPI3_MBOX1_WRITE_OFFSET		ULL(0x00000020)
+#define RPI3_MBOX1_PEEK_OFFSET		ULL(0x00000030)
+#define RPI3_MBOX1_SENDER_OFFSET	ULL(0x00000034)
+#define RPI3_MBOX1_STATUS_OFFSET	ULL(0x00000038)
+#define RPI3_MBOX1_CONFIG_OFFSET	ULL(0x0000003C)
+/* Mailbox status constants */
+#define RPI3_MBOX_STATUS_FULL_MASK	U(0x80000000) /* Set if full */
+#define RPI3_MBOX_STATUS_EMPTY_MASK	U(0x40000000) /* Set if empty */
+
 #define RPI3_MBOX_BUFFER_SIZE		U(256)
 
 /* Constants to perform a request/check the status of a request. */
diff --git a/plat/rpi/common/rpi3_pm.c b/plat/rpi/common/rpi3_pm.c
index d98ac66..456e160 100644
--- a/plat/rpi/common/rpi3_pm.c
+++ b/plat/rpi/common/rpi3_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,6 +21,22 @@
 #include <drivers/arm/gicv2.h>
 #endif
 
+/* Registers on top of RPI3_PM_BASE. */
+#define RPI3_PM_RSTC_OFFSET		ULL(0x0000001C)
+#define RPI3_PM_RSTS_OFFSET		ULL(0x00000020)
+#define RPI3_PM_WDOG_OFFSET		ULL(0x00000024)
+/* Watchdog constants */
+#define RPI3_PM_PASSWORD		U(0x5A000000)
+#define RPI3_PM_RSTC_WRCFG_MASK		U(0x00000030)
+#define RPI3_PM_RSTC_WRCFG_FULL_RESET	U(0x00000020)
+/*
+ * The RSTS register is used by the VideoCore firmware when booting the
+ * Raspberry Pi to know which partition to boot from. The partition value is
+ * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware
+ * to indicate halt.
+ */
+#define RPI3_PM_RSTS_WRCFG_HALT		U(0x00000555)
+
 /* Make composite power state parameter till power level 0 */
 #if PSCI_EXTENDED_STATE_ID
 
diff --git a/plat/rpi/rpi3/include/rpi_hw.h b/plat/rpi/rpi3/include/rpi_hw.h
index 2aecab3..dec5963 100644
--- a/plat/rpi/rpi3/include/rpi_hw.h
+++ b/plat/rpi/rpi3/include/rpi_hw.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,60 +21,18 @@
  */
 #define RPI3_MBOX_OFFSET		ULL(0x0000B880)
 #define RPI3_MBOX_BASE			(RPI_IO_BASE + RPI3_MBOX_OFFSET)
-/* VideoCore -> ARM */
-#define RPI3_MBOX0_READ_OFFSET		ULL(0x00000000)
-#define RPI3_MBOX0_PEEK_OFFSET		ULL(0x00000010)
-#define RPI3_MBOX0_SENDER_OFFSET	ULL(0x00000014)
-#define RPI3_MBOX0_STATUS_OFFSET	ULL(0x00000018)
-#define RPI3_MBOX0_CONFIG_OFFSET	ULL(0x0000001C)
-/* ARM -> VideoCore */
-#define RPI3_MBOX1_WRITE_OFFSET		ULL(0x00000020)
-#define RPI3_MBOX1_PEEK_OFFSET		ULL(0x00000030)
-#define RPI3_MBOX1_SENDER_OFFSET	ULL(0x00000034)
-#define RPI3_MBOX1_STATUS_OFFSET	ULL(0x00000038)
-#define RPI3_MBOX1_CONFIG_OFFSET	ULL(0x0000003C)
-/* Mailbox status constants */
-#define RPI3_MBOX_STATUS_FULL_MASK	U(0x80000000) /* Set if full */
-#define RPI3_MBOX_STATUS_EMPTY_MASK	U(0x40000000) /* Set if empty */
 
 /*
  * Power management, reset controller, watchdog.
  */
 #define RPI3_IO_PM_OFFSET		ULL(0x00100000)
 #define RPI3_PM_BASE			(RPI_IO_BASE + RPI3_IO_PM_OFFSET)
-/* Registers on top of RPI3_PM_BASE. */
-#define RPI3_PM_RSTC_OFFSET		ULL(0x0000001C)
-#define RPI3_PM_RSTS_OFFSET		ULL(0x00000020)
-#define RPI3_PM_WDOG_OFFSET		ULL(0x00000024)
-/* Watchdog constants */
-#define RPI3_PM_PASSWORD		U(0x5A000000)
-#define RPI3_PM_RSTC_WRCFG_MASK		U(0x00000030)
-#define RPI3_PM_RSTC_WRCFG_FULL_RESET	U(0x00000020)
-/*
- * The RSTS register is used by the VideoCore firmware when booting the
- * Raspberry Pi to know which partition to boot from. The partition value is
- * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware
- * to indicate halt.
- */
-#define RPI3_PM_RSTS_WRCFG_HALT		U(0x00000555)
 
 /*
  * Hardware random number generator.
  */
 #define RPI3_IO_RNG_OFFSET		ULL(0x00104000)
 #define RPI3_RNG_BASE			(RPI_IO_BASE + RPI3_IO_RNG_OFFSET)
-#define RPI3_RNG_CTRL_OFFSET		ULL(0x00000000)
-#define RPI3_RNG_STATUS_OFFSET		ULL(0x00000004)
-#define RPI3_RNG_DATA_OFFSET		ULL(0x00000008)
-#define RPI3_RNG_INT_MASK_OFFSET	ULL(0x00000010)
-/* Enable/disable RNG */
-#define RPI3_RNG_CTRL_ENABLE		U(0x1)
-#define RPI3_RNG_CTRL_DISABLE		U(0x0)
-/* Number of currently available words */
-#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT	U(24)
-#define RPI3_RNG_STATUS_NUM_WORDS_MASK	U(0xFF)
-/* Value to mask interrupts caused by the RNG */
-#define RPI3_RNG_INT_MASK_DISABLE	U(0x1)
 
 /*
  * Serial ports:
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
index 0430d46..8162492 100644
--- a/plat/rpi/rpi4/include/rpi_hw.h
+++ b/plat/rpi/rpi4/include/rpi_hw.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,60 +23,18 @@
  */
 #define RPI3_MBOX_OFFSET		ULL(0x0000B880)
 #define RPI3_MBOX_BASE			(RPI_LEGACY_BASE + RPI3_MBOX_OFFSET)
-/* VideoCore -> ARM */
-#define RPI3_MBOX0_READ_OFFSET		ULL(0x00000000)
-#define RPI3_MBOX0_PEEK_OFFSET		ULL(0x00000010)
-#define RPI3_MBOX0_SENDER_OFFSET	ULL(0x00000014)
-#define RPI3_MBOX0_STATUS_OFFSET	ULL(0x00000018)
-#define RPI3_MBOX0_CONFIG_OFFSET	ULL(0x0000001C)
-/* ARM -> VideoCore */
-#define RPI3_MBOX1_WRITE_OFFSET		ULL(0x00000020)
-#define RPI3_MBOX1_PEEK_OFFSET		ULL(0x00000030)
-#define RPI3_MBOX1_SENDER_OFFSET	ULL(0x00000034)
-#define RPI3_MBOX1_STATUS_OFFSET	ULL(0x00000038)
-#define RPI3_MBOX1_CONFIG_OFFSET	ULL(0x0000003C)
-/* Mailbox status constants */
-#define RPI3_MBOX_STATUS_FULL_MASK	U(0x80000000) /* Set if full */
-#define RPI3_MBOX_STATUS_EMPTY_MASK	U(0x40000000) /* Set if empty */
 
 /*
  * Power management, reset controller, watchdog.
  */
 #define RPI3_IO_PM_OFFSET		ULL(0x00100000)
 #define RPI3_PM_BASE			(RPI_LEGACY_BASE + RPI3_IO_PM_OFFSET)
-/* Registers on top of RPI3_PM_BASE. */
-#define RPI3_PM_RSTC_OFFSET		ULL(0x0000001C)
-#define RPI3_PM_RSTS_OFFSET		ULL(0x00000020)
-#define RPI3_PM_WDOG_OFFSET		ULL(0x00000024)
-/* Watchdog constants */
-#define RPI3_PM_PASSWORD		U(0x5A000000)
-#define RPI3_PM_RSTC_WRCFG_MASK		U(0x00000030)
-#define RPI3_PM_RSTC_WRCFG_FULL_RESET	U(0x00000020)
-/*
- * The RSTS register is used by the VideoCore firmware when booting the
- * Raspberry Pi to know which partition to boot from. The partition value is
- * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware
- * to indicate halt.
- */
-#define RPI3_PM_RSTS_WRCFG_HALT		U(0x00000555)
 
 /*
  * Hardware random number generator.
  */
 #define RPI3_IO_RNG_OFFSET		ULL(0x00104000)
 #define RPI3_RNG_BASE			(RPI_LEGACY_BASE + RPI3_IO_RNG_OFFSET)
-#define RPI3_RNG_CTRL_OFFSET		ULL(0x00000000)
-#define RPI3_RNG_STATUS_OFFSET		ULL(0x00000004)
-#define RPI3_RNG_DATA_OFFSET		ULL(0x00000008)
-#define RPI3_RNG_INT_MASK_OFFSET	ULL(0x00000010)
-/* Enable/disable RNG */
-#define RPI3_RNG_CTRL_ENABLE		U(0x1)
-#define RPI3_RNG_CTRL_DISABLE		U(0x0)
-/* Number of currently available words */
-#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT	U(24)
-#define RPI3_RNG_STATUS_NUM_WORDS_MASK	U(0xFF)
-/* Value to mask interrupts caused by the RNG */
-#define RPI3_RNG_INT_MASK_DISABLE	U(0x1)
 
 /*
  * Serial ports: