diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 40d14ab..d764eb2 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -34,21 +34,21 @@
 /* Helper macros to save and restore GICD registers to and from the context */
 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG)		\
 	do {								\
-		for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \
-				int_id += (1 << REG##_SHIFT)) {		\
+		for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
+				int_id += (1U << REG##_SHIFT)) {	\
 			gicd_write_##reg(base, int_id,			\
 				ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \
 		}							\
-	} while (0)
+	} while (false)
 
 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG)			\
 	do {								\
-		for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \
-				int_id += (1 << REG##_SHIFT)) {		\
+		for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
+				int_id += (1U << REG##_SHIFT)) {	\
 			ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\
 					gicd_read_##reg(base, int_id);	\
 		}							\
-	} while (0)
+	} while (false)
 
 
 /*******************************************************************************
@@ -59,11 +59,11 @@
 {
 	unsigned int gic_version;
 
-	assert(plat_driver_data);
-	assert(plat_driver_data->gicd_base);
-	assert(plat_driver_data->gicr_base);
-	assert(plat_driver_data->rdistif_num);
-	assert(plat_driver_data->rdistif_base_addrs);
+	assert(plat_driver_data != NULL);
+	assert(plat_driver_data->gicd_base != 0U);
+	assert(plat_driver_data->gicr_base != 0U);
+	assert(plat_driver_data->rdistif_num != 0U);
+	assert(plat_driver_data->rdistif_base_addrs != NULL);
 
 	assert(IS_IN_EL3());
 
@@ -109,10 +109,10 @@
 
 	/* Check for system register support */
 #ifdef AARCH32
-	assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT));
+	assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
 #else
-	assert(read_id_aa64pfr0_el1() &
-			(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT));
+	assert((read_id_aa64pfr0_el1() &
+			(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
 #endif /* AARCH32 */
 
 	/* The GIC version should be 3.0 */
@@ -170,8 +170,8 @@
 {
 	unsigned int bitmap = 0;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 
 	assert(IS_IN_EL3());
 
@@ -245,16 +245,16 @@
 void gicv3_rdistif_init(unsigned int proc_num)
 {
 	uintptr_t gicr_base;
-	unsigned int bitmap = 0;
+	unsigned int bitmap = 0U;
 	uint32_t ctlr;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 
 	ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base);
-	assert(ctlr & CTLR_ARE_S_BIT);
+	assert((ctlr & CTLR_ARE_S_BIT) != 0U);
 
 	assert(IS_IN_EL3());
 
@@ -333,9 +333,9 @@
 	unsigned int scr_el3;
 	unsigned int icc_sre_el3;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(IS_IN_EL3());
 
 	/* Mark the connected core as awake */
@@ -353,7 +353,7 @@
 	icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
 	write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
 
-	scr_el3 = read_scr_el3();
+	scr_el3 = (uint32_t) read_scr_el3();
 
 	/*
 	 * Switch to NS state to write Non secure ICC_SRE_EL1 and
@@ -393,9 +393,9 @@
 {
 	uintptr_t gicr_base;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 
 	assert(IS_IN_EL3());
 
@@ -429,14 +429,14 @@
 	unsigned int id;
 
 	assert(IS_IN_EL3());
-	id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
+	id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
 
 	/*
 	 * If the ID is special identifier corresponding to G1S or G1NS
 	 * interrupt, then read the highest pending group 1 interrupt.
 	 */
 	if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID))
-		return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
+		return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
 
 	return id;
 }
@@ -453,7 +453,7 @@
 unsigned int gicv3_get_pending_interrupt_type(void)
 {
 	assert(IS_IN_EL3());
-	return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
+	return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
 }
 
 /*******************************************************************************
@@ -473,10 +473,10 @@
 	uintptr_t gicr_base;
 
 	assert(IS_IN_EL3());
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 
 	/* Ensure the parameters are valid */
-	assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID);
+	assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID));
 	assert(proc_num < gicv3_driver_data->rdistif_num);
 
 	/* All LPI interrupts are Group 1 non secure */
@@ -484,12 +484,12 @@
 		return INTR_GROUP1NS;
 
 	if (id < MIN_SPI_ID) {
-		assert(gicv3_driver_data->rdistif_base_addrs);
+		assert(gicv3_driver_data->rdistif_base_addrs != 0U);
 		gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
 		igroup = gicr_get_igroupr0(gicr_base, id);
 		grpmodr = gicr_get_igrpmodr0(gicr_base, id);
 	} else {
-		assert(gicv3_driver_data->gicd_base);
+		assert(gicv3_driver_data->gicd_base != 0U);
 		igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id);
 		grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id);
 	}
@@ -498,11 +498,11 @@
 	 * If the IGROUP bit is set, then it is a Group 1 Non secure
 	 * interrupt
 	 */
-	if (igroup)
+	if (igroup != 0U)
 		return INTR_GROUP1NS;
 
 	/* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
-	if (grpmodr)
+	if (grpmodr != 0U)
 		return INTR_GROUP1S;
 
 	/* Else it is a Group 0 Secure interrupt */
@@ -522,12 +522,12 @@
  *****************************************************************************/
 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx)
 {
-	int i;
+	unsigned int i;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(IS_IN_EL3());
-	assert(its_ctx);
-	assert(gits_base);
+	assert(its_ctx != NULL);
+	assert(gits_base != 0U);
 
 	its_ctx->gits_ctlr = gits_read_ctlr(gits_base);
 
@@ -555,16 +555,16 @@
  *****************************************************************************/
 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx)
 {
-	int i;
+	unsigned int i;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(IS_IN_EL3());
-	assert(its_ctx);
-	assert(gits_base);
+	assert(its_ctx != NULL);
+	assert(gits_base != 0U);
 
 	/* Assert that the GITS is disabled and quiescent */
-	assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0);
-	assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0);
+	assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
+	assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U);
 
 	gits_write_cbaser(gits_base, its_ctx->gits_cbaser);
 	gits_write_cwriter(gits_base, its_ctx->gits_cwriter);
@@ -586,11 +586,11 @@
 	uintptr_t gicr_base;
 	unsigned int int_id;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(IS_IN_EL3());
-	assert(rdist_ctx);
+	assert(rdist_ctx != NULL);
 
 	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
 
@@ -614,7 +614,7 @@
 	rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base);
 	rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base);
 	for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
-			int_id += (1 << IPRIORITYR_SHIFT)) {
+			int_id += (1U << IPRIORITYR_SHIFT)) {
 		rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] =
 				gicr_read_ipriorityr(gicr_base, int_id);
 	}
@@ -641,11 +641,11 @@
 	uintptr_t gicr_base;
 	unsigned int int_id;
 
-	assert(gicv3_driver_data);
+	assert(gicv3_driver_data != NULL);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(IS_IN_EL3());
-	assert(rdist_ctx);
+	assert(rdist_ctx != NULL);
 
 	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
 
@@ -664,7 +664,7 @@
 	 * more scalable approach as it avoids clearing the enable bits in the
 	 * GICD_CTLR
 	 */
-	gicr_write_icenabler0(gicr_base, ~0);
+	gicr_write_icenabler0(gicr_base, ~0U);
 	/* Wait for pending writes to GICR_ICENABLER */
 	gicr_wait_for_pending_write(gicr_base);
 
@@ -682,7 +682,7 @@
 	gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0);
 
 	for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
-			int_id += (1 << IPRIORITYR_SHIFT)) {
+			int_id += (1U << IPRIORITYR_SHIFT)) {
 		gicr_write_ipriorityr(gicr_base, int_id,
 		rdist_ctx->gicr_ipriorityr[
 				(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]);
@@ -722,18 +722,18 @@
 {
 	unsigned int num_ints;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(IS_IN_EL3());
-	assert(dist_ctx);
+	assert(dist_ctx != NULL);
 
 	uintptr_t gicd_base = gicv3_driver_data->gicd_base;
 
 	num_ints = gicd_read_typer(gicd_base);
 	num_ints &= TYPER_IT_LINES_NO_MASK;
-	num_ints = (num_ints + 1) << 5;
+	num_ints = (num_ints + 1U) << 5;
 
-	assert(num_ints <= MAX_SPI_ID + 1);
+	assert(num_ints <= (MAX_SPI_ID + 1U));
 
 	/* Wait for pending write to complete */
 	gicd_wait_for_pending_write(gicd_base);
@@ -784,12 +784,12 @@
  *****************************************************************************/
 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
 {
-	unsigned int num_ints = 0;
+	unsigned int num_ints = 0U;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(IS_IN_EL3());
-	assert(dist_ctx);
+	assert(dist_ctx != NULL);
 
 	uintptr_t gicd_base = gicv3_driver_data->gicd_base;
 
@@ -809,9 +809,9 @@
 
 	num_ints = gicd_read_typer(gicd_base);
 	num_ints &= TYPER_IT_LINES_NO_MASK;
-	num_ints = (num_ints + 1) << 5;
+	num_ints = (num_ints + 1U) << 5;
 
-	assert(num_ints <= MAX_SPI_ID + 1);
+	assert(num_ints <= (MAX_SPI_ID + 1U));
 
 	/* Restore GICD_IGROUPR for INTIDs 32 - 1020 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
@@ -857,7 +857,7 @@
  ******************************************************************************/
 unsigned int gicv3_get_running_priority(void)
 {
-	return read_icc_rpr_el1();
+	return (unsigned int)read_icc_rpr_el1();
 }
 
 /*******************************************************************************
@@ -870,10 +870,10 @@
 {
 	unsigned int value;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(id <= MAX_SPI_ID);
 
 	if (id < MIN_SPI_ID) {
@@ -894,10 +894,10 @@
  ******************************************************************************/
 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
 {
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(id <= MAX_SPI_ID);
 
 	/*
@@ -922,10 +922,10 @@
  ******************************************************************************/
 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num)
 {
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(id <= MAX_SPI_ID);
 
 	/*
@@ -960,10 +960,10 @@
 {
 	uintptr_t gicr_base;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 	assert(id <= MAX_SPI_ID);
 
 	if (id < MIN_SPI_ID) {
@@ -982,29 +982,29 @@
 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
 		unsigned int type)
 {
-	unsigned int igroup = 0, grpmod = 0;
+	bool igroup = false, grpmod = false;
 	uintptr_t gicr_base;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 
 	switch (type) {
 	case INTR_GROUP1S:
-		igroup = 0;
-		grpmod = 1;
+		igroup = false;
+		grpmod = true;
 		break;
 	case INTR_GROUP0:
-		igroup = 0;
-		grpmod = 0;
+		igroup = false;
+		grpmod = false;
 		break;
 	case INTR_GROUP1NS:
-		igroup = 1;
-		grpmod = 0;
+		igroup = true;
+		grpmod = false;
 		break;
 	default:
-		assert(0);
+		assert(false);
 		break;
 	}
 
@@ -1040,7 +1040,7 @@
  *
  * The target parameter must be a valid MPIDR in the system.
  ******************************************************************************/
-void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target)
+void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target)
 {
 	unsigned int tgt, aff3, aff2, aff1, aff0;
 	uint64_t sgi_val;
@@ -1059,7 +1059,7 @@
 	 * this PE.
 	 */
 	assert(aff0 < GICV3_MAX_SGI_TARGETS);
-	tgt = BIT(aff0);
+	tgt = BIT_32(aff0);
 
 	/* Raise SGI to PE specified by its affinity */
 	sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF,
@@ -1090,11 +1090,11 @@
 	unsigned long long aff;
 	uint64_t router;
 
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 
 	assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE));
-	assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID);
+	assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID));
 
 	aff = gicd_irouter_val_from_mpidr(mpidr, irm);
 	gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff);
@@ -1105,7 +1105,7 @@
 	 */
 	if (irm == GICV3_IRM_ANY) {
 		router = gicd_read_irouter(gicv3_driver_data->gicd_base, id);
-		if (!((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK)) {
+		if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) {
 			ERROR("GICv3 implementation doesn't support routing ANY\n");
 			panic();
 		}
@@ -1119,10 +1119,10 @@
  ******************************************************************************/
 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
 {
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 
 	/*
 	 * Clear pending interrupt, and ensure that any shared variable updates
@@ -1145,10 +1145,10 @@
  ******************************************************************************/
 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num)
 {
-	assert(gicv3_driver_data);
-	assert(gicv3_driver_data->gicd_base);
+	assert(gicv3_driver_data != NULL);
+	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(proc_num < gicv3_driver_data->rdistif_num);
-	assert(gicv3_driver_data->rdistif_base_addrs);
+	assert(gicv3_driver_data->rdistif_base_addrs != NULL);
 
 	/*
 	 * Ensure that any shared variable updates depending on out of band
@@ -1172,7 +1172,7 @@
 {
 	unsigned int old_mask;
 
-	old_mask = read_icc_pmr_el1();
+	old_mask = (uint32_t) read_icc_pmr_el1();
 
 	/*
 	 * Order memory updates w.r.t. PMR write, and ensure they're visible