feat(neoverse_rd): deprecate and remove RD-V1 platform variants
deprecate and remove support for RD-V1 and RD-V1-MC platform variants.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ifab7b95e00615806986e316e0bde7788dc8af04f
diff --git a/changelog.yaml b/changelog.yaml
index acc9697..02c893d 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -189,12 +189,6 @@
- title: RD-E1-Edge
scope: rde1edge
- - title: RD-V1
- scope: rdv1
-
- - title: RD-V1-MC
- scope: rdv1mc
-
- title: RD-N2
scope: rdn2
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index ac36fdb..045250d 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -588,8 +588,6 @@
:|G|: `rohit-arm`_
:|F|: plat/arm/board/neoverse_rd/common
:|F|: plat/arm/board/neoverse_rd/platform/rdn2/
-:|F|: plat/arm/board/neoverse_rd/platform/rdv1/
-:|F|: plat/arm/board/neoverse_rd/platform/rdv1mc/
Arm Total Compute platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 87e6a92..d0d6889 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -84,6 +84,12 @@
| RD-N1-Edge | Arm | 2.13 | 2.13 |
| | | | |
+----------------+----------------+--------------------+--------------------+
+| RD-V1 | Arm | 2.13 | 2.13 |
+| | | | |
++----------------+----------------+--------------------+--------------------+
+| RD-V1-MC | Arm | 2.13 | 2.13 |
+| | | | |
++----------------+----------------+--------------------+--------------------+
--------------
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
deleted file mode 100644
index 74835f6..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS specific memory and interrupt map
- * definitions for the first generation platforms based on the A75, N1 and V1
- * CPUs. There are minor differences in the memory map of these platforms and
- * those differences are not in the scope of this file.
- */
-
-#ifndef NRD_CSS_DEF1_H
-#define NRD_CSS_DEF1_H
-
-/*******************************************************************************
- * CSS memory map related defines
- ******************************************************************************/
-
-/* On-Chip ROM */
-#define NRD_CSS_TRUSTED_ROM_BASE UL(0x00000000)
-#define NRD_CSS_TRUSTED_ROM_SIZE UL(0x00080000) /* 512KB */
-
-/* On-Chip RAM */
-#define NRD_CSS_TRUSTED_SRAM_SIZE UL(0x00080000) /* 512KB */
-#define NRD_CSS_NONTRUSTED_SRAM_BASE UL(0x06000000)
-#define NRD_CSS_NONTRUSTED_SRAM_SIZE UL(0x00080000) /* 512KB */
-
-/* PL011 UART */
-#define NRD_CSS_SEC_UART_BASE UL(0x2A410000)
-#define NRD_CSS_UART_SIZE UL(0x10000)
-
-/* CSS peripherals */
-#define NRD_CSS_PERIPH_BASE UL(0x20000000)
-#define NRD_CSS_PERIPH_SIZE UL(0x40000000)
-
-/* Secure Watchdog */
-#define NRD_CSS_WDOG_BASE UL(0x2A480000)
-
-/* DRAM2 */
-#define NRD_CSS_DRAM2_BASE ULL(0x8080000000)
-#define NRD_CSS_DRAM2_SIZE ULL(0x180000000)
-
-#endif /* NRD_CSS_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
deleted file mode 100644
index 70a7d49..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS firmware specific definitions for
- * the first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD1_CSS_FW_DEF1_H
-#define NRD1_CSS_FW_DEF1_H
-
-#include <nrd_css_def1.h>
-
-/*******************************************************************************
- * BL sizes
- ******************************************************************************/
-
-#define NRD_CSS_BL1_RW_SIZE UL(64 * 1024) /* 64KB */
-
-#if TRUSTED_BOARD_BOOT
-# define NRD_CSS_BL2_SIZE UL(0x28000)
-#else
-# define NRD_CSS_BL2_SIZE UL(0x14000)
-#endif
-
-/*
- * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
- * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
- * and BL1-RW.
- */
-#define NRD_CSS_BL31_SIZE UL(116 * 1024) /* 116 KB */
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define NRD_CSS_UART_CLK_IN_HZ UL(7372800)
-
-/*******************************************************************************
- * Watchdog config
- ******************************************************************************/
-
-#define NRD_CSS_WDOG_TIMEOUT UL(100)
-
-/*******************************************************************************
- * Platform ID
- ******************************************************************************/
-
-/* Platform ID address */
-#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
-#ifndef __ASSEMBLER__
-/* SSC_VERSION related accessors */
-/* Returns the part number of the platform */
-#define GET_NRD_PART_NUM \
- GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
-/* Returns the configuration number of the platform */
-#define GET_NRD_CONFIG_NUM \
- GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
-#endif /* __ASSEMBLER__ */
-
-/*******************************************************************************
- * MMU mappings
- ******************************************************************************/
-
-#define NRD_CSS_PERIPH_MMAP(n) \
- MAP_REGION_FLAT( \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
- NRD_CSS_PERIPH_BASE, \
- NRD_CSS_PERIPH_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define NRD_CSS_SHARED_RAM_MMAP(n) \
- MAP_REGION_FLAT( \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
- ARM_SHARED_RAM_BASE, \
- ARM_SHARED_RAM_SIZE, \
- MT_NON_CACHEABLE | MT_RW | MT_SECURE)
-
-#if SPM_MM
-/*
- * Stand-alone MM logs would be routed via secure UART. Define page table
- * entry for secure UART which would be common to all platforms.
- */
-#define NRD_CSS_SECURE_UART_MMAP \
- MAP_REGION_FLAT( \
- NRD_CSS_SEC_UART_BASE, \
- NRD_CSS_UART_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-#endif
-
-#endif /* NRD_CSS_FW_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
deleted file mode 100644
index bca095c..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the platform port definitions for the
- * first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD_PLAT_ARM_DEF1_H
-#define NRD_PLAT_ARM_DEF1_H
-
-#ifndef __ASSEMBLER__
-#include <lib/mmio.h>
-#endif /* __ASSEMBLER__ */
-
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <plat/arm/board/common/v2m_def.h>
-#include <plat/arm/common/arm_def.h>
-#include <plat/arm/common/arm_spm_def.h>
-#include <plat/arm/css/common/css_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
-#include <plat/common/common_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_ros_fw_def1.h>
-
-/*******************************************************************************
- * Core count
- ******************************************************************************/
-
-#define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \
- PLAT_ARM_CLUSTER_COUNT * \
- NRD_MAX_CPUS_PER_CLUSTER * \
- NRD_MAX_PE_PER_CPU)
-
-/*******************************************************************************
- * PA/VA config
- ******************************************************************************/
-
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#endif
-
-/*******************************************************************************
- * XLAT definitions
- ******************************************************************************/
-
-#if defined(IMAGE_BL31)
-# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
-# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
-# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 3))
-# define PLAT_SP_IMAGE_MMAP_REGIONS U(12)
-# define PLAT_SP_IMAGE_MAX_XLAT_TABLES U(14)
-# else
-# define PLAT_ARM_MMAP_ENTRIES (5 + ((NRD_CHIP_COUNT - 1) * 3))
-# define MAX_XLAT_TABLES (6 + ((NRD_CHIP_COUNT - 1) * 3))
-# endif
-#elif defined(IMAGE_BL32)
-# define PLAT_ARM_MMAP_ENTRIES U(8)
-# define MAX_XLAT_TABLES U(5)
-#elif defined(IMAGE_BL2)
-# define PLAT_ARM_MMAP_ENTRIES (11 + (NRD_CHIP_COUNT - 1))
-
-/*
- * MAX_XLAT_TABLES entries need to be doubled because when the address width
- * exceeds 40 bits an additional level of translation is required. In case of
- * multichip platforms peripherals also fall into address space with width
- * > 40 bits.
- */
-# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 2))
-#elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES U(11)
-# define MAX_XLAT_TABLES U(7)
-#else
-# define PLAT_ARM_MMAP_ENTRIES U(12)
-# define MAX_XLAT_TABLES U(6)
-#endif
-
-/*******************************************************************************
- * Stack size
- ******************************************************************************/
-
-#if defined(IMAGE_BL1)
-# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE U(0x1000)
-# else
-# define PLATFORM_STACK_SIZE U(0x440)
-# endif
-#elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE U(0x1000)
-# else
-# define PLATFORM_STACK_SIZE U(0x400)
-# endif
-#elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE U(0x400)
-#elif defined(IMAGE_BL31)
-# if SPM_MM
-# define PLATFORM_STACK_SIZE U(0x500)
-# else
-# define PLATFORM_STACK_SIZE U(0x400)
-# endif
-#elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE U(0x440)
-#endif
-
-#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
-/*
- * Secure partition stack follows right after the memory region that is shared
- * between EL3 and S-EL0.
- */
-#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
- PLAT_SP_IMAGE_NS_BUF_SIZE)
-#endif /* SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) */
-
-/*******************************************************************************
- * BL sizes
- ******************************************************************************/
-
-#if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0x1000)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0xe000)
-#else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0)
-#endif
-
-#define PLAT_ARM_MAX_BL1_RW_SIZE NRD_CSS_BL1_RW_SIZE
-
-/*
- * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
- * little space for growth. Additional 8KiB space is added per chip in
- * order to accommodate the additional level of translation required for "TZC"
- * peripheral access which lies in >4TB address space.
- *
- */
-#define PLAT_ARM_MAX_BL2_SIZE (NRD_CSS_BL2_SIZE + \
- ((NRD_CHIP_COUNT - 1) * 0x2000))
-
-#define PLAT_ARM_MAX_BL31_SIZE (NRD_CSS_BL31_SIZE + \
- PLAT_ARM_MAX_BL2_SIZE + \
- PLAT_ARM_MAX_BL1_RW_SIZE)
-
-/*******************************************************************************
- * ROM, SRAM and DRAM config
- ******************************************************************************/
-
-#define PLAT_ARM_TRUSTED_SRAM_SIZE NRD_CSS_TRUSTED_SRAM_SIZE
-
-#define PLAT_ARM_TRUSTED_ROM_BASE NRD_CSS_TRUSTED_ROM_BASE
-#define PLAT_ARM_TRUSTED_ROM_SIZE NRD_CSS_TRUSTED_ROM_SIZE
-
-#define PLAT_ARM_NSRAM_BASE NRD_CSS_NONTRUSTED_SRAM_BASE
-#define PLAT_ARM_NSRAM_SIZE NRD_CSS_NONTRUSTED_SRAM_SIZE
-
-#define PLAT_ARM_DRAM2_BASE NRD_CSS_DRAM2_BASE
-#define PLAT_ARM_DRAM2_SIZE NRD_CSS_DRAM2_SIZE
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define PLAT_ARM_BOOT_UART_BASE NRD_CSS_SEC_UART_BASE
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
-
-#define PLAT_ARM_RUN_UART_BASE NRD_CSS_SEC_UART_BASE
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
-
-#define PLAT_ARM_CRASH_UART_BASE NRD_CSS_SEC_UART_BASE
-#define PLAT_ARM_CRASH_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
-
-/*******************************************************************************
- * Timer config
- ******************************************************************************/
-
-#define PLAT_ARM_NSTIMER_FRAME_ID (0)
-
-/*******************************************************************************
- * Power config
- ******************************************************************************/
-
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
-/*******************************************************************************
- * Flash config
- ******************************************************************************/
-
-#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
- V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-/* IO storage framework */
-#define MAX_IO_DEVICES U(3)
-#define MAX_IO_HANDLES U(4)
-
-/*******************************************************************************
- * SCMI config
- ******************************************************************************/
-
-/* Number of SCMI channels on the platform */
-#define PLAT_ARM_SCMI_CHANNEL_COUNT NRD_CHIP_COUNT
-
-/*******************************************************************************
- * SDS config
- ******************************************************************************/
-
-/* Index of SDS region used in the communication with SCP */
-#define SDS_SCP_AP_REGION_ID U(0)
-/* SDS ID for unusable CPU MPID list structure */
-#define SDS_ISOLATED_CPU_LIST_ID U(128)
-
-/*******************************************************************************
- * GIC/EHF config
- ******************************************************************************/
-
-#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
-#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
-#define PLAT_SP_PRI U(0x10)
-
-/*******************************************************************************
- * Platform type identification macro
- ******************************************************************************/
-
-/* Platform ID related accessors */
-#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0f)
-#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x0)
-#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
-
-#ifndef __ASSEMBLER__
-#define BOARD_CSS_GET_PLAT_TYPE(addr) \
- ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
- >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
-#endif /* __ASSEMBLER__ */
-
-/* Platform ID address */
-#define BOARD_CSS_PLAT_ID_REG_ADDR NRD_ROS_PLATFORM_BASE + \
- UL(0x00fe00e0)
-
-#endif /* NRD_PLAT_ARM_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
deleted file mode 100644
index b86ab21..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the RoS specific definitions for the first
- * generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of System)
- * is used to refer to the part of the reference design platform that excludes
- * CSS.
- */
-
-#ifndef NRD_ROS_DEF1_H
-#define NRD_ROS_DEF1_H
-
-/*******************************************************************************
- * ROS configs
- ******************************************************************************/
-
-/* RoS Peripherals */
-#define NRD_ROS_PERIPH_BASE UL(0x60000000)
-#define NRD_ROS_PERIPH_SIZE UL(0x20000000)
-
-/* System Reg */
-#define NRD_ROS_SYSTEMREG_BASE UL(0x1C010000)
-#define NRD_ROS_SYSTEMREG_SIZE UL(0x00010000)
-
-/* NOR Flash 2 */
-#define NRD_ROS_NOR2_FLASH_BASE UL(0x10000000)
-#define NRD_ROS_NOR2_FLASH_SIZE UL(0x04000000)
-
-/* RoS Platform */
-#define NRD_ROS_PLATFORM_BASE UL(0x7F000000)
-#define NRD_ROS_PLATFORM_SIZE UL(0x20000000)
-
-#endif /* NRD_ROS_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
deleted file mode 100644
index c521043..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the RoS firmware specific definitions for the
- * first generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of
- * System) is used to refer to the part of the reference design platform that
- * excludes CSS.
- */
-
-#ifndef NRD_ROS_FW_DEF1_H
-#define NRD_ROS_FW_DEF1_H
-
-#include <nrd_ros_def1.h>
-
-/*******************************************************************************
- * MMU mapping
- ******************************************************************************/
-
-#define NRD_ROS_PERIPH_MMAP(n) \
- MAP_REGION_FLAT( \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
- NRD_ROS_PERIPH_BASE, \
- NRD_ROS_PERIPH_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP \
- MAP_REGION_FLAT( \
- NRD_ROS_SYSTEMREG_BASE, \
- NRD_ROS_SYSTEMREG_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-
-#define NRD_ROS_SECURE_NOR2_USER_MMAP \
- MAP_REGION_FLAT( \
- NRD_ROS_NOR2_FLASH_BASE, \
- NRD_ROS_NOR2_FLASH_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-
-#define NRD_MAP_FLASH0_RO \
- MAP_REGION_FLAT( \
- V2M_FLASH0_BASE, \
- V2M_FLASH0_SIZE, \
- MT_DEVICE | MT_RO | MT_SECURE)
-
-/*******************************************************************************
- * TZ config
- ******************************************************************************/
-
-/*
- * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms
- * where both the DRAM regions are marked for non-secure access. This applies
- * to multi-chip platforms.
- */
-#define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n) \
- {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
- ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
- ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
-
-#endif /* NRD_ROS_FW_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
index 813a17f..901cbf1 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
@@ -7,9 +7,6 @@
#ifndef NRD_VARIANT_H
#define NRD_VARIANT_H
-/* SID Version values for RD-V1 */
-#define RD_V1_SID_VER_PART_NUM 0x078a
-
/* SID Version values for RD-N2 */
#define RD_N2_SID_VER_PART_NUM 0x07B7
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index b7ed007..3ad586b 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -115,8 +115,7 @@
scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
{
- if (nrd_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
- nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
+ if (nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
nrd_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
nrd_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM ||
nrd_plat_info.platform_id == RD_N2_CFG3_SID_VER_PART_NUM) {
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat1.c b/plat/arm/board/neoverse_rd/common/nrd_plat1.c
deleted file mode 100644
index 32444f4..0000000
--- a/plat/arm/board/neoverse_rd/common/nrd_plat1.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/ccn.h>
-#include <drivers/arm/css/sds.h>
-#include <lib/utils_def.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <drivers/arm/sbsa.h>
-
-#if SPM_MM
-#include <services/spm_mm_partition.h>
-#endif
-
-/*
- * Table of regions for different BL stages to map using the MMU.
- * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
- * arm_configure_mmu_elx() will give the available subset of that.
- *
- * Replace or extend the below regions as required
- */
-#if IMAGE_BL1
-const mmap_region_t plat_arm_mmap[] = {
- ARM_MAP_SHARED_RAM,
- NRD_MAP_FLASH0_RO,
- NRD_CSS_PERIPH_MMAP(0),
- NRD_ROS_PERIPH_MMAP(0),
- {0}
-};
-#endif
-#if IMAGE_BL2
-const mmap_region_t plat_arm_mmap[] = {
- ARM_MAP_SHARED_RAM,
- NRD_MAP_FLASH0_RO,
-#ifdef PLAT_ARM_MEM_PROT_ADDR
- ARM_V2M_MAP_MEM_PROTECT,
-#endif
- NRD_CSS_PERIPH_MMAP(0),
- NRD_ROS_PERIPH_MMAP(0),
- ARM_MAP_NS_DRAM1,
-#if NRD_CHIP_COUNT > 1
- NRD_CSS_PERIPH_MMAP(1),
-#endif
-#if NRD_CHIP_COUNT > 2
- NRD_CSS_PERIPH_MMAP(2),
-#endif
-#if NRD_CHIP_COUNT > 3
- NRD_CSS_PERIPH_MMAP(3),
-#endif
-#if ARM_BL31_IN_DRAM
- ARM_MAP_BL31_SEC_DRAM,
-#endif
-#if SPM_MM
- ARM_SP_IMAGE_MMAP,
-#endif
-#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
- ARM_MAP_BL1_RW,
-#endif
- {0}
-};
-#endif
-#if IMAGE_BL31
-const mmap_region_t plat_arm_mmap[] = {
- ARM_MAP_SHARED_RAM,
- V2M_MAP_IOFPGA,
- NRD_CSS_PERIPH_MMAP(0),
-#ifdef PLAT_ARM_MEM_PROT_ADDR
- ARM_V2M_MAP_MEM_PROTECT,
-#endif
- NRD_ROS_PERIPH_MMAP(0),
-#if SPM_MM
- ARM_SPM_BUF_EL3_MMAP,
-#endif
- {0}
-};
-
-#if SPM_MM && defined(IMAGE_BL31)
-const mmap_region_t plat_arm_secure_partition_mmap[] = {
- NRD_ROS_SECURE_SYSTEMREG_USER_MMAP,
- NRD_ROS_SECURE_NOR2_USER_MMAP,
- NRD_CSS_SECURE_UART_MMAP,
- ARM_SP_IMAGE_MMAP,
- ARM_SP_IMAGE_NS_BUF_MMAP,
- ARM_SP_IMAGE_RW_MMAP,
- ARM_SPM_BUF_EL0_MMAP,
- {0}
-};
-#endif /* SPM_MM && defined(IMAGE_BL31) */
-#endif
-
-ARM_CASSERT_MMAP
-
-#if SPM_MM && defined(IMAGE_BL31)
-/*
- * Boot information passed to a secure partition during initialisation. Linear
- * indices in MP information will be filled at runtime.
- */
-static spm_mm_mp_info_t sp_mp_info[] = {
- [0] = {0x81000000, 0},
- [1] = {0x81000100, 0},
- [2] = {0x81000200, 0},
- [3] = {0x81000300, 0},
- [4] = {0x81010000, 0},
- [5] = {0x81010100, 0},
- [6] = {0x81010200, 0},
- [7] = {0x81010300, 0},
-};
-
-const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
- .h.type = PARAM_SP_IMAGE_BOOT_INFO,
- .h.version = VERSION_1,
- .h.size = sizeof(spm_mm_boot_info_t),
- .h.attr = 0,
- .sp_mem_base = ARM_SP_IMAGE_BASE,
- .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
- .sp_image_base = ARM_SP_IMAGE_BASE,
- .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
- .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
- .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
- .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
- .sp_image_size = ARM_SP_IMAGE_SIZE,
- .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
- .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
- .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
- .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
- .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
- .num_cpus = PLATFORM_CORE_COUNT,
- .mp_info = &sp_mp_info[0],
-};
-
-const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
-{
- return plat_arm_secure_partition_mmap;
-}
-
-const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
- void *cookie)
-{
- return &plat_arm_secure_partition_boot_info;
-}
-#endif /* SPM_MM && defined(IMAGE_BL31) */
-
-#if TRUSTED_BOARD_BOOT
-int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
-{
- assert(heap_addr != NULL);
- assert(heap_size != NULL);
-
- return arm_get_mbedtls_heap(heap_addr, heap_size);
-}
-#endif
-
-void plat_arm_secure_wdt_start(void)
-{
- sbsa_wdog_start(NRD_CSS_WDOG_BASE, NRD_CSS_WDOG_TIMEOUT);
-}
-
-void plat_arm_secure_wdt_stop(void)
-{
- sbsa_wdog_stop(NRD_CSS_WDOG_BASE);
-}
-
-static sds_region_desc_t nrd_sds_regions[] = {
- { .base = PLAT_ARM_SDS_MEM_BASE },
-};
-
-sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
-{
- *region_count = ARRAY_SIZE(nrd_sds_regions);
-
- return nrd_sds_regions;
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_fw_config.dts
deleted file mode 100644
index d443443..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-
-/ {
- dtb-registry {
- compatible = "fconf,dyn_cfg-dtb_registry";
-
- tb_fw-config {
- load-address = <0x0 0x4001300>;
- max-size = <0x200>;
- id = <TB_FW_CONFIG_ID>;
- };
-
- nt_fw-config {
- load-address = <0x0 0xFEF00000>;
- max-size = <0x0100000>;
- id = <NT_FW_CONFIG_ID>;
- };
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_nt_fw_config.dts
deleted file mode 100644
index fb08885..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_nt_fw_config.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
- /* compatible string */
- compatible = "arm,rd-v1";
-
- /*
- * Place holder for system-id node with default values. The
- * value of platform-id and config-id will be set to the
- * correct values during the BL2 stage of boot.
- */
- system-id {
- platform-id = <0x0>;
- config-id = <0x0>;
- multi-chip-mode = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_tb_fw_config.dts
deleted file mode 100644
index c370623..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_tb_fw_config.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
- tb_fw-config {
- compatible = "arm,tb_fw";
-
- /* Disable authentication for development */
- disable_auth = <0x0>;
-
- /*
- * The following two entries are placeholders for Mbed TLS
- * heap information. The default values don't matter since
- * they will be overwritten by BL1.
- * In case of having shared Mbed TLS heap between BL1 and BL2,
- * BL1 will populate these two properties with the respective
- * info about the shared heap. This info will be available for
- * BL2 in order to locate and re-use the heap.
- */
- mbedtls_heap_addr = <0x0 0x0>;
- mbedtls_heap_size = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
deleted file mode 100644
index cd40117..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
- ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT U(16)
-#define NRD_MAX_CPUS_PER_CLUSTER U(1)
-#define NRD_MAX_PE_PER_CPU U(1)
-
-#define PLAT_CSS_MHU_BASE UL(0x45400000)
-#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE UL(0x21830000)
-#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC400_OFFSET UL(0x1000000)
-#define TZC400_COUNT 4
-
-#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
- (n * TZC400_OFFSET))
-
-#define TZC_NSAID_ALL_AP U(0)
-#define TZC_NSAID_PCI U(1)
-#define TZC_NSAID_HDLCD0 U(2)
-#define TZC_NSAID_CLCD U(7)
-#define TZC_NSAID_AP U(9)
-#define TZC_NSAID_VIRTIO U(15)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
-
-/* Maximum number of address bits used per chip */
-#define NRD_ADDR_BITS_PER_CHIP U(42)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICR_BASE UL(0x30140000)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
deleted file mode 100644
index 241133f..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
+++ /dev/null
@@ -1,78 +0,0 @@
-# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# RD-V1 platform uses GIC-700 which is based on GICv4.1
-GIC_ENABLE_V4_EXTN := 1
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-RDV1_BASE = plat/arm/board/neoverse_rd/platform/rdv1
-
-PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
- -I${RDV1_BASE}/include/
-
-NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
-
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDV1_BASE}/rdv1_err.c
-
-BL2_SOURCES += ${RDV1_BASE}/rdv1_plat.c \
- ${RDV1_BASE}/rdv1_security.c \
- ${RDV1_BASE}/rdv1_err.c \
- lib/utils/mem_region.c \
- drivers/arm/tzc/tzc400.c \
- plat/arm/common/arm_tzc400.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDV1_BASE}/rdv1_plat.c \
- ${RDV1_BASE}/rdv1_topology.c \
- drivers/cfi/v2m/v2m_flash.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += ${RDV1_BASE}/rdv1_trusted_boot.c
-BL2_SOURCES += ${RDV1_BASE}/rdv1_trusted_boot.c
-endif
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${RDV1_BASE}/fdts/${PLAT}_fw_config.dts \
- ${RDV1_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-FDT_SOURCES += ${RDV1_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-override CTX_INCLUDE_AARCH32_REGS := 0
-override ENABLE_FEAT_AMU := 2
-override SPMD_SPM_AT_SEL2 := 0
-
-# FEAT_SVE related flags
-override SVE_VECTOR_LEN := 256
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for RD-V1 should always be 0, \
- currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
-# Enable the flag since RD-V1 has a system level cache
-NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_err.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_err.c
deleted file mode 100644
index d75f525..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_err.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * rdv1 error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
- while (1) {
- wfi();
- }
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_plat.c
deleted file mode 100644
index 7cdc19a..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_plat.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
- & SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
- return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
- SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
-}
-
-void bl31_platform_setup(void)
-{
- nrd_bl31_common_platform_setup();
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_security.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_security.c
deleted file mode 100644
index a936a71..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_security.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <platform_def.h>
-
-static const arm_tzc_regions_info_t tzc_regions[] = {
- ARM_TZC_REGIONS_DEF,
- {}
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
- int i;
-
- for (i = 0; i < TZC400_COUNT; i++)
- arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
deleted file mode 100644
index 20e4266..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-const unsigned char rd_v1_pd_tree_desc[] = {
- PLAT_ARM_CLUSTER_COUNT,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return rd_v1_pd_tree_desc;
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF))
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_trusted_boot.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier ::= SEQUENCE {
- * algorithm OBJECT IDENTIFIER,
- * parameters ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- * digestAlgorithm AlgorithmIdentifier,
- * digest OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
- unsigned int *flags)
-{
- return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_fw_config.dts
deleted file mode 100644
index d443443..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-
-/ {
- dtb-registry {
- compatible = "fconf,dyn_cfg-dtb_registry";
-
- tb_fw-config {
- load-address = <0x0 0x4001300>;
- max-size = <0x200>;
- id = <TB_FW_CONFIG_ID>;
- };
-
- nt_fw-config {
- load-address = <0x0 0xFEF00000>;
- max-size = <0x0100000>;
- id = <NT_FW_CONFIG_ID>;
- };
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_nt_fw_config.dts
deleted file mode 100644
index 78fa31e..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_nt_fw_config.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
- /* compatible string */
- compatible = "arm,rd-v1-mc";
-
- /*
- * Place holder for system-id node with default values. The
- * value of platform-id and config-id will be set to the
- * correct values during the BL2 stage of boot.
- */
- system-id {
- platform-id = <0x0>;
- config-id = <0x0>;
- multi-chip-mode = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_tb_fw_config.dts
deleted file mode 100644
index c370623..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_tb_fw_config.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
- tb_fw-config {
- compatible = "arm,tb_fw";
-
- /* Disable authentication for development */
- disable_auth = <0x0>;
-
- /*
- * The following two entries are placeholders for Mbed TLS
- * heap information. The default values don't matter since
- * they will be overwritten by BL1.
- * In case of having shared Mbed TLS heap between BL1 and BL2,
- * BL1 will populate these two properties with the respective
- * info about the shared heap. This info will be available for
- * BL2 in order to locate and re-use the heap.
- */
- mbedtls_heap_addr = <0x0 0x0>;
- mbedtls_heap_size = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
deleted file mode 100644
index b4c5c0a..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
- ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT U(4)
-#define NRD_MAX_CPUS_PER_CLUSTER U(1)
-#define NRD_MAX_PE_PER_CPU U(1)
-
-#define PLAT_CSS_MHU_BASE UL(0x45400000)
-#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE UL(0x21830000)
-#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
- (n * TZC400_OFFSET))
-#define TZC400_OFFSET UL(0x1000000)
-#define TZC400_COUNT U(8)
-#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC_NSAID_ALL_AP U(0)
-#define TZC_NSAID_PCI U(1)
-#define TZC_NSAID_HDLCD0 U(2)
-#define TZC_NSAID_CLCD U(7)
-#define TZC_NSAID_AP U(9)
-#define TZC_NSAID_VIRTIO U(15)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
-
-/* Virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
-
-/* Remote chip address offset (4TB per chip) */
-#define NRD_ADDR_BITS_PER_CHIP U(42)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICR_BASE UL(0x30140000)
-
-/* GIC SPI range for multichip */
-#define NRD_CHIP0_SPI_MIN U(32)
-#define NRD_CHIP0_SPI_MAX U(991)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
deleted file mode 100644
index 7af0bd8..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
+++ /dev/null
@@ -1,89 +0,0 @@
-# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Enable GICv4 extension with multichip driver
-GIC_ENABLE_V4_EXTN := 1
-GICV3_IMPL_GIC600_MULTICHIP := 1
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-RDV1MC_BASE = plat/arm/board/neoverse_rd/platform/rdv1mc
-
-PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
- -I${RDV1MC_BASE}/include/
-
-NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
-
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDV1MC_BASE}/rdv1mc_err.c
-
-BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_plat.c \
- ${RDV1MC_BASE}/rdv1mc_security.c \
- ${RDV1MC_BASE}/rdv1mc_err.c \
- drivers/arm/tzc/tzc400.c \
- plat/arm/common/arm_tzc400.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDV1MC_BASE}/rdv1mc_plat.c \
- ${RDV1MC_BASE}/rdv1mc_topology.c \
- drivers/cfi/v2m/v2m_flash.c \
- drivers/arm/gic/v3/gic600_multichip.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += ${RDV1MC_BASE}/rdv1mc_trusted_boot.c
-BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_trusted_boot.c
-endif
-
-# Enable dynamic addition of MMAP regions in BL31
-BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${RDV1MC_BASE}/fdts/${PLAT}_fw_config.dts \
- ${RDV1MC_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-$(eval $(call CREATE_SEQ,SEQ,4))
-ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
- $(error "Chip count for RD-V1-MC should be either $(SEQ) \
- currently it is set to ${NRD_CHIP_COUNT}.")
-endif
-
-FDT_SOURCES += ${RDV1MC_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-override CTX_INCLUDE_AARCH32_REGS := 0
-override ENABLE_FEAT_AMU := 2
-override SPMD_SPM_AT_SEL2 := 0
-
-# FEAT_SVE related flags
-override SVE_VECTOR_LEN := 256
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
- currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
-# Enable the flag since RD-V1-MC has a system level cache
-NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_err.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_err.c
deleted file mode 100644
index b855edd..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_err.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * rdv1mc error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
- while (true) {
- wfi();
- }
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
deleted file mode 100644
index 0a40762..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/gic600_multichip.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-
-#define RT_OWNER 0
-
-#if defined(IMAGE_BL31)
-static const mmap_region_t rdv1mc_dynamic_mmap[] = {
- NRD_CSS_SHARED_RAM_MMAP(1),
- NRD_CSS_PERIPH_MMAP(1),
- NRD_ROS_PERIPH_MMAP(1),
-#if (NRD_CHIP_COUNT > 2)
- NRD_CSS_SHARED_RAM_MMAP(2),
- NRD_CSS_PERIPH_MMAP(2),
- NRD_ROS_PERIPH_MMAP(2),
-#endif
-#if (NRD_CHIP_COUNT > 3)
- NRD_CSS_SHARED_RAM_MMAP(3),
- NRD_CSS_PERIPH_MMAP(3),
- NRD_ROS_PERIPH_MMAP(3)
-#endif
-};
-
-static struct gic600_multichip_data rdv1mc_multichip_data __init = {
- .base_addrs = {
- PLAT_ARM_GICD_BASE
- },
- .rt_owner = RT_OWNER,
- .chip_count = NRD_CHIP_COUNT,
- .chip_addrs = {
- [RT_OWNER] = {
- PLAT_ARM_GICD_BASE >> 16,
- (PLAT_ARM_GICD_BASE
- + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
-#if (NRD_CHIP_COUNT > 2)
- (PLAT_ARM_GICD_BASE
- + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
-#endif
-#if (NRD_CHIP_COUNT > 3)
- (PLAT_ARM_GICD_BASE
- + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
-#endif
- }
- },
- .spi_ids = {
- {PLAT_ARM_GICD_BASE,
- NRD_CHIP0_SPI_MIN,
- NRD_CHIP0_SPI_MAX},
- {0, 0, 0},
-#if (NRD_CHIP_COUNT > 2)
- {0, 0, 0},
-#endif
-#if (NRD_CHIP_COUNT > 3)
- {0, 0, 0},
-#endif
- }
-};
-
-static uintptr_t rdv1mc_multichip_gicr_frames[] = {
- /* Chip 0's GICR Base */
- PLAT_ARM_GICR_BASE,
- /* Chip 1's GICR BASE */
- PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
-#if (NRD_CHIP_COUNT > 2)
- /* Chip 2's GICR BASE */
- PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
-#endif
-#if (NRD_CHIP_COUNT > 3)
- /* Chip 3's GICR BASE */
- PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
-#endif
- UL(0) /* Zero Termination */
-};
-#endif /* IMAGE_BL31 */
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
- & SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
- return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
- SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
-}
-
-/*
- * bl31_platform_setup_function is guarded by IMAGE_BL31 macro because
- * PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
- * for other stages.
- */
-#if defined(IMAGE_BL31)
-void bl31_platform_setup(void)
-{
- int ret;
- unsigned int i;
-
- if ((plat_arm_nrd_get_multi_chip_mode() == 0) &&
- (NRD_CHIP_COUNT > 1)) {
- ERROR("Chip Count is %u but multi-chip mode is not enabled\n",
- NRD_CHIP_COUNT);
- panic();
- } else if ((plat_arm_nrd_get_multi_chip_mode() == 1) &&
- (NRD_CHIP_COUNT > 1)) {
- INFO("Enabling support for multi-chip in RD-V1-MC\n");
-
- for (i = 0; i < ARRAY_SIZE(rdv1mc_dynamic_mmap); i++) {
- ret = mmap_add_dynamic_region(
- rdv1mc_dynamic_mmap[i].base_pa,
- rdv1mc_dynamic_mmap[i].base_va,
- rdv1mc_dynamic_mmap[i].size,
- rdv1mc_dynamic_mmap[i].attr);
- if (ret != 0) {
- ERROR("Failed to add dynamic mmap entry "
- "(ret=%d)\n", ret);
- panic();
- }
- }
-
- plat_arm_override_gicr_frames(
- rdv1mc_multichip_gicr_frames);
- gic600_multichip_init(&rdv1mc_multichip_data);
- }
-
- nrd_bl31_common_platform_setup();
-}
-#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
deleted file mode 100644
index 1e59831..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <plat/arm/common/plat_arm.h>
-#include <platform_def.h>
-
-/* TZC memory regions for the first chip */
-static const arm_tzc_regions_info_t tzc_regions[] = {
- ARM_TZC_REGIONS_DEF,
- {}
-};
-
-#if NRD_CHIP_COUNT > 1
-static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
- {
- /* TZC memory regions for second chip */
- NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(1),
- {}
- },
-#if NRD_CHIP_COUNT > 2
- {
- /* TZC memory regions for third chip */
- NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(2),
- {}
- },
-#endif
-#if NRD_CHIP_COUNT > 3
- {
- /* TZC memory regions for fourth chip */
- NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(3),
- {}
- },
-#endif
-};
-#endif /* NRD_CHIP_COUNT */
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
- unsigned int i;
-
- INFO("Configuring TrustZone Controller for Chip 0\n");
-
- for (i = 0; i < TZC400_COUNT; i++) {
- arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
- }
-
-#if NRD_CHIP_COUNT > 1
- unsigned int j;
-
- for (i = 1; i < NRD_CHIP_COUNT; i++) {
- INFO("Configuring TrustZone Controller for Chip %u\n", i);
-
- for (j = 0; j < TZC400_COUNT; j++) {
- arm_tzc400_setup(NRD_REMOTE_CHIP_MEM_OFFSET(i)
- + TZC400_BASE(j), tzc_regions_mc[i-1]);
- }
- }
-#endif
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
deleted file mode 100644
index 52514ca..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-#include <nrd_variant.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-const unsigned char rd_v1_mc_pd_tree_desc_multi_chip[] = {
- ((PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT)),
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
-#if (NRD_CHIP_COUNT > 1)
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
-#endif
-#if (NRD_CHIP_COUNT > 2)
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
-#endif
-#if (NRD_CHIP_COUNT > 3)
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER
-#endif
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- if (plat_arm_nrd_get_multi_chip_mode() == 1)
- return rd_v1_mc_pd_tree_desc_multi_chip;
- panic();
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
-#if (NRD_CHIP_COUNT > 1)
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
-#endif
-#if (NRD_CHIP_COUNT > 2)
- (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
-#endif
-#if (NRD_CHIP_COUNT > 3)
- (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3))
-#endif
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_trusted_boot.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier ::= SEQUENCE {
- * algorithm OBJECT IDENTIFIER,
- * parameters ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- * digestAlgorithm AlgorithmIdentifier,
- * digest OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
- unsigned int *flags)
-{
- return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}