b19ac616b629aff017ba00789bbcaa12f57598f8 - filogic/atf

commit	b19ac616b629aff017ba00789bbcaa12f57598f8	[log] [tgz]
author	Boon Khai Ng <boon.khai.ng@intel.com>	Fri Aug 06 01:16:46 2021 +0800
committer	Sieu Mun Tang <sieu.mun.tang@intel.com>	Tue Apr 05 14:25:30 2022 +0800
tree	5311083dbcc6709ab4af99452e354fc1a29fbb07
parent	a34b881c2e51a1bb9f0781ae3728bacf3350ed09 [diff]

feat(intel): add macro to switch between different UART PORT

HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using parameter PLAT_INTEL_UART_BASE

This patch also fixing the plat_helpers.S where the
UART BASE is hardcoded to PLAT_UART0_BASE. It is then
switched to CRASH_CONSOLE_BASE.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Change-Id: Iccfa7ec64e4955b531905778be4da803045d3c8f

plat/intel/soc/agilex/bl2_plat_setup.c[diff]
plat/intel/soc/agilex/bl31_plat_setup.c[diff]
plat/intel/soc/common/aarch64/plat_helpers.S[diff]
plat/intel/soc/common/include/platform_def.h[diff]
plat/intel/soc/n5x/bl31_plat_setup.c[diff]
plat/intel/soc/stratix10/bl2_plat_setup.c[diff]
plat/intel/soc/stratix10/bl31_plat_setup.c[diff]

7 files changed

tree: 5311083dbcc6709ab4af99452e354fc1a29fbb07