tree 32013e3827a7b15c48b91c2c40089676f58dd2b5
parent e60f1bfe77105f243af3d5afe73576c7e5addd0f
author Varun Wadekar <vwadekar@nvidia.com> 1455750469 -0800
committer Varun Wadekar <vwadekar@nvidia.com> 1490026491 -0700

Tegra: memctrl_v2: implement MC txn override WAR

This patch sets the Memory Controller's TXN_OVERRIDE registers
for most write clients to CGID_ADR. This ensures ordering is maintained.
In some cases WAW ordering problems could occur. There are different
settings for Tegra version A01 v A02.

Original changes by Alex Waterman <alexw@nvidia.com>

Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>