diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S
index b3f5979..4050678 100644
--- a/bl31/aarch64/crash_reporting.S
+++ b/bl31/aarch64/crash_reporting.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,10 +45,14 @@
 		"spsr_irq", "spsr_fiq", "sctlr_el1", "actlr_el1", "cpacr_el1",\
 		"csselr_el1", "sp_el1", "esr_el1", "ttbr0_el1", "ttbr1_el1",\
 		"mair_el1", "amair_el1", "tcr_el1", "tpidr_el1", "tpidr_el0",\
-		"tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\
-		"mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\
-		"vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\
-		"cntv_cval_el0", "cntkctl_el1", "sp_el0", "isr_el1", ""
+		"tpidrro_el0",  "par_el1", "mpidr_el1", "afsr0_el1", "afsr1_el1",\
+		"contextidr_el1", "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0",\
+		"cntv_ctl_el0", "cntv_cval_el0", "cntkctl_el1", "sp_el0", "isr_el1", ""
+
+#if CTX_INCLUDE_AARCH32_REGS
+aarch32_regs:
+	.asciz	"dacr32_el2", "ifsr32_el2", ""
+#endif /* CTX_INCLUDE_AARCH32_REGS */
 
 panic_msg:
 	.asciz "PANIC in EL3 at x30 = 0x"
@@ -299,24 +303,30 @@
 	mrs	x9, tpidr_el1
 	mrs	x10, tpidr_el0
 	mrs	x11, tpidrro_el0
-	mrs	x12, dacr32_el2
-	mrs	x13, ifsr32_el2
-	mrs	x14, par_el1
-	mrs	x15, mpidr_el1
+	mrs	x12, par_el1
+	mrs	x13, mpidr_el1
+	mrs	x14, afsr0_el1
+	mrs	x15, afsr1_el1
 	bl	str_in_crash_buf_print
-	mrs	x8, afsr0_el1
-	mrs	x9, afsr1_el1
-	mrs	x10, contextidr_el1
-	mrs	x11, vbar_el1
-	mrs	x12, cntp_ctl_el0
-	mrs	x13, cntp_cval_el0
-	mrs	x14, cntv_ctl_el0
-	mrs	x15, cntv_cval_el0
+	mrs	x8, contextidr_el1
+	mrs	x9, vbar_el1
+	mrs	x10, cntp_ctl_el0
+	mrs	x11, cntp_cval_el0
+	mrs	x12, cntv_ctl_el0
+	mrs	x13, cntv_cval_el0
+	mrs	x14, cntkctl_el1
+	mrs	x15, sp_el0
 	bl	str_in_crash_buf_print
-	mrs	x8, cntkctl_el1
-	mrs	x9, sp_el0
-	mrs	x10, isr_el1
+	mrs	x8, isr_el1
+	bl	str_in_crash_buf_print
+
+#if CTX_INCLUDE_AARCH32_REGS
+	/* Print the AArch32 registers */
+	adr	x6, aarch32_regs
+	mrs	x8, dacr32_el2
+	mrs	x9, ifsr32_el2
 	bl	str_in_crash_buf_print
+#endif /* CTX_INCLUDE_AARCH32_REGS */
 
 	/* Get the cpu specific registers to report */
 	bl	do_cpu_reg_dump
diff --git a/common/desc_image_load.c b/common/desc_image_load.c
index 405bb83..f2e8f60 100644
--- a/common/desc_image_load.c
+++ b/common/desc_image_load.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 #include <arch_helpers.h>
 #include <common/bl_common.h>
 #include <common/desc_image_load.h>
+#include <common/tbbr/tbbr_img_def.h>
 
 static bl_load_info_t bl_load_info;
 static bl_params_t next_bl_params;
@@ -275,3 +276,47 @@
 		}
 	}
 }
+
+/*******************************************************************************
+ * Helper to extract BL32/BL33 entry point info from arg0 passed to BL31, for
+ * platforms that are only interested in those. Platforms that need to extract
+ * more information can parse the structures themselves.
+ ******************************************************************************/
+
+void bl31_params_parse_helper(u_register_t param,
+			      entry_point_info_t *bl32_ep_info_out,
+			      entry_point_info_t *bl33_ep_info_out)
+{
+	bl_params_node_t *node;
+	bl_params_t *v2 = (void *)(uintptr_t)param;
+
+#if !ERROR_DEPRECATED
+	if (v2->h.version == PARAM_VERSION_1) {
+		struct { /* Deprecated version 1 parameter structure. */
+			param_header_t h;
+			image_info_t *bl31_image_info;
+			entry_point_info_t *bl32_ep_info;
+			image_info_t *bl32_image_info;
+			entry_point_info_t *bl33_ep_info;
+			image_info_t *bl33_image_info;
+		} *v1 = (void *)(uintptr_t)param;
+		assert(v1->h.type == PARAM_BL31);
+		if (bl32_ep_info_out)
+			*bl32_ep_info_out = *v1->bl32_ep_info;
+		if (bl33_ep_info_out)
+			*bl33_ep_info_out = *v1->bl33_ep_info;
+		return;
+	}
+#endif /* !ERROR_DEPRECATED */
+
+	assert(v2->h.version == PARAM_VERSION_2);
+	assert(v2->h.type == PARAM_BL_PARAMS);
+	for (node = v2->head; node; node = node->next_params_info) {
+		if (node->image_id == BL32_IMAGE_ID)
+			if (bl32_ep_info_out)
+				*bl32_ep_info_out = *node->ep_info;
+		if (node->image_id == BL33_IMAGE_ID)
+			if (bl33_ep_info_out)
+				*bl33_ep_info_out = *node->ep_info;
+	}
+}
diff --git a/docs/plat/rockchip.rst b/docs/plat/rockchip.rst
index cee35e4..b7c43fb 100644
--- a/docs/plat/rockchip.rst
+++ b/docs/plat/rockchip.rst
@@ -5,6 +5,7 @@
 AARCH32 and AARCH64 fields.
 
 This includes right now:
+-  px30: Quad-Core Cortex-A53
 -  rk3288: Quad-Core Cortex-A17 (past A12)
 -  rk3328: Quad-Core Cortex-A53
 -  rk3368: Octa-Core Cortex-A53
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 9683964..fa857fb 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -219,6 +219,13 @@
 
 #define BTI_IMPLEMENTED		ULL(1)	/* The BTI mechanism is implemented */
 
+#define ID_AA64PFR1_EL1_MTE_SHIFT	U(8)
+#define ID_AA64PFR1_EL1_MTE_MASK	ULL(0xf)
+
+#define MTE_UNIMPLEMENTED	ULL(0)
+#define MTE_IMPLEMENTED_EL0	ULL(1)	/* MTE is only implemented at EL0 */
+#define MTE_IMPLEMENTED_ELX	ULL(2)	/* MTE is implemented at all ELs */
+
 /* ID_PFR1_EL1 definitions */
 #define ID_PFR1_VIRTEXT_SHIFT	U(12)
 #define ID_PFR1_VIRTEXT_MASK	U(0xf)
@@ -278,6 +285,7 @@
 
 /* SCR definitions */
 #define SCR_RES1_BITS		((U(1) << 4) | (U(1) << 5))
+#define SCR_ATA_BIT		(U(1) << 26)
 #define SCR_FIEN_BIT		(U(1) << 21)
 #define SCR_API_BIT		(U(1) << 17)
 #define SCR_APK_BIT		(U(1) << 16)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 1129b8e..2f29f48 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -54,4 +54,10 @@
 		ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
 }
 
+static inline unsigned int get_armv8_5_mte_support(void)
+{
+	return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
+		ID_AA64PFR1_EL1_MTE_MASK);
+}
+
 #endif /* ARCH_FEATURES_H */
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 457dc2a..eb96df0 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -11,6 +11,14 @@
 #include <common/param_header.h>
 #include <lib/utils_def.h>
 
+#ifndef __ASSEMBLY__
+#include <stddef.h>
+#include <stdint.h>
+#include <lib/cassert.h>
+#endif /* __ASSEMBLY__ */
+
+#include <export/common/bl_common_exp.h>
+
 #define UP	U(1)
 #define DOWN	U(0)
 
@@ -21,22 +29,6 @@
 #define TOP	U(0x1)
 #define BOTTOM	U(0x0)
 
-/*
- * The following are used for image state attributes.
- * Image can only be in one of the following state.
- */
-#define IMAGE_STATE_RESET		U(0)
-#define IMAGE_STATE_COPIED		U(1)
-#define IMAGE_STATE_COPYING		U(2)
-#define IMAGE_STATE_AUTHENTICATED	U(3)
-#define IMAGE_STATE_EXECUTED		U(4)
-#define IMAGE_STATE_INTERRUPTED		U(5)
-
-#define IMAGE_ATTRIB_SKIP_LOADING	U(0x02)
-#define IMAGE_ATTRIB_PLAT_SETUP		U(0x04)
-
-#define INVALID_IMAGE_ID		U(0xFFFFFFFF)
-
 /*******************************************************************************
  * Constants to indicate type of exception to the common exception handler.
  ******************************************************************************/
@@ -101,11 +93,6 @@
 
 #ifndef __ASSEMBLY__
 
-#include <stddef.h>
-#include <stdint.h>
-
-#include <lib/cassert.h>
-
 /*
  * Declarations of linker defined symbols to help determine memory layout of
  * BL images
@@ -165,66 +152,6 @@
 	size_t total_size;
 } meminfo_t;
 
-/*****************************************************************************
- * Image info binary provides information from the image loader that
- * can be used by the firmware to manage available trusted RAM.
- * More advanced firmware image formats can provide additional
- * information that enables optimization or greater flexibility in the
- * common firmware code
- *****************************************************************************/
-typedef struct image_info {
-	param_header_t h;
-	uintptr_t image_base;   /* physical address of base of image */
-	uint32_t image_size;    /* bytes read from image file */
-	uint32_t image_max_size;
-} image_info_t;
-
-/*****************************************************************************
- * The image descriptor struct definition.
- *****************************************************************************/
-typedef struct image_desc {
-	/* Contains unique image id for the image. */
-	unsigned int image_id;
-	/*
-	 * This member contains Image state information.
-	 * Refer IMAGE_STATE_XXX defined above.
-	 */
-	unsigned int state;
-	uint32_t copied_size;	/* image size copied in blocks */
-	image_info_t image_info;
-	entry_point_info_t ep_info;
-} image_desc_t;
-
-/* BL image node in the BL image loading sequence */
-typedef struct bl_load_info_node {
-	unsigned int image_id;
-	image_info_t *image_info;
-	struct bl_load_info_node *next_load_info;
-} bl_load_info_node_t;
-
-/* BL image head node in the BL image loading sequence */
-typedef struct bl_load_info {
-	param_header_t h;
-	bl_load_info_node_t *head;
-} bl_load_info_t;
-
-/* BL image node in the BL image execution sequence */
-typedef struct bl_params_node {
-	unsigned int image_id;
-	image_info_t *image_info;
-	entry_point_info_t *ep_info;
-	struct bl_params_node *next_params_info;
-} bl_params_node_t;
-
-/*
- * BL image head node in the BL image execution sequence
- * It is also used to pass information to next BL image.
- */
-typedef struct bl_params {
-	param_header_t h;
-	bl_params_node_t *head;
-} bl_params_t;
-
 /*******************************************************************************
  * Function & variable prototypes
  ******************************************************************************/
diff --git a/include/common/desc_image_load.h b/include/common/desc_image_load.h
index e46eb27..b044f3e 100644
--- a/include/common/desc_image_load.h
+++ b/include/common/desc_image_load.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -40,4 +40,9 @@
 bl_params_t *get_next_bl_params_from_mem_params_desc(void);
 void populate_next_bl_params_config(bl_params_t *bl2_to_next_bl_params);
 
+/* Helper to extract BL32/BL33 entry point info from arg0 passed to BL31. */
+void bl31_params_parse_helper(u_register_t param,
+			      entry_point_info_t *bl32_ep_info_out,
+			      entry_point_info_t *bl33_ep_info_out);
+
 #endif /* DESC_IMAGE_LOAD_H */
diff --git a/include/common/ep_info.h b/include/common/ep_info.h
index a09d03b..6cb903e 100644
--- a/include/common/ep_info.h
+++ b/include/common/ep_info.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,105 +8,30 @@
 #define EP_INFO_H
 
 #include <common/param_header.h>
-#include <lib/utils_def.h>
 
-#define SECURE		U(0x0)
-#define NON_SECURE	U(0x1)
+#ifndef __ASSEMBLY__
+#include <stdint.h>
+#include <lib/cassert.h>
+#endif /* __ASSEMBLY__ */
+
+#include <export/common/ep_info_exp.h>
+
+#define SECURE		EP_SECURE
+#define NON_SECURE	EP_NON_SECURE
 #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
 
-/*******************************************************************************
- * Constants that allow assembler code to access members of and the
- * 'entry_point_info' structure at their correct offsets.
- ******************************************************************************/
-#define ENTRY_POINT_INFO_PC_OFFSET	U(0x08)
-#ifdef AARCH32
-#define ENTRY_POINT_INFO_LR_SVC_OFFSET	U(0x10)
-#define ENTRY_POINT_INFO_ARGS_OFFSET	U(0x14)
-#else
-#define ENTRY_POINT_INFO_ARGS_OFFSET	U(0x18)
-#endif
+#define PARAM_EP_SECURITY_MASK	EP_SECURITY_MASK
 
-/* The following are used to set/get image attributes. */
-#define PARAM_EP_SECURITY_MASK		U(0x1)
+#define NON_EXECUTABLE	EP_NON_EXECUTABLE
+#define EXECUTABLE	EP_EXECUTABLE
 
 /* Secure or Non-secure image */
-#define GET_SECURITY_STATE(x) ((x) & PARAM_EP_SECURITY_MASK)
+#define GET_SECURITY_STATE(x) ((x) & EP_SECURITY_MASK)
 #define SET_SECURITY_STATE(x, security) \
-			((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security))
-
-/* Endianness of the image. */
-#define EP_EE_MASK		U(0x2)
-#define EP_EE_SHIFT		U(1)
-#define EP_EE_LITTLE		U(0x0)
-#define EP_EE_BIG		U(0x2)
-#define EP_GET_EE(x)		((x) & EP_EE_MASK)
-#define EP_SET_EE(x, ee)	((x) = ((x) & ~EP_EE_MASK) | (ee))
-
-/* Enable or disable access to the secure timer from secure images. */
-#define EP_ST_MASK		U(0x4)
-#define EP_ST_DISABLE		U(0x0)
-#define EP_ST_ENABLE		U(0x4)
-#define EP_GET_ST(x)		((x) & EP_ST_MASK)
-#define EP_SET_ST(x, ee)	((x) = ((x) & ~EP_ST_MASK) | (ee))
-
-/* Determine if an image is executable or not. */
-#define EP_EXE_MASK		U(0x8)
-#define NON_EXECUTABLE		U(0x0)
-#define EXECUTABLE		U(0x8)
-#define EP_GET_EXE(x)		((x) & EP_EXE_MASK)
-#define EP_SET_EXE(x, ee)	((x) = ((x) & ~EP_EXE_MASK) | (ee))
-
-/* Flag to indicate the first image that is executed. */
-#define EP_FIRST_EXE_MASK	U(0x10)
-#define EP_FIRST_EXE		U(0x10)
-#define EP_GET_FIRST_EXE(x)	((x) & EP_FIRST_EXE_MASK)
-#define EP_SET_FIRST_EXE(x, ee)	((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee))
+			((x) = ((x) & ~EP_SECURITY_MASK) | (security))
 
 #ifndef __ASSEMBLY__
 
-#include <stdint.h>
-
-#include <lib/cassert.h>
-
-typedef struct aapcs64_params {
-	u_register_t arg0;
-	u_register_t arg1;
-	u_register_t arg2;
-	u_register_t arg3;
-	u_register_t arg4;
-	u_register_t arg5;
-	u_register_t arg6;
-	u_register_t arg7;
-} aapcs64_params_t;
-
-typedef struct aapcs32_params {
-	u_register_t arg0;
-	u_register_t arg1;
-	u_register_t arg2;
-	u_register_t arg3;
-} aapcs32_params_t;
-
-/*****************************************************************************
- * This structure represents the superset of information needed while
- * switching exception levels. The only two mechanisms to do so are
- * ERET & SMC. Security state is indicated using bit zero of header
- * attribute
- * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
- * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
- * processing SMC to jump to BL31.
- *****************************************************************************/
-typedef struct entry_point_info {
-	param_header_t h;
-	uintptr_t pc;
-	uint32_t spsr;
-#ifdef AARCH32
-	uintptr_t lr_svc;
-	aapcs32_params_t args;
-#else
-	aapcs64_params_t args;
-#endif
-} entry_point_info_t;
-
 /*
  * Compile time assertions related to the 'entry_point_info' structure to
  * ensure that the assembler and the compiler view of the offsets of
diff --git a/include/common/param_header.h b/include/common/param_header.h
index 0c1503f..b885286 100644
--- a/include/common/param_header.h
+++ b/include/common/param_header.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,20 +9,14 @@
 
 #include <stdbool.h>
 
-#include <lib/utils_def.h>
+#ifndef __ASSEMBLY__
+#include <stdint.h>
+#endif /*__ASSEMBLY__*/
 
-/* Param header types */
-#define PARAM_EP			U(0x01)
-#define PARAM_IMAGE_BINARY		U(0x02)
-#define PARAM_BL31			U(0x03)
-#define PARAM_BL_LOAD_INFO		U(0x04)
-#define PARAM_BL_PARAMS			U(0x05)
-#define PARAM_PSCI_LIB_ARGS		U(0x06)
-#define PARAM_SP_IMAGE_BOOT_INFO	U(0x07)
+#include <export/common/param_header_exp.h>
 
-/* Param header version */
-#define VERSION_1	U(0x01)
-#define VERSION_2	U(0x02)
+#define VERSION_1	PARAM_VERSION_1
+#define VERSION_2	PARAM_VERSION_2
 
 #define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
 	(_p)->h.type = (uint8_t)(_type); \
@@ -38,21 +32,4 @@
 	._p.h.size = (uint16_t)sizeof(_p_type), \
 	._p.h.attr = (uint32_t)(_attr)
 
-#ifndef __ASSEMBLY__
-
-#include <stdint.h>
-
-/***************************************************************************
- * This structure provides version information and the size of the
- * structure, attributes for the structure it represents
- ***************************************************************************/
-typedef struct param_header {
-	uint8_t type;		/* type of the structure */
-	uint8_t version;    /* version of this structure */
-	uint16_t size;      /* size of this structure in bytes */
-	uint32_t attr;      /* attributes: unused bits SBZ */
-} param_header_t;
-
-#endif /*__ASSEMBLY__*/
-
 #endif /* PARAM_HEADER_H */
diff --git a/include/common/tbbr/tbbr_img_def.h b/include/common/tbbr/tbbr_img_def.h
index 672886d..1701995 100644
--- a/include/common/tbbr/tbbr_img_def.h
+++ b/include/common/tbbr/tbbr_img_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,83 +7,6 @@
 #ifndef TBBR_IMG_DEF_H
 #define TBBR_IMG_DEF_H
 
-#include <lib/utils_def.h>
-
-/* Firmware Image Package */
-#define FIP_IMAGE_ID			U(0)
-
-/* Trusted Boot Firmware BL2 */
-#define BL2_IMAGE_ID			U(1)
-
-/* SCP Firmware SCP_BL2 */
-#define SCP_BL2_IMAGE_ID		U(2)
-
-/* EL3 Runtime Firmware BL31 */
-#define BL31_IMAGE_ID			U(3)
-
-/* Secure Payload BL32 (Trusted OS) */
-#define BL32_IMAGE_ID			U(4)
-
-/* Non-Trusted Firmware BL33 */
-#define BL33_IMAGE_ID			U(5)
-
-/* Certificates */
-#define TRUSTED_BOOT_FW_CERT_ID		U(6)
-#define TRUSTED_KEY_CERT_ID		U(7)
-
-#define SCP_FW_KEY_CERT_ID		U(8)
-#define SOC_FW_KEY_CERT_ID		U(9)
-#define TRUSTED_OS_FW_KEY_CERT_ID	U(10)
-#define NON_TRUSTED_FW_KEY_CERT_ID	U(11)
-
-#define SCP_FW_CONTENT_CERT_ID		U(12)
-#define SOC_FW_CONTENT_CERT_ID		U(13)
-#define TRUSTED_OS_FW_CONTENT_CERT_ID	U(14)
-#define NON_TRUSTED_FW_CONTENT_CERT_ID	U(15)
-
-/* Non-Trusted ROM Firmware NS_BL1U */
-#define NS_BL1U_IMAGE_ID		U(16)
-
-/* Trusted FWU Certificate */
-#define FWU_CERT_ID			U(17)
-
-/* Trusted FWU SCP Firmware SCP_BL2U */
-#define SCP_BL2U_IMAGE_ID		U(18)
-
-/* Trusted FWU Boot Firmware BL2U */
-#define BL2U_IMAGE_ID			U(19)
-
-/* Non-Trusted FWU Firmware NS_BL2U */
-#define NS_BL2U_IMAGE_ID		U(20)
-
-/* Secure Payload BL32_EXTRA1 (Trusted OS Extra1) */
-#define BL32_EXTRA1_IMAGE_ID		U(21)
-
-/* Secure Payload BL32_EXTRA2 (Trusted OS Extra2) */
-#define BL32_EXTRA2_IMAGE_ID		U(22)
-
-/* HW_CONFIG (e.g. Kernel DT) */
-#define HW_CONFIG_ID			U(23)
-
-/* TB_FW_CONFIG */
-#define TB_FW_CONFIG_ID			U(24)
-
-/* SOC_FW_CONFIG */
-#define SOC_FW_CONFIG_ID		U(25)
-
-/* TOS_FW_CONFIG */
-#define TOS_FW_CONFIG_ID		U(26)
-
-/* NT_FW_CONFIG */
-#define NT_FW_CONFIG_ID			U(27)
-
-/* GPT Partition */
-#define GPT_IMAGE_ID			U(28)
-
-/* Binary with STM32 header */
-#define STM32_IMAGE_ID			U(29)
-
-/* Define size of the array */
-#define MAX_NUMBER_IDS			U(30)
+#include <export/common/tbbr/tbbr_img_def_exp.h>
 
 #endif /* TBBR_IMG_DEF_H */
diff --git a/include/drivers/gpio.h b/include/drivers/gpio.h
index bef62f7..99c18a4 100644
--- a/include/drivers/gpio.h
+++ b/include/drivers/gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,15 +7,17 @@
 #ifndef GPIO_H
 #define GPIO_H
 
-#define GPIO_DIR_OUT		0
-#define GPIO_DIR_IN		1
+#include <export/drivers/gpio_exp.h>
 
-#define GPIO_LEVEL_LOW		0
-#define GPIO_LEVEL_HIGH		1
+#define GPIO_DIR_OUT		ARM_TF_GPIO_DIR_OUT
+#define GPIO_DIR_IN		ARM_TF_GPIO_DIR_IN
+
+#define GPIO_LEVEL_LOW		ARM_TF_GPIO_LEVEL_LOW
+#define GPIO_LEVEL_HIGH		ARM_TF_GPIO_LEVEL_HIGH
 
-#define GPIO_PULL_NONE		0
-#define GPIO_PULL_UP		1
-#define GPIO_PULL_DOWN		2
+#define GPIO_PULL_NONE		ARM_TF_GPIO_PULL_NONE
+#define GPIO_PULL_UP		ARM_TF_GPIO_PULL_UP
+#define GPIO_PULL_DOWN		ARM_TF_GPIO_PULL_DOWN
 
 typedef struct gpio_ops {
 	int (*get_direction)(int gpio);
diff --git a/include/export/README b/include/export/README
new file mode 100644
index 0000000..2de8d6b
--- /dev/null
+++ b/include/export/README
@@ -0,0 +1,33 @@
+All headers under include/export/ are export headers that are intended for
+inclusion in third-party code which needs to interact with TF-A data structures
+or interfaces. They must follow these special rules:
+
+- Header guards should start with ARM_TRUSTED_FIRMWARE_ to reduce clash risk.
+
+- All definitions should be sufficiently namespaced (e.g. with BL_ or TF_) to
+  make name clashes with third-party code unlikely.
+
+- They must not #include any headers except other export headers, and those
+  includes must use relative paths with "../double_quotes.h" notation.
+
+- They must not rely on any type definitions other that <stdint.h> types defined
+  in the ISO C standard (i.e. uint64_t is fine, but not u_register_t). They
+  should still not #include <stdint.h>. Instead, wrapper headers including
+  export headers need to ensure that they #include <stdint.h> earlier in their
+  include order.
+
+- They must not rely on any macro definitions other than those which are
+  pre-defined by all common compilers (e.g. __ASSEMBLER__ or __aarch64__).
+
+- They must only contain macro, type and structure definitions, no prototypes.
+
+- They should avoid using integer types with architecture-dependent widths
+  (e.g. long, uintptr_t, pointer types) where possible. (Some existing export
+  headers are violating this for now.)
+
+- Their names should always end in "_exp.h".
+
+- Normal TF-A code should never include export headers directly. Instead, it
+  should include a wrapper header that ensures the export header is included in
+  the right manner. (The wrapper header for include/export/x/y/z_exp.h should
+  normally be placed at include/x/y/z.h.)
diff --git a/include/export/common/bl_common_exp.h b/include/export/common/bl_common_exp.h
new file mode 100644
index 0000000..8f09017
--- /dev/null
+++ b/include/export/common/bl_common_exp.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_BL_COMMON_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_BL_COMMON_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "ep_info_exp.h"
+#include "tbbr/tbbr_img_def_exp.h"
+
+/*
+ * The following are used for image state attributes.
+ * Image can only be in one of the following state.
+ */
+#define IMAGE_STATE_RESET		U(0)
+#define IMAGE_STATE_COPIED		U(1)
+#define IMAGE_STATE_COPYING		U(2)
+#define IMAGE_STATE_AUTHENTICATED	U(3)
+#define IMAGE_STATE_EXECUTED		U(4)
+#define IMAGE_STATE_INTERRUPTED		U(5)
+
+#define IMAGE_ATTRIB_SKIP_LOADING	U(0x02)
+#define IMAGE_ATTRIB_PLAT_SETUP		U(0x04)
+
+#define INVALID_IMAGE_ID		U(0xFFFFFFFF)
+
+#ifndef __ASSEMBLER__
+
+/*****************************************************************************
+ * Image info binary provides information from the image loader that
+ * can be used by the firmware to manage available trusted RAM.
+ * More advanced firmware image formats can provide additional
+ * information that enables optimization or greater flexibility in the
+ * common firmware code
+ *****************************************************************************/
+typedef struct image_info {
+	param_header_t h;
+	uintptr_t image_base;   /* physical address of base of image */
+	uint32_t image_size;    /* bytes read from image file */
+	uint32_t image_max_size;
+} image_info_t;
+
+/* BL image node in the BL image execution sequence */
+typedef struct bl_params_node {
+	unsigned int image_id;
+	image_info_t *image_info;
+	entry_point_info_t *ep_info;
+	struct bl_params_node *next_params_info;
+} bl_params_node_t;
+
+/*
+ * BL image head node in the BL image execution sequence
+ * It is also used to pass information to next BL image.
+ */
+typedef struct bl_params {
+	param_header_t h;
+	bl_params_node_t *head;
+} bl_params_t;
+
+/*****************************************************************************
+ * The image descriptor struct definition.
+ *****************************************************************************/
+typedef struct image_desc {
+	/* Contains unique image id for the image. */
+	unsigned int image_id;
+	/*
+	 * This member contains Image state information.
+	 * Refer IMAGE_STATE_XXX defined above.
+	 */
+	unsigned int state;
+	uint32_t copied_size;	/* image size copied in blocks */
+	image_info_t image_info;
+	entry_point_info_t ep_info;
+} image_desc_t;
+
+/* BL image node in the BL image loading sequence */
+typedef struct bl_load_info_node {
+	unsigned int image_id;
+	image_info_t *image_info;
+	struct bl_load_info_node *next_load_info;
+} bl_load_info_node_t;
+
+/* BL image head node in the BL image loading sequence */
+typedef struct bl_load_info {
+	param_header_t h;
+	bl_load_info_node_t *head;
+} bl_load_info_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_BL_COMMON_EXP_H */
diff --git a/include/export/common/ep_info_exp.h b/include/export/common/ep_info_exp.h
new file mode 100644
index 0000000..4c703e6
--- /dev/null
+++ b/include/export/common/ep_info_exp.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../lib/utils_def_exp.h"
+#include "param_header_exp.h"
+
+/*******************************************************************************
+ * Constants that allow assembler code to access members of and the
+ * 'entry_point_info' structure at their correct offsets.
+ ******************************************************************************/
+#define ENTRY_POINT_INFO_PC_OFFSET	U(0x08)
+#ifdef __aarch64__
+#define ENTRY_POINT_INFO_ARGS_OFFSET	U(0x18)
+#else
+#define ENTRY_POINT_INFO_LR_SVC_OFFSET	U(0x10)
+#define ENTRY_POINT_INFO_ARGS_OFFSET	U(0x14)
+#endif
+
+/* Security state of the image. */
+#define EP_SECURITY_MASK	U(0x1)
+#define EP_SECURITY_SHIFT	U(0)
+#define EP_SECURE		U(0x0)
+#define EP_NON_SECURE		U(0x1)
+
+/* Endianness of the image. */
+#define EP_EE_MASK		U(0x2)
+#define EP_EE_SHIFT		U(1)
+#define EP_EE_LITTLE		U(0x0)
+#define EP_EE_BIG		U(0x2)
+#define EP_GET_EE(x)		((x) & EP_EE_MASK)
+#define EP_SET_EE(x, ee)	((x) = ((x) & ~EP_EE_MASK) | (ee))
+
+/* Enable or disable access to the secure timer from secure images. */
+#define EP_ST_MASK		U(0x4)
+#define EP_ST_SHIFT		U(2)
+#define EP_ST_DISABLE		U(0x0)
+#define EP_ST_ENABLE		U(0x4)
+#define EP_GET_ST(x)		((x) & EP_ST_MASK)
+#define EP_SET_ST(x, ee)	((x) = ((x) & ~EP_ST_MASK) | (ee))
+
+/* Determine if an image is executable or not. */
+#define EP_EXE_MASK		U(0x8)
+#define EP_EXE_SHIFT		U(3)
+#define EP_NON_EXECUTABLE	U(0x0)
+#define EP_EXECUTABLE		U(0x8)
+#define EP_GET_EXE(x)		((x) & EP_EXE_MASK)
+#define EP_SET_EXE(x, ee)	((x) = ((x) & ~EP_EXE_MASK) | (ee))
+
+/* Flag to indicate the first image that is executed. */
+#define EP_FIRST_EXE_MASK	U(0x10)
+#define EP_FIRST_EXE_SHIFT	U(4)
+#define EP_FIRST_EXE		U(0x10)
+#define EP_GET_FIRST_EXE(x)	((x) & EP_FIRST_EXE_MASK)
+#define EP_SET_FIRST_EXE(x, ee)	((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee))
+
+#ifndef __ASSEMBLER__
+
+typedef struct aapcs64_params {
+	uint64_t arg0;
+	uint64_t arg1;
+	uint64_t arg2;
+	uint64_t arg3;
+	uint64_t arg4;
+	uint64_t arg5;
+	uint64_t arg6;
+	uint64_t arg7;
+} aapcs64_params_t;
+
+typedef struct aapcs32_params {
+	uint32_t arg0;
+	uint32_t arg1;
+	uint32_t arg2;
+	uint32_t arg3;
+} aapcs32_params_t;
+
+/*****************************************************************************
+ * This structure represents the superset of information needed while
+ * switching exception levels. The only two mechanisms to do so are
+ * ERET & SMC. Security state is indicated using bit zero of header
+ * attribute
+ * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
+ * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
+ * processing SMC to jump to BL31.
+ *****************************************************************************/
+typedef struct entry_point_info {
+	param_header_t h;
+	uintptr_t pc;
+	uint32_t spsr;
+#ifdef __aarch64__
+	aapcs64_params_t args;
+#else
+	uintptr_t lr_svc;
+	aapcs32_params_t args;
+#endif
+} entry_point_info_t;
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H */
diff --git a/include/export/common/param_header_exp.h b/include/export/common/param_header_exp.h
new file mode 100644
index 0000000..15bb6f2
--- /dev/null
+++ b/include/export/common/param_header_exp.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_PARAM_HEADER_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_PARAM_HEADER_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../lib/utils_def_exp.h"
+
+/* Param header types */
+#define PARAM_EP			U(0x01)
+#define PARAM_IMAGE_BINARY		U(0x02)
+#define PARAM_BL31			U(0x03)
+#define PARAM_BL_LOAD_INFO		U(0x04)
+#define PARAM_BL_PARAMS			U(0x05)
+#define PARAM_PSCI_LIB_ARGS		U(0x06)
+#define PARAM_SP_IMAGE_BOOT_INFO	U(0x07)
+
+/* Param header version */
+#define PARAM_VERSION_1			U(0x01)
+#define PARAM_VERSION_2			U(0x02)
+
+#ifndef __ASSEMBLER__
+
+/***************************************************************************
+ * This structure provides version information and the size of the
+ * structure, attributes for the structure it represents
+ ***************************************************************************/
+typedef struct param_header {
+	uint8_t type;		/* type of the structure */
+	uint8_t version;	/* version of this structure */
+	uint16_t size;		/* size of this structure in bytes */
+	uint32_t attr;		/* attributes: unused bits SBZ */
+} param_header_t;
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_PARAM_HEADER_EXP_H */
diff --git a/include/export/common/tbbr/tbbr_img_def_exp.h b/include/export/common/tbbr/tbbr_img_def_exp.h
new file mode 100644
index 0000000..ff0d16c
--- /dev/null
+++ b/include/export/common/tbbr/tbbr_img_def_exp.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../../lib/utils_def_exp.h"
+
+/* Firmware Image Package */
+#define FIP_IMAGE_ID			U(0)
+
+/* Trusted Boot Firmware BL2 */
+#define BL2_IMAGE_ID			U(1)
+
+/* SCP Firmware SCP_BL2 */
+#define SCP_BL2_IMAGE_ID		U(2)
+
+/* EL3 Runtime Firmware BL31 */
+#define BL31_IMAGE_ID			U(3)
+
+/* Secure Payload BL32 (Trusted OS) */
+#define BL32_IMAGE_ID			U(4)
+
+/* Non-Trusted Firmware BL33 */
+#define BL33_IMAGE_ID			U(5)
+
+/* Certificates */
+#define TRUSTED_BOOT_FW_CERT_ID		U(6)
+#define TRUSTED_KEY_CERT_ID		U(7)
+
+#define SCP_FW_KEY_CERT_ID		U(8)
+#define SOC_FW_KEY_CERT_ID		U(9)
+#define TRUSTED_OS_FW_KEY_CERT_ID	U(10)
+#define NON_TRUSTED_FW_KEY_CERT_ID	U(11)
+
+#define SCP_FW_CONTENT_CERT_ID		U(12)
+#define SOC_FW_CONTENT_CERT_ID		U(13)
+#define TRUSTED_OS_FW_CONTENT_CERT_ID	U(14)
+#define NON_TRUSTED_FW_CONTENT_CERT_ID	U(15)
+
+/* Non-Trusted ROM Firmware NS_BL1U */
+#define NS_BL1U_IMAGE_ID		U(16)
+
+/* Trusted FWU Certificate */
+#define FWU_CERT_ID			U(17)
+
+/* Trusted FWU SCP Firmware SCP_BL2U */
+#define SCP_BL2U_IMAGE_ID		U(18)
+
+/* Trusted FWU Boot Firmware BL2U */
+#define BL2U_IMAGE_ID			U(19)
+
+/* Non-Trusted FWU Firmware NS_BL2U */
+#define NS_BL2U_IMAGE_ID		U(20)
+
+/* Secure Payload BL32_EXTRA1 (Trusted OS Extra1) */
+#define BL32_EXTRA1_IMAGE_ID		U(21)
+
+/* Secure Payload BL32_EXTRA2 (Trusted OS Extra2) */
+#define BL32_EXTRA2_IMAGE_ID		U(22)
+
+/* HW_CONFIG (e.g. Kernel DT) */
+#define HW_CONFIG_ID			U(23)
+
+/* TB_FW_CONFIG */
+#define TB_FW_CONFIG_ID			U(24)
+
+/* SOC_FW_CONFIG */
+#define SOC_FW_CONFIG_ID		U(25)
+
+/* TOS_FW_CONFIG */
+#define TOS_FW_CONFIG_ID		U(26)
+
+/* NT_FW_CONFIG */
+#define NT_FW_CONFIG_ID			U(27)
+
+/* GPT Partition */
+#define GPT_IMAGE_ID			U(28)
+
+/* Binary with STM32 header */
+#define STM32_IMAGE_ID			U(29)
+
+/* Define size of the array */
+#define MAX_NUMBER_IDS			U(30)
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H */
diff --git a/include/export/drivers/gpio_exp.h b/include/export/drivers/gpio_exp.h
new file mode 100644
index 0000000..a37f190
--- /dev/null
+++ b/include/export/drivers/gpio_exp.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_DRIVERS_GPIO_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_DRIVERS_GPIO_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#define ARM_TF_GPIO_DIR_OUT		0
+#define ARM_TF_GPIO_DIR_IN		1
+
+#define ARM_TF_GPIO_LEVEL_LOW		0
+#define ARM_TF_GPIO_LEVEL_HIGH		1
+
+#define ARM_TF_GPIO_PULL_NONE		0
+#define ARM_TF_GPIO_PULL_UP		1
+#define ARM_TF_GPIO_PULL_DOWN		2
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_DRIVERS_GPIO_EXP_H */
diff --git a/include/export/lib/bl_aux_params/bl_aux_params_exp.h b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
new file mode 100644
index 0000000..7391dec
--- /dev/null
+++ b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_LIB_BL_AUX_PARAMS_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_LIB_BL_AUX_PARAMS_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../../drivers/gpio_exp.h"
+
+/*
+ * This API implements a lightweight parameter passing mechanism that can be
+ * used to pass SoC Firmware configuration data from BL2 to BL31 by platforms or
+ * configurations that do not want to depend on libfdt. It is structured as a
+ * singly-linked list of parameter structures that all share the same common
+ * header but may have different (and differently-sized) structure bodies after
+ * that. The header contains a type field to indicate the parameter type (which
+ * is used to infer the structure length and how to interpret its contents) and
+ * a next pointer which contains the absolute physical address of the next
+ * parameter structure. The next pointer in the last structure block is set to
+ * NULL. The picture below shows how the parameters are kept in memory.
+ *
+ * head of list  ---> +----------------+ --+
+ *                    |      type      |   |
+ *                    +----------------+   |--> struct bl_aux_param
+ *               +----|      next      |   |
+ *               |    +----------------+ --+
+ *               |    | parameter data |
+ *               |    +----------------+
+ *               |
+ *               +--> +----------------+ --+
+ *                    |      type      |   |
+ *                    +----------------+   |--> struct bl_aux_param
+ *           NULL <---|      next      |   |
+ *                    +----------------+ --+
+ *                    | parameter data |
+ *                    +----------------+
+ *
+ * Note: The SCTLR_EL3.A bit (Alignment fault check enable) is set in TF-A, so
+ * BL2 must ensure that each parameter struct starts on a 64-bit aligned address
+ * to avoid alignment faults. Parameters may be allocated in any address range
+ * accessible at the time of BL31 handoff (e.g. SRAM, DRAM, SoC-internal scratch
+ * registers, etc.), in particular address ranges that may not be mapped in
+ * BL31's page tables, so the parameter list must be parsed before the MMU is
+ * enabled and any information that is required at a later point should be
+ * deep-copied out into BL31-internal data structures.
+ */
+
+enum bl_aux_param_type {
+	BL_AUX_PARAM_NONE = 0,
+	BL_AUX_PARAM_VENDOR_SPECIFIC_FIRST = 0x1,
+	/* 0x1 - 0x7fffffff can be used by vendor-specific handlers. */
+	BL_AUX_PARAM_VENDOR_SPECIFIC_LAST = 0x7fffffff,
+	BL_AUX_PARAM_GENERIC_FIRST = 0x80000001,
+	BL_AUX_PARAM_COREBOOT_TABLE = BL_AUX_PARAM_GENERIC_FIRST,
+	/* 0x80000001 - 0xffffffff are reserved for the generic handler. */
+	BL_AUX_PARAM_GENERIC_LAST = 0xffffffff,
+	/* Top 32 bits of the type field are reserved for future use. */
+};
+
+/* common header for all BL aux parameters */
+struct bl_aux_param_header {
+	uint64_t type;
+	uint64_t next;
+};
+
+/* commonly useful parameter structures that can be shared by multiple types */
+struct bl_aux_param_uint64 {
+	struct bl_aux_param_header h;
+	uint64_t value;
+};
+
+struct bl_aux_gpio_info {
+	uint8_t polarity;
+	uint8_t direction;
+	uint8_t pull_mode;
+	uint8_t reserved;
+	uint32_t index;
+};
+
+struct bl_aux_param_gpio {
+	struct bl_aux_param_header h;
+	struct bl_aux_gpio_info gpio;
+};
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_LIB_BL_AUX_PARAMS_EXP_H */
diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h
new file mode 100644
index 0000000..86c409c
--- /dev/null
+++ b/include/export/lib/utils_def_exp.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H
+#define	ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+/*
+ * For those constants to be shared between C and other sources, apply a 'U',
+ * 'UL', 'ULL', 'L' or 'LL' suffix to the argument only in C, to avoid
+ * undefined or unintended behaviour.
+ *
+ * The GNU assembler and linker do not support these suffixes (it causes the
+ * build process to fail) therefore the suffix is omitted when used in linker
+ * scripts and assembler files.
+*/
+#if defined(__ASSEMBLER__)
+# define   U(_x)	(_x)
+# define  UL(_x)	(_x)
+# define ULL(_x)	(_x)
+# define   L(_x)	(_x)
+# define  LL(_x)	(_x)
+#else
+# define   U(_x)	(_x##U)
+# define  UL(_x)	(_x##UL)
+# define ULL(_x)	(_x##ULL)
+# define   L(_x)	(_x##L)
+# define  LL(_x)	(_x##LL)
+#endif
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H */
diff --git a/include/export/plat/rockchip/common/plat_params_exp.h b/include/export/plat/rockchip/common/plat_params_exp.h
new file mode 100644
index 0000000..ccc9cd9
--- /dev/null
+++ b/include/export/plat/rockchip/common/plat_params_exp.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_ROCKCHIP_COMMON_PLAT_PARAMS_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_ROCKCHIP_COMMON_PLAT_PARAMS_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../../../lib/bl_aux_params/bl_aux_params_exp.h"
+
+/* param type */
+enum bl_aux_rk_param_type {
+	BL_AUX_PARAM_RK_RESET_GPIO = BL_AUX_PARAM_VENDOR_SPECIFIC_FIRST,
+	BL_AUX_PARAM_RK_POWEROFF_GPIO,
+	BL_AUX_PARAM_RK_SUSPEND_GPIO,
+	BL_AUX_PARAM_RK_SUSPEND_APIO,
+};
+
+struct bl_aux_rk_apio_info {
+	uint8_t apio1 : 1;
+	uint8_t apio2 : 1;
+	uint8_t apio3 : 1;
+	uint8_t apio4 : 1;
+	uint8_t apio5 : 1;
+};
+
+struct bl_aux_param_rk_apio {
+	struct bl_aux_param_header h;
+	struct bl_aux_rk_apio_info apio;
+};
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_ROCKCHIP_COMMON_PLAT_PARAMS_EXP_H */
diff --git a/include/lib/bl_aux_params/bl_aux_params.h b/include/lib/bl_aux_params/bl_aux_params.h
new file mode 100644
index 0000000..f6ce802
--- /dev/null
+++ b/include/lib/bl_aux_params/bl_aux_params.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef LIB_BL_AUX_PARAMS_H
+#define LIB_BL_AUX_PARAMS_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <export/lib/bl_aux_params/bl_aux_params_exp.h>
+
+/*
+ * Handler function that handles an individual aux parameter. Return true if
+ * the parameter was handled, and flase if bl_aux_params_parse() should make its
+ * own attempt at handling it (for generic parameters).
+ */
+typedef bool (*bl_aux_param_handler_t)(struct bl_aux_param_header *param);
+
+/*
+ * Interprets head as the start of an aux parameter list, and passes the
+ * parameters individually to handler(). Handles generic parameters directly if
+ * handler() hasn't already done so. If only generic parameters are expected,
+ * handler() can be NULL.
+ */
+void bl_aux_params_parse(u_register_t head,
+			 bl_aux_param_handler_t handler);
+
+#endif /* LIB_BL_AUX_PARAMS_H */
diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_hercules.h
new file mode 100644
index 0000000..86e8af0
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_hercules.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_HERCULES_H
+#define CORTEX_HERCULES_H
+
+#include <lib/utils_def.h>
+
+#define CORTEX_HERCULES_MIDR					U(0x410FD410)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_HERCULES_CPUECTLR_EL1				S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_HERCULES_CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT	U(1)
+
+#endif /* CORTEX_HERCULES_H */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 2b48967..41f71e8 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,6 +7,8 @@
 #ifndef UTILS_DEF_H
 #define UTILS_DEF_H
 
+#include <export/lib/utils_def_exp.h>
+
 /* Compute the number of elements in the given array */
 #define ARRAY_SIZE(a)				\
 	(sizeof(a) / sizeof((a)[0]))
@@ -106,29 +108,6 @@
 #define check_u32_overflow(_u32, _inc) \
 	((_u32) > (UINT32_MAX - (_inc)))
 
-/*
- * For those constants to be shared between C and other sources, apply a 'U',
- * 'UL', 'ULL', 'L' or 'LL' suffix to the argument only in C, to avoid
- * undefined or unintended behaviour.
- *
- * The GNU assembler and linker do not support these suffixes (it causes the
- * build process to fail) therefore the suffix is omitted when used in linker
- * scripts and assembler files.
-*/
-#if defined(__LINKER__) || defined(__ASSEMBLY__)
-# define   U(_x)	(_x)
-# define  UL(_x)	(_x)
-# define ULL(_x)	(_x)
-# define   L(_x)	(_x)
-# define  LL(_x)	(_x)
-#else
-# define   U(_x)	(_x##U)
-# define  UL(_x)	(_x##UL)
-# define ULL(_x)	(_x##ULL)
-# define   L(_x)	(_x##L)
-# define  LL(_x)	(_x##LL)
-#endif
-
 /* Register size of the current architecture. */
 #ifdef AARCH32
 #define REGSZ		U(4)
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 97e6722..c8260e8 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -252,7 +252,7 @@
 void plat_arm_interconnect_exit_coherency(void);
 void plat_arm_program_trusted_mailbox(uintptr_t address);
 int plat_arm_bl1_fwu_needed(void);
-void plat_arm_error_handler(int err);
+__dead2 void plat_arm_error_handler(int err);
 
 #if ARM_PLAT_MT
 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
diff --git a/lib/bl_aux_params/bl_aux_params.c b/lib/bl_aux_params/bl_aux_params.c
new file mode 100644
index 0000000..7a8115c
--- /dev/null
+++ b/lib/bl_aux_params/bl_aux_params.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/coreboot.h>
+#include <lib/bl_aux_params/bl_aux_params.h>
+
+void bl_aux_params_parse(u_register_t head,
+			 bl_aux_param_handler_t handler)
+{
+	struct bl_aux_param_header *p;
+
+	for (p = (void *)head; p; p = (void *)(uintptr_t)p->next) {
+		if (handler && handler(p))
+			continue;
+
+		switch (p->type) {
+#if COREBOOT
+		case BL_AUX_PARAM_COREBOOT_TABLE:
+			coreboot_table_setup((void *)(uintptr_t)
+				((struct bl_aux_param_uint64 *)p)->value);
+			break;
+#endif
+		default:
+			ERROR("Ignoring unknown BL aux parameter: 0x%llx",
+			      p->type);
+			break;
+		}
+	}
+}
diff --git a/lib/cpus/aarch64/cortex_hercules.S b/lib/cpus/aarch64/cortex_hercules.S
new file mode 100644
index 0000000..25287de
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_hercules.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_hercules.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+	/* ---------------------------------------------
+	 * HW will do the cache maintenance while powering down
+	 * ---------------------------------------------
+	 */
+func cortex_hercules_core_pwr_dwn
+	/* ---------------------------------------------
+	 * Enable CPU power down bit in power control register
+	 * ---------------------------------------------
+	 */
+	mrs	x0, CORTEX_HERCULES_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+	msr	CORTEX_HERCULES_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_hercules_core_pwr_dwn
+
+	/*
+	 * Errata printing function for cortex_hercules. Must follow AAPCS.
+	 */
+#if REPORT_ERRATA
+func cortex_hercules_errata_report
+	ret
+endfunc cortex_hercules_errata_report
+#endif
+
+	/* ---------------------------------------------
+	 * This function provides cortex_hercules specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.cortex_hercules_regs, "aS"
+cortex_hercules_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_hercules_cpu_reg_dump
+	adr	x6, cortex_hercules_regs
+	mrs	x8, CORTEX_HERCULES_CPUECTLR_EL1
+	ret
+endfunc cortex_hercules_cpu_reg_dump
+
+declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
+	CPU_NO_RESET_FUNC, \
+	cortex_hercules_core_pwr_dwn
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 89d7ed6..05ba5ed 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -12,6 +12,7 @@
 
 #include <arch.h>
 #include <arch_helpers.h>
+#include <arch_features.h>
 #include <bl31/interrupt_mgmt.h>
 #include <common/bl_common.h>
 #include <context.h>
@@ -136,6 +137,18 @@
 		scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
 #endif /* !CTX_INCLUDE_PAUTH_REGS */
 
+	unsigned int mte = get_armv8_5_mte_support();
+
+	/*
+	 * Enable MTE support unilaterally for normal world if the CPU supports
+	 * it.
+	 */
+	if (mte != MTE_UNIMPLEMENTED) {
+		if (security_state == NON_SECURE) {
+			scr_el3 |= SCR_ATA_BIT;
+		}
+	}
+
 #ifdef IMAGE_BL31
 	/*
 	 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
diff --git a/plat/arm/board/a5ds/a5ds_err.c b/plat/arm/board/a5ds/a5ds_err.c
new file mode 100644
index 0000000..65b41dd
--- /dev/null
+++ b/plat/arm/board/a5ds/a5ds_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * a5ds error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+	while (1) {
+		wfi();
+	}
+}
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 4fd357b..d42b2bf 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -36,6 +36,7 @@
 				drivers/cfi/v2m/v2m_flash.c			\
 				plat/arm/common/arm_bl1_setup.c			\
 				plat/arm/common/arm_err.c			\
+				plat/arm/board/a5ds/a5ds_err.c			\
 				plat/arm/common/arm_io_storage.c		\
 				plat/arm/board/a5ds/${ARCH}/a5ds_helpers.S	\
 				plat/arm/board/a5ds/a5ds_bl1_setup.c		\
@@ -55,6 +56,7 @@
 				plat/arm/board/a5ds/a5ds_bl2_setup.c		\
 				plat/arm/common/arm_bl2_setup.c			\
 				plat/arm/common/arm_err.c			\
+				plat/arm/board/a5ds/a5ds_err.c			\
 				plat/arm/common/arm_io_storage.c		\
 				plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c	\
 				plat/arm/common/arm_image_load.c		\
diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c
index 420df45..b90ddcd 100644
--- a/plat/arm/board/fvp/fvp_bl1_setup.c
+++ b/plat/arm/board/fvp/fvp_bl1_setup.c
@@ -52,3 +52,12 @@
 	if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
 		smmuv3_security_init(PLAT_FVP_SMMUV3_BASE);
 }
+
+__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
+{
+	/* Setup the watchdog to reset the system as soon as possible */
+	sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
+
+	while (1)
+		wfi();
+}
diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c
new file mode 100644
index 0000000..2437cd4
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_err.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/arm/sp805.h>
+#include <drivers/cfi/v2m_flash.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+/*
+ * FVP error handler
+ */
+__dead2 void plat_arm_error_handler(int err)
+{
+	int ret;
+
+	switch (err) {
+	case -ENOENT:
+	case -EAUTH:
+		/* Image load or authentication error. Erase the ToC */
+		INFO("Erasing FIP ToC from flash...\n");
+		(void)nor_unlock(PLAT_ARM_FIP_BASE);
+		ret = nor_word_program(PLAT_ARM_FIP_BASE, 0);
+		if (ret != 0) {
+			ERROR("Cannot erase ToC\n");
+		} else {
+			INFO("Done\n");
+		}
+		break;
+	default:
+		/* Unexpected error */
+		break;
+	}
+
+	(void)console_flush();
+
+	/* Setup the watchdog to reset the system as soon as possible */
+	sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
+
+	for (;;)
+		wfi();
+}
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index bd6812b..0eb62c4 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -112,7 +112,8 @@
 					lib/cpus/aarch64/cortex_a77.S		\
 					lib/cpus/aarch64/neoverse_n1.S		\
 					lib/cpus/aarch64/neoverse_e1.S		\
-					lib/cpus/aarch64/neoverse_zeus.S
+					lib/cpus/aarch64/neoverse_zeus.S	\
+					lib/cpus/aarch64/cortex_hercules.S
 	# AArch64/AArch32
 	else
 		FVP_CPU_LIBS	+=	lib/cpus/aarch64/cortex_a55.S		\
@@ -131,17 +132,20 @@
 				lib/semihosting/${ARCH}/semihosting_call.S	\
 				plat/arm/board/fvp/${ARCH}/fvp_helpers.S	\
 				plat/arm/board/fvp/fvp_bl1_setup.c		\
+				plat/arm/board/fvp/fvp_err.c			\
 				plat/arm/board/fvp/fvp_io_storage.c		\
 				plat/arm/board/fvp/fvp_trusted_boot.c		\
 				${FVP_CPU_LIBS}					\
 				${FVP_INTERCONNECT_SOURCES}
 
 
-BL2_SOURCES		+=	drivers/io/io_semihosting.c			\
+BL2_SOURCES		+=	drivers/arm/sp805/sp805.c			\
+				drivers/io/io_semihosting.c			\
 				lib/utils/mem_region.c				\
 				lib/semihosting/semihosting.c			\
 				lib/semihosting/${ARCH}/semihosting_call.S	\
 				plat/arm/board/fvp/fvp_bl2_setup.c		\
+				plat/arm/board/fvp/fvp_err.c			\
 				plat/arm/board/fvp/fvp_io_storage.c		\
 				plat/arm/board/fvp/fvp_trusted_boot.c		\
 				plat/arm/common/arm_nor_psci_mem_protect.c	\
diff --git a/plat/arm/board/fvp_ve/fvp_ve_err.c b/plat/arm/board/fvp_ve/fvp_ve_err.c
new file mode 100644
index 0000000..7f9d2f7
--- /dev/null
+++ b/plat/arm/board/fvp_ve/fvp_ve_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * FVP VE error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+	while (1) {
+		wfi();
+	}
+}
diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk
index f85452d..4d21f4b 100644
--- a/plat/arm/board/fvp_ve/platform.mk
+++ b/plat/arm/board/fvp_ve/platform.mk
@@ -40,6 +40,7 @@
 				drivers/io/io_storage.c				\
 				plat/arm/common/arm_bl1_setup.c			\
 				plat/arm/common/arm_err.c			\
+				plat/arm/board/fvp_ve/fvp_ve_err.c		\
 				plat/arm/common/arm_io_storage.c		\
 				drivers/cfi/v2m/v2m_flash.c			\
 				plat/arm/board/fvp_ve/${ARCH}/fvp_ve_helpers.S	\
@@ -60,6 +61,7 @@
 				drivers/io/io_storage.c				\
 				plat/arm/common/arm_bl2_setup.c			\
 				plat/arm/common/arm_err.c			\
+				plat/arm/board/fvp_ve/fvp_ve_err.c		\
 				plat/arm/common/arm_io_storage.c		\
 				plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c	\
 				plat/arm/common/arm_image_load.c		\
diff --git a/plat/arm/board/juno/juno_bl1_setup.c b/plat/arm/board/juno/juno_bl1_setup.c
index 7a3d22d..89398d6 100644
--- a/plat/arm/board/juno/juno_bl1_setup.c
+++ b/plat/arm/board/juno/juno_bl1_setup.c
@@ -98,6 +98,9 @@
 	/* Clear the NV flags register. */
 	*nv_flags_clr = *nv_flags_ptr;
 
+	/* Setup the watchdog to reset the system as soon as possible */
+	sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
+
 	while (1)
 		wfi();
 }
diff --git a/plat/arm/board/juno/juno_err.c b/plat/arm/board/juno/juno_err.c
index 700b96c..961bfda 100644
--- a/plat/arm/board/juno/juno_err.c
+++ b/plat/arm/board/juno/juno_err.c
@@ -7,6 +7,7 @@
 #include <errno.h>
 
 #include <arch_helpers.h>
+#include <drivers/arm/sp805.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
@@ -21,7 +22,9 @@
 	/* Propagate the err code in the NV-flags register */
 	*flags_ptr = err;
 
-	/* Loop until the watchdog resets the system */
+	/* Setup the watchdog to reset the system as soon as possible */
+	sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
+
 	for (;;)
 		wfi();
 }
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 40e6264..ea7f851 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -66,7 +66,8 @@
 				${JUNO_INTERCONNECT_SOURCES}		\
 				${JUNO_SECURITY_SOURCES}
 
-BL2_SOURCES		+=	lib/utils/mem_region.c			\
+BL2_SOURCES		+=	drivers/arm/sp805/sp805.c		\
+				lib/utils/mem_region.c			\
 				plat/arm/board/juno/juno_err.c		\
 				plat/arm/board/juno/juno_bl2_setup.c	\
 				plat/arm/common/arm_nor_psci_mem_protect.c \
diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
index a831b89..632af7b 100644
--- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
+++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
@@ -80,8 +80,17 @@
 	flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
 
 	INFO("Enabling ECC on DMCs\n");
+	/* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
+	mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
+	mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
+
+	/* Enable ECC in DMCs */
 	mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
 	mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
+
+	/* Set DMCs to READY state */
+	mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
+	mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
 }
 
 void copy_bl33(uint32_t src, uint32_t dst, uint32_t size)
diff --git a/plat/arm/board/n1sdp/n1sdp_def.h b/plat/arm/board/n1sdp/n1sdp_def.h
index b7f7213..d43c5a4 100644
--- a/plat/arm/board/n1sdp/n1sdp_def.h
+++ b/plat/arm/board/n1sdp/n1sdp_def.h
@@ -25,10 +25,18 @@
 #define N1SDP_SDS_BL33_INFO_OFFSET		0
 #define N1SDP_SDS_BL33_INFO_SIZE		12
 
+/* DMC memory command registers */
+#define N1SDP_DMC0_MEMC_CMD_REG			0x4E000008
+#define N1SDP_DMC1_MEMC_CMD_REG			0x4E100008
+
 /* DMC ERR0CTLR0 registers */
 #define N1SDP_DMC0_ERR0CTLR0_REG		0x4E000708
 #define N1SDP_DMC1_ERR0CTLR0_REG		0x4E100708
 
+/* DMC memory commands */
+#define N1SDP_DMC_MEMC_CMD_CONFIG		0
+#define N1SDP_DMC_MEMC_CMD_READY		3
+
 /* DMC ECC enable bit in ERR0CTLR0 register */
 #define N1SDP_DMC_ERR0CTLR0_ECC_EN		0x1
 
diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk
index 833bb82..db41e0e 100644
--- a/plat/arm/board/rde1edge/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -12,10 +12,12 @@
 
 SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_e1.S
 
-BL1_SOURCES		+=	${SGI_CPU_SOURCES}
+BL1_SOURCES		+=	${SGI_CPU_SOURCES}			\
+				${RDE1EDGE_BASE}/rde1edge_err.c
 
 BL2_SOURCES		+=	${RDE1EDGE_BASE}/rde1edge_plat.c	\
 				${RDE1EDGE_BASE}/rde1edge_security.c	\
+				${RDE1EDGE_BASE}/rde1edge_err.c		\
 				drivers/arm/tzc/tzc_dmc620.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/rde1edge/rde1edge_err.c b/plat/arm/board/rde1edge/rde1edge_err.c
new file mode 100644
index 0000000..e344d82
--- /dev/null
+++ b/plat/arm/board/rde1edge/rde1edge_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * rde1edge error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+	while (1) {
+		wfi();
+	}
+}
diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk
index cacdaa1..b44c70a 100644
--- a/plat/arm/board/rdn1edge/platform.mk
+++ b/plat/arm/board/rdn1edge/platform.mk
@@ -12,10 +12,12 @@
 
 SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_n1.S
 
-BL1_SOURCES		+=	${SGI_CPU_SOURCES}
+BL1_SOURCES		+=	${SGI_CPU_SOURCES}			\
+				${RDN1EDGE_BASE}/rdn1edge_err.c
 
 BL2_SOURCES		+=	${RDN1EDGE_BASE}/rdn1edge_plat.c	\
 				${RDN1EDGE_BASE}/rdn1edge_security.c	\
+				${RDN1EDGE_BASE}/rdn1edge_err.c		\
 				drivers/arm/tzc/tzc_dmc620.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/rdn1edge/rdn1edge_err.c b/plat/arm/board/rdn1edge/rdn1edge_err.c
new file mode 100644
index 0000000..cdcbf25
--- /dev/null
+++ b/plat/arm/board/rdn1edge/rdn1edge_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * rdn1edge error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+	while (1) {
+		wfi();
+	}
+}
diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk
index e72225d..b9fa099 100644
--- a/plat/arm/board/sgi575/platform.mk
+++ b/plat/arm/board/sgi575/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -12,10 +12,12 @@
 
 SGI_CPU_SOURCES		:=	lib/cpus/aarch64/cortex_a75.S
 
-BL1_SOURCES		+=	${SGI_CPU_SOURCES}
+BL1_SOURCES		+=	${SGI_CPU_SOURCES}			\
+				${SGI575_BASE}/sgi575_err.c
 
 BL2_SOURCES		+=	${SGI575_BASE}/sgi575_plat.c		\
 				${SGI575_BASE}/sgi575_security.c	\
+				${SGI575_BASE}/sgi575_err.c		\
 				drivers/arm/tzc/tzc_dmc620.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/sgi575/sgi575_err.c b/plat/arm/board/sgi575/sgi575_err.c
new file mode 100644
index 0000000..c1cc1a7
--- /dev/null
+++ b/plat/arm/board/sgi575/sgi575_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * sgi575 error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+	while (1) {
+		wfi();
+	}
+}
diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk
index c833755..7a843c3 100644
--- a/plat/arm/board/sgm775/platform.mk
+++ b/plat/arm/board/sgm775/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -12,7 +12,10 @@
 
 PLAT_INCLUDES +=-I${SGM775_BASE}/include/
 
+BL1_SOURCES		+=	${SGM775_BASE}/sgm775_err.c
+
 BL2_SOURCES		+=	lib/utils/mem_region.c                  \
+				${SGM775_BASE}/sgm775_err.c		\
 				plat/arm/common/arm_nor_psci_mem_protect.c
 
 BL31_SOURCES		+=	drivers/cfi/v2m/v2m_flash.c		\
diff --git a/plat/arm/board/sgm775/sgm775_err.c b/plat/arm/board/sgm775/sgm775_err.c
new file mode 100644
index 0000000..e1e0586
--- /dev/null
+++ b/plat/arm/board/sgm775/sgm775_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * sgm775 error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+	while (1) {
+		wfi();
+	}
+}
diff --git a/plat/arm/common/arm_err.c b/plat/arm/common/arm_err.c
index e77f5dc..f80ba78 100644
--- a/plat/arm/common/arm_err.c
+++ b/plat/arm/common/arm_err.c
@@ -1,55 +1,14 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <errno.h>
-#include <stdint.h>
 
-#include <platform_def.h>
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <drivers/cfi/v2m_flash.h>
-#include <drivers/console.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 
-#pragma weak plat_arm_error_handler
-
-/*
- * ARM common implementation for error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
-	int ret;
-
-	switch (err) {
-	case -ENOENT:
-	case -EAUTH:
-		/* Image load or authentication error. Erase the ToC */
-		INFO("Erasing FIP ToC from flash...\n");
-		(void)nor_unlock(PLAT_ARM_FIP_BASE);
-		ret = nor_word_program(PLAT_ARM_FIP_BASE, 0);
-		if (ret != 0) {
-			ERROR("Cannot erase ToC\n");
-		} else {
-			INFO("Done\n");
-		}
-		break;
-	default:
-		/* Unexpected error */
-		break;
-	}
-
-	(void)console_flush();
-
-	/* Loop until the watchdog resets the system */
-	for (;;)
-		wfi();
-}
-
 void __dead2 plat_error_handler(int err)
 {
 	plat_arm_error_handler(err);
diff --git a/plat/hisilicon/poplar/bl31_plat_setup.c b/plat/hisilicon/poplar/bl31_plat_setup.c
index f81078f..981ef37 100644
--- a/plat/hisilicon/poplar/bl31_plat_setup.c
+++ b/plat/hisilicon/poplar/bl31_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -130,6 +130,6 @@
 			       BL_COHERENT_RAM_BASE,
 			       BL_COHERENT_RAM_END);
 
-	INFO("Boot BL33 from 0x%lx for %lu Bytes\n",
+	INFO("Boot BL33 from 0x%lx for %llu Bytes\n",
 	     bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);
 }
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index 63d9223..c3cd0d0 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -24,6 +24,7 @@
 #include <gpc.h>
 #include <imx_aipstz.h>
 #include <imx_uart.h>
+#include <imx_rdc.h>
 #include <imx8m_caam.h>
 #include <plat_imx8.h>
 
@@ -41,6 +42,18 @@
 	{0},
 };
 
+static const struct imx_rdc_cfg rdc[] = {
+	/* Master domain assignment */
+	RDC_MDAn(0x1, DID1),
+
+	/* peripherals domain permission */
+
+	/* memory region */
+
+	/* Sentinel */
+	{0},
+};
+
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
 
@@ -94,6 +107,8 @@
 
 	imx_aipstz_init(aipstz);
 
+	imx_rdc_init(rdc);
+
 	imx8m_caam_init();
 
 	console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index c28463b..6d32dbb 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -20,6 +20,7 @@
 BL31_SOURCES		+=	plat/imx/common/imx8_helpers.S			\
 				plat/imx/imx8m/gpc_common.c			\
 				plat/imx/imx8m/imx_aipstz.c			\
+				plat/imx/imx8m/imx_rdc.c			\
 				plat/imx/imx8m/imx8m_caam.c			\
 				plat/imx/imx8m/imx8m_psci_common.c		\
 				plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c	\
diff --git a/plat/imx/imx8m/imx_rdc.c b/plat/imx/imx8m/imx_rdc.c
new file mode 100644
index 0000000..85de191
--- /dev/null
+++ b/plat/imx/imx8m/imx_rdc.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019, NXP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+
+#include <imx_rdc.h>
+
+void imx_rdc_init(const struct imx_rdc_cfg *rdc_cfg)
+{
+	const struct imx_rdc_cfg *rdc = rdc_cfg;
+
+	while (rdc->type != RDC_INVALID) {
+		switch (rdc->type) {
+		case RDC_MDA:
+			/* MDA config */
+			mmio_write_32(MDAn(rdc->index), rdc->setting.rdc_mda);
+			break;
+		case RDC_PDAP:
+			/* peripheral access permission config */
+			mmio_write_32(PDAPn(rdc->index), rdc->setting.rdc_pdap);
+			break;
+		case RDC_MEM_REGION:
+			/* memory region access permission config */
+			mmio_write_32(MRSAn(rdc->index), rdc->setting.rdc_mem_region[0]);
+			mmio_write_32(MREAn(rdc->index), rdc->setting.rdc_mem_region[1]);
+			mmio_write_32(MRCn(rdc->index), rdc->setting.rdc_mem_region[2]);
+			break;
+		default:
+			break;
+		}
+
+		rdc++;
+	}
+}
diff --git a/plat/imx/imx8m/include/imx_rdc.h b/plat/imx/imx8m/include/imx_rdc.h
new file mode 100644
index 0000000..6be8550
--- /dev/null
+++ b/plat/imx/imx8m/include/imx_rdc.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2019, NXP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX_RDC_H
+#define IMX_RDC_H
+
+#include <lib/utils_def.h>
+
+#include <platform_def.h>
+
+#define MDAn(x)		(IMX_RDC_BASE + 0x200 + (x) * 4)
+#define PDAPn(x)	(IMX_RDC_BASE + 0x400 + (x) * 4)
+#define MRSAn(x)	(IMX_RDC_BASE + 0x800 + (x) * 4)
+#define MREAn(x)	(IMX_RDC_BASE + 0x804 + (x) * 4)
+#define MRCn(x)		(IMX_RDC_BASE + 0x808 + (x) * 4)
+
+#define LCK		BIT(31)
+#define SREQ		BIT(30)
+#define ENA		BIT(30)
+
+#define DID0		U(0x0)
+#define DID1		U(0x1)
+#define DID2		U(0x2)
+#define DID3		U(0x3)
+
+#define D3R		BIT(7)
+#define D3W		BIT(6)
+#define D2R		BIT(5)
+#define D2W		BIT(4)
+#define D1R		BIT(3)
+#define D1W		BIT(2)
+#define D0R		BIT(1)
+#define D0W		BIT(0)
+
+union rdc_setting {
+	uint32_t rdc_mda; /* Master Domain Assignment */
+	uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */
+	uint32_t rdc_mem_region[3]; /* Memory Region Access Control */
+};
+
+enum rdc_type {
+	RDC_INVALID,
+	RDC_MDA,
+	RDC_PDAP,
+	RDC_MEM_REGION,
+};
+
+struct imx_rdc_cfg {
+	enum rdc_type type; /* config type Master, Peripheral or Memory region */
+	int index;
+	union rdc_setting setting;
+};
+
+#define RDC_MDAn(i, mda)	\
+	{RDC_MDA, (i), .setting.rdc_mda = (mda), }
+#define RDC_PDAPn(i, pdap)	\
+	{RDC_PDAP, (i), .setting.rdc_pdap = (pdap), }
+
+#define RDC_MEM_REGIONn(i, msa, mea, mrc)	\
+	{ RDC_MEM_REGION, (i), 			\
+	  .setting.rdc_mem_region[0] = (msa),	\
+	  .setting.rdc_mem_region[1] = (mea),	\
+	  .setting.rdc_mem_region[2] = (mrc),	\
+	}
+
+void imx_rdc_init(const struct imx_rdc_cfg *cfg);
+
+#endif /* IMX_RDC_H */
+
diff --git a/plat/intel/soc/agilex/include/agilex_mailbox.h b/plat/intel/soc/agilex/include/agilex_mailbox.h
index 2a21447..cd8be28 100644
--- a/plat/intel/soc/agilex/include/agilex_mailbox.h
+++ b/plat/intel/soc/agilex/include/agilex_mailbox.h
@@ -7,6 +7,8 @@
 #ifndef AGX_MBOX_H
 #define AGX_MBOX_H
 
+#include <lib/utils_def.h>
+
 #define MBOX_OFFSET			0xffa30000
 
 #define MBOX_ATF_CLIENT_ID		0x1
@@ -76,7 +78,7 @@
 #define RECONFIG_STATUS_STATE		0
 #define RECONFIG_STATUS_PIN_STATUS	2
 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3
-#define PIN_STATUS_NSTATUS		(1 << 31)
+#define PIN_STATUS_NSTATUS		(U(1) << 31)
 #define SOFTFUNC_STATUS_SEU_ERROR	(1 << 3)
 #define SOFTFUNC_STATUS_INIT_DONE	(1 << 1)
 #define SOFTFUNC_STATUS_CONF_DONE	(1 << 0)
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index dd23e63..ad81b16 100644
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <common/desc_image_load.h>
 #include <drivers/console.h>
 #include <drivers/generic_delay_timer.h>
 #include <lib/mmio.h>
@@ -79,6 +80,7 @@
 	entry_point_info_t *next_image_info;
 
 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
 
 	/* None of the images on this platform can have 0x0 as the entrypoint */
 	if (next_image_info->pc)
@@ -98,18 +100,11 @@
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				u_register_t arg2, u_register_t arg3)
 {
-	struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0;
-
 	console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
 
 	VERBOSE("bl31_setup\n");
 
-	assert(arg_from_bl2 != NULL);
-	assert(arg_from_bl2->h.type == PARAM_BL31);
-	assert(arg_from_bl2->h.version >= VERSION_1);
-
-	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
-	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
+	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
 }
 
 /*******************************************************************************
diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk
index 0726efe..24e4ec6 100644
--- a/plat/mediatek/mt8173/platform.mk
+++ b/plat/mediatek/mt8173/platform.mk
@@ -23,7 +23,8 @@
 				plat/arm/common/arm_gicv2.c			\
 				plat/common/plat_gicv2.c
 
-BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
+BL31_SOURCES		+=	common/desc_image_load.c			\
+				drivers/arm/cci/cci.c				\
 				drivers/arm/gic/common/gic_common.c		\
 				drivers/arm/gic/v2/gicv2_main.c			\
 				drivers/arm/gic/v2/gicv2_helpers.c		\
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index b451189..e623e96 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -7,6 +7,7 @@
 #include <assert.h>
 #include <arch_helpers.h>
 #include <common/bl_common.h>
+#include <common/desc_image_load.h>
 #include <plat/common/common_def.h>
 #include <drivers/console.h>
 #include <common/debug.h>
@@ -50,6 +51,7 @@
 	entry_point_info_t *next_image_info;
 
 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
 
 	/* None of the images on this platform can have 0x0 as the entrypoint */
 	if (next_image_info->pc)
@@ -69,19 +71,13 @@
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				u_register_t arg2, u_register_t arg3)
 {
-	struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0;
 	static console_16550_t console;
 
 	console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
 
 	NOTICE("MT8183 bl31_setup\n");
 
-	assert(arg_from_bl2 != NULL);
-	assert(arg_from_bl2->h.type == PARAM_BL31);
-	assert(arg_from_bl2->h.version >= VERSION_1);
-
-	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
-	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
+	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
 }
 
 
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 8c8e2fe..f0a598a 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -16,7 +16,8 @@
                           plat/common/plat_psci_common.c              \
                           plat/common/aarch64/crash_console_helpers.S
 
-BL31_SOURCES    += drivers/arm/cci/cci.c                                 \
+BL31_SOURCES    += common/desc_image_load.c                              \
+                   drivers/arm/cci/cci.c                                 \
                    drivers/arm/gic/common/gic_common.c                   \
                    drivers/arm/gic/v3/arm_gicv3_common.c                 \
                    drivers/arm/gic/v3/gicv3_helpers.c                    \
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index 18f8dd9..a13ee49 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <common/desc_image_load.h>
 #include <drivers/console.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/ti/uart/uart_16550.h>
@@ -32,6 +33,7 @@
 	entry_point_info_t *next_image_info;
 
 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
 
 	/* None of the images on this platform can have 0x0 as the entrypoint */
 	if (next_image_info->pc)
@@ -41,7 +43,7 @@
 }
 
 #pragma weak params_early_setup
-void params_early_setup(void *plat_param_from_bl2)
+void params_early_setup(u_register_t plat_param_from_bl2)
 {
 }
 
@@ -57,10 +59,8 @@
 				u_register_t arg2, u_register_t arg3)
 {
 	static console_16550_t console;
-	struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
-	void *plat_params_from_bl2 = (void *) arg1;
 
-	params_early_setup(plat_params_from_bl2);
+	params_early_setup(arg1);
 
 #if COREBOOT
 	if (coreboot_serial.type)
@@ -75,14 +75,7 @@
 
 	VERBOSE("bl31_setup\n");
 
-	/* Passing a NULL context is a critical programming error */
-	assert(arg_from_bl2);
-
-	assert(arg_from_bl2->h.type == PARAM_BL31);
-	assert(arg_from_bl2->h.version >= VERSION_1);
-
-	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
-	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
+	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
 }
 
 /*******************************************************************************
diff --git a/plat/rockchip/common/include/plat_params.h b/plat/rockchip/common/include/plat_params.h
index 1ec02f5..95b850f 100644
--- a/plat/rockchip/common/include/plat_params.h
+++ b/plat/rockchip/common/include/plat_params.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,90 +9,6 @@
 
 #include <stdint.h>
 
-/*
- * We defined several plat parameter structs for BL2 to pass platform related
- * parameters to Rockchip BL31 platform code.  All plat parameters start with
- * a common header, which has a type field to indicate the parameter type, and
- * a next pointer points to next parameter. If the parameter is the last one in
- * the list, next pointer will points to NULL.  After the header comes the
- * variable-sized members that describe the parameter. The picture below shows
- * how the parameters are kept in memory.
- *
- * head of list  ---> +----------------+ --+
- *                    |      type      |   |
- *                    +----------------+   |--> struct bl31_plat_param
- *               +----|      next      |   |
- *               |    +----------------+ --+
- *               |    | parameter data |
- *               |    +----------------+
- *               |
- *               +--> +----------------+ --+
- *                    |      type      |   |
- *                    +----------------+   |--> struct bl31_plat_param
- *           NULL <---|      next      |   |
- *                    +----------------+ --+
- *                    | parameter data |
- *                    +----------------+
- *
- * Note: The SCTLR_EL3.A bit (Alignment fault check enable) of ARM TF is set,
- * so be sure each parameter struct starts on 64-bit aligned address. If not,
- * alignment fault will occur during accessing its data member.
- */
-
-#define BL31_GPIO_DIR_OUT		0
-#define BL31_GPIO_DIR_IN		1
-
-#define BL31_GPIO_LEVEL_LOW		0
-#define BL31_GPIO_LEVEL_HIGH		1
-
-#define BL31_GPIO_PULL_NONE		0
-#define BL31_GPIO_PULL_UP		1
-#define BL31_GPIO_PULL_DOWN		2
-
-/* param type */
-enum {
-	PARAM_NONE = 0,
-	PARAM_RESET,
-	PARAM_POWEROFF,
-	PARAM_SUSPEND_GPIO,
-	PARAM_SUSPEND_APIO,
-	PARAM_COREBOOT_TABLE,
-};
-
-struct apio_info {
-	uint8_t apio1 : 1;
-	uint8_t apio2 : 1;
-	uint8_t apio3 : 1;
-	uint8_t apio4 : 1;
-	uint8_t apio5 : 1;
-};
-
-struct gpio_info {
-	uint8_t polarity;
-	uint8_t direction;
-	uint8_t pull_mode;
-	uint32_t index;
-};
-
-/* common header for all plat parameter type */
-struct bl31_plat_param {
-	uint64_t type;
-	void *next;
-};
-
-struct bl31_gpio_param {
-	struct bl31_plat_param h;
-	struct gpio_info gpio;
-};
-
-struct bl31_apio_param {
-	struct bl31_plat_param h;
-	struct apio_info apio;
-};
-
-struct bl31_u64_param {
-	struct bl31_plat_param h;
-	uint64_t value;
-};
+#include <export/plat/rockchip/common/plat_params_exp.h>
 
 #endif /* PLAT_PARAMS_H */
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index c0ebefc..66b6185 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,6 +14,7 @@
 #include <lib/psci/psci.h>
 #include <lib/xlat_tables/xlat_tables.h>
 #include <lib/mmio.h>
+#include <plat_params.h>
 
 #define __sramdata __attribute__((section(".sram.data")))
 #define __sramconst __attribute__((section(".sram.rodata")))
@@ -30,15 +31,6 @@
 extern uint32_t __sram_incbin_start, __sram_incbin_end;
 extern uint32_t __sram_incbin_real_end;
 
-struct rockchip_bl31_params {
-       param_header_t h;
-       image_info_t *bl31_image_info;
-       entry_point_info_t *bl32_ep_info;
-       image_info_t *bl32_image_info;
-       entry_point_info_t *bl33_ep_info;
-       image_info_t *bl33_image_info;
-};
-
 /******************************************************************************
  * The register have write-mask bits, it is mean, if you want to set the bits,
  * you needs set the write-mask bits at the same time,
@@ -94,7 +86,7 @@
 
 void plat_delay_timer_init(void);
 
-void params_early_setup(void *plat_params_from_bl2);
+void params_early_setup(u_register_t plat_params_from_bl2);
 
 void plat_rockchip_gic_driver_init(void);
 void plat_rockchip_gic_init(void);
@@ -108,10 +100,10 @@
 
 void platform_cpu_warmboot(void);
 
-struct gpio_info *plat_get_rockchip_gpio_reset(void);
-struct gpio_info *plat_get_rockchip_gpio_poweroff(void);
-struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
-struct apio_info *plat_get_rockchip_suspend_apio(void);
+struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void);
+struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void);
+struct bl_aux_gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
+struct bl_aux_rk_apio_info *plat_get_rockchip_suspend_apio(void);
 void plat_rockchip_gpio_init(void);
 void plat_rockchip_save_gpio(void);
 void plat_rockchip_restore_gpio(void);
diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
index 8a743bf..d0fea4f 100644
--- a/plat/rockchip/common/params_setup.c
+++ b/plat/rockchip/common/params_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #include <errno.h>
 #include <string.h>
 
+#include <lib/bl_aux_params/bl_aux_params.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <drivers/console.h>
@@ -20,14 +21,11 @@
 #include <plat_params.h>
 #include <plat_private.h>
 
-static struct gpio_info param_reset;
-static struct gpio_info param_poweroff;
-static struct bl31_apio_param param_apio;
-static struct gpio_info *rst_gpio;
-static struct gpio_info *poweroff_gpio;
-static struct gpio_info suspend_gpio[10];
+static struct bl_aux_gpio_info rst_gpio;
+static struct bl_aux_gpio_info poweroff_gpio;
+static struct bl_aux_gpio_info suspend_gpio[10];
 uint32_t suspend_gpio_cnt;
-static struct apio_info *suspend_apio;
+static struct bl_aux_rk_apio_info suspend_apio;
 static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
 
 uint32_t rockchip_get_uart_base(void)
@@ -36,7 +34,7 @@
 }
 
 #if COREBOOT
-static int dt_process_fdt(void *blob)
+static int dt_process_fdt(u_register_t param_from_bl2)
 {
 	return -ENODEV;
 }
@@ -105,12 +103,12 @@
 	rk_uart_base = uart_base;
 }
 
-static int dt_process_fdt(void *blob)
+static int dt_process_fdt(u_register_t param_from_bl2)
 {
 	void *fdt = plat_get_fdt();
 	int ret;
 
-	ret = fdt_open_into(blob, fdt, 0x10000);
+	ret = fdt_open_into((void *)param_from_bl2, fdt, 0x10000);
 	if (ret < 0)
 		return ret;
 
@@ -120,33 +118,56 @@
 }
 #endif
 
-struct gpio_info *plat_get_rockchip_gpio_reset(void)
+struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void)
 {
-	return rst_gpio;
+	return &rst_gpio;
 }
 
-struct gpio_info *plat_get_rockchip_gpio_poweroff(void)
+struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void)
 {
-	return poweroff_gpio;
+	return &poweroff_gpio;
 }
 
-struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count)
+struct bl_aux_gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count)
 {
 	*count = suspend_gpio_cnt;
 
 	return &suspend_gpio[0];
 }
 
-struct apio_info *plat_get_rockchip_suspend_apio(void)
+struct bl_aux_rk_apio_info *plat_get_rockchip_suspend_apio(void)
 {
-	return suspend_apio;
+	return &suspend_apio;
 }
 
-void params_early_setup(void *plat_param_from_bl2)
+static bool rk_aux_param_handler(struct bl_aux_param_header *param)
 {
-	struct bl31_plat_param *bl2_param;
-	struct bl31_gpio_param *gpio_param;
+	/* Store platform parameters for later processing if needed. */
+	switch (param->type) {
+	case BL_AUX_PARAM_RK_RESET_GPIO:
+		rst_gpio = ((struct bl_aux_param_gpio *)param)->gpio;
+		return true;
+	case BL_AUX_PARAM_RK_POWEROFF_GPIO:
+		poweroff_gpio = ((struct bl_aux_param_gpio *)param)->gpio;
+		return true;
+	case BL_AUX_PARAM_RK_SUSPEND_GPIO:
+		if (suspend_gpio_cnt >= ARRAY_SIZE(suspend_gpio)) {
+			ERROR("Exceeded the supported suspend GPIO number.\n");
+			return true;
+		}
+		suspend_gpio[suspend_gpio_cnt++] =
+			((struct bl_aux_param_gpio *)param)->gpio;
+		return true;
+	case BL_AUX_PARAM_RK_SUSPEND_APIO:
+		suspend_apio = ((struct bl_aux_param_rk_apio *)param)->apio;
+		return true;
+	}
 
+	return false;
+}
+
+void params_early_setup(u_register_t plat_param_from_bl2)
+{
 	/*
 	 * Test if this is a FDT passed as a platform-specific parameter
 	 * block.
@@ -154,49 +175,5 @@
 	if (!dt_process_fdt(plat_param_from_bl2))
 		return;
 
-	/* keep plat parameters for later processing if need */
-	bl2_param = (struct bl31_plat_param *)plat_param_from_bl2;
-	while (bl2_param) {
-		switch (bl2_param->type) {
-		case PARAM_RESET:
-			gpio_param = (struct bl31_gpio_param *)bl2_param;
-			memcpy(&param_reset, &gpio_param->gpio,
-			       sizeof(struct gpio_info));
-			rst_gpio = &param_reset;
-			break;
-		case PARAM_POWEROFF:
-			gpio_param = (struct bl31_gpio_param *)bl2_param;
-			memcpy(&param_poweroff, &gpio_param->gpio,
-				sizeof(struct gpio_info));
-			poweroff_gpio = &param_poweroff;
-			break;
-		case PARAM_SUSPEND_GPIO:
-			if (suspend_gpio_cnt >= ARRAY_SIZE(suspend_gpio)) {
-				ERROR("exceed support suspend gpio number\n");
-				break;
-			}
-			gpio_param = (struct bl31_gpio_param *)bl2_param;
-			memcpy(&suspend_gpio[suspend_gpio_cnt],
-			       &gpio_param->gpio,
-			       sizeof(struct gpio_info));
-			suspend_gpio_cnt++;
-			break;
-		case PARAM_SUSPEND_APIO:
-			memcpy(&param_apio, bl2_param,
-			       sizeof(struct bl31_apio_param));
-			suspend_apio = &param_apio.apio;
-			break;
-#if COREBOOT
-		case PARAM_COREBOOT_TABLE:
-			coreboot_table_setup((void *)
-				((struct bl31_u64_param *)bl2_param)->value);
-			break;
-#endif
-		default:
-			ERROR("not expected type found %lld\n",
-			      bl2_param->type);
-			break;
-		}
-		bl2_param = bl2_param->next;
-	}
+	bl_aux_params_parse(plat_param_from_bl2, rk_aux_param_handler);
 }
diff --git a/plat/rockchip/common/pmusram/cpus_on_fixed_addr.S b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.S
new file mode 100644
index 0000000..6cea2ea
--- /dev/null
+++ b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+#include <cpus_on_fixed_addr.h>
+
+	.globl sys_sleep_flag_sram
+	.globl pmu_cpuson_entrypoint
+
+	.macro pmusram_entry_func _name
+	.section .pmusram.entry, "ax"
+	.type \_name, %function
+	.cfi_startproc
+	\_name:
+	.endm
+
+pmusram_entry_func pmu_cpuson_entrypoint
+	adr	x5, sys_sleep_flag_sram
+	ldr	w2, [x5, #PSRAM_DT_PM_FLAG]
+
+	tbz	w2, #PM_WARM_BOOT_SHT, sys_resume_sp
+	ldr	x1, =platform_cpu_warmboot
+	br	x1
+sys_resume_sp:
+	adr	x5, sys_sleep_flag_sram
+	ldr	x1, [x5, #PSRAM_DT_SP]
+	mov	sp, x1
+ddr_resume:
+	ldr	x1, [x5, #PSRAM_DT_DDR_FUNC]
+	cmp	x1, #0
+	b.eq	sys_resume
+	blr	x1
+sys_resume:
+	ldr	x1, =bl31_warm_entrypoint
+	br	x1
+endfunc pmu_cpuson_entrypoint
+
+	.section .pmusram.data, "a"
+	.align  3
+sys_sleep_flag_sram:
+	.rept	PSRAM_DT_SIZE_WORDS
+	.word	0
+	.endr
diff --git a/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h
new file mode 100644
index 0000000..b22ddc2
--- /dev/null
+++ b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __CPU_ON_FIXED_ADDR_H__
+#define __CPU_ON_FIXED_ADDR_H__
+
+/*****************************************************************************
+ * define data offset in struct psram_data
+ *****************************************************************************/
+#define PSRAM_DT_SP		0x0
+#define PSRAM_DT_DDR_FUNC	0x8
+#define PSRAM_DT_DDR_DATA	0x10
+#define PSRAM_DT_DDRFLAG	0x18
+#define PSRAM_DT_MPIDR		0x1c
+#define PSRAM_DT_PM_FLAG	0x20
+#define PSRAM_DT_END		0x24
+
+/* reserve 4 byte */
+#define PSRAM_DT_END_RES4	(PSRAM_DT_END + 4)
+
+#define PSRAM_DT_SIZE_WORDS	(PSRAM_DT_END_RES4 / 4)
+
+#define PM_WARM_BOOT_SHT	0
+#define PM_WARM_BOOT_BIT	(1 << PM_WARM_BOOT_SHT)
+
+#ifndef __ASSEMBLY__
+
+struct psram_data_t {
+	uint64_t sp;
+	uint64_t ddr_func;
+	uint64_t ddr_data;
+	uint32_t ddr_flag;
+	uint32_t boot_mpidr;
+	uint32_t pm_flag;
+};
+
+CASSERT(__builtin_offsetof(struct psram_data_t, sp) == PSRAM_DT_SP,
+	assert_psram_dt_sp_offset_mistmatch);
+CASSERT(__builtin_offsetof(struct psram_data_t, ddr_func) == PSRAM_DT_DDR_FUNC,
+	assert_psram_dt_ddr_func_offset_mistmatch);
+CASSERT(__builtin_offsetof(struct psram_data_t, ddr_data) == PSRAM_DT_DDR_DATA,
+	assert_psram_dt_ddr_data_offset_mistmatch);
+CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG,
+	assert_psram_dt_ddr_flag_offset_mistmatch);
+CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR,
+	assert_psram_dt_mpidr_offset_mistmatch);
+
+extern void *sys_sleep_flag_sram;
+
+#endif  /* __ASSEMBLY__ */
+
+#endif
diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c
index 7cdbaba..7b1a0b5 100644
--- a/plat/rockchip/common/sp_min_plat_setup.c
+++ b/plat/rockchip/common/sp_min_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #include <arch_helpers.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <common/desc_image_load.h>
 #include <drivers/console.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/ti/uart/uart_16550.h>
@@ -40,7 +41,7 @@
 }
 
 #pragma weak params_early_setup
-void params_early_setup(void *plat_param_from_bl2)
+void params_early_setup(u_register_t plat_param_from_bl2)
 {
 }
 
@@ -53,10 +54,8 @@
 				  u_register_t arg2, u_register_t arg3)
 {
 	static console_16550_t console;
-	struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
-	void *plat_params_from_bl2 = (void *) arg1;
 
-	params_early_setup(plat_params_from_bl2);
+	params_early_setup(arg1);
 
 #if COREBOOT
 	if (coreboot_serial.type)
@@ -70,13 +69,7 @@
 #endif
 	VERBOSE("sp_min_setup\n");
 
-	/* Passing a NULL context is a critical programming error */
-	assert(arg_from_bl2);
-
-	assert(arg_from_bl2->h.type == PARAM_BL31);
-	assert(arg_from_bl2->h.version >= VERSION_1);
-
-	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
+	bl31_params_parse_helper(arg0, NULL, &bl33_ep_info);
 }
 
 /*******************************************************************************
diff --git a/plat/rockchip/px30/drivers/pmu/plat_pmu_macros.S b/plat/rockchip/px30/drivers/pmu/plat_pmu_macros.S
new file mode 100644
index 0000000..a757621
--- /dev/null
+++ b/plat/rockchip/px30/drivers/pmu/plat_pmu_macros.S
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+.globl	clst_warmboot_data
+
+.macro	func_rockchip_clst_warmboot
+.endm
+
+.macro rockchip_clst_warmboot_data
+clst_warmboot_data:
+	.rept	PLATFORM_CLUSTER_COUNT
+	.word	0
+	.endr
+.endm
diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c
new file mode 100644
index 0000000..a5ed766
--- /dev/null
+++ b/plat/rockchip/px30/drivers/pmu/pmu.c
@@ -0,0 +1,1070 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <bl31/bl31.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <drivers/delay_timer.h>
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+
+#include <cpus_on_fixed_addr.h>
+#include <plat_private.h>
+#include <pmu.h>
+#include <px30_def.h>
+#include <soc.h>
+
+DEFINE_BAKERY_LOCK(rockchip_pd_lock);
+#define rockchip_pd_lock_init()	bakery_lock_init(&rockchip_pd_lock)
+#define rockchip_pd_lock_get()	bakery_lock_get(&rockchip_pd_lock)
+#define rockchip_pd_lock_rls()	bakery_lock_release(&rockchip_pd_lock)
+
+static struct psram_data_t *psram_boot_cfg =
+	(struct psram_data_t *)&sys_sleep_flag_sram;
+
+/*
+ * There are two ways to powering on or off on core.
+ * 1) Control it power domain into on or off in PMU_PWRDN_CON reg,
+ *    it is core_pwr_pd mode
+ * 2) Enable the core power manage in PMU_CORE_PM_CON reg,
+ *     then, if the core enter into wfi, it power domain will be
+ *     powered off automatically. it is core_pwr_wfi or core_pwr_wfi_int mode
+ * so we need core_pm_cfg_info to distinguish which method be used now.
+ */
+
+static uint32_t cores_pd_cfg_info[PLATFORM_CORE_COUNT]
+#if USE_COHERENT_MEM
+__attribute__ ((section("tzfw_coherent_mem")))
+#endif
+;
+
+struct px30_sleep_ddr_data {
+	uint32_t clk_sel0;
+	uint32_t cru_mode_save;
+	uint32_t cru_pmu_mode_save;
+	uint32_t ddrc_hwlpctl;
+	uint32_t ddrc_pwrctrl;
+	uint32_t ddrgrf_con0;
+	uint32_t ddrgrf_con1;
+	uint32_t ddrstdby_con0;
+	uint32_t gpio0b_iomux;
+	uint32_t gpio0c_iomux;
+	uint32_t pmu_pwrmd_core_l;
+	uint32_t pmu_pwrmd_core_h;
+	uint32_t pmu_pwrmd_cmm_l;
+	uint32_t pmu_pwrmd_cmm_h;
+	uint32_t pmu_wkup_cfg2_l;
+	uint32_t pmu_cru_clksel_con0;
+	uint32_t pmugrf_soc_con0;
+	uint32_t pmusgrf_soc_con0;
+	uint32_t pmic_slp_iomux;
+	uint32_t pgrf_pvtm_con[2];
+	uint32_t cru_clk_gate[CRU_CLKGATES_CON_CNT];
+	uint32_t cru_pmu_clk_gate[CRU_PMU_CLKGATE_CON_CNT];
+	uint32_t cru_plls_con_save[END_PLL_ID][PLL_CON_CNT];
+	uint32_t cpu_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t isp_128m_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t isp_rd_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t isp_wr_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t isp_m1_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t vip_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t rga_rd_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t rga_wr_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t vop_m0_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t vop_m1_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t vpu_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t vpu_r128_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t dmac_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t crypto_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t nand_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t sfc_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t usb_host_qos[CPU_AXI_QOS_NUM_REGS];
+	uint32_t usb_otg_qos[CPU_AXI_QOS_NUM_REGS];
+};
+
+static struct px30_sleep_ddr_data ddr_data
+#if USE_COHERENT_MEM
+__attribute__ ((section("tzfw_coherent_mem")))
+#endif
+;
+
+static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id)
+{
+	assert(cpu_id < PLATFORM_CORE_COUNT);
+	return cores_pd_cfg_info[cpu_id];
+}
+
+static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value)
+{
+	assert(cpu_id < PLATFORM_CORE_COUNT);
+	cores_pd_cfg_info[cpu_id] = value;
+#if !USE_COHERENT_MEM
+	flush_dcache_range((uintptr_t)&cores_pd_cfg_info[cpu_id],
+			   sizeof(uint32_t));
+#endif
+}
+
+static inline uint32_t pmu_power_domain_st(uint32_t pd)
+{
+	return mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd) ?
+	       pmu_pd_off :
+	       pmu_pd_on;
+}
+
+static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state)
+{
+	uint32_t loop = 0;
+	int ret = 0;
+
+	rockchip_pd_lock_get();
+
+	mmio_write_32(PMU_BASE + PMU_PWRDN_CON,
+		      BITS_WITH_WMASK(pd_state, 0x1, pd));
+	dsb();
+
+	while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) {
+		udelay(1);
+		loop++;
+	}
+
+	if (pmu_power_domain_st(pd) != pd_state) {
+		WARN("%s: %d, %d, error!\n", __func__, pd, pd_state);
+		ret = -EINVAL;
+	}
+
+	rockchip_pd_lock_rls();
+
+	return ret;
+}
+
+static inline uint32_t pmu_bus_idle_st(uint32_t bus)
+{
+	return !!((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & BIT(bus)) &&
+		  (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & BIT(bus + 16)));
+}
+
+static void pmu_bus_idle_req(uint32_t bus, uint32_t state)
+{
+	uint32_t wait_cnt = 0;
+
+	mmio_write_32(PMU_BASE + PMU_BUS_IDLE_REQ,
+		      BITS_WITH_WMASK(state, 0x1, bus));
+
+	while (pmu_bus_idle_st(bus) != state &&
+	       wait_cnt < BUS_IDLE_LOOP) {
+		udelay(1);
+		wait_cnt++;
+	}
+
+	if (pmu_bus_idle_st(bus) != state)
+		WARN("%s:idle_st=0x%x, bus_id=%d\n",
+		     __func__, mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), bus);
+}
+
+static void qos_save(void)
+{
+	/* scu powerdomain will power off, so cpu qos should be saved */
+	SAVE_QOS(ddr_data.cpu_qos, CPU);
+
+	if (pmu_power_domain_st(PD_GPU) == pmu_pd_on)
+		SAVE_QOS(ddr_data.gpu_qos, GPU);
+	if (pmu_power_domain_st(PD_VI) == pmu_pd_on) {
+		SAVE_QOS(ddr_data.isp_128m_qos, ISP_128M);
+		SAVE_QOS(ddr_data.isp_rd_qos, ISP_RD);
+		SAVE_QOS(ddr_data.isp_wr_qos, ISP_WR);
+		SAVE_QOS(ddr_data.isp_m1_qos, ISP_M1);
+		SAVE_QOS(ddr_data.vip_qos, VIP);
+	}
+	if (pmu_power_domain_st(PD_VO) == pmu_pd_on) {
+		SAVE_QOS(ddr_data.rga_rd_qos, RGA_RD);
+		SAVE_QOS(ddr_data.rga_wr_qos, RGA_WR);
+		SAVE_QOS(ddr_data.vop_m0_qos, VOP_M0);
+		SAVE_QOS(ddr_data.vop_m1_qos, VOP_M1);
+	}
+	if (pmu_power_domain_st(PD_VPU) == pmu_pd_on) {
+		SAVE_QOS(ddr_data.vpu_qos, VPU);
+		SAVE_QOS(ddr_data.vpu_r128_qos, VPU_R128);
+	}
+	if (pmu_power_domain_st(PD_MMC_NAND) == pmu_pd_on) {
+		SAVE_QOS(ddr_data.emmc_qos, EMMC);
+		SAVE_QOS(ddr_data.nand_qos, NAND);
+		SAVE_QOS(ddr_data.sdio_qos, SDIO);
+		SAVE_QOS(ddr_data.sfc_qos, SFC);
+	}
+	if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on)
+		SAVE_QOS(ddr_data.gmac_qos, GMAC);
+	if (pmu_power_domain_st(PD_CRYPTO) == pmu_pd_on)
+		SAVE_QOS(ddr_data.crypto_qos, CRYPTO);
+	if (pmu_power_domain_st(PD_SDCARD) == pmu_pd_on)
+		SAVE_QOS(ddr_data.sdmmc_qos, SDMMC);
+	if (pmu_power_domain_st(PD_USB) == pmu_pd_on) {
+		SAVE_QOS(ddr_data.usb_host_qos, USB_HOST);
+		SAVE_QOS(ddr_data.usb_otg_qos, USB_OTG);
+	}
+}
+
+static void qos_restore(void)
+{
+	RESTORE_QOS(ddr_data.cpu_qos, CPU);
+
+	if (pmu_power_domain_st(PD_GPU) == pmu_pd_on)
+		RESTORE_QOS(ddr_data.gpu_qos, GPU);
+	if (pmu_power_domain_st(PD_VI) == pmu_pd_on) {
+		RESTORE_QOS(ddr_data.isp_128m_qos, ISP_128M);
+		RESTORE_QOS(ddr_data.isp_rd_qos, ISP_RD);
+		RESTORE_QOS(ddr_data.isp_wr_qos, ISP_WR);
+		RESTORE_QOS(ddr_data.isp_m1_qos, ISP_M1);
+		RESTORE_QOS(ddr_data.vip_qos, VIP);
+	}
+	if (pmu_power_domain_st(PD_VO) == pmu_pd_on) {
+		RESTORE_QOS(ddr_data.rga_rd_qos, RGA_RD);
+		RESTORE_QOS(ddr_data.rga_wr_qos, RGA_WR);
+		RESTORE_QOS(ddr_data.vop_m0_qos, VOP_M0);
+		RESTORE_QOS(ddr_data.vop_m1_qos, VOP_M1);
+	}
+	if (pmu_power_domain_st(PD_VPU) == pmu_pd_on) {
+		RESTORE_QOS(ddr_data.vpu_qos, VPU);
+		RESTORE_QOS(ddr_data.vpu_r128_qos, VPU_R128);
+	}
+	if (pmu_power_domain_st(PD_MMC_NAND) == pmu_pd_on) {
+		RESTORE_QOS(ddr_data.emmc_qos, EMMC);
+		RESTORE_QOS(ddr_data.nand_qos, NAND);
+		RESTORE_QOS(ddr_data.sdio_qos, SDIO);
+		RESTORE_QOS(ddr_data.sfc_qos, SFC);
+	}
+	if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on)
+		RESTORE_QOS(ddr_data.gmac_qos, GMAC);
+	if (pmu_power_domain_st(PD_CRYPTO) == pmu_pd_on)
+		RESTORE_QOS(ddr_data.crypto_qos, CRYPTO);
+	if (pmu_power_domain_st(PD_SDCARD) == pmu_pd_on)
+		RESTORE_QOS(ddr_data.sdmmc_qos, SDMMC);
+	if (pmu_power_domain_st(PD_USB) == pmu_pd_on) {
+		RESTORE_QOS(ddr_data.usb_host_qos, USB_HOST);
+		RESTORE_QOS(ddr_data.usb_otg_qos, USB_OTG);
+	}
+}
+
+static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state)
+{
+	uint32_t state;
+
+	if (pmu_power_domain_st(pd_id) == pd_state)
+		goto out;
+
+	if (pd_state == pmu_pd_on)
+		pmu_power_domain_ctr(pd_id, pd_state);
+
+	state = (pd_state == pmu_pd_off) ? bus_idle : bus_active;
+
+	switch (pd_id) {
+	case PD_GPU:
+		pmu_bus_idle_req(BUS_ID_GPU, state);
+		break;
+	case PD_VI:
+		pmu_bus_idle_req(BUS_ID_VI, state);
+		break;
+	case PD_VO:
+		pmu_bus_idle_req(BUS_ID_VO, state);
+		break;
+	case PD_VPU:
+		pmu_bus_idle_req(BUS_ID_VPU, state);
+		break;
+	case PD_MMC_NAND:
+		pmu_bus_idle_req(BUS_ID_MMC, state);
+		break;
+	case PD_GMAC:
+		pmu_bus_idle_req(BUS_ID_GMAC, state);
+		break;
+	case PD_CRYPTO:
+		pmu_bus_idle_req(BUS_ID_CRYPTO, state);
+		break;
+	case PD_SDCARD:
+		pmu_bus_idle_req(BUS_ID_SDCARD, state);
+		break;
+	case PD_USB:
+		pmu_bus_idle_req(BUS_ID_USB, state);
+		break;
+	default:
+		break;
+	}
+
+	if (pd_state == pmu_pd_off)
+		pmu_power_domain_ctr(pd_id, pd_state);
+
+out:
+	return 0;
+}
+
+static uint32_t pmu_powerdomain_state;
+
+static void pmu_power_domains_suspend(void)
+{
+	uint32_t clkgt_save[CRU_CLKGATES_CON_CNT + CRU_PMU_CLKGATE_CON_CNT];
+
+	clk_gate_con_save(clkgt_save);
+	clk_gate_con_disable();
+	qos_save();
+
+	pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST);
+	pmu_set_power_domain(PD_GPU, pmu_pd_off);
+	pmu_set_power_domain(PD_VI, pmu_pd_off);
+	pmu_set_power_domain(PD_VO, pmu_pd_off);
+	pmu_set_power_domain(PD_VPU, pmu_pd_off);
+	pmu_set_power_domain(PD_MMC_NAND, pmu_pd_off);
+	pmu_set_power_domain(PD_GMAC, pmu_pd_off);
+	pmu_set_power_domain(PD_CRYPTO, pmu_pd_off);
+	pmu_set_power_domain(PD_SDCARD, pmu_pd_off);
+	pmu_set_power_domain(PD_USB, pmu_pd_off);
+
+	clk_gate_con_restore(clkgt_save);
+}
+
+static void pmu_power_domains_resume(void)
+{
+	uint32_t clkgt_save[CRU_CLKGATES_CON_CNT + CRU_PMU_CLKGATE_CON_CNT];
+
+	clk_gate_con_save(clkgt_save);
+	clk_gate_con_disable();
+
+	if (!(pmu_powerdomain_state & BIT(PD_USB)))
+		pmu_set_power_domain(PD_USB, pmu_pd_on);
+	if (!(pmu_powerdomain_state & BIT(PD_SDCARD)))
+		pmu_set_power_domain(PD_SDCARD, pmu_pd_on);
+	if (!(pmu_powerdomain_state & BIT(PD_CRYPTO)))
+		pmu_set_power_domain(PD_CRYPTO, pmu_pd_on);
+	if (!(pmu_powerdomain_state & BIT(PD_GMAC)))
+		pmu_set_power_domain(PD_GMAC, pmu_pd_on);
+	if (!(pmu_powerdomain_state & BIT(PD_MMC_NAND)))
+		pmu_set_power_domain(PD_MMC_NAND, pmu_pd_on);
+	if (!(pmu_powerdomain_state & BIT(PD_VPU)))
+		pmu_set_power_domain(PD_VPU, pmu_pd_on);
+	if (!(pmu_powerdomain_state & BIT(PD_VO)))
+		pmu_set_power_domain(PD_VO, pmu_pd_on);
+	if (!(pmu_powerdomain_state & BIT(PD_VI)))
+		pmu_set_power_domain(PD_VI, pmu_pd_on);
+	if (!(pmu_powerdomain_state & BIT(PD_GPU)))
+		pmu_set_power_domain(PD_GPU, pmu_pd_on);
+
+	qos_restore();
+	clk_gate_con_restore(clkgt_save);
+}
+
+static int check_cpu_wfie(uint32_t cpu)
+{
+	uint32_t loop = 0, wfie_msk = CKECK_WFEI_MSK << cpu;
+
+	while (!(mmio_read_32(GRF_BASE + GRF_CPU_STATUS1) & wfie_msk) &&
+	       (loop < WFEI_CHECK_LOOP)) {
+		udelay(1);
+		loop++;
+	}
+
+	if ((mmio_read_32(GRF_BASE + GRF_CPU_STATUS1) & wfie_msk) == 0) {
+		WARN("%s: %d, %d, error!\n", __func__, cpu, wfie_msk);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int cpus_power_domain_on(uint32_t cpu_id)
+{
+	uint32_t cpu_pd, apm_value, cfg_info, loop = 0;
+
+	cpu_pd = PD_CPU0 + cpu_id;
+	cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id);
+
+	if (cfg_info == core_pwr_pd) {
+		/* disable apm cfg */
+		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
+			      WITH_16BITS_WMSK(CORES_PM_DISABLE));
+		if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) {
+			mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
+				      WITH_16BITS_WMSK(CORES_PM_DISABLE));
+			pmu_power_domain_ctr(cpu_pd, pmu_pd_off);
+		}
+		pmu_power_domain_ctr(cpu_pd, pmu_pd_on);
+	} else {
+		/* wait cpu down */
+		while (pmu_power_domain_st(cpu_pd) == pmu_pd_on && loop < 100) {
+			udelay(2);
+			loop++;
+		}
+
+		/* return error if can't wait cpu down */
+		if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) {
+			WARN("%s:can't wait cpu down\n", __func__);
+			return -EINVAL;
+		}
+
+		/* power up cpu in power down state */
+		apm_value = BIT(core_pm_sft_wakeup_en);
+		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
+			      WITH_16BITS_WMSK(apm_value));
+	}
+
+	return 0;
+}
+
+static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg)
+{
+	uint32_t cpu_pd, apm_value;
+
+	cpu_pd = PD_CPU0 + cpu_id;
+	if (pmu_power_domain_st(cpu_pd) == pmu_pd_off)
+		return 0;
+
+	if (pd_cfg == core_pwr_pd) {
+		if (check_cpu_wfie(cpu_id))
+			return -EINVAL;
+		/* disable apm cfg */
+		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
+			      WITH_16BITS_WMSK(CORES_PM_DISABLE));
+		set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg);
+		pmu_power_domain_ctr(cpu_pd, pmu_pd_off);
+	} else {
+		set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg);
+		apm_value = BIT(core_pm_en) | BIT(core_pm_dis_int);
+		if (pd_cfg == core_pwr_wfi_int)
+			apm_value |= BIT(core_pm_int_wakeup_en);
+		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
+			      WITH_16BITS_WMSK(apm_value));
+	}
+
+	return 0;
+}
+
+static void nonboot_cpus_off(void)
+{
+	uint32_t boot_cpu, cpu;
+
+	boot_cpu = plat_my_core_pos();
+
+	for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) {
+		if (cpu == boot_cpu)
+			continue;
+		cpus_power_domain_off(cpu, core_pwr_pd);
+	}
+}
+
+int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr,
+				 uint64_t entrypoint)
+{
+	uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
+
+	assert(cpu_id < PLATFORM_CORE_COUNT);
+	assert(cpuson_flags[cpu_id] == 0);
+	cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG;
+	cpuson_entry_point[cpu_id] = entrypoint;
+	dsb();
+
+	cpus_power_domain_on(cpu_id);
+
+	return PSCI_E_SUCCESS;
+}
+
+int rockchip_soc_cores_pwr_dm_on_finish(void)
+{
+	uint32_t cpu_id = plat_my_core_pos();
+
+	mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
+		      WITH_16BITS_WMSK(CORES_PM_DISABLE));
+	return PSCI_E_SUCCESS;
+}
+
+int rockchip_soc_cores_pwr_dm_off(void)
+{
+	uint32_t cpu_id = plat_my_core_pos();
+
+	cpus_power_domain_off(cpu_id, core_pwr_wfi);
+
+	return PSCI_E_SUCCESS;
+}
+
+int rockchip_soc_cores_pwr_dm_suspend(void)
+{
+	uint32_t cpu_id = plat_my_core_pos();
+
+	assert(cpu_id < PLATFORM_CORE_COUNT);
+	assert(cpuson_flags[cpu_id] == 0);
+	cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN;
+	cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint();
+	dsb();
+
+	cpus_power_domain_off(cpu_id, core_pwr_wfi_int);
+
+	return PSCI_E_SUCCESS;
+}
+
+int rockchip_soc_cores_pwr_dm_resume(void)
+{
+	uint32_t cpu_id = plat_my_core_pos();
+
+	/* Disable core_pm */
+	mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
+		      WITH_16BITS_WMSK(CORES_PM_DISABLE));
+
+	return PSCI_E_SUCCESS;
+}
+
+#define CLK_MSK_GATING(msk, con) \
+	mmio_write_32(CRU_BASE + (con), ((msk) << 16) | 0xffff)
+#define CLK_MSK_UNGATING(msk, con) \
+	mmio_write_32(CRU_BASE + (con), ((~(msk)) << 16) | 0xffff)
+
+static uint32_t clk_ungt_msk[CRU_CLKGATES_CON_CNT] = {
+	0xe0ff, 0xffff, 0x0000, 0x0000,
+	0x0000, 0x0380, 0x0000, 0x0000,
+	0x07c0, 0x0000, 0x0000, 0x000f,
+	0x0061, 0x1f02, 0x0440, 0x1801,
+	0x004b, 0x0000
+};
+
+static uint32_t clk_pmu_ungt_msk[CRU_PMU_CLKGATE_CON_CNT] = {
+	0xf1ff, 0x0310
+};
+
+void clk_gate_suspend(void)
+{
+	int i;
+
+	for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
+		ddr_data.cru_clk_gate[i] =
+			mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i));
+			mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i),
+				      WITH_16BITS_WMSK(~clk_ungt_msk[i]));
+	}
+
+	for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++) {
+		ddr_data.cru_pmu_clk_gate[i] =
+			mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i));
+			mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i),
+				      WITH_16BITS_WMSK(~clk_pmu_ungt_msk[i]));
+	}
+}
+
+void clk_gate_resume(void)
+{
+	int i;
+
+	for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++)
+		mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i),
+			      WITH_16BITS_WMSK(ddr_data.cru_pmu_clk_gate[i]));
+
+	for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
+		mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i),
+			      WITH_16BITS_WMSK(ddr_data.cru_clk_gate[i]));
+}
+
+static void pvtm_32k_config(void)
+{
+	uint32_t  pvtm_freq_khz, pvtm_div;
+
+	ddr_data.pmu_cru_clksel_con0 =
+		mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0));
+
+	ddr_data.pgrf_pvtm_con[0] =
+		mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_CON0);
+	ddr_data.pgrf_pvtm_con[1] =
+		mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_CON1);
+
+	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,
+		      BITS_WITH_WMASK(0, 0x3, pgrf_pvtm_st));
+	dsb();
+	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,
+		      BITS_WITH_WMASK(1, 0x1, pgrf_pvtm_en));
+	dsb();
+	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON1, PVTM_CALC_CNT);
+	dsb();
+
+	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,
+		      BITS_WITH_WMASK(1, 0x1, pgrf_pvtm_st));
+
+	/* pmugrf_pvtm_st0 will be clear after PVTM start,
+	 * which will cost about 6 cycles of pvtm at least.
+	 * So we wait 30 cycles of pvtm for security.
+	 */
+	while (mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST1) < 30)
+		;
+
+	dsb();
+	while (!(mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST0) & 0x1))
+		;
+
+	pvtm_freq_khz =
+		(mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST1) * 24000 +
+		PVTM_CALC_CNT / 2) / PVTM_CALC_CNT;
+	pvtm_div = (pvtm_freq_khz + 16) / 32;
+
+	/* pvtm_div = div_factor << 2 + 1,
+	 * so div_factor = (pvtm_div - 1) >> 2.
+	 * But the operation ">> 2" will clear the low bit of pvtm_div,
+	 * so we don't have to do "- 1" for compasation
+	 */
+	pvtm_div = pvtm_div >> 2;
+	if (pvtm_div > 0x3f)
+		pvtm_div = 0x3f;
+
+	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,
+		      BITS_WITH_WMASK(pvtm_div, 0x3f, pgrf_pvtm_div));
+
+	/* select pvtm as 32k source */
+	mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0),
+		      BITS_WITH_WMASK(1, 0x3, 14));
+}
+
+static void pvtm_32k_config_restore(void)
+{
+	mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0),
+		      ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3, 14));
+
+	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,
+		      WITH_16BITS_WMSK(ddr_data.pgrf_pvtm_con[0]));
+	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON1,
+		      ddr_data.pgrf_pvtm_con[1]);
+}
+
+static void ddr_sleep_config(void)
+{
+	/* disable ddr pd, sr */
+	ddr_data.ddrc_pwrctrl = mmio_read_32(DDR_UPCTL_BASE + 0x30);
+	mmio_write_32(DDR_UPCTL_BASE + 0x30, BITS_WITH_WMASK(0x0, 0x3, 0));
+
+	/* disable ddr auto gt */
+	ddr_data.ddrgrf_con1 = mmio_read_32(DDRGRF_BASE + 0x4);
+	mmio_write_32(DDRGRF_BASE + 0x4, BITS_WITH_WMASK(0x0, 0x1f, 0));
+
+	/* disable ddr standby */
+	ddr_data.ddrstdby_con0 = mmio_read_32(DDR_STDBY_BASE + 0x0);
+	mmio_write_32(DDR_STDBY_BASE + 0x0, BITS_WITH_WMASK(0x0, 0x1, 0));
+	while ((mmio_read_32(DDR_UPCTL_BASE + 0x4) & 0x7) != 1)
+		;
+
+	/* ddr pmu ctrl */
+	ddr_data.ddrgrf_con0 = mmio_read_32(DDRGRF_BASE + 0x0);
+	mmio_write_32(DDRGRF_BASE + 0x0, BITS_WITH_WMASK(0x0, 0x1, 5));
+	dsb();
+	mmio_write_32(DDRGRF_BASE + 0x0, BITS_WITH_WMASK(0x1, 0x1, 4));
+
+	/* ddr ret sel */
+	ddr_data.pmugrf_soc_con0 =
+		mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(0));
+	mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(0),
+		      BITS_WITH_WMASK(0x0, 0x1, 12));
+}
+
+static void ddr_sleep_config_restore(void)
+{
+	/* restore ddr ret sel */
+	mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(0),
+		      ddr_data.pmugrf_soc_con0 | BITS_WMSK(0x1, 12));
+
+	/* restore ddr pmu ctrl */
+	mmio_write_32(DDRGRF_BASE + 0x0,
+		      ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 4));
+	dsb();
+	mmio_write_32(DDRGRF_BASE + 0x0,
+		      ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 5));
+
+	/* restore ddr standby */
+	mmio_write_32(DDR_STDBY_BASE + 0x0,
+		      ddr_data.ddrstdby_con0 | BITS_WMSK(0x1, 0));
+
+	/* restore ddr auto gt */
+	mmio_write_32(DDRGRF_BASE + 0x4,
+		      ddr_data.ddrgrf_con1 | BITS_WMSK(0x1f, 0));
+
+	/* restore ddr pd, sr */
+	mmio_write_32(DDR_UPCTL_BASE + 0x30,
+		      ddr_data.ddrc_pwrctrl | BITS_WMSK(0x3, 0));
+}
+
+static void pmu_sleep_config(void)
+{
+	uint32_t pwrmd_core_lo, pwrmd_core_hi, pwrmd_com_lo, pwrmd_com_hi;
+	uint32_t pmu_wkup_cfg2_lo;
+	uint32_t clk_freq_khz;
+
+	/* save pmic_sleep iomux gpio0_a4 */
+	ddr_data.pmic_slp_iomux = mmio_read_32(PMUGRF_BASE + GPIO0A_IOMUX);
+
+	ddr_data.pmu_pwrmd_core_l =
+			mmio_read_32(PMU_BASE + PMU_PWRMODE_CORE_LO);
+	ddr_data.pmu_pwrmd_core_h =
+			mmio_read_32(PMU_BASE + PMU_PWRMODE_CORE_HI);
+	ddr_data.pmu_pwrmd_cmm_l =
+			mmio_read_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_LO);
+	ddr_data.pmu_pwrmd_cmm_h =
+			mmio_read_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_HI);
+	ddr_data.pmu_wkup_cfg2_l = mmio_read_32(PMU_BASE + PMU_WKUP_CFG2_LO);
+
+	pwrmd_core_lo = BIT(pmu_global_int_dis) |
+			BIT(pmu_core_src_gt) |
+			BIT(pmu_cpu0_pd) |
+			BIT(pmu_clr_core) |
+			BIT(pmu_scu_pd) |
+			BIT(pmu_l2_idle) |
+			BIT(pmu_l2_flush) |
+			BIT(pmu_clr_bus2main) |
+			BIT(pmu_clr_peri2msch);
+
+	pwrmd_core_hi = BIT(pmu_dpll_pd_en) |
+			BIT(pmu_apll_pd_en) |
+			BIT(pmu_cpll_pd_en) |
+			BIT(pmu_gpll_pd_en) |
+			BIT(pmu_npll_pd_en);
+
+	pwrmd_com_lo = BIT(pmu_mode_en) |
+		       BIT(pmu_pll_pd) |
+		       BIT(pmu_pmu_use_if) |
+		       BIT(pmu_alive_use_if) |
+		       BIT(pmu_osc_dis) |
+		       BIT(pmu_sref_enter) |
+		       BIT(pmu_ddrc_gt) |
+		       BIT(pmu_clr_pmu) |
+		       BIT(pmu_clr_peri_pmu);
+
+	pwrmd_com_hi = BIT(pmu_clr_bus) |
+		       BIT(pmu_clr_msch) |
+		       BIT(pmu_wakeup_begin_cfg);
+
+	pmu_wkup_cfg2_lo = BIT(pmu_cluster_wkup_en) |
+			   BIT(pmu_gpio_wkup_en) |
+			   BIT(pmu_timer_wkup_en);
+
+	/* set pmic_sleep iomux gpio0_a4 */
+	mmio_write_32(PMUGRF_BASE + GPIO0A_IOMUX,
+		      BITS_WITH_WMASK(1, 0x3, 8));
+
+	clk_freq_khz = 32;
+
+	mmio_write_32(PMU_BASE + PMU_OSC_CNT_LO,
+		      WITH_16BITS_WMSK(clk_freq_khz * 32 & 0xffff));
+	mmio_write_32(PMU_BASE + PMU_OSC_CNT_HI,
+		      WITH_16BITS_WMSK(clk_freq_khz * 32 >> 16));
+
+	mmio_write_32(PMU_BASE + PMU_STABLE_CNT_LO,
+		      WITH_16BITS_WMSK(clk_freq_khz * 32 & 0xffff));
+	mmio_write_32(PMU_BASE + PMU_STABLE_CNT_HI,
+		      WITH_16BITS_WMSK(clk_freq_khz * 32 >> 16));
+
+	mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_LO,
+		      WITH_16BITS_WMSK(clk_freq_khz * 2 & 0xffff));
+	mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_HI,
+		      WITH_16BITS_WMSK(clk_freq_khz * 2 >> 16));
+
+	/* Pmu's clk has switched to 24M back When pmu FSM counts
+	 * the follow counters, so we should use 24M to calculate
+	 * these counters.
+	 */
+	mmio_write_32(PMU_BASE + PMU_SCU_PWRDN_CNT_LO,
+		      WITH_16BITS_WMSK(24000 * 2 & 0xffff));
+	mmio_write_32(PMU_BASE + PMU_SCU_PWRDN_CNT_HI,
+		      WITH_16BITS_WMSK(24000 * 2 >> 16));
+
+	mmio_write_32(PMU_BASE + PMU_SCU_PWRUP_CNT_LO,
+		      WITH_16BITS_WMSK(24000 * 2 & 0xffff));
+	mmio_write_32(PMU_BASE + PMU_SCU_PWRUP_CNT_HI,
+		      WITH_16BITS_WMSK(24000 * 2 >> 16));
+
+	mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT_LO,
+		      WITH_16BITS_WMSK(24000 * 5 & 0xffff));
+	mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT_HI,
+		      WITH_16BITS_WMSK(24000 * 5 >> 16));
+
+	mmio_write_32(PMU_BASE + PMU_PLLRST_CNT_LO,
+		      WITH_16BITS_WMSK(24000 * 2 & 0xffff));
+	mmio_write_32(PMU_BASE + PMU_PLLRST_CNT_HI,
+		      WITH_16BITS_WMSK(24000 * 2 >> 16));
+
+	/* Config pmu power mode and pmu wakeup source */
+	mmio_write_32(PMU_BASE + PMU_PWRMODE_CORE_LO,
+		      WITH_16BITS_WMSK(pwrmd_core_lo));
+	mmio_write_32(PMU_BASE + PMU_PWRMODE_CORE_HI,
+		      WITH_16BITS_WMSK(pwrmd_core_hi));
+
+	mmio_write_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_LO,
+		      WITH_16BITS_WMSK(pwrmd_com_lo));
+	mmio_write_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_HI,
+		      WITH_16BITS_WMSK(pwrmd_com_hi));
+
+	mmio_write_32(PMU_BASE + PMU_WKUP_CFG2_LO,
+		      WITH_16BITS_WMSK(pmu_wkup_cfg2_lo));
+}
+
+static void pmu_sleep_restore(void)
+{
+	mmio_write_32(PMU_BASE + PMU_PWRMODE_CORE_LO,
+		      WITH_16BITS_WMSK(ddr_data.pmu_pwrmd_core_l));
+	mmio_write_32(PMU_BASE + PMU_PWRMODE_CORE_HI,
+		      WITH_16BITS_WMSK(ddr_data.pmu_pwrmd_core_h));
+	mmio_write_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_LO,
+		      WITH_16BITS_WMSK(ddr_data.pmu_pwrmd_cmm_l));
+	mmio_write_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_HI,
+		      WITH_16BITS_WMSK(ddr_data.pmu_pwrmd_cmm_h));
+	mmio_write_32(PMU_BASE + PMU_WKUP_CFG2_LO,
+		      WITH_16BITS_WMSK(ddr_data.pmu_wkup_cfg2_l));
+
+	/* restore pmic_sleep iomux */
+	mmio_write_32(PMUGRF_BASE + GPIO0A_IOMUX,
+		      WITH_16BITS_WMSK(ddr_data.pmic_slp_iomux));
+}
+
+static void soc_sleep_config(void)
+{
+	ddr_data.gpio0c_iomux = mmio_read_32(PMUGRF_BASE + GPIO0C_IOMUX);
+
+	pmu_sleep_config();
+
+	ddr_sleep_config();
+
+	pvtm_32k_config();
+}
+
+static void soc_sleep_restore(void)
+{
+	secure_timer_init();
+
+	pvtm_32k_config_restore();
+
+	ddr_sleep_config_restore();
+
+	pmu_sleep_restore();
+
+	mmio_write_32(PMUGRF_BASE + GPIO0C_IOMUX,
+		      WITH_16BITS_WMSK(ddr_data.gpio0c_iomux));
+}
+
+static inline void pm_pll_wait_lock(uint32_t pll_base, uint32_t pll_id)
+{
+	uint32_t delay = PLL_LOCKED_TIMEOUT;
+
+	while (delay > 0) {
+		if (mmio_read_32(pll_base + PLL_CON(1)) &
+		    PLL_LOCK_MSK)
+			break;
+		delay--;
+	}
+
+	if (delay == 0)
+		ERROR("Can't wait pll:%d lock\n", pll_id);
+}
+
+static inline void pll_pwr_ctr(uint32_t pll_base, uint32_t pll_id, uint32_t pd)
+{
+	mmio_write_32(pll_base + PLL_CON(1),
+		      BITS_WITH_WMASK(1, 1, 15));
+	if (pd)
+		mmio_write_32(pll_base + PLL_CON(1),
+			      BITS_WITH_WMASK(1, 1, 14));
+	else
+		mmio_write_32(pll_base + PLL_CON(1),
+			      BITS_WITH_WMASK(0, 1, 14));
+}
+
+static inline void pll_set_mode(uint32_t pll_id, uint32_t mode)
+{
+	uint32_t val = BITS_WITH_WMASK(mode, 0x3, PLL_MODE_SHIFT(pll_id));
+
+	if (pll_id != GPLL_ID)
+		mmio_write_32(CRU_BASE + CRU_MODE, val);
+	else
+		mmio_write_32(PMUCRU_BASE + CRU_PMU_MODE,
+			      BITS_WITH_WMASK(mode, 0x3, 0));
+}
+
+static inline void pll_suspend(uint32_t pll_id)
+{
+	int i;
+	uint32_t pll_base;
+
+	if (pll_id != GPLL_ID)
+		pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0);
+	else
+		pll_base = PMUCRU_BASE + CRU_PLL_CONS(0, 0);
+
+	/* save pll con */
+	for (i = 0; i < PLL_CON_CNT; i++)
+		ddr_data.cru_plls_con_save[pll_id][i] =
+				mmio_read_32(pll_base + PLL_CON(i));
+
+	/* slow mode */
+	pll_set_mode(pll_id, SLOW_MODE);
+}
+
+static inline void pll_resume(uint32_t pll_id)
+{
+	uint32_t mode, pll_base;
+
+	if (pll_id != GPLL_ID) {
+		pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0);
+		mode = (ddr_data.cru_mode_save >> PLL_MODE_SHIFT(pll_id)) & 0x3;
+	} else {
+		pll_base = PMUCRU_BASE + CRU_PLL_CONS(0, 0);
+		mode = ddr_data.cru_pmu_mode_save & 0x3;
+	}
+
+	/* if pll locked before suspend, we should wait atfer resume */
+	if (ddr_data.cru_plls_con_save[pll_id][1] & PLL_LOCK_MSK)
+		pm_pll_wait_lock(pll_base, pll_id);
+
+	pll_set_mode(pll_id, mode);
+}
+
+static void pm_plls_suspend(void)
+{
+	ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_MODE);
+	ddr_data.cru_pmu_mode_save = mmio_read_32(PMUCRU_BASE + CRU_PMU_MODE);
+	ddr_data.clk_sel0 = mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(0));
+
+	pll_suspend(GPLL_ID);
+	pll_suspend(NPLL_ID);
+	pll_suspend(CPLL_ID);
+	pll_suspend(APLL_ID);
+
+	/* core */
+	mmio_write_32(CRU_BASE + CRU_CLKSELS_CON(0),
+		      BITS_WITH_WMASK(0, 0xf, 0));
+
+	/* pclk_dbg */
+	mmio_write_32(CRU_BASE + CRU_CLKSELS_CON(0),
+		      BITS_WITH_WMASK(0, 0xf, 8));
+}
+
+static void pm_plls_resume(void)
+{
+	/* pclk_dbg */
+	mmio_write_32(CRU_BASE + CRU_CLKSELS_CON(0),
+		      ddr_data.clk_sel0 | BITS_WMSK(0xf, 8));
+
+	/* core */
+	mmio_write_32(CRU_BASE + CRU_CLKSELS_CON(0),
+		      ddr_data.clk_sel0 | BITS_WMSK(0xf, 0));
+
+	pll_resume(APLL_ID);
+	pll_resume(CPLL_ID);
+	pll_resume(NPLL_ID);
+	pll_resume(GPLL_ID);
+}
+
+int rockchip_soc_sys_pwr_dm_suspend(void)
+{
+	pmu_power_domains_suspend();
+
+	clk_gate_suspend();
+
+	soc_sleep_config();
+
+	pm_plls_suspend();
+
+	psram_boot_cfg->pm_flag &= ~PM_WARM_BOOT_BIT;
+
+	return 0;
+}
+
+int rockchip_soc_sys_pwr_dm_resume(void)
+{
+	psram_boot_cfg->pm_flag |= PM_WARM_BOOT_BIT;
+
+	pm_plls_resume();
+
+	soc_sleep_restore();
+
+	clk_gate_resume();
+
+	pmu_power_domains_resume();
+
+	plat_rockchip_gic_cpuif_enable();
+
+	return 0;
+}
+
+void __dead2 rockchip_soc_soft_reset(void)
+{
+	pll_set_mode(GPLL_ID, SLOW_MODE);
+	pll_set_mode(CPLL_ID, SLOW_MODE);
+	pll_set_mode(NPLL_ID, SLOW_MODE);
+	pll_set_mode(APLL_ID, SLOW_MODE);
+	dsb();
+
+	mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, CRU_GLB_SRST_FST_VALUE);
+	dsb();
+
+	/*
+	 * Maybe the HW needs some times to reset the system,
+	 * so we do not hope the core to execute valid codes.
+	 */
+	psci_power_down_wfi();
+}
+
+void __dead2 rockchip_soc_system_off(void)
+{
+	uint32_t val;
+
+	/* set pmic_sleep pin(gpio0_a4) to gpio mode */
+	mmio_write_32(PMUGRF_BASE + GPIO0A_IOMUX, BITS_WITH_WMASK(0, 0x3, 8));
+
+	/* config output */
+	val = mmio_read_32(GPIO0_BASE + SWPORTA_DDR);
+	val |= BIT(4);
+	mmio_write_32(GPIO0_BASE + SWPORTA_DDR, val);
+
+	/* config output high level */
+	val = mmio_read_32(GPIO0_BASE);
+	val |= BIT(4);
+	mmio_write_32(GPIO0_BASE, val);
+	dsb();
+
+	/*
+	 * Maybe the HW needs some times to reset the system,
+	 * so we do not hope the core to execute valid codes.
+	 */
+	psci_power_down_wfi();
+}
+
+void rockchip_plat_mmu_el3(void)
+{
+	/* TODO: support the el3 for px30 SoCs */
+}
+
+void plat_rockchip_pmu_init(void)
+{
+	uint32_t cpu;
+
+	rockchip_pd_lock_init();
+
+	for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++)
+		cpuson_flags[cpu] = 0;
+
+	psram_boot_cfg->ddr_func = (uint64_t)0;
+	psram_boot_cfg->ddr_data = (uint64_t)0;
+	psram_boot_cfg->sp = PSRAM_SP_TOP;
+	psram_boot_cfg->ddr_flag = 0x0;
+	psram_boot_cfg->boot_mpidr = read_mpidr_el1() & 0xffff;
+	psram_boot_cfg->pm_flag = PM_WARM_BOOT_BIT;
+
+	nonboot_cpus_off();
+
+	/* Remap pmu_sram's base address to boot address */
+	mmio_write_32(PMUSGRF_BASE + PMUSGRF_SOC_CON(0),
+		      BITS_WITH_WMASK(1, 0x1, 13));
+
+	INFO("%s: pd status %x\n",
+	     __func__, mmio_read_32(PMU_BASE + PMU_PWRDN_ST));
+}
diff --git a/plat/rockchip/px30/drivers/pmu/pmu.h b/plat/rockchip/px30/drivers/pmu/pmu.h
new file mode 100644
index 0000000..416d1c1
--- /dev/null
+++ b/plat/rockchip/px30/drivers/pmu/pmu.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PMU_H__
+#define __PMU_H__
+
+/* Needed aligned 16 bytes for sp stack top */
+#define PSRAM_SP_TOP		((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf)
+
+/*****************************************************************************
+ * pmu con,reg
+ *****************************************************************************/
+#define PMU_WKUP_CFG0_LO		0x00
+#define PMU_WKUP_CFG0_HI		0x04
+#define PMU_WKUP_CFG1_LO		0x08
+#define PMU_WKUP_CFG1_HI		0x0c
+#define PMU_WKUP_CFG2_LO		0x10
+
+#define PMU_PWRDN_CON			0x18
+#define PMU_PWRDN_ST			0x20
+
+#define PMU_PWRMODE_CORE_LO		0x24
+#define PMU_PWRMODE_CORE_HI		0x28
+#define PMU_PWRMODE_COMMON_CON_LO	0x2c
+#define PMU_PWRMODE_COMMON_CON_HI	0x30
+
+#define PMU_SFT_CON			0x34
+#define PMU_INT_ST			0x44
+#define PMU_BUS_IDLE_REQ		0x64
+#define PMU_BUS_IDLE_ST			0x6c
+
+#define PMU_OSC_CNT_LO			0x74
+#define PMU_OSC_CNT_HI			0x78
+#define PMU_PLLLOCK_CNT_LO		0x7c
+#define PMU_PLLLOCK_CNT_HI		0x80
+#define PMU_PLLRST_CNT_LO		0x84
+#define PMU_PLLRST_CNT_HI		0x88
+#define PMU_STABLE_CNT_LO		0x8c
+#define PMU_STABLE_CNT_HI		0x90
+#define PMU_WAKEUP_RST_CLR_LO		0x9c
+#define PMU_WAKEUP_RST_CLR_HI		0xa0
+
+#define PMU_DDR_SREF_ST			0xa4
+
+#define PMU_SYS_REG0_LO			0xa8
+#define PMU_SYS_REG0_HI			0xac
+#define PMU_SYS_REG1_LO			0xb0
+#define PMU_SYS_REG1_HI			0xb4
+#define PMU_SYS_REG2_LO			0xb8
+#define PMU_SYS_REG2_HI			0xbc
+#define PMU_SYS_REG3_LO			0xc0
+#define PMU_SYS_REG3_HI			0xc4
+
+#define PMU_SCU_PWRDN_CNT_LO		0xc8
+#define PMU_SCU_PWRDN_CNT_HI		0xcc
+#define PMU_SCU_PWRUP_CNT_LO		0xd0
+#define PMU_SCU_PWRUP_CNT_HI		0xd4
+
+#define PMU_TIMEOUT_CNT_LO		0xd8
+#define PMU_TIMEOUT_CNT_HI		0xdc
+
+#define PMU_CPUAPM_CON(cpu)		(0xe0 + (cpu) * 0x4)
+
+#define CORES_PM_DISABLE	0x0
+#define CLST_CPUS_MSK		0xf
+
+#define PD_CTR_LOOP		500
+#define PD_CHECK_LOOP		500
+#define WFEI_CHECK_LOOP		500
+#define BUS_IDLE_LOOP		1000
+
+enum pmu_wkup_cfg2 {
+	pmu_cluster_wkup_en = 0,
+	pmu_gpio_wkup_en = 2,
+	pmu_sdio_wkup_en = 3,
+	pmu_sdmmc_wkup_en = 4,
+	pmu_uart0_wkup_en = 5,
+	pmu_timer_wkup_en = 6,
+	pmu_usbdev_wkup_en = 7,
+	pmu_sft_wkup_en = 8,
+	pmu_timeout_wkup_en = 10,
+};
+
+enum pmu_powermode_core_lo {
+	pmu_global_int_dis = 0,
+	pmu_core_src_gt = 1,
+	pmu_cpu0_pd = 3,
+	pmu_clr_core = 5,
+	pmu_scu_pd = 6,
+	pmu_l2_idle = 8,
+	pmu_l2_flush = 9,
+	pmu_clr_bus2main = 10,
+	pmu_clr_peri2msch = 11,
+};
+
+enum pmu_powermode_core_hi {
+	pmu_apll_pd_en = 3,
+	pmu_dpll_pd_en = 4,
+	pmu_cpll_pd_en = 5,
+	pmu_gpll_pd_en = 6,
+	pmu_npll_pd_en = 7,
+};
+
+enum pmu_powermode_common_lo {
+	pmu_mode_en = 0,
+	pmu_ddr_pd_en = 1,
+	pmu_wkup_rst = 3,
+	pmu_pll_pd = 4,
+	pmu_pmu_use_if = 6,
+	pmu_alive_use_if = 7,
+	pmu_osc_dis = 8,
+	pmu_input_clamp = 9,
+	pmu_sref_enter = 10,
+	pmu_ddrc_gt = 11,
+	pmu_ddrio_ret = 12,
+	pmu_ddrio_ret_deq = 13,
+	pmu_clr_pmu = 14,
+	pmu_clr_peri_pmu = 15,
+};
+
+enum pmu_powermode_common_hi {
+	pmu_clr_bus = 0,
+	pmu_clr_mmc = 1,
+	pmu_clr_msch = 2,
+	pmu_clr_nandc = 3,
+	pmu_clr_gmac = 4,
+	pmu_clr_vo = 5,
+	pmu_clr_vi = 6,
+	pmu_clr_gpu = 7,
+	pmu_clr_usb = 8,
+	pmu_clr_vpu = 9,
+	pmu_clr_crypto = 10,
+	pmu_wakeup_begin_cfg = 11,
+	pmu_peri_clk_src_gt = 12,
+	pmu_bus_clk_src_gt = 13,
+};
+
+enum pmu_pd_id {
+	PD_CPU0 = 0,
+	PD_CPU1 = 1,
+	PD_CPU2 = 2,
+	PD_CPU3 = 3,
+	PD_SCU = 4,
+	PD_USB = 5,
+	PD_DDR = 6,
+	PD_SDCARD = 8,
+	PD_CRYPTO = 9,
+	PD_GMAC = 10,
+	PD_MMC_NAND = 11,
+	PD_VPU = 12,
+	PD_VO = 13,
+	PD_VI = 14,
+	PD_GPU = 15,
+	PD_END = 16,
+};
+
+enum pmu_bus_id {
+	BUS_ID_BUS = 0,
+	BUS_ID_BUS2MAIN = 1,
+	BUS_ID_GPU = 2,
+	BUS_ID_CORE = 3,
+	BUS_ID_CRYPTO = 4,
+	BUS_ID_MMC = 5,
+	BUS_ID_GMAC = 6,
+	BUS_ID_VO = 7,
+	BUS_ID_VI = 8,
+	BUS_ID_SDCARD = 9,
+	BUS_ID_USB = 10,
+	BUS_ID_MSCH = 11,
+	BUS_ID_PERI = 12,
+	BUS_ID_PMU = 13,
+	BUS_ID_VPU = 14,
+	BUS_ID_PERI2MSCH = 15,
+};
+
+enum pmu_pd_state {
+	pmu_pd_on = 0,
+	pmu_pd_off = 1
+};
+
+enum pmu_bus_state {
+	bus_active = 0,
+	bus_idle = 1,
+};
+
+enum cores_pm_ctr_mode {
+	core_pwr_pd = 0,
+	core_pwr_wfi = 1,
+	core_pwr_wfi_int = 2
+};
+
+enum pmu_cores_pm_by_wfi {
+	core_pm_en = 0,
+	core_pm_int_wakeup_en,
+	core_pm_dis_int,
+	core_pm_sft_wakeup_en
+};
+
+/*****************************************************************************
+ * pmu_sgrf
+ *****************************************************************************/
+#define PMUSGRF_SOC_CON(i)	((i) * 0x4)
+
+/*****************************************************************************
+ * pmu_grf
+ *****************************************************************************/
+#define GPIO0A_IOMUX		0x0
+#define GPIO0B_IOMUX		0x4
+#define GPIO0C_IOMUX		0x8
+#define GPIO0A_PULL		0x10
+
+#define GPIO0L_SMT		0x38
+#define GPIO0H_SMT		0x3c
+
+#define PMUGRF_SOC_CON(i)	(0x100 + (i) * 4)
+
+#define PMUGRF_PVTM_CON0	0x180
+#define PMUGRF_PVTM_CON1	0x184
+#define PMUGRF_PVTM_ST0		0x190
+#define PMUGRF_PVTM_ST1		0x194
+
+#define PVTM_CALC_CNT		0x200
+
+#define PMUGRF_OS_REG(n)	(0x200 + (n) * 4)
+
+#define GPIO0A6_IOMUX_MSK	(0x3 << 12)
+#define GPIO0A6_IOMUX_GPIO	(0x0 << 12)
+#define GPIO0A6_IOMUX_RSTOUT	(0x1 << 12)
+#define GPIO0A6_IOMUX_SHTDN	(0x2 << 12)
+
+enum px30_pmugrf_pvtm_con0 {
+	pgrf_pvtm_st = 0,
+	pgrf_pvtm_en = 1,
+	pgrf_pvtm_div = 2,
+};
+
+/*****************************************************************************
+ * pmu_cru
+ *****************************************************************************/
+#define CRU_PMU_MODE			0x20
+#define CRU_PMU_CLKSEL_CON		0x40
+#define CRU_PMU_CLKSELS_CON(i)		(CRU_PMU_CLKSEL_CON + (i) * 4)
+#define CRU_PMU_CLKSEL_CON_CNT		5
+#define CRU_PMU_CLKGATE_CON		0x80
+#define CRU_PMU_CLKGATES_CON(i)		(CRU_PMU_CLKGATE_CON + (i) * 4)
+#define CRU_PMU_CLKGATE_CON_CNT		2
+#define CRU_PMU_ATCS_CON		0xc0
+#define CRU_PMU_ATCSS_CON(i)		(CRU_PMU_ATCS_CON + (i) * 4)
+#define CRU_PMU_ATCS_CON_CNT		2
+
+/*****************************************************************************
+ * pmusgrf
+ *****************************************************************************/
+#define PMUSGRF_RSTOUT_EN (0x7 << 10)
+#define PMUSGRF_RSTOUT_FST 10
+#define PMUSGRF_RSTOUT_TSADC 11
+#define PMUSGRF_RSTOUT_WDT 12
+
+#define PMUGRF_SOC_CON2_US_WMSK  (0x1fff << 16)
+#define PMUGRF_SOC_CON2_MAX_341US  0x1fff
+#define PMUGRF_SOC_CON2_200US  0x12c0
+
+#define PMUGRF_FAILSAFE_SHTDN_TSADC BIT(0)
+#define PMUGRF_FAILSAFE_SHTDN_WDT BIT(1)
+
+/*****************************************************************************
+ * QOS
+ *****************************************************************************/
+#define CPU_AXI_QOS_ID_COREID		0x00
+#define CPU_AXI_QOS_REVISIONID		0x04
+#define CPU_AXI_QOS_PRIORITY		0x08
+#define CPU_AXI_QOS_MODE		0x0c
+#define CPU_AXI_QOS_BANDWIDTH		0x10
+#define CPU_AXI_QOS_SATURATION		0x14
+#define CPU_AXI_QOS_EXTCONTROL		0x18
+#define CPU_AXI_QOS_NUM_REGS		0x07
+
+#define CPU_AXI_CPU_QOS_BASE		0xff508000
+#define CPU_AXI_GPU_QOS_BASE		0xff520000
+#define CPU_AXI_ISP_128M_QOS_BASE	0xff548000
+#define CPU_AXI_ISP_RD_QOS_BASE		0xff548080
+#define CPU_AXI_ISP_WR_QOS_BASE		0xff548100
+#define CPU_AXI_ISP_M1_QOS_BASE		0xff548180
+#define CPU_AXI_VIP_QOS_BASE		0xff548200
+#define CPU_AXI_RGA_RD_QOS_BASE		0xff550000
+#define CPU_AXI_RGA_WR_QOS_BASE		0xff550080
+#define CPU_AXI_VOP_M0_QOS_BASE		0xff550100
+#define CPU_AXI_VOP_M1_QOS_BASE		0xff550180
+#define CPU_AXI_VPU_QOS_BASE		0xff558000
+#define CPU_AXI_VPU_R128_QOS_BASE	0xff558080
+#define CPU_AXI_DCF_QOS_BASE		0xff500000
+#define CPU_AXI_DMAC_QOS_BASE		0xff500080
+#define CPU_AXI_CRYPTO_QOS_BASE		0xff510000
+#define CPU_AXI_GMAC_QOS_BASE		0xff518000
+#define CPU_AXI_EMMC_QOS_BASE		0xff538000
+#define CPU_AXI_NAND_QOS_BASE		0xff538080
+#define CPU_AXI_SDIO_QOS_BASE		0xff538100
+#define CPU_AXI_SFC_QOS_BASE		0xff538180
+#define CPU_AXI_SDMMC_QOS_BASE		0xff52c000
+#define CPU_AXI_USB_HOST_QOS_BASE	0xff540000
+#define CPU_AXI_USB_OTG_QOS_BASE	0xff540080
+
+#define PX30_CPU_AXI_SAVE_QOS(array, base) do { \
+	array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \
+	array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \
+	array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \
+	array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \
+	array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \
+	array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \
+	array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \
+} while (0)
+
+#define PX30_CPU_AXI_RESTORE_QOS(array, base) do { \
+	mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \
+	mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \
+	mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \
+	mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \
+	mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \
+	mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \
+	mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \
+} while (0)
+
+#define SAVE_QOS(array, NAME) \
+	PX30_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
+#define RESTORE_QOS(array, NAME) \
+	PX30_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
+
+#endif /* __PMU_H__ */
diff --git a/plat/rockchip/px30/drivers/soc/soc.c b/plat/rockchip/px30/drivers/soc/soc.c
new file mode 100644
index 0000000..e00561d
--- /dev/null
+++ b/plat/rockchip/px30/drivers/soc/soc.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <ddr_parameter.h>
+#include <platform_def.h>
+#include <pmu.h>
+#include <px30_def.h>
+#include <soc.h>
+#include <rockchip_sip_svc.h>
+
+/* Aggregate of all devices in the first GB */
+#define PX30_DEV_RNG0_BASE	0xff000000
+#define PX30_DEV_RNG0_SIZE	0x00ff0000
+
+const mmap_region_t plat_rk_mmap[] = {
+	MAP_REGION_FLAT(PX30_DEV_RNG0_BASE, PX30_DEV_RNG0_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	{ 0 }
+};
+
+/* The RockChip power domain tree descriptor */
+const unsigned char rockchip_power_domain_tree_desc[] = {
+	/* No of root nodes */
+	PLATFORM_SYSTEM_COUNT,
+	/* No of children for the root node */
+	PLATFORM_CLUSTER_COUNT,
+	/* No of children for the first cluster node */
+	PLATFORM_CLUSTER0_CORE_COUNT,
+};
+
+void clk_gate_con_save(uint32_t *clkgt_save)
+{
+	uint32_t i, j;
+
+	for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
+		clkgt_save[i] =
+			mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i));
+	j = i;
+	for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++)
+		clkgt_save[j] =
+			mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i));
+}
+
+void clk_gate_con_restore(uint32_t *clkgt_save)
+{
+	uint32_t i, j;
+
+	for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
+		mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i),
+			      WITH_16BITS_WMSK(clkgt_save[i]));
+
+	j = i;
+	for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++)
+		mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i),
+			      WITH_16BITS_WMSK(clkgt_save[j]));
+}
+
+void clk_gate_con_disable(void)
+{
+	uint32_t i;
+
+	for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
+		mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i),
+			      0xffff0000);
+
+	for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++)
+		mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i),
+			      0xffff0000);
+}
+
+void secure_timer_init(void)
+{
+	mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
+		      TIMER_DIS);
+
+	mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
+	mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
+
+	/* auto reload & enable the timer */
+	mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
+		      TIMER_EN | TIMER_FMODE);
+}
+
+static void sgrf_init(void)
+{
+	uint32_t i, val;
+	struct param_ddr_usage usg;
+
+	/* general secure regions */
+	usg = ddr_region_usage_parse(DDR_PARAM_BASE,
+				     PLAT_MAX_DDR_CAPACITY_MB);
+	for (i = 0; i < usg.s_nr; i++) {
+		/* enable secure */
+		val = mmio_read_32(FIREWALL_DDR_BASE +
+			      FIREWALL_DDR_FW_DDR_CON_REG);
+		val |= BIT(7 - i);
+		mmio_write_32(FIREWALL_DDR_BASE +
+			      FIREWALL_DDR_FW_DDR_CON_REG, val);
+		/* map top and base */
+		mmio_write_32(FIREWALL_DDR_BASE +
+			      FIREWALL_DDR_FW_DDR_RGN(7 - i),
+			      RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
+	}
+
+	/* set ddr rgn0_top and rga0_top as 0 */
+	mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
+
+	/* set all slave ip into no-secure, except stimer */
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS);
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS);
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS);
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS);
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000);
+
+	/* set master crypto to no-secure, dcf to secure */
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003);
+
+	/* set DMAC into no-secure */
+	mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS);
+	mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0);
+	mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16);
+	mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS);
+
+	/* soft reset dma before use */
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ);
+	udelay(5);
+	mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS);
+}
+
+static void soc_reset_config_all(void)
+{
+	uint32_t tmp;
+
+	/* tsadc and wdt can trigger a first rst */
+	tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON);
+	tmp |= CRU_GLB_RST_TSADC_FST | CRU_GLB_RST_WDT_FST;
+	mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp);
+	return;
+	tmp = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(3));
+	tmp &= ~(PMUGRF_FAILSAFE_SHTDN_TSADC | PMUGRF_FAILSAFE_SHTDN_WDT);
+	mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(3), tmp);
+
+	/* wdt pin rst eable */
+	mmio_write_32(GRF_BASE + GRF_SOC_CON(2),
+		      BIT_WITH_WMSK(GRF_SOC_CON2_NSWDT_RST_EN));
+}
+
+void px30_soc_reset_config(void)
+{
+	uint32_t tmp;
+
+	/* enable soc ip rst hold time cfg */
+	tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON);
+	tmp |= BIT(CRU_GLB_RST_TSADC_EXT) | BIT(CRU_GLB_RST_WDT_EXT);
+	mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp);
+	/* soc ip rst hold time, 24m */
+	tmp = mmio_read_32(CRU_BASE + CRU_GLB_CNT_TH);
+	tmp &= ~CRU_GLB_CNT_RST_MSK;
+	tmp |= (CRU_GLB_CNT_RST_1MS / 2);
+	mmio_write_32(CRU_BASE + CRU_GLB_CNT_TH, tmp);
+
+	mmio_write_32(PMUSGRF_BASE + PMUSGRF_SOC_CON(0),
+		      BIT_WITH_WMSK(PMUSGRF_RSTOUT_FST) |
+		      BIT_WITH_WMSK(PMUSGRF_RSTOUT_TSADC) |
+		      BIT_WITH_WMSK(PMUSGRF_RSTOUT_WDT));
+
+	/* rst_out pulse time */
+	mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(2),
+		      PMUGRF_SOC_CON2_MAX_341US | PMUGRF_SOC_CON2_US_WMSK);
+
+	soc_reset_config_all();
+}
+
+void plat_rockchip_soc_init(void)
+{
+	secure_timer_init();
+	sgrf_init();
+}
diff --git a/plat/rockchip/px30/drivers/soc/soc.h b/plat/rockchip/px30/drivers/soc/soc.h
new file mode 100644
index 0000000..69f2de4
--- /dev/null
+++ b/plat/rockchip/px30/drivers/soc/soc.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#include <plat_private.h>
+
+#ifndef BITS_WMSK
+#define BITS_WMSK(msk, shift)	((msk) << (shift + REG_MSK_SHIFT))
+#endif
+
+enum plls_id {
+	APLL_ID = 0,
+	DPLL_ID,
+	CPLL_ID,
+	NPLL_ID,
+	GPLL_ID,
+	END_PLL_ID,
+};
+
+enum pll_mode {
+	SLOW_MODE,
+	NORM_MODE,
+	DEEP_SLOW_MODE,
+};
+
+/***************************************************************************
+ * SGRF
+ ***************************************************************************/
+#define SGRF_SOC_CON(i)		((i) * 0x4)
+#define SGRF_DMAC_CON(i)	(0x30 + (i) * 0x4)
+
+#define SGRF_MST_S_ALL_NS	0xffffffff
+#define SGRF_SLV_S_ALL_NS	0xffff0000
+#define DMA_IRQ_BOOT_NS		0xffffffff
+#define DMA_PERI_CH_NS_15_0	0xffffffff
+#define DMA_PERI_CH_NS_19_16	0x000f000f
+#define DMA_MANAGER_BOOT_NS	0x00010001
+#define DMA_SOFTRST_REQ		BITS_WITH_WMASK(1, 0x1, 12)
+#define DMA_SOFTRST_RLS		BITS_WITH_WMASK(0, 0x1, 12)
+
+/***************************************************************************
+ * GRF
+ ***************************************************************************/
+#define GRF_SOC_CON(i)		(0x0400 + (i) * 4)
+#define GRF_PD_VO_CON0		0x0434
+#define GRF_SOC_STATUS0		0x0480
+#define GRF_CPU_STATUS0		0x0520
+#define GRF_CPU_STATUS1		0x0524
+#define GRF_SOC_NOC_CON0	0x0530
+#define GRF_SOC_NOC_CON1	0x0534
+
+#define CKECK_WFE_MSK		0x1
+#define CKECK_WFI_MSK		0x10
+#define CKECK_WFEI_MSK		0x11
+
+#define GRF_SOC_CON2_NSWDT_RST_EN 12
+
+/***************************************************************************
+ * DDR FIREWALL
+ ***************************************************************************/
+#define FIREWALL_DDR_FW_DDR_RGN(i)	((i) * 0x4)
+#define FIREWALL_DDR_FW_DDR_MST(i)	(0x20 + (i) * 0x4)
+#define FIREWALL_DDR_FW_DDR_CON_REG	0x40
+#define FIREWALL_DDR_FW_DDR_RGN_NUM	8
+#define FIREWALL_DDR_FW_DDR_MST_NUM	6
+
+#define PLAT_MAX_DDR_CAPACITY_MB	4096
+#define RG_MAP_SECURE(top, base)	((((top) - 1) << 16) | (base))
+
+/***************************************************************************
+ * cru
+ ***************************************************************************/
+#define CRU_MODE		0xa0
+#define CRU_MISC		0xa4
+#define CRU_GLB_CNT_TH	0xb0
+#define CRU_GLB_RST_ST	0xb4
+#define CRU_GLB_SRST_FST	0xb8
+#define CRU_GLB_SRST_SND	0xbc
+#define CRU_GLB_RST_CON		0xc0
+
+#define CRU_CLKSEL_CON		0x100
+#define CRU_CLKSELS_CON(i)	(CRU_CLKSEL_CON + (i) * 4)
+#define CRU_CLKSEL_CON_CNT	60
+
+#define CRU_CLKGATE_CON		0x200
+#define CRU_CLKGATES_CON(i)	(CRU_CLKGATE_CON + (i) * 4)
+#define CRU_CLKGATES_CON_CNT	18
+
+#define CRU_SOFTRST_CON		0x300
+#define CRU_SOFTRSTS_CON(n)	(CRU_SOFTRST_CON + ((n) * 4))
+#define CRU_SOFTRSTS_CON_CNT	12
+
+#define CRU_AUTOCS_CON0(id)	(0x400 + (id) * 8)
+#define CRU_AUTOCS_CON1(id)	(0x404 + (id) * 8)
+
+#define CRU_CONS_GATEID(i)	(16 * (i))
+#define GATE_ID(reg, bit)	((reg) * 16 + (bit))
+
+#define CRU_GLB_SRST_FST_VALUE	0xfdb9
+#define CRU_GLB_SRST_SND_VALUE	0xeca8
+
+#define CRU_GLB_RST_TSADC_EXT 6
+#define CRU_GLB_RST_WDT_EXT 7
+
+#define CRU_GLB_CNT_RST_MSK  0xffff
+#define CRU_GLB_CNT_RST_1MS  0x5DC0
+
+#define CRU_GLB_RST_TSADC_FST BIT(0)
+#define CRU_GLB_RST_WDT_FST BIT(1)
+
+/***************************************************************************
+ * pll
+ ***************************************************************************/
+#define CRU_PLL_CONS(id, i)	((id) * 0x20 + (i) * 4)
+#define PLL_CON(i)		((i) * 4)
+#define PLL_CON_CNT		5
+#define PLL_LOCK_MSK		BIT(10)
+#define PLL_MODE_SHIFT(id)	((id) == CPLL_ID ? \
+				  2 : \
+				  ((id) == DPLL_ID ? 4 : 2 * (id)))
+#define PLL_MODE_MSK(id)	(0x3 << PLL_MODE_SHIFT(id))
+
+#define PLL_LOCKED_TIMEOUT	600000U
+
+/***************************************************************************
+ * GPIO
+ ***************************************************************************/
+#define SWPORTA_DR		0x00
+#define SWPORTA_DDR		0x04
+#define GPIO_INTEN		0x30
+#define GPIO_INT_STATUS		0x40
+#define GPIO_NUMS		4
+
+/**************************************************
+ * secure timer
+ **************************************************/
+
+/* chanal0~5 */
+#define STIMER_CHN_BASE(n)	(STIME_BASE + 0x20 * (n))
+
+#define TIMER_LOAD_COUNT0	0x0
+#define TIMER_LOAD_COUNT1	0x4
+
+#define TIMER_CUR_VALUE0	0x8
+#define TIMER_CUR_VALUE1	0xc
+
+#define TIMER_CONTROL_REG	0x10
+#define TIMER_INTSTATUS		0x18
+
+#define TIMER_DIS		0x0
+#define TIMER_EN		0x1
+
+#define TIMER_FMODE		(0x0 << 1)
+#define TIMER_RMODE		(0x1 << 1)
+
+#define TIMER_LOAD_COUNT0_MSK	(0xffffffff)
+#define TIMER_LOAD_COUNT1_MSK	(0xffffffff00000000)
+
+void clk_gate_con_save(uint32_t *clkgt_save);
+void clk_gate_con_restore(uint32_t *clkgt_save);
+void clk_gate_con_disable(void);
+
+void secure_timer_init(void);
+void secure_timer_disable(void);
+void px30_soc_reset_config(void);
+
+#endif /* __SOC_H__ */
diff --git a/plat/rockchip/px30/include/plat.ld.S b/plat/rockchip/px30/include/plat.ld.S
new file mode 100644
index 0000000..44cca0d
--- /dev/null
+++ b/plat/rockchip/px30/include/plat.ld.S
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ROCKCHIP_PLAT_LD_S__
+#define __ROCKCHIP_PLAT_LD_S__
+
+MEMORY {
+    PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
+}
+
+SECTIONS
+{
+	. = PMUSRAM_BASE;
+
+	/*
+	 * pmu_cpuson_entrypoint request address
+	 * align 64K when resume, so put it in the
+	 * start of pmusram
+	 */
+	.pmusram : {
+		ASSERT(. == ALIGN(64 * 1024),
+			".pmusram.entry request 64K aligned.");
+		KEEP(*(.pmusram.entry))
+
+		__bl31_pmusram_text_start = .;
+		*(.pmusram.text)
+		*(.pmusram.rodata)
+		__bl31_pmusram_text_end = .;
+		__bl31_pmusram_data_start = .;
+		*(.pmusram.data)
+		__bl31_pmusram_data_end = .;
+	} >PMUSRAM
+}
+
+#endif /* __ROCKCHIP_PLAT_LD_S__ */
diff --git a/plat/rockchip/px30/include/plat_sip_calls.h b/plat/rockchip/px30/include/plat_sip_calls.h
new file mode 100644
index 0000000..7b6a6a8
--- /dev/null
+++ b/plat/rockchip/px30/include/plat_sip_calls.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_SIP_CALLS_H__
+#define __PLAT_SIP_CALLS_H__
+
+#define RK_PLAT_SIP_NUM_CALLS	0
+
+#endif /* __PLAT_SIP_CALLS_H__ */
diff --git a/plat/rockchip/px30/include/platform_def.h b/plat/rockchip/px30/include/platform_def.h
new file mode 100644
index 0000000..c101cdc
--- /dev/null
+++ b/plat/rockchip/px30/include/platform_def.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <arch.h>
+#include <common_def.h>
+#include <px30_def.h>
+
+#define DEBUG_XLAT_TABLE 0
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+/* Size of cacheable stacks */
+#if DEBUG_XLAT_TABLE
+#define PLATFORM_STACK_SIZE 0x800
+#elif IMAGE_BL1
+#define PLATFORM_STACK_SIZE 0x440
+#elif IMAGE_BL2
+#define PLATFORM_STACK_SIZE 0x400
+#elif IMAGE_BL31
+#define PLATFORM_STACK_SIZE 0x800
+#elif IMAGE_BL32
+#define PLATFORM_STACK_SIZE 0x440
+#endif
+
+#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
+
+#define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL2
+#define PLATFORM_SYSTEM_COUNT		1
+#define PLATFORM_CLUSTER_COUNT		1
+#define PLATFORM_CLUSTER0_CORE_COUNT	4
+#define PLATFORM_CLUSTER1_CORE_COUNT	0
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT +	\
+					 PLATFORM_CLUSTER0_CORE_COUNT)
+
+#define PLATFORM_NUM_AFFS		(PLATFORM_SYSTEM_COUNT +	\
+					 PLATFORM_CLUSTER_COUNT +	\
+					 PLATFORM_CORE_COUNT)
+
+#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL2
+
+#define PLAT_RK_CLST_TO_CPUID_SHIFT	8
+
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * id will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE		1
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE		2
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+/* TF txet, ro, rw, Size: 512KB */
+#define TZRAM_BASE		(0x0)
+#define TZRAM_SIZE		(0x80000)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted RAM
+ */
+#define BL31_BASE		(TZRAM_BASE + 0x10000)
+#define BL31_LIMIT		(TZRAM_BASE + TZRAM_SIZE)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_VIRT_ADDR_SPACE_SIZE   (1ull << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE    (1ull << 32)
+#define ADDR_SPACE_SIZE		(1ull << 32)
+#define MAX_XLAT_TABLES		8
+#define MAX_MMAP_REGIONS	27
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT	6
+#define CACHE_WRITEBACK_GRANULE	(1 << CACHE_WRITEBACK_SHIFT)
+
+/*
+ * Define GICD and GICC and GICR base
+ */
+#define PLAT_RK_GICD_BASE	PX30_GICD_BASE
+#define PLAT_RK_GICC_BASE	PX30_GICC_BASE
+
+#define PLAT_RK_UART_BASE	PX30_UART_BASE
+#define PLAT_RK_UART_CLOCK	PX30_UART_CLOCK
+#define PLAT_RK_UART_BAUDRATE	PX30_BAUDRATE
+
+#define PLAT_RK_PRIMARY_CPU	0x0
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/rockchip/px30/plat_sip_calls.c b/plat/rockchip/px30/plat_sip_calls.c
new file mode 100644
index 0000000..a4b8e55
--- /dev/null
+++ b/plat/rockchip/px30/plat_sip_calls.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <lib/mmio.h>
+
+#include <plat_sip_calls.h>
+#include <rockchip_sip_svc.h>
+
+uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid,
+				    u_register_t x1,
+				    u_register_t x2,
+				    u_register_t x3,
+				    u_register_t x4,
+				    void *cookie,
+				    void *handle,
+				    u_register_t flags)
+{
+	ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+	SMC_RET1(handle, SMC_UNK);
+}
diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk
new file mode 100644
index 0000000..e947682
--- /dev/null
+++ b/plat/rockchip/px30/platform.mk
@@ -0,0 +1,63 @@
+#
+#Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+#
+#SPDX-License-Identifier: BSD-3-Clause
+#
+
+
+RK_PLAT			:=	plat/rockchip
+RK_PLAT_SOC		:=	${RK_PLAT}/${PLAT}
+RK_PLAT_COMMON		:=	${RK_PLAT}/common
+
+DISABLE_BIN_GENERATION	:=	1
+
+PLAT_INCLUDES		:=	-Idrivers/arm/gic/common/			\
+				-Idrivers/arm/gic/v2/				\
+				-Iinclude/plat/common/				\
+				-I${RK_PLAT_COMMON}/				\
+				-I${RK_PLAT_COMMON}/include/			\
+				-I${RK_PLAT_COMMON}/drivers/parameter/		\
+				-I${RK_PLAT_COMMON}/pmusram			\
+				-I${RK_PLAT_SOC}/				\
+				-I${RK_PLAT_SOC}/drivers/pmu/			\
+				-I${RK_PLAT_SOC}/drivers/soc/			\
+				-I${RK_PLAT_SOC}/include/
+
+RK_GIC_SOURCES         :=	drivers/arm/gic/common/gic_common.c		\
+				drivers/arm/gic/v2/gicv2_main.c			\
+				drivers/arm/gic/v2/gicv2_helpers.c		\
+				plat/common/plat_gicv2.c			\
+				plat/common/aarch64/crash_console_helpers.S	\
+				${RK_PLAT}/common/rockchip_gicv2.c
+
+PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c		\
+				lib/xlat_tables/aarch64/xlat_tables.c		\
+				plat/common/plat_psci_common.c
+
+BL31_SOURCES		+=	${RK_GIC_SOURCES}				\
+				drivers/arm/cci/cci.c				\
+				drivers/delay_timer/delay_timer.c		\
+				drivers/delay_timer/generic_delay_timer.c	\
+				drivers/ti/uart/aarch64/16550_console.S		\
+				lib/cpus/aarch64/cortex_a35.S			\
+				${RK_PLAT_COMMON}/aarch64/plat_helpers.S	\
+				${RK_PLAT_COMMON}/aarch64/platform_common.c	\
+				${RK_PLAT_COMMON}/bl31_plat_setup.c		\
+				${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c	\
+				${RK_PLAT_COMMON}/params_setup.c		\
+				${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S	\
+				${RK_PLAT_COMMON}/plat_pm.c			\
+				${RK_PLAT_COMMON}/plat_topology.c		\
+				${RK_PLAT_COMMON}/rockchip_sip_svc.c		\
+				${RK_PLAT_SOC}/drivers/pmu/pmu.c		\
+				${RK_PLAT_SOC}/drivers/soc/soc.c		\
+				${RK_PLAT_SOC}/plat_sip_calls.c
+
+ENABLE_PLAT_COMPAT	:=	0
+MULTI_CONSOLE_API	:=	1
+
+include lib/libfdt/libfdt.mk
+
+$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
+$(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))
+$(eval $(call add_define,PLAT_WARMBOOT_ADDR_NOT_ALIGN))
diff --git a/plat/rockchip/px30/px30_def.h b/plat/rockchip/px30/px30_def.h
new file mode 100644
index 0000000..021165a
--- /dev/null
+++ b/plat/rockchip/px30/px30_def.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PX30_DEF_H__
+#define __PX30_DEF_H__
+
+#define MAJOR_VERSION		(1)
+#define MINOR_VERSION		(0)
+
+#define SIZE_K(n)		((n) * 1024)
+
+#define WITH_16BITS_WMSK(bits)	(0xffff0000 | (bits))
+
+/* Special value used to verify platform parameters from BL2 to BL3-1 */
+#define RK_BL31_PLAT_PARAM_VAL	0x0f1e2d3c4b5a6978ULL
+
+#define PMU_BASE		0xff000000
+#define PMU_SIZE		SIZE_K(64)
+
+#define PMUGRF_BASE		0xff010000
+#define PMUGRF_SIZE		SIZE_K(64)
+
+#define PMUSRAM_BASE		0xff020000
+#define PMUSRAM_SIZE		SIZE_K(64)
+#define PMUSRAM_RSIZE		SIZE_K(8)
+
+#define UART0_BASE		0xff030000
+#define UART0_SIZE		SIZE_K(64)
+
+#define GPIO0_BASE		0xff040000
+#define GPIO0_SIZE		SIZE_K(64)
+
+#define PMUSGRF_BASE		0xff050000
+#define PMUSGRF_SIZE		SIZE_K(64)
+
+#define INTSRAM_BASE		0xff0e0000
+#define INTSRAM_SIZE		SIZE_K(64)
+
+#define SGRF_BASE		0xff11c000
+#define SGRF_SIZE		SIZE_K(16)
+
+#define GIC400_BASE		0xff130000
+#define GIC400_SIZE		SIZE_K(64)
+
+#define GRF_BASE		0xff140000
+#define GRF_SIZE		SIZE_K(64)
+
+#define UART1_BASE		0xff158000
+#define UART1_SIZE		SIZE_K(64)
+
+#define UART2_BASE		0xff160000
+#define UART2_SIZE		SIZE_K(64)
+
+#define I2C0_BASE		0xff180000
+#define I2C0_SIZE		SIZE_K(64)
+
+#define PWM0_BASE		0xff200000
+#define PWM0_SIZE		SIZE_K(32)
+
+#define PWM1_BASE		0xff208000
+#define PWM1_SIZE		SIZE_K(32)
+
+#define NTIME_BASE		0xff210000
+#define NTIME_SIZE		SIZE_K(64)
+
+#define STIME_BASE		0xff220000
+#define STIME_SIZE		SIZE_K(64)
+
+#define DCF_BASE		0xff230000
+#define DCF_SIZE		SIZE_K(64)
+
+#define GPIO1_BASE		0xff250000
+#define GPIO1_SIZE		SIZE_K(64)
+
+#define GPIO2_BASE		0xff260000
+#define GPIO2_SIZE		SIZE_K(64)
+
+#define GPIO3_BASE		0xff270000
+#define GPIO3_SIZE		SIZE_K(64)
+
+#define DDR_PHY_BASE		0xff2a0000
+#define DDR_PHY_SIZE		SIZE_K(64)
+
+#define CRU_BASE		0xff2b0000
+#define CRU_SIZE		SIZE_K(32)
+
+#define CRU_BOOST_BASE		0xff2b8000
+#define CRU_BOOST_SIZE		SIZE_K(16)
+
+#define PMUCRU_BASE		0xff2bc000
+#define PMUCRU_SIZE		SIZE_K(16)
+
+#define VOP_BASE		0xff460000
+#define VOP_SIZE		SIZE_K(16)
+
+#define SERVER_MSCH_BASE	0xff530000
+#define SERVER_MSCH_SIZE	SIZE_K(64)
+
+#define FIREWALL_DDR_BASE	0xff534000
+#define FIREWALL_DDR_SIZE	SIZE_K(16)
+
+#define DDR_UPCTL_BASE		0xff600000
+#define DDR_UPCTL_SIZE		SIZE_K(64)
+
+#define DDR_MNTR_BASE		0xff610000
+#define DDR_MNTR_SIZE		SIZE_K(64)
+
+#define DDR_STDBY_BASE		0xff620000
+#define DDR_STDBY_SIZE		SIZE_K(64)
+
+#define DDRGRF_BASE		0xff630000
+#define DDRGRF_SIZE		SIZE_K(32)
+
+/**************************************************************************
+ * UART related constants
+ **************************************************************************/
+#define PX30_UART_BASE		UART2_BASE
+#define PX30_BAUDRATE		1500000
+#define PX30_UART_CLOCK		24000000
+
+/******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define SYS_COUNTER_FREQ_IN_TICKS	24000000
+#define SYS_COUNTER_FREQ_IN_MHZ		24
+
+/******************************************************************************
+ * GIC-400 & interrupt handling related constants
+ ******************************************************************************/
+
+/* Base rk_platform compatible GIC memory map */
+#define PX30_GICD_BASE		(GIC400_BASE + 0x1000)
+#define PX30_GICC_BASE		(GIC400_BASE + 0x2000)
+#define PX30_GICR_BASE		0	/* no GICR in GIC-400 */
+
+/******************************************************************************
+ * sgi, ppi
+ ******************************************************************************/
+#define RK_IRQ_SEC_PHY_TIMER	29
+
+#define RK_IRQ_SEC_SGI_0	8
+#define RK_IRQ_SEC_SGI_1	9
+#define RK_IRQ_SEC_SGI_2	10
+#define RK_IRQ_SEC_SGI_3	11
+#define RK_IRQ_SEC_SGI_4	12
+#define RK_IRQ_SEC_SGI_5	13
+#define RK_IRQ_SEC_SGI_6	14
+#define RK_IRQ_SEC_SGI_7	15
+
+/*
+ * Define a list of Group 0 interrupts.
+ */
+#define PLAT_RK_GICV2_G0_IRQS						\
+	INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,	\
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),		\
+	INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,	\
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
+
+#define SHARE_MEM_BASE		0x100000/* [1MB, 1MB+60K]*/
+#define SHARE_MEM_PAGE_NUM	15
+#define SHARE_MEM_SIZE		SIZE_K(SHARE_MEM_PAGE_NUM * 4)
+
+#define DDR_PARAM_BASE		0x02000000
+#define DDR_PARAM_SIZE		SIZE_K(4)
+
+#endif /* __PLAT_DEF_H__ */
diff --git a/plat/rockchip/rk3288/platform.mk b/plat/rockchip/rk3288/platform.mk
index 1811b3a..faf7a15 100644
--- a/plat/rockchip/rk3288/platform.mk
+++ b/plat/rockchip/rk3288/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -30,7 +30,9 @@
 				plat/common/plat_gicv2.c			\
 				${RK_PLAT}/common/rockchip_gicv2.c
 
-PLAT_BL_COMMON_SOURCES	:=	plat/common/aarch32/crash_console_helpers.S	\
+PLAT_BL_COMMON_SOURCES	:=	common/desc_image_load.c			\
+				lib/bl_aux_params/bl_aux_params.c		\
+				plat/common/aarch32/crash_console_helpers.S	\
 				plat/common/plat_psci_common.c
 
 PLAT_BL_COMMON_SOURCES	+=	lib/xlat_tables/xlat_tables_common.c		\
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index fa207aa..0da4f2d 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -28,7 +28,9 @@
 				plat/common/plat_gicv2.c			\
 				${RK_PLAT}/common/rockchip_gicv2.c
 
-PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/aarch64/xlat_tables.c		\
+PLAT_BL_COMMON_SOURCES	:=	common/desc_image_load.c			\
+				lib/bl_aux_params/bl_aux_params.c		\
+				lib/xlat_tables/aarch64/xlat_tables.c		\
 				lib/xlat_tables/xlat_tables_common.c		\
 				plat/common/aarch64/crash_console_helpers.S	\
 				plat/common/plat_psci_common.c
diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index f8878f1..cb0cb89 100644
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -26,7 +26,9 @@
 				plat/common/plat_gicv2.c			\
 				${RK_PLAT}/common/rockchip_gicv2.c
 
-PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c		\
+PLAT_BL_COMMON_SOURCES	:=	common/desc_image_load.c			\
+				lib/bl_aux_params/bl_aux_params.c		\
+				lib/xlat_tables/xlat_tables_common.c		\
 				lib/xlat_tables/aarch64/xlat_tables.c		\
 				plat/common/aarch64/crash_console_helpers.S	\
 				plat/common/plat_psci_common.c
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index 42589b9..a6b5973 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -890,7 +890,7 @@
 
 static void suspend_apio(void)
 {
-	struct apio_info *suspend_apio;
+	struct bl_aux_rk_apio_info *suspend_apio;
 	int i;
 
 	suspend_apio = plat_get_rockchip_suspend_apio();
@@ -1010,7 +1010,7 @@
 
 static void resume_apio(void)
 {
-	struct apio_info *suspend_apio;
+	struct bl_aux_rk_apio_info *suspend_apio;
 	int i;
 
 	suspend_apio = plat_get_rockchip_suspend_apio();
@@ -1038,7 +1038,7 @@
 
 static void suspend_gpio(void)
 {
-	struct gpio_info *suspend_gpio;
+	struct bl_aux_gpio_info *suspend_gpio;
 	uint32_t count;
 	int i;
 
@@ -1053,7 +1053,7 @@
 
 static void resume_gpio(void)
 {
-	struct gpio_info *suspend_gpio;
+	struct bl_aux_gpio_info *suspend_gpio;
 	uint32_t count;
 	int i;
 
@@ -1491,7 +1491,7 @@
 
 void __dead2 rockchip_soc_soft_reset(void)
 {
-	struct gpio_info *rst_gpio;
+	struct bl_aux_gpio_info *rst_gpio;
 
 	rst_gpio = plat_get_rockchip_gpio_reset();
 
@@ -1508,7 +1508,7 @@
 
 void __dead2 rockchip_soc_system_off(void)
 {
-	struct gpio_info *poweroff_gpio;
+	struct bl_aux_gpio_info *poweroff_gpio;
 
 	poweroff_gpio = plat_get_rockchip_gpio_poweroff();
 
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
index e1ba410..74db82f 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index 1d81d7e..cfc48e8 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -32,7 +32,9 @@
 				plat/common/plat_gicv3.c		\
 				${RK_PLAT}/common/rockchip_gicv3.c
 
-PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c	\
+PLAT_BL_COMMON_SOURCES	:=	common/desc_image_load.c			\
+				lib/bl_aux_params/bl_aux_params.c		\
+				lib/xlat_tables/xlat_tables_common.c	\
 				lib/xlat_tables/aarch64/xlat_tables.c	\
 				plat/common/aarch64/crash_console_helpers.S \
 				plat/common/plat_psci_common.c