Merge "docs(porting-guide): correct typo of "bits" to "bytes"" into integration
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 52e1c7d..5bf6fb3 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -335,6 +335,10 @@
Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
it is still open.
+- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to
+ Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
+ erratum is still open.
+
- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
erratum is still open.
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1b6e96b..8e83464 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -16,6 +16,7 @@
#include <drivers/delay_timer.h>
#include <drivers/mmc.h>
#include <lib/utils.h>
+#include <plat/common/common_def.h>
#define MMC_DEFAULT_MAX_RETRIES 5
#define SEND_OP_COND_MAX_RETRIES 100
@@ -805,6 +806,11 @@
return ret;
}
+size_t mmc_boot_part_size(void)
+{
+ return mmc_ext_csd[CMD_EXTCSD_BOOT_SIZE_MULT] * SZ_128K;
+}
+
size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size)
{
size_t size_read;
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index e973248..e94693d 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -62,6 +62,7 @@
#define CMD_EXTCSD_HS_TIMING 185
#define CMD_EXTCSD_PART_SWITCH_TIME 199
#define CMD_EXTCSD_SEC_CNT 212
+#define CMD_EXTCSD_BOOT_SIZE_MULT 226
#define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0)
#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
@@ -262,6 +263,7 @@
size_t mmc_erase_blocks(int lba, size_t size);
int mmc_part_switch_current_boot(void);
int mmc_part_switch_user(void);
+size_t mmc_boot_part_size(void);
size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size);
int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
unsigned int width, unsigned int flags,
diff --git a/include/export/common/bl_common_exp.h b/include/export/common/bl_common_exp.h
index 8f09017..2cc7c54 100644
--- a/include/export/common/bl_common_exp.h
+++ b/include/export/common/bl_common_exp.h
@@ -39,8 +39,8 @@
*****************************************************************************/
typedef struct image_info {
param_header_t h;
- uintptr_t image_base; /* physical address of base of image */
- uint32_t image_size; /* bytes read from image file */
+ uintptr_t image_base; /* physical address of base of image */
+ uint32_t image_size; /* bytes read from image file */
uint32_t image_max_size;
} image_info_t;
diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h
index 7f7b9a5..35e543c 100644
--- a/include/lib/cpus/aarch64/cortex_a78c.h
+++ b/include/lib/cpus/aarch64/cortex_a78c.h
@@ -17,6 +17,7 @@
* CPU Auxiliary Control register 2 specific definitions.
* ****************************************************************************/
#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1
+#define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
/*******************************************************************************
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 4f0bb49..49cebfe 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -18,6 +18,35 @@
#endif
/* --------------------------------------------------
+ * Errata Workaround for Cortex A78C Erratum 2376749.
+ * This applies to revision r0p1 and r0p2 of the A78C
+ * and is currently open. It is a Cat B erratum.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x4, x17
+ * --------------------------------------------------
+ */
+func errata_a78c_2376749_wa
+ /* Check revision */
+ mov x17, x30
+ bl check_errata_2376749
+ cbz x0, 1f
+ /* Set CPUACTLR2_EL1[0] to 1. */
+ mrs x1, CORTEX_A78C_CPUACTLR2_EL1
+ orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0
+ msr CORTEX_A78C_CPUACTLR2_EL1, x1
+1:
+ ret x17
+endfunc errata_a78c_2376749_wa
+
+func check_errata_2376749
+ /* Applies to r0p1 and r0p2*/
+ mov x1, #0x01
+ mov x2, #0x02
+ b cpu_rev_var_range
+endfunc check_errata_2376749
+
+/* --------------------------------------------------
* Errata Workaround for Cortex A78C Erratum 2395411.
* This applies to revision r0p1 and r0p2 of the A78C
* and is currently open. It is a Cat B erratum.
@@ -151,6 +180,11 @@
bl errata_a78c_2242638_wa
#endif
+#if ERRATA_A78C_2376749
+ mov x0, x18
+ bl errata_a78c_2376749_wa
+#endif
+
#if ERRATA_A78C_2395411
mov x0, x18
bl errata_a78c_2395411_wa
@@ -201,6 +235,7 @@
*/
report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
+ report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 36832cd..f8e2cbf 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -369,6 +369,10 @@
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
ERRATA_A78C_2242638 ?=0
+# Flag to apply erratum 2376749 workaround during reset. This erratum applies
+# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
+ERRATA_A78C_2376749 ?=0
+
# Flag to apply erratum 2395411 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
ERRATA_A78C_2395411 ?=0
@@ -964,6 +968,10 @@
$(eval $(call assert_boolean,ERRATA_A78C_2242638))
$(eval $(call add_define,ERRATA_A78C_2242638))
+# Process ERRATA_A78C_2376749 flag
+$(eval $(call assert_boolean,ERRATA_A78C_2376749))
+$(eval $(call add_define,ERRATA_A78C_2376749))
+
# Process ERRATA_A78C_2395411 flag
$(eval $(call assert_boolean,ERRATA_A78C_2395411))
$(eval $(call add_define,ERRATA_A78C_2395411))
diff --git a/plat/mediatek/drivers/msdc/mt8186/mt_msdc_priv.h b/plat/mediatek/drivers/msdc/mt8186/mt_msdc_priv.h
new file mode 100644
index 0000000..b3337ca
--- /dev/null
+++ b/plat/mediatek/drivers/msdc/mt8186/mt_msdc_priv.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_MSDC_PRIV_H
+#define MT_MSDC_PRIV_H
+
+#define MSDC_CQHCI_CFG 0x808
+#define MSDC_CQHCI_CRYPTO_ENABLE BIT(1)
+
+#endif
diff --git a/plat/mediatek/drivers/msdc/mt_msdc.c b/plat/mediatek/drivers/msdc/mt_msdc.c
new file mode 100644
index 0000000..ccf440f
--- /dev/null
+++ b/plat/mediatek/drivers/msdc/mt_msdc.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_msdc.h>
+#include <platform_def.h>
+
+uint64_t msdc_smc_dispatcher(uint64_t arg0, uint64_t arg1,
+ uint64_t arg2, uint64_t arg3)
+{
+ INFO("[%s] msdc setup call from kernel\n", __func__);
+ mmio_setbits_32(MSDC0_BASE + MSDC_CQHCI_CFG, MSDC_CQHCI_CRYPTO_ENABLE);
+
+ return 0L;
+}
diff --git a/plat/mediatek/drivers/msdc/mt_msdc.h b/plat/mediatek/drivers/msdc/mt_msdc.h
new file mode 100644
index 0000000..1c500c2
--- /dev/null
+++ b/plat/mediatek/drivers/msdc/mt_msdc.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_MSDC_H
+#define MT_MSDC_H
+
+#include <mt_msdc_priv.h>
+
+uint64_t msdc_smc_dispatcher(uint64_t arg0, uint64_t arg1,
+ uint64_t arg2, uint64_t arg3);
+
+#endif
diff --git a/plat/mediatek/include/mtk_sip_def.h b/plat/mediatek/include/mtk_sip_def.h
index d760101..907f0c1 100644
--- a/plat/mediatek/include/mtk_sip_def.h
+++ b/plat/mediatek/include/mtk_sip_def.h
@@ -10,6 +10,8 @@
/* Define SiP SMC ID here */
#define MTK_SIP_SMC_FROM_NS_EL1_TABLE(_func) \
_func(MTK_SIP_KERNEL_TIME_SYNC, 0x202) \
+ _func(MTK_SIP_KERNEL_DFD, 0x205) \
+ _func(MTK_SIP_KERNEL_MSDC, 0x273) \
_func(MTK_SIP_VCORE_CONTROL, 0x506) \
_func(MTK_SIP_IOMMU_CONTROL, 0x514) \
_func(MTK_SIP_APUSYS_CONTROL, 0x51E) \
diff --git a/plat/mediatek/mt8186/include/plat_sip_calls.h b/plat/mediatek/mt8186/include/plat_sip_calls.h
index 9e3726b..f5c15e3 100644
--- a/plat/mediatek/mt8186/include/plat_sip_calls.h
+++ b/plat/mediatek/mt8186/include/plat_sip_calls.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,10 +10,6 @@
/*******************************************************************************
* Plat SiP function constants
******************************************************************************/
-#define MTK_PLAT_SIP_NUM_CALLS (2)
-
-/* DFD */
-#define MTK_SIP_KERNEL_DFD_AARCH32 (0x82000205)
-#define MTK_SIP_KERNEL_DFD_AARCH64 (0xC2000205)
+#define MTK_PLAT_SIP_NUM_CALLS (6)
#endif /* PLAT_SIP_CALLS_H */
diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h
index f3d15f3..850ce2f 100644
--- a/plat/mediatek/mt8186/include/platform_def.h
+++ b/plat/mediatek/mt8186/include/platform_def.h
@@ -72,6 +72,11 @@
#define EMI_MPU_BASE (IO_PHYS + 0x0021B000)
/*******************************************************************************
+ * MSDC related constants
+ ******************************************************************************/
+#define MSDC0_BASE (IO_PHYS + 0x01230000)
+
+/*******************************************************************************
* GIC-600 & interrupt handling related constants
******************************************************************************/
/* Base MTK_platform compatible GIC memory map */
diff --git a/plat/mediatek/mt8186/plat_sip_calls.c b/plat/mediatek/mt8186/plat_sip_calls.c
index d9144d8..0e9c270 100644
--- a/plat/mediatek/mt8186/plat_sip_calls.c
+++ b/plat/mediatek/mt8186/plat_sip_calls.c
@@ -6,6 +6,8 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <lib/mmio.h>
+#include <mt_msdc.h>
#include <mt_spm_vcorefs.h>
#include <mtk_sip_svc.h>
#include <plat_dfd.h>
@@ -33,6 +35,11 @@
ret = dfd_smc_dispatcher(x1, x2, x3, x4);
SMC_RET1(handle, ret);
break;
+ case MTK_SIP_KERNEL_MSDC_AARCH32:
+ case MTK_SIP_KERNEL_MSDC_AARCH64:
+ ret = msdc_smc_dispatcher(x1, x2, x3, x4);
+ SMC_RET1(handle, ret);
+ break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
diff --git a/plat/mediatek/mt8186/platform.mk b/plat/mediatek/mt8186/platform.mk
index 8717d7d..6587970 100644
--- a/plat/mediatek/mt8186/platform.mk
+++ b/plat/mediatek/mt8186/platform.mk
@@ -12,6 +12,8 @@
-I${MTK_PLAT}/drivers/gic600/ \
-I${MTK_PLAT}/drivers/gpio/ \
-I${MTK_PLAT}/drivers/lpm/ \
+ -I${MTK_PLAT}/drivers/msdc/ \
+ -I${MTK_PLAT}/drivers/msdc/${PLAT} \
-I${MTK_PLAT}/drivers/pmic_wrap/ \
-I${MTK_PLAT}/drivers/timer/ \
-I${MTK_PLAT}/drivers/uart/ \
@@ -53,6 +55,7 @@
${MTK_PLAT}/drivers/gic600/mt_gic_v3.c \
${MTK_PLAT}/drivers/gpio/mtgpio_common.c \
${MTK_PLAT}/drivers/lpm/mt_lp_rm.c \
+ ${MTK_PLAT}/drivers/msdc/mt_msdc.c \
${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init.c \
${MTK_PLAT}/drivers/rtc/rtc_common.c \
${MTK_PLAT}/drivers/timer/mt_timer.c \
diff --git a/plat/mediatek/mt8192/include/plat_sip_calls.h b/plat/mediatek/mt8192/include/plat_sip_calls.h
index f68a4ea..fdc7bea 100644
--- a/plat/mediatek/mt8192/include/plat_sip_calls.h
+++ b/plat/mediatek/mt8192/include/plat_sip_calls.h
@@ -10,10 +10,6 @@
/*******************************************************************************
* Plat SiP function constants
******************************************************************************/
-#define MTK_PLAT_SIP_NUM_CALLS 2
-
-/* DFD */
-#define MTK_SIP_KERNEL_DFD_AARCH32 0x82000205
-#define MTK_SIP_KERNEL_DFD_AARCH64 0xC2000205
+#define MTK_PLAT_SIP_NUM_CALLS (4)
#endif /* PLAT_SIP_CALLS_H */
diff --git a/plat/mediatek/mt8195/include/plat_sip_calls.h b/plat/mediatek/mt8195/include/plat_sip_calls.h
index 5562a67..7d1f9fc 100644
--- a/plat/mediatek/mt8195/include/plat_sip_calls.h
+++ b/plat/mediatek/mt8195/include/plat_sip_calls.h
@@ -10,18 +10,6 @@
/*******************************************************************************
* Plat SiP function constants
******************************************************************************/
-#define MTK_PLAT_SIP_NUM_CALLS 6
-
-/* DFD */
-#define MTK_SIP_KERNEL_DFD_AARCH32 0x82000205
-#define MTK_SIP_KERNEL_DFD_AARCH64 0xC2000205
-
-/* DP/eDP */
-#define MTK_SIP_DP_CONTROL_AARCH32 0x82000523
-#define MTK_SIP_DP_CONTROL_AARCH64 0xC2000523
-
-/* APUSYS SMC call */
-#define MTK_SIP_APUSYS_CONTROL_AARCH32 0x8200051E
-#define MTK_SIP_APUSYS_CONTROL_AARCH64 0xC200051E
+#define MTK_PLAT_SIP_NUM_CALLS (8)
#endif /* PLAT_SIP_CALLS_H */
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index 8d0bdcc..7222584 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -257,6 +257,7 @@
VERBOSE("%s: FIP header found on eMMC boot partition\n",
__func__);
image_block_spec.offset = STM32MP_EMMC_BOOT_FIP_OFFSET;
+ image_block_spec.length = mmc_boot_part_size() - STM32MP_EMMC_BOOT_FIP_OFFSET;
}
#endif
}