feat(imx8ulp): allow RTD to reset APD through MU
Clear HRM bit in MU0_B CCR0 register to allow RTD to reset APD.
The action needs at both ATF init and APD resume.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2475e34b13f57818580a478ab567bfb9fc6cf174
diff --git a/plat/imx/imx8ulp/apd_context.c b/plat/imx/imx8ulp/apd_context.c
index dad3d77..8f179e7 100644
--- a/plat/imx/imx8ulp/apd_context.c
+++ b/plat/imx/imx8ulp/apd_context.c
@@ -561,6 +561,8 @@
/* FIXME: make uart work for ATF */
mmio_write_32(IMX_LPUART_BASE + 0x18, 0xc0000);
+ /* Allow M core to reset A core */
+ mmio_clrbits_32(IMX_MU0B_BASE + 0x10, BIT(2));
/*
* Ask S400 to release caam to APD as it is owned by s400
*/
diff --git a/plat/imx/imx8ulp/imx8ulp_bl31_setup.c b/plat/imx/imx8ulp/imx8ulp_bl31_setup.c
index 64895a0..af4a4e8 100644
--- a/plat/imx/imx8ulp/imx8ulp_bl31_setup.c
+++ b/plat/imx/imx8ulp/imx8ulp_bl31_setup.c
@@ -103,6 +103,9 @@
/* TODO: Hack, refine this piece, scmi channel free */
mmio_write_32(SRAM0_BASE + 0x4, 1);
+
+ /* Allow M core to reset A core */
+ mmio_clrbits_32(IMX_MU0B_BASE + 0x10, BIT(2));
}
void bl31_platform_setup(void)
diff --git a/plat/imx/imx8ulp/include/platform_def.h b/plat/imx/imx8ulp/include/platform_def.h
index d5f4033..e8e72e5 100644
--- a/plat/imx/imx8ulp/include/platform_def.h
+++ b/plat/imx/imx8ulp/include/platform_def.h
@@ -65,6 +65,7 @@
#define IMX_SIM2_BASE U(0x2da50000)
#define IMX_CGC2_BASE U(0x2da60000)
#define IMX_PCC5_BASE U(0x2da70000)
+#define IMX_MU0B_BASE U(0x29220000)
#define IMX_CMC1_BASE U(0x29240000)
#define IMX_WUU1_BASE U(0x29260000)
#define IMX_SIM1_BASE U(0x29290000)