Merge "chore(romlib): remove unused jmptbl.i file" into integration
diff --git a/Makefile b/Makefile
index 8e99259..384c1e4 100644
--- a/Makefile
+++ b/Makefile
@@ -1021,6 +1021,10 @@
$(info DRTM_SUPPORT is an experimental feature)
endif
+ifeq (${HOB_LIST},1)
+ $(warning HOB_LIST is an experimental feature)
+endif
+
ifeq (${TRANSFER_LIST},1)
$(info TRANSFER_LIST is an experimental feature)
endif
@@ -1234,6 +1238,7 @@
PLATFORM_REPORT_CTX_MEM_USE \
EARLY_CONSOLE \
PRESERVE_DSU_PMU_REGS \
+ HOB_LIST \
)))
# Numeric_Flags
@@ -1451,6 +1456,7 @@
PLATFORM_REPORT_CTX_MEM_USE \
EARLY_CONSOLE \
PRESERVE_DSU_PMU_REGS \
+ HOB_LIST \
)))
ifeq (${PLATFORM_REPORT_CTX_MEM_USE}, 1)
diff --git a/docs/design/auth-framework.rst b/docs/design/auth-framework.rst
index 6dc2245..9c04a8b 100644
--- a/docs/design/auth-framework.rst
+++ b/docs/design/auth-framework.rst
@@ -232,22 +232,42 @@
.. code:: c
void (*init)(void);
- int (*verify_signature)(void *data_ptr, unsigned int data_len,
+ int (*verify_signature)(
+ /* Data to verify. */
+ void *data_ptr, unsigned int data_len,
+ /* Bit string of the signature in DER format. */
void *sig_ptr, unsigned int sig_len,
+ /* ASN1 SignatureAlgorithm struct. */
void *sig_alg, unsigned int sig_alg_len,
+ /* ASN1 SubjectPublicKeyInfo struct. */
void *pk_ptr, unsigned int pk_len);
- int (*calc_hash)(enum crypto_md_algo alg, void *data_ptr,
- unsigned int data_len,
- unsigned char output[CRYPTO_MD_MAX_SIZE])
- int (*verify_hash)(void *data_ptr, unsigned int data_len,
- void *digest_info_ptr, unsigned int digest_info_len);
- int (*auth_decrypt)(enum crypto_dec_algo dec_algo, void *data_ptr,
- size_t len, const void *key, unsigned int key_len,
- unsigned int key_flags, const void *iv,
- unsigned int iv_len, const void *tag,
- unsigned int tag_len);
+ int (*calc_hash)(
+ /* SHA256, SHA384 and SHA512 can be used. */
+ enum crypto_md_algo alg
+ /* Data to hash. */
+ void *data_ptr, unsigned int data_len,
+ /* Buffer to store the output. */
+ unsigned char output[CRYPTO_MD_MAX_SIZE]);
+ int (*verify_hash)(
+ /* Data to verify. */
+ void *data_ptr, unsigned int data_len,
+ /* ASN1 DigestInfo struct. */
+ void *digest_info_ptr, unsigned int digest_info_len);
+ int (*auth_decrypt)(
+ /* Currently AES-GCM is the only supported alg. */
+ enum crypto_dec_algo dec_algo,
+ /* Data to decrypt. */
+ void *data_ptr, size_t len,
+ /* Decryption key. */
+ const void *key, unsigned int key_len,
+ unsigned int key_flags,
+ /* Initialization vector. */
+ const void *iv, unsigned int iv_len,
+ /* Authentication tag. */
+ const void *tag, unsigned int tag_len);
-These functions are registered in the CM using the macro:
+The above functions return values from the enum ``crypto_ret_value``.
+The functions are registered in the CM using the macro:
.. code:: c
@@ -262,10 +282,21 @@
``_name`` must be a string containing the name of the CL. This name is used for
debugging purposes.
-Crypto module provides a function ``_calc_hash`` to calculate and
-return the hash of the given data using the provided hash algorithm.
-This function is mainly used in the ``MEASURED_BOOT`` and ``DRTM_SUPPORT``
-features to calculate the hashes of various images/data.
+The ``_init`` function is used to perform any initialization required for
+the specific CM and CL.
+
+The ``_verify_signature`` function is used to verify certificates,
+and ``_verify_hash`` is used to verify raw images.
+
+The ``_calc_hash`` function is mainly used in the ``MEASURED_BOOT``
+and ``DRTM_SUPPORT`` features to calculate the hashes of various images/data.
+
+The ``_auth_decrypt`` function uses an authentication tag to perform
+authenticated decryption, providing guarantees on the authenticity
+of encrypted data. This function is used when the optional encrypted
+firmware feature is enabled, that is when ``ENCRYPT_BL31`` or
+``ENCRYPT_BL32`` are set to ``1`` and ``DECRYPTION_SUPPORT`` is
+set to ``aes_gcm``.
Optionally, a platform function can be provided to convert public key
(_convert_pk). It is only used if the platform saves a hash of the ROTPK.
@@ -970,30 +1001,44 @@
The cryptographic library
~~~~~~~~~~~~~~~~~~~~~~~~~
-The cryptographic module relies on a library to perform the required operations,
-i.e. verify a hash or a digital signature. Arm platforms will use a library
-based on mbed TLS, which can be found in
-``drivers/auth/mbedtls/mbedtls_crypto.c``. This library is registered in the
-authentication framework using the macro ``REGISTER_CRYPTO_LIB()`` and exports
-below functions:
+The cryptographic module relies on a library to perform essential operations
+such as verifying a hash or a digital signature.
+Arm platforms use a library based on mbedTLS located at
+``drivers/auth/mbedtls/mbedtls_crypto.c``.
+Additionally, an experimental alternative library based on PSA Crypto
+is available at ``drivers/auth/mbedtls/mbedtls_psa_crypto.c``. In future,
+``mbedtls_psa_crypto.c`` will replace ``mbedtls_crypto.c`` as the default Arm
+CM. Both libraries are registered in the authentication framework using
+the macro ``REGISTER_CRYPTO_LIB()``. These libraries implement the following
+exported functions, their implementations are compared side-by-side below:
-.. code:: c
+.. list-table:: Comparison of exported CM function implementations
+ :widths: 20 40 40
+ :header-rows: 1
- void init(void);
- int verify_signature(void *data_ptr, unsigned int data_len,
- void *sig_ptr, unsigned int sig_len,
- void *sig_alg, unsigned int sig_alg_len,
- void *pk_ptr, unsigned int pk_len);
- int crypto_mod_calc_hash(enum crypto_md_algo alg, void *data_ptr,
- unsigned int data_len,
- unsigned char output[CRYPTO_MD_MAX_SIZE])
- int verify_hash(void *data_ptr, unsigned int data_len,
- void *digest_info_ptr, unsigned int digest_info_len);
- int auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr,
- size_t len, const void *key, unsigned int key_len,
- unsigned int key_flags, const void *iv,
- unsigned int iv_len, const void *tag,
- unsigned int tag_len)
+ * - CM function
+ - ``mbedtls_crypto.c``
+ - ``mbedtls_psa_crypto.c``
+ * - ``init``
+ - Initialize the heap for mbedTLS.
+ - Initialize the heap for mbedTLS and call ``psa_crypto_init``.
+ * - ``verify_signature``
+ - Use mbedTLS to parse the ASN1 inputs, and then use the mbedTLS pk module to verify the signature.
+ - Use mbedTLS to parse the ASN1 inputs, use the mbedTLS pk module to parse the key,
+ import it into the PSA key system and then use ``psa_verify_message`` to verify the signature.
+ * - ``calc_hash``
+ - Use the ``mbedtls_md`` API to calculate the hash of the given data.
+ - Use ``psa_hash_compute`` to calculate the hash of the given data.
+ * - ``verify_hash``
+ - Use the ``mbedtls_md`` API to calculate the hash of the given data,
+ and then compare it against the data which is to be verified.
+ - Call ``psa_hash_compare``, which both calculates the hash of the given data and
+ compares this hash against the data to be verified.
+ * - ``auth_decrypt``
+ - Use the ``mbedtls_gcm`` API to decrypt the data, and then verify the returned
+ tag by comparing it to the inputted tag.
+ - Load the key into the PSA key store, and then use ``psa_aead_verify`` to
+ decrypt and verify the tag.
The mbedTLS library algorithm support is configured by both the
``TF_MBEDTLS_KEY_ALG`` and ``TF_MBEDTLS_KEY_SIZE`` variables.
@@ -1017,6 +1062,6 @@
--------------
-*Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.*
.. _TBBR-Client specification: https://developer.arm.com/docs/den0006/latest
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index ab0b94d..7d067c6 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -1411,6 +1411,10 @@
interface through BL31 as a SiP SMC function.
Default is disabled (0).
+- ``HOB_LIST``: Setting this to ``1`` enables support for passing boot
+ information using HOB defined in `Platform Initialization specification`_.
+ This defaults to ``0``.
+
Firmware update options
~~~~~~~~~~~~~~~~~~~~~~~
@@ -1454,3 +1458,4 @@
.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html
.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9
.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/
+.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index c414b1f..32c2b39 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -31,7 +31,7 @@
Clang/LLVM 18.1.8
Device Tree Compiler 1.6.1
GNU make 3.81
-mbed TLS\ [#f1]_ 3.6.1
+mbed TLS\ [#f1]_ 3.6.2
Node.js [#f2]_ 16
OpenSSL 1.0.0
Poetry 1.3.2
diff --git a/docs/license.rst b/docs/license.rst
index 9e0298b..e35b9bb 100644
--- a/docs/license.rst
+++ b/docs/license.rst
@@ -110,6 +110,14 @@
- ``tools/cot_dt2c/cot_dt2c/pydevicetree/source/parser.py``
- ``tools/cot_dt2c/cot_dt2c/pydevicetree/__init__.py``
+- Some source files originating from the `edk2`_ project.
+ These files are licensed under the BSD-2-Clause. Any contributions to this
+ code must also be made under the terms of BSD-2-Clause.
+ These files are:
+
+ - ``lib/hob/hob.c``
+ - ``include/lib/hob/mmram.h``
+ - ``include/lib/hob/mpinfo.h``
.. _FreeBSD: http://www.freebsd.org
.. _Linux MIT license: https://raw.githubusercontent.com/torvalds/linux/master/LICENSES/preferred/MIT
@@ -117,3 +125,4 @@
.. _Open Profile for DICE: https://pigweed.googlesource.com/open-dice/
.. _Apache License 2.0: https://www.apache.org/licenses/LICENSE-2.0.txt
.. _pydevicetree: https://pypi.org/project/pydevicetree/
+.. _edk2: https://github.com/tianocore/edk2
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index 765491e..b3c4c91 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -25,9 +25,9 @@
# Specify mbed TLS configuration file
ifeq (${PSA_CRYPTO},1)
- MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/psa_mbedtls_config.h>"
+ MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/default_psa_mbedtls_config.h>"
else
- MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/mbedtls_config-3.h>"
+ MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/default_mbedtls_config.h>"
endif
$(eval $(call add_define,MBEDTLS_CONFIG_FILE))
diff --git a/drivers/renesas/common/io/io_rcar.c b/drivers/renesas/common/io/io_rcar.c
index 66662c1..1529dc0 100644
--- a/drivers/renesas/common/io/io_rcar.c
+++ b/drivers/renesas/common/io/io_rcar.c
@@ -149,6 +149,9 @@
static uint64_t rcar_image_header_prttn[RCAR_MAX_BL3X_IMAGE + 2U] = { 0U };
static uint64_t rcar_image_number = { 0U };
static uint32_t rcar_cert_load = { 0U };
+#if (RCAR_RPC_HYPERFLASH_ABLOADER == 1)
+static uint32_t rcar_image_offset = 0U;
+#endif
static io_type_t device_type_rcar(void)
{
@@ -196,8 +199,10 @@
*offset = rcar_image_header[addr];
+#if (RCAR_RPC_HYPERFLASH_ABLOADER == 1)
+ *offset += rcar_image_offset;
+#endif
+
- if (mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION)
- *offset += 0x800000;
*cert = RCAR_CERT_SIZE;
*cert *= RCAR_ATTR_GET_CERTOFF(name_offset[i].attr);
*cert += RCAR_SDRAM_certESS;
@@ -499,6 +504,15 @@
*/
offset = name == EMMC_DEV_ID ? RCAR_EMMC_CERT_HEADER :
RCAR_FLASH_CERT_HEADER;
+
+#if (RCAR_RPC_HYPERFLASH_ABLOADER == 1)
+ rcar_image_offset = 0;
+ if ((name == FLASH_DEV_ID) &&
+ (mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION)) {
+ rcar_image_offset = 0x800000;
+ }
+#endif
+
rc = io_seek(handle, IO_SEEK_SET, offset);
if (rc != IO_SUCCESS) {
WARN("Firmware Image Package header failed to seek\n");
diff --git a/fdts/rd1ae.dts b/fdts/rd1ae.dts
index 6e821ae..26eaa65 100644
--- a/fdts/rd1ae.dts
+++ b/fdts/rd1ae.dts
@@ -273,7 +273,7 @@
gic: interrupt-controller@30000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x30000000 0 0x10000>, // GICD
- <0x0 0x301c0000 0 0x8000000>; // GICR
+ <0x0 0x301c0000 0 0x400000>; // GICR
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
@@ -425,7 +425,7 @@
method = "smc";
cpu_suspend = <0xc4000001>;
cpu_off = <0x84000002>;
- cpu_on = <0x84000003>;
+ cpu_on = <0xc4000003>;
};
};
diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index 735d429..e898399 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -405,34 +405,50 @@
dpu_aclk: dpu_aclk {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <VENCODER_TIMING_CLK>;
+ clock-frequency = <LCD_TIMING_CLK>;
clock-output-names = "fpga:dpu_aclk";
};
dpu_pixel_clk: dpu-pixel-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <VENCODER_TIMING_CLK>;
+ clock-frequency = <LCD_TIMING_CLK>;
clock-output-names = "pxclk";
};
#endif /* !TC_DPU_USE_SCMI_CLK */
+#if TC_DPU_USE_SIMPLE_PANEL
+ vpanel {
+ compatible = "panel-dpi";
+ post-init-providers = <&pl0>;
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dp_pl0_out0>;
+ };
+ };
+
+ panel-timing {
+ LCD_TIMING;
+ };
+ };
+
+#else
vencoder {
compatible = "drm,virtual-encoder";
port {
- vencoder_in: endpoint {
+ lcd_in: endpoint {
remote-endpoint = <&dp_pl0_out0>;
};
};
display-timings {
timing-panel {
- VENCODER_TIMING;
+ LCD_TIMING;
};
};
};
-
+#endif
ethernet: ethernet@ETHERNET_ADDR {
reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>;
interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>;
@@ -575,7 +591,7 @@
port@0 {
reg = <0>;
dp_pl0_out0: endpoint {
- remote-endpoint = <&vencoder_in>;
+ remote-endpoint = <&lcd_in>;
};
};
};
diff --git a/fdts/tc-fpga.dtsi b/fdts/tc-fpga.dtsi
index 08b9ae5..af140bb 100644
--- a/fdts/tc-fpga.dtsi
+++ b/fdts/tc-fpga.dtsi
@@ -8,9 +8,9 @@
#define GIC_GICR_OFFSET 0x1000000
#define UART_OFFSET 0x10000
/* 1440x3200@120 framebuffer */
-#define VENCODER_TIMING_CLK 836000000
-#define VENCODER_TIMING \
- clock-frequency = <VENCODER_TIMING_CLK>; \
+#define LCD_TIMING_CLK 836000000
+#define LCD_TIMING \
+ clock-frequency = <LCD_TIMING_CLK>; \
hactive = <1440>; \
vactive = <3200>; \
hfront-porch = <136>; \
@@ -25,6 +25,19 @@
stdout-path = "serial0:38400n8";
};
+#if TC_FPGA_ANDROID_IMG_IN_RAM
+ reserved-memory {
+ phram@0x880000000 {
+ /*
+ * starting from 0x8_8000_0000 reserve some memory
+ * android image will be side loaded to this location
+ */
+ reg = <0x8 0x80000000 HI(ANDROID_FS_SIZE) LO(ANDROID_FS_SIZE)>
+ no-map;
+ };
+ };
+#endif /* TC_FPGA_ANDROID_IMG_IN_RAM */
+
ethernet: ethernet@ETHERNET_ADDR {
compatible = "smsc,lan9115";
phy-mode = "mii";
diff --git a/fdts/tc-fvp.dtsi b/fdts/tc-fvp.dtsi
index f57e21d..960730c 100644
--- a/fdts/tc-fvp.dtsi
+++ b/fdts/tc-fvp.dtsi
@@ -10,9 +10,9 @@
#ifdef TC_RESOLUTION_1920X1080P60
-#define VENCODER_TIMING_CLK 148500000
-#define VENCODER_TIMING \
- clock-frequency = <VENCODER_TIMING_CLK>; \
+#define LCD_TIMING_CLK 148500000
+#define LCD_TIMING \
+ clock-frequency = <LCD_TIMING_CLK>; \
hactive = <1920>; \
vactive = <1080>; \
hfront-porch = <88>; \
@@ -24,9 +24,9 @@
#else /* TC_RESOLUTION_640X480P60 */
-#define VENCODER_TIMING_CLK 25175000
-#define VENCODER_TIMING \
- clock-frequency = <VENCODER_TIMING_CLK>; \
+#define LCD_TIMING_CLK 25175000
+#define LCD_TIMING \
+ clock-frequency = <LCD_TIMING_CLK>; \
hactive = <640>; \
vactive = <480>; \
hfront-porch = <16>; \
diff --git a/include/drivers/auth/mbedtls/mbedtls_config-3.h b/include/drivers/auth/mbedtls/default_mbedtls_config.h
similarity index 96%
rename from include/drivers/auth/mbedtls/mbedtls_config-3.h
rename to include/drivers/auth/mbedtls/default_mbedtls_config.h
index 6ed9397..12a5fe1 100644
--- a/include/drivers/auth/mbedtls/mbedtls_config-3.h
+++ b/include/drivers/auth/mbedtls/default_mbedtls_config.h
@@ -11,6 +11,11 @@
*/
/*
+ * This file is compatible with versions >= 3.6.2
+ */
+#define MBEDTLS_CONFIG_VERSION 0x03060200
+
+/*
* Key algorithms currently supported on mbed TLS libraries
*/
#define TF_MBEDTLS_RSA 1
diff --git a/include/drivers/auth/mbedtls/psa_mbedtls_config.h b/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
similarity index 95%
rename from include/drivers/auth/mbedtls/psa_mbedtls_config.h
rename to include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
index 1001d89..8926051 100644
--- a/include/drivers/auth/mbedtls/psa_mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
@@ -7,7 +7,7 @@
#ifndef PSA_MBEDTLS_CONFIG_H
#define PSA_MBEDTLS_CONFIG_H
-#include "mbedtls_config-3.h"
+#include "default_mbedtls_config.h"
#define MBEDTLS_PSA_CRYPTO_C
#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS
diff --git a/include/lib/cpus/aarch64/cortex_alto.h b/include/lib/cpus/aarch64/cortex_alto.h
new file mode 100644
index 0000000..1c8786a
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_alto.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_ALTO_H
+#define CORTEX_ALTO_H
+
+#define CORTEX_ALTO_MIDR U(0x411FD900)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_ALTO_IMP_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_ALTO_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_ALTO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
+
+/*******************************************************************************
+ * SME Control registers
+ ******************************************************************************/
+#define CORTEX_ALTO_SVCRSM S0_3_C4_C2_3
+#define CORTEX_ALTO_SVCRZA S0_3_C4_C4_3
+
+#endif /* CORTEX_ALTO_H */
diff --git a/include/lib/hob/efi_types.h b/include/lib/hob/efi_types.h
new file mode 100644
index 0000000..071d012
--- /dev/null
+++ b/include/lib/hob/efi_types.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EFI_TYPES_H
+#define EFI_TYPES_H
+
+#include <stdint.h>
+#include <tools_share/uuid.h>
+
+typedef uint64_t efi_physical_address_t;
+
+/*****************************************************************************
+ * EFI_BOOT_MODE *
+ *****************************************************************************/
+
+typedef uint32_t efi_boot_mode_t;
+/**
+ * EFI boot mode.
+ */
+#define EFI_BOOT_WITH_FULL_CONFIGURATION U(0x00)
+#define EFI_BOOT_WITH_MINIMAL_CONFIGURATION U(0x01)
+#define EFI_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES U(0x02)
+#define EFI_BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS U(0x03)
+#define EFI_BOOT_WITH_DEFAULT_SETTINGS U(0x04)
+#define EFI_BOOT_ON_S4_RESUME U(0x05)
+#define EFI_BOOT_ON_S5_RESUME U(0x06)
+#define EFI_BOOT_WITH_MFG_MODE_SETTINGS U(0x07)
+#define EFI_BOOT_ON_S2_RESUME U(0x10)
+#define EFI_BOOT_ON_S3_RESUME U(0x11)
+#define EFI_BOOT_ON_FLASH_UPDATE U(0x12)
+#define EFI_BOOT_IN_RECOVERY_MODE U(0x20)
+
+/*****************************************************************************
+ * EFI_RESOURCE_TYPE *
+ *****************************************************************************/
+
+typedef uint32_t efi_resource_type_t;
+
+/**
+ * Value of EFI_RESOURCE_TYPE used in EFI_HOB_RESOURCE_DESCRIPTOR.
+ */
+#define EFI_RESOURCE_SYSTEM_MEMORY U(0x00000000)
+#define EFI_RESOURCE_MEMORY_MAPPED_IO U(0x00000001)
+#define EFI_RESOURCE_IO U(0x00000002)
+#define EFI_RESOURCE_FIRMWARE_DEVICE U(0x00000003)
+#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT U(0x00000004)
+#define EFI_RESOURCE_MEMORY_RESERVED U(0x00000005)
+#define EFI_RESOURCE_IO_RESERVED U(0x00000006)
+
+/*****************************************************************************
+ * EFI_RESOURCE_ATTRIBUTE_TYPE *
+ *****************************************************************************/
+
+typedef uint32_t efi_resource_attribute_type_t;
+
+#define EFI_RESOURCE_ATTRIBUTE_PRESENT U(0x00000001)
+#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED U(0x00000002)
+#define EFI_RESOURCE_ATTRIBUTE_TESTED U(0x00000004)
+#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED U(0x00000080)
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED U(0x00000100)
+#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED U(0x00000200)
+#define EFI_RESOURCE_ATTRIBUTE_PERSISTENT U(0x00800000)
+#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC U(0x00000008)
+#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC U(0x00000010)
+#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 U(0x00000020)
+#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 U(0x00000040)
+#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE U(0x00000400)
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE U(0x00000800)
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE U(0x00001000)
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE U(0x00002000)
+#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO U(0x00004000)
+#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO U(0x00008000)
+#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO U(0x00010000)
+#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED U(0x00020000)
+#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTABLE U(0x00100000)
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE U(0x00200000)
+#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE U(0x00400000)
+#define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE U(0x01000000)
+#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED U(0x00040000)
+#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE U(0x00080000)
+#define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE U(0x02000000)
+
+#endif /* EFI_TYPES_H */
diff --git a/include/lib/hob/hob.h b/include/lib/hob/hob.h
new file mode 100644
index 0000000..120f5da
--- /dev/null
+++ b/include/lib/hob/hob.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef HOB_H
+#define HOB_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <lib/hob/efi_types.h>
+#include <lib/utils_def.h>
+#include <tools_share/uuid.h>
+
+/*****************************************************************************
+ * Hob Generic Header *
+ *****************************************************************************/
+
+/**
+ * HobType values of EFI_HOB_GENERIC_HEADER.
+ */
+#define EFI_HOB_TYPE_HANDOFF U(0x0001)
+#define EFI_HOB_TYPE_MEMORY_ALLOCATION U(0x0002)
+#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR U(0x0003)
+#define EFI_HOB_TYPE_GUID_EXTENSION U(0x0004)
+#define EFI_HOB_TYPE_FV U(0x0005)
+#define EFI_HOB_TYPE_CPU U(0x0006)
+#define EFI_HOB_TYPE_MEMORY_POOL U(0x0007)
+#define EFI_HOB_TYPE_FV2 U(0x0009)
+#define EFI_HOB_TYPE_LOAD_PEIM_UNUSED U(0x000A)
+#define EFI_HOB_TYPE_UEFI_CAPSULE U(0x000B)
+#define EFI_HOB_TYPE_FV3 U(0x000C)
+#define EFI_HOB_TYPE_UNUSED U(0xFFFE)
+#define EFI_HOB_TYPE_END_OF_HOB_LIST U(0xFFFF)
+
+struct efi_hob_generic_header {
+ uint16_t hob_type;
+ uint16_t hob_length;
+ uint32_t reserved;
+};
+
+/*****************************************************************************
+ * PHIT Hob. *
+ *****************************************************************************/
+
+#define EFI_HOB_HANDOFF_TABLE_VERSION U(0x000a)
+
+struct efi_hob_handoff_info_table {
+ struct efi_hob_generic_header header;
+ uint32_t version;
+ efi_boot_mode_t boot_mode;
+ efi_physical_address_t efi_memory_top;
+ efi_physical_address_t efi_memory_bottom;
+ efi_physical_address_t efi_free_memory_top;
+ efi_physical_address_t efi_free_memory_bottom;
+ efi_physical_address_t efi_end_of_hob_list;
+};
+
+/*****************************************************************************
+ * Resource Descriptor Hob. *
+ *****************************************************************************/
+
+struct efi_hob_resource_descriptor {
+ struct efi_hob_generic_header header;
+ struct efi_guid owner;
+ efi_resource_type_t resource_type;
+ efi_resource_attribute_type_t resource_attribute;
+ efi_physical_address_t physical_start;
+ uint64_t resource_length;
+};
+
+/*****************************************************************************
+ * Guid Extension Hob. *
+ *****************************************************************************/
+struct efi_hob_guid_type {
+ struct efi_hob_generic_header header;
+ struct efi_guid name;
+ /**
+ * Guid specific data goes here.
+ */
+};
+
+/*****************************************************************************
+ * Firmware Volume Hob. *
+ *****************************************************************************/
+struct efi_hob_firmware_volume {
+ struct efi_hob_generic_header header;
+ efi_physical_address_t base_address;
+ uint64_t length;
+ /**
+ * Guid specific data goes here.
+ */
+};
+
+/*****************************************************************************
+ * Interfaces. *
+ *****************************************************************************/
+
+struct efi_hob_handoff_info_table *
+create_hob_list(
+ efi_physical_address_t efi_memory_begin, size_t efi_memory_length,
+ efi_physical_address_t efi_free_memory_bottom, size_t efi_free_memory_length);
+
+int create_resource_descriptor_hob(
+ struct efi_hob_handoff_info_table *hob_table,
+ efi_resource_type_t resource_type,
+ efi_resource_attribute_type_t resource_attribute,
+ efi_physical_address_t phy_addr_start,
+ uint64_t resource_length);
+
+int create_guid_hob(struct efi_hob_handoff_info_table *hob_table,
+ struct efi_guid *guid, uint16_t data_length, void **data);
+
+int create_fv_hob(struct efi_hob_handoff_info_table *hob_table,
+ efi_physical_address_t base_addr, uint64_t size);
+
+#endif /* HOB_H */
diff --git a/include/lib/hob/hob_guid.h b/include/lib/hob/hob_guid.h
new file mode 100644
index 0000000..65d3dbf
--- /dev/null
+++ b/include/lib/hob/hob_guid.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef HOB_GUID_H
+#define HOB_GUID_H
+
+#include <lib/hob/efi_types.h>
+
+/**
+ * Guid used for creating StandaloneMm related information.
+ */
+
+#define MM_PEI_MMRAM_MEMORY_RESERVE_GUID \
+{ \
+ 0x0703f912, 0xbf8d, 0x4e2a, {0xbe, 0x07, 0xab, 0x27, 0x25, 0x25, 0xc5, 0x92 } \
+}
+
+#define MM_NS_BUFFER_GUID \
+{ \
+ 0xf00497e3, 0xbfa2, 0x41a1, {0x9d, 0x29, 0x54, 0xc2, 0xe9, 0x37, 0x21, 0xc5 } \
+}
+
+#define MM_MP_INFORMATION_GUID \
+{ \
+ 0xba33f15d, 0x4000, 0x45c1, {0x8e, 0x88, 0xf9, 0x16, 0x92, 0xd4, 0x57, 0xe3} \
+}
+
+#endif /* HOB_GUID_H */
diff --git a/include/lib/hob/mmram.h b/include/lib/hob/mmram.h
new file mode 100644
index 0000000..b269c64
--- /dev/null
+++ b/include/lib/hob/mmram.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#ifndef MMRAM_H
+#define MMRAM_H
+
+#include <lib/hob/efi_types.h>
+
+/**
+ * MMRAM states and capabilities
+ * See UEFI Platform Initialization Specification Version 1.8, IV-5.3.5
+ */
+#define EFI_MMRAM_OPEN U(0x00000001)
+#define EFI_MMRAM_CLOSED U(0x00000002)
+#define EFI_MMRAM_LOCKED U(0x00000004)
+#define EFI_CACHEABLE U(0x00000008)
+#define EFI_ALLOCATED U(0x00000010)
+#define EFI_NEEDS_TESTING U(0x00000020)
+#define EFI_NEEDS_ECC_INITIALIZATION U(0x00000040)
+
+#define EFI_SMRAM_OPEN EFI_MMRAM_OPEN
+#define EFI_SMRAM_CLOSED EFI_MMRAM_CLOSED
+#define EFI_SMRAM_LOCKED EFI_MMRAM_LOCKED
+
+struct efi_mmram_descriptor {
+ efi_physical_address_t physical_start;
+ efi_physical_address_t cpu_start;
+ uint64_t physical_size;
+ uint64_t region_state;
+};
+
+/**
+ * MMRAM block descriptor
+ * This definition comes from
+ * https://github.com/tianocore/edk2/blob/master/StandaloneMmPkg/Include/Guid/MmramMemoryReserve.h
+ */
+struct efi_mmram_hob_descriptor_block {
+ uint32_t number_of_mm_reserved_regions;
+ struct efi_mmram_descriptor descriptor[];
+};
+
+#endif /* MMRAM_H */
diff --git a/include/lib/hob/mpinfo.h b/include/lib/hob/mpinfo.h
new file mode 100644
index 0000000..b80d8f1
--- /dev/null
+++ b/include/lib/hob/mpinfo.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#ifndef MPINFO_H
+#define MPINFO_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <lib/utils_def.h>
+
+/*
+ * Value used in the NumberProcessors parameter of the GetProcessorInfo function
+ */
+#define CPU_V2_EXTENDED_TOPOLOGY UL(1 << 24)
+
+/*
+ * This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and
+ * indicates whether the processor is playing the role of BSP. If the bit is 1,
+ * then the processor is BSP. Otherwise, it is AP.
+ */
+#define PROCESSOR_AS_BSP_BIT UL(1 << 0)
+
+/*
+ * This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and
+ * indicates whether the processor is enabled. If the bit is 1, then the
+ * processor is enabled. Otherwise, it is disabled.
+ */
+#define PROCESSOR_ENABLED_BIT UL(1 << 1)
+
+/*
+ * This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and
+ * indicates whether the processor is healthy. If the bit is 1, then the
+ * processor is healthy. Otherwise, some fault has been detected for the processor.
+ */
+#define PROCESSOR_HEALTH_STATUS_BIT UL(1 << 2)
+
+/*
+ * Structure that describes the physical location of a logical CPU.
+ */
+struct efi_cpu_physical_location {
+ uint32_t package;
+ uint32_t core;
+ uint32_t thread;
+};
+
+/*
+ * Structure that defines the 6-level physical location of the processor
+ */
+struct efi_cpu_physical_location2 {
+ uint32_t package;
+ uint32_t module;
+ uint32_t tile;
+ uint32_t die;
+ uint32_t core;
+ uint32_t thread;
+};
+
+union extended_processor_information {
+ /*
+ * The 6-level physical location of the processor, including the
+ * physical package number that identifies the cartridge, the physical
+ * module number within package, the physical tile number within the module,
+ * the physical die number within the tile, the physical core number within
+ * package, and logical thread number within core.
+ */
+ struct efi_cpu_physical_location2 location2;
+};
+
+/*
+ * Structure that describes information about a logical CPU.
+ */
+struct efi_processor_information {
+ /*
+ * The unique processor ID determined by system hardware.
+ */
+ uint64_t processor_id;
+
+ /*
+ * Flags indicating if the processor is BSP or AP, if the processor is enabled
+ * or disabled, and if the processor is healthy. Bits 3..31 are reserved and
+ * must be 0.
+ *
+ * <pre>
+ * BSP ENABLED HEALTH Description
+ * === ======= ====== ===================================================
+ * 0 0 0 Unhealthy Disabled AP.
+ * 0 0 1 Healthy Disabled AP.
+ * 0 1 0 Unhealthy Enabled AP.
+ * 0 1 1 Healthy Enabled AP.
+ * 1 0 0 Invalid. The BSP can never be in the disabled state.
+ * 1 0 1 Invalid. The BSP can never be in the disabled state.
+ * 1 1 0 Unhealthy Enabled BSP.
+ * 1 1 1 Healthy Enabled BSP.
+ * </pre>
+ */
+ uint32_t status_flags;
+
+ /*
+ * The physical location of the processor, including the physical package number
+ * that identifies the cartridge, the physical core number within package, and
+ * logical thread number within core.
+ */
+ struct efi_cpu_physical_location location;
+
+ /*
+ * The extended information of the processor. This field is filled only when
+ * CPU_V2_EXTENDED_TOPOLOGY is set in parameter ProcessorNumber.
+ */
+ union extended_processor_information extended_information;
+};
+
+struct efi_mp_information_hob_data {
+ uint64_t number_of_processors;
+ uint64_t number_of_enabled_processors;
+ struct efi_processor_information processor_info[];
+};
+
+#endif /* MPINFO_H */
diff --git a/lib/cpus/aarch64/cortex_alto.S b/lib/cpus/aarch64/cortex_alto.S
new file mode 100644
index 0000000..c0815f9
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_alto.S
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_alto.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Alto must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Alto supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start cortex_alto
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_alto
+
+func cortex_alto_core_pwr_dwn
+#if ENABLE_SME_FOR_NS
+ /* ---------------------------------------------------
+ * Disable SME if enabled and supported
+ * ---------------------------------------------------
+ */
+ mrs x0, ID_AA64PFR1_EL1
+ ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
+ #ID_AA64PFR1_EL1_SME_WIDTH
+ cmp x0, #SME_NOT_IMPLEMENTED
+ b.eq 1f
+ msr CORTEX_ALTO_SVCRSM, xzr
+ msr CORTEX_ALTO_SVCRZA, xzr
+1:
+#endif
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_ALTO_IMP_CPUPWRCTLR_EL1, \
+ CORTEX_ALTO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+ isb
+ ret
+endfunc cortex_alto_core_pwr_dwn
+
+.section .rodata.cortex_alto_regs, "aS"
+cortex_alto_regs: /* The ASCII list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_alto_cpu_reg_dump
+ adr x6, cortex_alto_regs
+ mrs x8, CORTEX_ALTO_IMP_CPUECTLR_EL1
+ ret
+endfunc cortex_alto_cpu_reg_dump
+
+declare_cpu_ops cortex_alto, CORTEX_ALTO_MIDR, \
+ cortex_alto_reset_func, \
+ cortex_alto_core_pwr_dwn
diff --git a/lib/hob/hob.c b/lib/hob/hob.c
new file mode 100644
index 0000000..60d8571
--- /dev/null
+++ b/lib/hob/hob.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2006-2014, Intel Corporation. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#include <assert.h>
+#include <errno.h>
+#include <inttypes.h>
+#include <string.h>
+
+#include <arch.h>
+#include <common/debug.h>
+#include <lib/hob/hob.h>
+#include <lib/hob/hob_guid.h>
+#include <lib/hob/mmram.h>
+#include <lib/utils_def.h>
+
+#define ALIGN_UP(x, a) ((x + (a - 1)) & ~(a - 1))
+
+static void *_create_hob(struct efi_hob_handoff_info_table *hob_table,
+ uint16_t hob_type, uint16_t hob_length)
+{
+ size_t free_mem_size;
+ struct efi_hob_generic_header *new_hob;
+ struct efi_hob_generic_header *hob_end;
+
+ if ((hob_table == NULL) || (hob_length == 0)) {
+ return NULL;
+ }
+
+ hob_length = ALIGN_UP(hob_length, 8);
+ free_mem_size = hob_table->efi_free_memory_top - hob_table->efi_free_memory_bottom;
+
+ /**
+ * hob_length already including sizeof(efi_hob_generic_header).
+ * See the each export interface create_xxx_hob.
+ */
+ if ((size_t) hob_length > free_mem_size) {
+ return NULL;
+ }
+
+ new_hob = (struct efi_hob_generic_header *) hob_table->efi_end_of_hob_list;
+ new_hob->hob_type = hob_type;
+ new_hob->hob_length = hob_length;
+ new_hob->reserved = 0x00;
+
+ hob_end = (struct efi_hob_generic_header *) (hob_table->efi_end_of_hob_list + hob_length);
+ hob_end->hob_type = EFI_HOB_TYPE_END_OF_HOB_LIST;
+ hob_end->hob_length = sizeof(struct efi_hob_generic_header);
+ hob_end->reserved = 0x00;
+
+ hob_table->efi_end_of_hob_list = (efi_physical_address_t) hob_end;
+ hob_table->efi_free_memory_bottom = (efi_physical_address_t) (hob_end + 1);
+
+ return new_hob;
+}
+
+/*
+ * Create PHIT HOB list.
+ *
+ * On success, return the address PHIT HOB list
+ * On error, return NULL.
+ *
+ * efi_memory_begin
+ * Base address for partition.
+ * efi_memory_length
+ * Size of memory for patition.
+ * efi_free_memory_bottom
+ * Base address PHIT HOB list can be allocated
+ * efi_free_memory_length.
+ * Maximum size of PHIT HOB list can have
+ */
+struct efi_hob_handoff_info_table *create_hob_list(
+ efi_physical_address_t efi_memory_begin, size_t efi_memory_length,
+ efi_physical_address_t efi_free_memory_bottom, size_t efi_free_memory_length)
+{
+ struct efi_hob_handoff_info_table *hob_table;
+ struct efi_hob_generic_header *hob_end;
+
+ if ((efi_memory_begin == 0) || (efi_free_memory_bottom == 0) ||
+ (efi_memory_length == 0) || (efi_free_memory_length == 0)) {
+ return NULL;
+ }
+
+ hob_table = (struct efi_hob_handoff_info_table *) efi_free_memory_bottom;
+ hob_end = (struct efi_hob_generic_header *) (hob_table + 1);
+
+ hob_table->header.hob_type = EFI_HOB_TYPE_HANDOFF;
+ hob_table->header.hob_length = sizeof(struct efi_hob_handoff_info_table);
+ hob_table->header.reserved = 0;
+
+ hob_end->hob_type = EFI_HOB_TYPE_END_OF_HOB_LIST;
+ hob_end->hob_length = sizeof(struct efi_hob_generic_header);
+ hob_end->reserved = 0;
+
+ hob_table->version = EFI_HOB_HANDOFF_TABLE_VERSION;
+ hob_table->boot_mode = EFI_BOOT_WITH_FULL_CONFIGURATION;
+
+ hob_table->efi_memory_top = efi_memory_begin + efi_memory_length;
+ hob_table->efi_memory_bottom = efi_memory_begin;
+ hob_table->efi_free_memory_top = efi_memory_begin + efi_free_memory_length;
+ hob_table->efi_free_memory_bottom = (efi_physical_address_t) (hob_end + 1);
+ hob_table->efi_end_of_hob_list = (efi_physical_address_t) hob_end;
+
+ return hob_table;
+}
+
+/*
+ * Create resource description HOB in PHIT HOB list.
+ *
+ * On success, return 0.
+ * On error, return error code.
+ *
+ * hob_table
+ * Address of PHIT HOB list
+ * resource_type
+ * Resource type see EFI_RESOURCE_* in the include/lib/hob/efi_types.h
+ * resource_attribute
+ * Resource attribute see EFI_RESOURCE_ATTRIBUTES_*
+ * in the include/lib/hob/efi_types.h
+ * phy_addr_start
+ * Physical base address of resource
+ * resource_length
+ * Size of resource
+ */
+int create_resource_descriptor_hob(
+ struct efi_hob_handoff_info_table *hob_table,
+ efi_resource_type_t resource_type,
+ efi_resource_attribute_type_t resource_attribute,
+ efi_physical_address_t phy_addr_start,
+ uint64_t resource_length)
+{
+ struct efi_hob_resource_descriptor *rd_hop;
+
+ rd_hop = _create_hob(hob_table, EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
+ sizeof(struct efi_hob_resource_descriptor));
+
+ if (rd_hop == NULL) {
+ ERROR("No space for creating resource descriptor type hob...\n");
+ return -ENOMEM;
+ }
+
+ rd_hop->resource_type = resource_type;
+ rd_hop->resource_attribute = resource_attribute;
+ rd_hop->physical_start = phy_addr_start;
+ rd_hop->resource_length = resource_length;
+ memset(&rd_hop->owner, 0, sizeof(struct efi_guid));
+
+ return 0;
+}
+
+/*
+ * Create GUID HOB in PHIT HOB list.
+ *
+ * On success, return 0.
+ * On error, return error code.
+ *
+ * hob_table
+ * Address of PHIT HOB list
+ * guid
+ * guid.
+ * data length
+ * Size of data
+ * data
+ * Data
+ */
+int create_guid_hob(struct efi_hob_handoff_info_table *hob_table,
+ struct efi_guid *guid, uint16_t data_length, void **data)
+{
+ struct efi_hob_guid_type *guid_hob;
+ uint16_t hob_length;
+
+ hob_length = data_length + sizeof(struct efi_hob_guid_type);
+
+ if ((guid == NULL) || (data == NULL) || (hob_length < data_length)) {
+ return -EINVAL;
+ }
+
+ guid_hob = _create_hob(hob_table, EFI_HOB_TYPE_GUID_EXTENSION, hob_length);
+ if (guid_hob == NULL) {
+ ERROR("No space for creating guid type hob...\n");
+ return -ENOMEM;
+ }
+
+ memcpy(&guid_hob->name, guid, sizeof(struct efi_guid));
+
+ *data = (void *) (guid_hob + 1);
+
+ return 0;
+}
+
+/*
+ * Create Firmware Volume HOB in PHIT HOB list.
+ *
+ * On success, return 0.
+ * On error, return error code.
+ *
+ * hob_table
+ * Address of PHIT HOB list
+ * base_addr
+ * Base address of firmware volume
+ * size
+ * Size of Firmware Volume
+ */
+int create_fv_hob(struct efi_hob_handoff_info_table *hob_table,
+ efi_physical_address_t base_addr, uint64_t size)
+{
+ struct efi_hob_firmware_volume *fv_hob;
+
+ fv_hob = _create_hob(hob_table, EFI_HOB_TYPE_FV,
+ sizeof(struct efi_hob_firmware_volume));
+ if (fv_hob == NULL) {
+ ERROR("No space for creating fv type hob...\n");
+ return -ENOMEM;
+ }
+
+ fv_hob->base_address = base_addr;
+ fv_hob->length = size;
+
+ return 0;
+}
diff --git a/lib/hob/hob.mk b/lib/hob/hob.mk
new file mode 100644
index 0000000..332738b
--- /dev/null
+++ b/lib/hob/hob.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+HOB_LIST_SOURCES += $(addprefix lib/hob/, \
+ hob.c)
+
+INCLUDES += -Iinclude/lib/hob
+
+BL31_SOURCES += $(HOB_LIST_SOURCES)
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index d6c09de..8a0975b 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -159,6 +159,9 @@
# Enable Handoff protocol using transfer lists
TRANSFER_LIST := 0
+# Enable HOB list to generate boot information
+HOB_LIST := 0
+
# Enables support for the gcc compiler option "-mharden-sls=all".
# By default, disables all SLS hardening.
HARDEN_SLS := 0
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 0156b31..1340a65 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -218,7 +218,8 @@
lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S \
lib/cpus/aarch64/travis.S \
- lib/cpus/aarch64/cortex_arcadia.S
+ lib/cpus/aarch64/cortex_arcadia.S \
+ lib/cpus/aarch64/cortex_alto.S
endif
else
@@ -406,6 +407,10 @@
endif
endif
+ifeq (${HOB_LIST}, 1)
+include lib/hob/hob.mk
+endif
+
# Enable dynamic mitigation support by default
DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 86fce0e..7f24f84 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -207,7 +207,21 @@
#if defined(TARGET_FLAVOUR_FPGA)
#undef V2M_FLASH0_BASE
#undef V2M_FLASH0_SIZE
+#if TC_FPGA_FIP_IMG_IN_RAM
+/*
+ * Note that this is just used for the FIP, which is not required
+ * anymore once Linux has commenced booting. So we are safe allowing
+ * Linux to also make use of this memory and it doesn't need to be
+ * carved out of the devicetree.
+ *
+ * This only needs to match the RAM load address that we give the FIP
+ * on either the FPGA or FVP command line so there is no need to link
+ * it to say halfway through the RAM or anything like that.
+ */
+#define V2M_FLASH0_BASE UL(0xB0000000)
+#else
#define V2M_FLASH0_BASE UL(0x0C000000)
+#endif
#define V2M_FLASH0_SIZE UL(0x02000000)
#endif
@@ -242,10 +256,28 @@
#if TARGET_PLATFORM <= 2
#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
+#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#elif TARGET_PLATFORM >= 3
-#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
-#endif /* TARGET_PLATFORM >= 3 */
-#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
+
+#if TC_FPGA_ANDROID_IMG_IN_RAM
+/* 10GB reserved for system+userdata+vendor images */
+#define SYSTEM_IMAGE_SIZE 0xC0000000 /* 3GB */
+#define USERDATA_IMAGE_SIZE 0x140000000 /* 5GB */
+#define VENDOR_IMAGE_SIZE 0x20000000 /* 512MB */
+#define RESERVE_IMAGE_SIZE 0x60000000 /* 1.5GB */
+#define ANDROID_FS_SIZE (SYSTEM_IMAGE_SIZE + \
+ USERDATA_IMAGE_SIZE + \
+ VENDOR_IMAGE_SIZE + RESERVE_IMAGE_SIZE)
+
+#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) + ANDROID_FS_SIZE
+#define PLAT_ARM_DRAM2_SIZE ULL(0x380000000) - ANDROID_FS_SIZE
+#else
+#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
+#define PLAT_ARM_DRAM2_SIZE ULL(0x380000000)
+#endif /* TC_FPGA_ANDROID_IMG_IN_RAM */
+
+#endif /* TARGET_VERSION >= 3 */
+
#define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL)
#define TC_NS_MTE_SIZE (256 * SZ_1M)
@@ -341,13 +373,13 @@
* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
* SCP_BL2 size plus a little space for growth.
*/
-#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000
+#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x30000
/*
* PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
* SCP_BL2U size plus a little space for growth.
*/
-#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000
+#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x30000
#if TARGET_PLATFORM <= 2
/* TZC Related Constants */
diff --git a/plat/arm/board/tc/plat_tc_mbedtls_config.h b/plat/arm/board/tc/plat_tc_mbedtls_config.h
index 4fd8b6b..9118b0b 100644
--- a/plat/arm/board/tc/plat_tc_mbedtls_config.h
+++ b/plat/arm/board/tc/plat_tc_mbedtls_config.h
@@ -8,7 +8,7 @@
#define PLAT_TC_MBEDTLS_CONFIG_H
#include <export/lib/utils_def_exp.h>
-#include <mbedtls_config-3.h>
+#include <default_mbedtls_config.h>
#ifndef TF_MBEDTLS_HEAP_SIZE
#error TF_MBEDTLS_HEAP_SIZE is not defined
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 9cd3011..3178c06 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -77,12 +77,24 @@
$(error TARGET_FLAVOUR must be fvp or fpga)
endif
+# Support for loading Android Image to DRAM
+TC_FPGA_ANDROID_IMG_IN_RAM := 0
+
+# Support Loading of FIP image to DRAM
+TC_FPGA_FIP_IMG_IN_RAM := 0
+
+# Use simple panel instead of vencoder with DPU
+TC_DPU_USE_SIMPLE_PANEL := 0
+
$(eval $(call add_defines, \
TARGET_PLATFORM \
TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \
TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \
TC_DPU_USE_SCMI_CLK \
TC_SCMI_PD_CTRL_EN \
+ TC_FPGA_ANDROID_IMG_IN_RAM \
+ TC_FPGA_FIP_IMG_IN_RAM \
+ TC_DPU_USE_SIMPLE_PANEL \
))
CSS_LOAD_SCP_IMAGES := 1
diff --git a/plat/arm/common/plat_arm_mbedtls_config.h b/plat/arm/common/plat_arm_mbedtls_config.h
index a5d0ec4..c2db595 100644
--- a/plat/arm/common/plat_arm_mbedtls_config.h
+++ b/plat/arm/common/plat_arm_mbedtls_config.h
@@ -7,7 +7,7 @@
#ifndef PLAT_ARM_MBEDTLS_CONFIG_H
#define PLAT_ARM_MBEDTLS_CONFIG_H
-#include <mbedtls_config-3.h>
+#include <default_mbedtls_config.h>
/**
* On Arm platforms, the ROTPK is always hashed using the SHA-256
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index dfa409f..e27af21 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -243,7 +243,8 @@
void mailbox_reset_warm(uint32_t reset_type);
void mailbox_clear_response(void);
-int intel_mailbox_get_config_status(uint32_t cmd, bool init_done);
+int intel_mailbox_get_config_status(uint32_t cmd, bool init_done,
+ uint32_t *err_states);
int intel_mailbox_is_fpga_not_ready(void);
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 94895ba..69f0008 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -638,7 +638,8 @@
return MBOX_RET_OK;
}
-int intel_mailbox_get_config_status(uint32_t cmd, bool init_done)
+int intel_mailbox_get_config_status(uint32_t cmd, bool init_done,
+ uint32_t *err_states)
{
int status;
uint32_t res, response[6];
@@ -653,6 +654,9 @@
res = response[RECONFIG_STATUS_STATE];
+ if (err_states != NULL)
+ *err_states = res;
+
if (res == MBOX_CFGSTAT_VAB_BS_PREAUTH) {
return MBOX_CFGSTAT_STATE_CONFIG;
}
@@ -684,11 +688,11 @@
int intel_mailbox_is_fpga_not_ready(void)
{
- int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true);
+ int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true, NULL);
if ((ret != MBOX_RET_OK) && (ret != MBOX_CFGSTAT_STATE_CONFIG)) {
ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
- false);
+ false, NULL);
}
return ret;
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 68deab9..71a626d 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -94,22 +94,25 @@
return 0;
}
-static uint32_t intel_mailbox_fpga_config_isdone(void)
+static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states)
{
uint32_t ret;
+ if (err_states == NULL)
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+
switch (request_type) {
case RECONFIGURATION:
ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
- true);
+ true, err_states);
break;
case BITSTREAM_AUTH:
ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
- false);
+ false, err_states);
break;
default:
ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
- false);
+ false, err_states);
break;
}
@@ -814,6 +817,7 @@
uint32_t retval = 0, completed_addr[3];
uint32_t retval2 = 0;
uint32_t mbox_error = 0;
+ uint32_t err_states = 0;
uint64_t retval64, rsu_respbuf[9];
uint32_t seu_respbuf[3];
int status = INTEL_SIP_SMC_STATUS_OK;
@@ -827,8 +831,8 @@
SMC_UUID_RET(handle, intl_svc_uid);
case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
- status = intel_mailbox_fpga_config_isdone();
- SMC_RET4(handle, status, 0, 0, 0);
+ status = intel_mailbox_fpga_config_isdone(&err_states);
+ SMC_RET4(handle, status, err_states, 0, 0);
case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
diff --git a/plat/mediatek/drivers/gpio/mtgpio_common.h b/plat/mediatek/drivers/gpio/mtgpio_common.h
index d6b858c..a93a065 100644
--- a/plat/mediatek/drivers/gpio/mtgpio_common.h
+++ b/plat/mediatek/drivers/gpio/mtgpio_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -97,7 +97,7 @@
}
struct mt_pin_info {
- uint8_t id;
+ uint16_t id;
uint8_t flag;
uint8_t bit;
uint16_t base;
diff --git a/plat/mediatek/mt8196/drivers/gpio/mtgpio.c b/plat/mediatek/mt8196/drivers/gpio/mtgpio.c
new file mode 100644
index 0000000..6257159
--- /dev/null
+++ b/plat/mediatek/mt8196/drivers/gpio/mtgpio.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2024, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <platform_def.h>
+#include <mtgpio.h>
+
+typedef enum {
+ REG_0 = 0,
+ REG_1,
+ REG_2,
+ REG_3,
+ REG_4,
+ REG_5,
+ REG_6,
+ REG_7,
+ REG_8,
+ REG_9,
+ REG_10,
+ REG_11,
+ REG_12,
+ REG_13,
+ REG_14
+} RegEnum;
+
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+{
+ uintptr_t reg_addr = 0U;
+ struct mt_pin_info gpio_info;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ gpio_info = mt_pin_infos[pin];
+
+ switch (gpio_info.base & 0xF) {
+ case REG_0:
+ reg_addr = IOCFG_RT_BASE;
+ break;
+ case REG_1:
+ reg_addr = IOCFG_RM1_BASE;
+ break;
+ case REG_2:
+ reg_addr = IOCFG_RM2_BASE;
+ break;
+ case REG_3:
+ reg_addr = IOCFG_RB_BASE;
+ break;
+ case REG_4:
+ reg_addr = IOCFG_BM1_BASE;
+ break;
+ case REG_5:
+ reg_addr = IOCFG_BM2_BASE;
+ break;
+ case REG_6:
+ reg_addr = IOCFG_BM3_BASE;
+ break;
+ case REG_7:
+ reg_addr = IOCFG_LT_BASE;
+ break;
+ case REG_8:
+ reg_addr = IOCFG_LM1_BASE;
+ break;
+ case REG_9:
+ reg_addr = IOCFG_LM2_BASE;
+ break;
+ case REG_10:
+ reg_addr = IOCFG_LB1_BASE;
+ break;
+ case REG_11:
+ reg_addr = IOCFG_LB2_BASE;
+ break;
+ case REG_12:
+ reg_addr = IOCFG_TM1_BASE;
+ break;
+ case REG_13:
+ reg_addr = IOCFG_TM2_BASE;
+ break;
+ case REG_14:
+ reg_addr = IOCFG_TM3_BASE;
+ break;
+ default:
+ break;
+ }
+
+ return reg_addr;
+}
diff --git a/plat/mediatek/mt8196/drivers/gpio/mtgpio.h b/plat/mediatek/mt8196/drivers/gpio/mtgpio.h
new file mode 100644
index 0000000..a33bdad
--- /dev/null
+++ b/plat/mediatek/mt8196/drivers/gpio/mtgpio.h
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2024, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <mtgpio_common.h>
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+ GPIO_UNSUPPORTED = -1,
+ GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6,
+ GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14,
+ GPIO15, GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22,
+ GPIO23, GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30,
+ GPIO31, GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38,
+ GPIO39, GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46,
+ GPIO47, GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54,
+ GPIO55, GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62,
+ GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70,
+ GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78,
+ GPIO79, GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86,
+ GPIO87, GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94,
+ GPIO95, GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102,
+ GPIO103, GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110,
+ GPIO111, GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118,
+ GPIO119, GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126,
+ GPIO127, GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134,
+ GPIO135, GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142,
+ GPIO143, GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150,
+ GPIO151, GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158,
+ GPIO159, GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166,
+ GPIO167, GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174,
+ GPIO175, GPIO176, GPIO177, GPIO178, GPIO179, GPIO180, GPIO181, GPIO182,
+ GPIO183, GPIO184, GPIO185, GPIO186, GPIO187, GPIO188, GPIO189, GPIO190,
+ GPIO191, GPIO192, GPIO193, GPIO194, GPIO195, GPIO196, GPIO197, GPIO198,
+ GPIO199, GPIO200, GPIO201, GPIO202, GPIO203, GPIO204, GPIO205, GPIO206,
+ GPIO207, GPIO208, GPIO209, GPIO210, GPIO211, GPIO212, GPIO213, GPIO214,
+ GPIO215, GPIO216, GPIO217, GPIO218, GPIO219, GPIO220, GPIO221, GPIO222,
+ GPIO223, GPIO224, GPIO225, GPIO226, GPIO227, GPIO228, GPIO229, GPIO230,
+ GPIO231, GPIO232, GPIO233, GPIO234, GPIO235, GPIO236, GPIO237, GPIO238,
+ GPIO239, GPIO240, GPIO241, GPIO242, GPIO243, GPIO244, GPIO245, GPIO246,
+ GPIO247, GPIO248, GPIO249, GPIO250, GPIO251, GPIO252, GPIO253, GPIO254,
+ GPIO255, GPIO256, GPIO257, GPIO258, GPIO259, GPIO260, GPIO261, GPIO262,
+ GPIO263, GPIO264, GPIO265, GPIO266, GPIO267, GPIO268, GPIO269, GPIO270,
+ MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+static const struct mt_pin_info mt_pin_infos[] = {
+ PIN(0, 0, 0, 0x18, 0x90),
+ PIN(1, 0, 1, 0x18, 0x90),
+ PIN(2, 0, 1, 0x1b, 0x70),
+ PIN(3, 0, 2, 0x1b, 0x70),
+ PIN(4, 0, 3, 0x1b, 0x70),
+ PIN(5, 0, 4, 0x1b, 0x70),
+ PIN(6, 0, 5, 0x1b, 0x70),
+ PIN(7, 0, 6, 0x1b, 0x70),
+ PIN(8, 0, 7, 0x1b, 0x70),
+ PIN(9, 0, 14, 0x29, 0xa0),
+ PIN(10, 0, 12, 0x29, 0xa0),
+ PIN(11, 0, 2, 0x18, 0x90),
+ PIN(12, 0, 13, 0x29, 0xa0),
+ PIN(13, 0, 1, 0x26, 0x90),
+ PIN(14, 0, 0, 0x13, 0x80),
+ PIN(15, 0, 2, 0x26, 0x90),
+ PIN(16, 0, 3, 0x26, 0x90),
+ PIN(17, 0, 4, 0x26, 0x90),
+ PIN(18, 0, 5, 0x26, 0x90),
+ PIN(19, 0, 6, 0x26, 0x90),
+ PIN(20, 0, 1, 0x13, 0x80),
+ PIN(21, 0, 3, 0x12, 0x80),
+ PIN(22, 0, 4, 0x12, 0x80),
+ PIN(23, 0, 5, 0x12, 0x80),
+ PIN(24, 0, 6, 0x12, 0x80),
+ PIN(25, 0, 7, 0x12, 0x80),
+ PIN(26, 0, 8, 0x12, 0x80),
+ PIN(27, 0, 9, 0x12, 0x80),
+ PIN(28, 0, 10, 0x12, 0x80),
+ PIN(29, 0, 11, 0x12, 0x80),
+ PIN(30, 0, 12, 0x12, 0x80),
+ PIN(31, 0, 13, 0x12, 0x80),
+ PIN(32, 0, 8, 0x11, 0x80),
+ PIN(33, 0, 9, 0x11, 0x80),
+ PIN(34, 0, 10, 0x11, 0x80),
+ PIN(35, 0, 11, 0x11, 0x80),
+ PIN(36, 0, 12, 0x11, 0x80),
+ PIN(37, 0, 13, 0x11, 0x80),
+ PIN(38, 0, 14, 0x11, 0x80),
+ PIN(39, 0, 6, 0x18, 0x90),
+ PIN(40, 0, 3, 0x18, 0x90),
+ PIN(41, 0, 5, 0x18, 0x90),
+ PIN(42, 0, 4, 0x18, 0x90),
+ PIN(43, 0, 7, 0x18, 0x90),
+ PIN(44, 0, 8, 0x18, 0x90),
+ PIN(45, 0, 9, 0x18, 0x90),
+ PIN(46, 0, 10, 0x18, 0x90),
+ PIN(47, 0, 13, 0x18, 0x90),
+ PIN(48, 0, 11, 0x18, 0x90),
+ PIN(49, 0, 14, 0x18, 0x90),
+ PIN(50, 0, 12, 0x18, 0x90),
+ PIN(51, 0, 15, 0x18, 0x90),
+ PIN(52, 0, 7, 0x29, 0xa0),
+ PIN(53, 0, 8, 0x29, 0xa0),
+ PIN(54, 0, 2, 0x29, 0xa0),
+ PIN(55, 0, 1, 0x29, 0xa0),
+ PIN(56, 0, 5, 0x29, 0xa0),
+ PIN(57, 0, 6, 0x29, 0xa0),
+ PIN(58, 0, 3, 0x29, 0xa0),
+ PIN(59, 0, 4, 0x29, 0xa0),
+ PIN(60, 1, 0, 0x29, 0xb0),
+ PIN(61, 0, 10, 0x29, 0xa0),
+ PIN(62, 0, 9, 0x29, 0xa0),
+ PIN(63, 0, 18, 0x29, 0xa0),
+ PIN(64, 0, 0, 0x29, 0xa0),
+ PIN(65, 0, 11, 0x29, 0xa0),
+ PIN(66, 0, 24, 0x29, 0xa0),
+ PIN(67, 0, 21, 0x29, 0xa0),
+ PIN(68, 0, 20, 0x29, 0xa0),
+ PIN(69, 0, 25, 0x29, 0xa0),
+ PIN(70, 0, 16, 0x29, 0xa0),
+ PIN(71, 0, 15, 0x29, 0xa0),
+ PIN(72, 0, 23, 0x29, 0xa0),
+ PIN(73, 0, 19, 0x29, 0xa0),
+ PIN(74, 0, 17, 0x29, 0xa0),
+ PIN(75, 0, 2, 0x1a, 0x80),
+ PIN(76, 0, 3, 0x1a, 0x80),
+ PIN(77, 0, 4, 0x1a, 0x80),
+ PIN(78, 0, 5, 0x1a, 0x80),
+ PIN(79, 0, 0, 0x1a, 0x80),
+ PIN(80, 0, 1, 0x1a, 0x80),
+ PIN(81, 0, 9, 0x1b, 0x70),
+ PIN(82, 0, 10, 0x1b, 0x70),
+ PIN(83, 0, 12, 0x1b, 0x70),
+ PIN(84, 0, 11, 0x1b, 0x70),
+ PIN(85, 0, 13, 0x1b, 0x70),
+ PIN(86, 0, 14, 0x1b, 0x70),
+ PIN(87, 0, 16, 0x1b, 0x70),
+ PIN(88, 0, 15, 0x1b, 0x70),
+ PIN(89, 0, 0, 0x1b, 0x70),
+ PIN(90, 0, 8, 0x1b, 0x70),
+ PIN(91, 0, 6, 0x1c, 0x80),
+ PIN(92, 0, 7, 0x1c, 0x80),
+ PIN(93, 0, 8, 0x1c, 0x80),
+ PIN(94, 0, 4, 0x1c, 0x80),
+ PIN(95, 0, 1, 0x1c, 0x80),
+ PIN(96, 0, 3, 0x1c, 0x80),
+ PIN(97, 0, 2, 0x1c, 0x80),
+ PIN(98, 0, 5, 0x1c, 0x80),
+ PIN(99, 0, 9, 0x1c, 0x80),
+ PIN(100, 0, 12, 0x1c, 0x80),
+ PIN(101, 0, 10, 0x1c, 0x80),
+ PIN(102, 0, 13, 0x1c, 0x80),
+ PIN(103, 0, 0, 0x1c, 0x80),
+ PIN(104, 0, 11, 0x1c, 0x80),
+ PIN(105, 0, 14, 0x1c, 0x80),
+ PIN(106, 0, 0, 0x15, 0x80),
+ PIN(107, 0, 1, 0x15, 0x80),
+ PIN(108, 0, 3, 0x15, 0x80),
+ PIN(109, 0, 2, 0x15, 0x80),
+ PIN(110, 0, 4, 0x15, 0x80),
+ PIN(111, 0, 5, 0x15, 0x80),
+ PIN(112, 0, 7, 0x15, 0x80),
+ PIN(113, 0, 6, 0x15, 0x80),
+ PIN(114, 0, 8, 0x15, 0x80),
+ PIN(115, 0, 9, 0x15, 0x80),
+ PIN(116, 0, 11, 0x15, 0x80),
+ PIN(117, 0, 10, 0x15, 0x80),
+ PIN(118, 0, 9, 0x26, 0x90),
+ PIN(119, 0, 10, 0x26, 0x90),
+ PIN(120, 0, 12, 0x26, 0x90),
+ PIN(121, 0, 11, 0x26, 0x90),
+ PIN(122, 0, 0, 0x26, 0x90),
+ PIN(123, 0, 7, 0x26, 0x90),
+ PIN(124, 0, 8, 0x26, 0x90),
+ PIN(125, 1, 0, 0x17, 0x80),
+ PIN(126, 1, 1, 0x17, 0x80),
+ PIN(127, 1, 2, 0x17, 0x80),
+ PIN(128, 1, 3, 0x17, 0x80),
+ PIN(129, 1, 4, 0x17, 0x80),
+ PIN(130, 1, 5, 0x17, 0x80),
+ PIN(131, 1, 9, 0x17, 0x80),
+ PIN(132, 1, 11, 0x17, 0x80),
+ PIN(133, 1, 10, 0x17, 0x80),
+ PIN(134, 1, 6, 0x17, 0x80),
+ PIN(135, 1, 8, 0x17, 0x80),
+ PIN(136, 1, 7, 0x17, 0x80),
+ PIN(137, 1, 10, 0x14, 0x70),
+ PIN(138, 1, 11, 0x14, 0x70),
+ PIN(139, 1, 12, 0x14, 0x70),
+ PIN(140, 1, 13, 0x14, 0x70),
+ PIN(141, 1, 14, 0x14, 0x70),
+ PIN(142, 1, 15, 0x14, 0x70),
+ PIN(143, 1, 16, 0x14, 0x70),
+ PIN(144, 1, 17, 0x14, 0x70),
+ PIN(145, 1, 0, 0x14, 0x70),
+ PIN(146, 1, 1, 0x14, 0x70),
+ PIN(147, 1, 2, 0x14, 0x70),
+ PIN(148, 1, 3, 0x14, 0x70),
+ PIN(149, 1, 4, 0x14, 0x70),
+ PIN(150, 1, 5, 0x14, 0x70),
+ PIN(151, 1, 6, 0x14, 0x70),
+ PIN(152, 1, 7, 0x14, 0x70),
+ PIN(153, 1, 9, 0x14, 0x70),
+ PIN(154, 1, 8, 0x14, 0x70),
+ PIN(155, 1, 18, 0x14, 0x70),
+ PIN(156, 1, 19, 0x14, 0x70),
+ PIN(157, 0, 1, 0x12, 0x80),
+ PIN(158, 0, 2, 0x12, 0x80),
+ PIN(159, 0, 0, 0x12, 0x80),
+ PIN(160, 0, 22, 0x13, 0x80),
+ PIN(161, 0, 20, 0x13, 0x80),
+ PIN(162, 0, 23, 0x13, 0x80),
+ PIN(163, 0, 21, 0x13, 0x80),
+ PIN(164, 0, 12, 0x13, 0x80),
+ PIN(165, 0, 14, 0x13, 0x80),
+ PIN(166, 0, 13, 0x13, 0x80),
+ PIN(167, 0, 15, 0x13, 0x80),
+ PIN(168, 0, 16, 0x13, 0x80),
+ PIN(169, 0, 17, 0x13, 0x80),
+ PIN(170, 0, 19, 0x13, 0x80),
+ PIN(171, 0, 18, 0x13, 0x80),
+ PIN(172, 0, 10, 0x13, 0x80),
+ PIN(173, 0, 11, 0x13, 0x80),
+ PIN(174, 0, 15, 0x11, 0x80),
+ PIN(175, 0, 16, 0x11, 0x80),
+ PIN(176, 0, 17, 0x11, 0x80),
+ PIN(177, 0, 18, 0x11, 0x80),
+ PIN(178, 0, 6, 0x11, 0x80),
+ PIN(179, 0, 7, 0x11, 0x80),
+ PIN(180, 0, 0, 0x11, 0x80),
+ PIN(181, 0, 1, 0x11, 0x80),
+ PIN(182, 0, 2, 0x11, 0x80),
+ PIN(183, 0, 3, 0x11, 0x80),
+ PIN(184, 0, 4, 0x11, 0x80),
+ PIN(185, 0, 5, 0x11, 0x80),
+ PIN(186, 0, 4, 0x1d, 0xc0),
+ PIN(187, 0, 5, 0x1d, 0xc0),
+ PIN(188, 0, 12, 0x1d, 0xc0),
+ PIN(189, 0, 17, 0x1d, 0xc0),
+ PIN(190, 0, 13, 0x1d, 0xc0),
+ PIN(191, 0, 18, 0x1d, 0xc0),
+ PIN(192, 0, 0, 0x1d, 0xc0),
+ PIN(193, 0, 6, 0x1d, 0xc0),
+ PIN(194, 0, 14, 0x1d, 0xc0),
+ PIN(195, 0, 19, 0x1d, 0xc0),
+ PIN(196, 0, 1, 0x1d, 0xc0),
+ PIN(197, 0, 7, 0x1d, 0xc0),
+ PIN(198, 0, 15, 0x1d, 0xc0),
+ PIN(199, 0, 20, 0x1d, 0xc0),
+ PIN(200, 0, 22, 0x1d, 0xc0),
+ PIN(201, 0, 25, 0x1d, 0xc0),
+ PIN(202, 0, 16, 0x1d, 0xc0),
+ PIN(203, 0, 21, 0x1d, 0xc0),
+ PIN(204, 0, 2, 0x1d, 0xc0),
+ PIN(205, 0, 3, 0x1d, 0xc0),
+ PIN(206, 0, 8, 0x1d, 0xc0),
+ PIN(207, 0, 9, 0x1d, 0xc0),
+ PIN(208, 0, 10, 0x1d, 0xc0),
+ PIN(209, 0, 11, 0x1d, 0xc0),
+ PIN(210, 0, 0, 0x2e, 0x90),
+ PIN(211, 0, 1, 0x2e, 0x90),
+ PIN(212, 0, 2, 0x2e, 0x90),
+ PIN(213, 0, 3, 0x2e, 0x90),
+ PIN(214, 0, 23, 0x1d, 0xc0),
+ PIN(215, 0, 24, 0x1d, 0xc0),
+ PIN(216, 0, 4, 0x2e, 0x90),
+ PIN(217, 1, 1, 0x2e, 0xa0),
+ PIN(218, 1, 2, 0x2e, 0xa0),
+ PIN(219, 1, 0, 0x2e, 0xa0),
+ PIN(220, 0, 5, 0x2e, 0x90),
+ PIN(221, 0, 6, 0x2e, 0x90),
+ PIN(222, 0, 8, 0x2e, 0x90),
+ PIN(223, 0, 7, 0x2e, 0x90),
+ PIN(224, 1, 3, 0x2e, 0xa0),
+ PIN(225, 1, 4, 0x2e, 0xa0),
+ PIN(226, 1, 5, 0x2e, 0xa0),
+ PIN(227, 1, 6, 0x2e, 0xa0),
+ PIN(228, 1, 7, 0x2e, 0xa0),
+ PIN(229, 1, 8, 0x2e, 0xa0),
+ PIN(230, 0, 13, 0x2f, 0x70),
+ PIN(231, 0, 14, 0x2f, 0x70),
+ PIN(232, 0, 10, 0x2f, 0x70),
+ PIN(233, 0, 0, 0x2f, 0x70),
+ PIN(234, 0, 3, 0x2f, 0x70),
+ PIN(235, 0, 1, 0x2f, 0x70),
+ PIN(236, 0, 2, 0x2f, 0x70),
+ PIN(237, 0, 6, 0x2f, 0x70),
+ PIN(238, 0, 5, 0x2f, 0x70),
+ PIN(239, 0, 19, 0x2f, 0x70),
+ PIN(240, 0, 18, 0x2f, 0x70),
+ PIN(241, 0, 16, 0x2f, 0x70),
+ PIN(242, 0, 17, 0x2f, 0x70),
+ PIN(243, 0, 15, 0x2f, 0x70),
+ PIN(244, 0, 12, 0x2f, 0x70),
+ PIN(245, 0, 9, 0x2f, 0x70),
+ PIN(246, 0, 8, 0x2f, 0x70),
+ PIN(247, 0, 7, 0x2f, 0x70),
+ PIN(248, 0, 4, 0x2f, 0x70),
+ PIN(249, 0, 20, 0x2f, 0x70),
+ PIN(250, 0, 11, 0x2f, 0x70),
+ PIN(251, 0, 2, 0x13, 0x80),
+ PIN(252, 0, 3, 0x13, 0x80),
+ PIN(253, 0, 4, 0x13, 0x80),
+ PIN(254, 0, 5, 0x13, 0x80),
+ PIN(255, 0, 6, 0x13, 0x80),
+ PIN(256, 0, 7, 0x13, 0x80),
+ PIN(257, 0, 8, 0x13, 0x80),
+ PIN(258, 0, 9, 0x13, 0x80),
+ PIN(259, 1, 9, 0x2e, 0xa0),
+ PIN(260, 1, 10, 0x2e, 0xa0),
+ PIN(261, 1, 11, 0x2e, 0xa0),
+ PIN(262, 1, 12, 0x2e, 0xa0),
+ PIN(263, 1, 13, 0x2e, 0xa0),
+ PIN(264, 1, 14, 0x2e, 0xa0),
+ PIN(265, 1, 15, 0x2e, 0xa0),
+ PIN(266, 1, 16, 0x2e, 0xa0),
+ PIN(267, 1, 2, 0x2f, 0x80),
+ PIN(268, 1, 3, 0x2f, 0x80),
+ PIN(269, 1, 0, 0x2f, 0x80),
+ PIN(270, 1, 1, 0x2f, 0x80),
+};
+
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8196/include/platform_def.h b/plat/mediatek/mt8196/include/platform_def.h
index 66c7cf8..5b45d92 100644
--- a/plat/mediatek/mt8196/include/platform_def.h
+++ b/plat/mediatek/mt8196/include/platform_def.h
@@ -36,6 +36,28 @@
#define SPM_BASE (IO_PHYS + 0x0C004000)
/*******************************************************************************
+ * GPIO related constants
+ ******************************************************************************/
+#define GPIO_BASE (IO_PHYS + 0x0002D000)
+#define RGU_BASE (IO_PHYS + 0x0C00B000)
+#define DRM_BASE (IO_PHYS + 0x0000D000)
+#define IOCFG_RT_BASE (IO_PHYS + 0x02000000)
+#define IOCFG_RM1_BASE (IO_PHYS + 0x02020000)
+#define IOCFG_RM2_BASE (IO_PHYS + 0x02040000)
+#define IOCFG_RB_BASE (IO_PHYS + 0x02060000)
+#define IOCFG_BM1_BASE (IO_PHYS + 0x02820000)
+#define IOCFG_BM2_BASE (IO_PHYS + 0x02840000)
+#define IOCFG_BM3_BASE (IO_PHYS + 0x02860000)
+#define IOCFG_LT_BASE (IO_PHYS + 0x03000000)
+#define IOCFG_LM1_BASE (IO_PHYS + 0x03020000)
+#define IOCFG_LM2_BASE (IO_PHYS + 0x03040000)
+#define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000)
+#define IOCFG_LB2_BASE (IO_PHYS + 0x03110000)
+#define IOCFG_TM1_BASE (IO_PHYS + 0x03800000)
+#define IOCFG_TM2_BASE (IO_PHYS + 0x03820000)
+#define IOCFG_TM3_BASE (IO_PHYS + 0x03860000)
+
+/*******************************************************************************
* UART related constants
******************************************************************************/
#define UART0_BASE (IO_PHYS + 0x06000000)
diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk
index cd428b2..fede717 100644
--- a/plat/mediatek/mt8196/platform.mk
+++ b/plat/mediatek/mt8196/platform.mk
@@ -14,9 +14,11 @@
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_INCLUDES := -I${MTK_PLAT}/common \
+ -I${MTK_PLAT}/drivers/gpio/ \
-I${MTK_PLAT}/include \
-I${MTK_PLAT}/include/${ARCH_VERSION} \
-I${MTK_PLAT} \
+ -I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/include \
-Idrivers/arm/gic \
@@ -34,6 +36,7 @@
BL31_SOURCES += drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
+ drivers/gpio/gpio.c \
lib/cpus/aarch64/cortex_a720.S \
lib/cpus/aarch64/cortex_x4.S \
lib/cpus/aarch64/cortex_x925.S \
@@ -44,6 +47,8 @@
plat/common/aarch64/crash_console_helpers.S \
${MTK_PLAT}/common/mtk_plat_common.c \
${MTK_PLAT}/common/params_setup.c \
+ ${MTK_PLAT}/drivers/gpio/mtgpio_common.c \
+ $(MTK_PLAT)/$(MTK_SOC)/drivers/gpio/mtgpio.c \
$(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c
include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 4813949..c19eb36 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -148,6 +148,13 @@
endif
$(eval $(call add_define,RCAR_RPC_HYPERFLASH_LOCKED))
+# Support A/B switching with RPC HYPERFLASH access by default
+# Use together with https://github.com/marex/abloader .
+ifndef RCAR_RPC_HYPERFLASH_ABLOADER
+RCAR_RPC_HYPERFLASH_ABLOADER := 0
+endif
+$(eval $(call add_define,RCAR_RPC_HYPERFLASH_ABLOADER))
+
# Process RCAR_SECURE_BOOT flag
ifndef RCAR_SECURE_BOOT
RCAR_SECURE_BOOT := 1
diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c
index 190c096..4fc0add 100644
--- a/tools/cert_create/src/key.c
+++ b/tools/cert_create/src/key.c
@@ -17,6 +17,7 @@
#include <openssl/engine.h>
#include <openssl/evp.h>
#include <openssl/pem.h>
+#include <openssl/ssl.h>
#include "cert.h"
#include "cmd_opt.h"
@@ -214,6 +215,13 @@
EVP_PKEY *pkey;
ENGINE *e;
+#if !USING_OPENSSL3
+ if (!OPENSSL_init_crypto(OPENSSL_INIT_LOAD_CONFIG, NULL)) {
+ fprintf(stderr, "Failed to init SSL\n");
+ return NULL;
+ }
+#endif
+
ENGINE_load_builtin_engines();
e = ENGINE_by_id("pkcs11");
if (!e) {
diff --git a/tools/renesas/rcar_layout_create/makefile b/tools/renesas/rcar_layout_create/makefile
index 7a64b19..f89f379 100644
--- a/tools/renesas/rcar_layout_create/makefile
+++ b/tools/renesas/rcar_layout_create/makefile
@@ -102,7 +102,7 @@
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
$(OUTPUT_FILE_SA0): $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) | $$(@D)/
- $(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib -T $(MEMORY_DEF_SA0) -o $(OUTPUT_FILE_SA0) -Wl,-Map $(FILE_NAME_SA0).map
+ $(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib -static -Wl,--build-id=none -T $(MEMORY_DEF_SA0) -o $(OUTPUT_FILE_SA0) -Wl,-Map $(FILE_NAME_SA0).map
$(FILE_NAME_SA6).srec: $(OUTPUT_FILE_SA6) | $$(@D)/
$(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
@@ -111,7 +111,7 @@
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
$(OUTPUT_FILE_SA6): $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6) | $$(@D)/
- $(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib -T $(MEMORY_DEF_SA6) -o $(OUTPUT_FILE_SA6) -Wl,-Map $(FILE_NAME_SA6).map
+ $(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib -static -Wl,--build-id=none -T $(MEMORY_DEF_SA6) -o $(OUTPUT_FILE_SA6) -Wl,-Map $(FILE_NAME_SA6).map
###################################################
# Compile