Merge pull request #116 from 'danh-arm:dh/refactoring-docs'
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index 46c70a1..691973f 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -38,24 +38,6 @@
#include <stdio.h>
#include "bl2_private.h"
-/*******************************************************************************
- * Runs BL31 from the given entry point. It jumps to a higher exception level
- * through an SMC.
- ******************************************************************************/
-static void __dead2 bl2_run_bl31(entry_point_info_t *bl31_ep_info,
- unsigned long arg1,
- unsigned long arg2)
-{
- /* Set the args pointer */
- bl31_ep_info->args.arg0 = arg1;
- bl31_ep_info->args.arg1 = arg2;
-
- /* Flush the params to be passed to memory */
- bl2_plat_flush_bl31_params();
-
- smc(RUN_IMAGE, (unsigned long)bl31_ep_info, 0, 0, 0, 0, 0, 0);
-}
-
/*******************************************************************************
* The only thing to do in BL2 is to load further images and pass control to
@@ -91,6 +73,9 @@
bl2_to_bl31_params = bl2_plat_get_bl31_params();
bl31_ep_info = bl2_plat_get_bl31_ep_info();
+ /* Set the X0 parameter to bl31 */
+ bl31_ep_info->args.arg0 = (unsigned long)bl2_to_bl31_params;
+
/*
* Load BL31. BL1 tells BL2 whether it has been TOP or BOTTOM loaded.
* To avoid fragmentation of trusted SRAM memory, BL31 is always
@@ -163,10 +148,13 @@
}
#endif /* BL32_BASE */
+ /* Flush the params to be passed to memory */
+ bl2_plat_flush_bl31_params();
+
/*
* Run BL31 via an SMC to BL1. Information on how to pass control to
* the BL32 (if present) and BL33 software images will be passed to
* BL31 as an argument.
*/
- bl2_run_bl31(bl31_ep_info, (unsigned long)bl2_to_bl31_params, 0);
+ smc(RUN_IMAGE, (unsigned long)bl31_ep_info, 0, 0, 0, 0, 0, 0);
}
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index e3673f0..a11cd71 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -105,8 +105,9 @@
* Read the id of the highest priority pending interrupt. If
* no interrupt is asserted then return to where we came from.
*/
+ mov x19, #INTR_ID_UNAVAILABLE
bl plat_ic_get_pending_interrupt_id
- cmp x0, #INTR_ID_UNAVAILABLE
+ cmp x19, x0
b.eq interrupt_exit_\label
#endif
@@ -125,6 +126,9 @@
/* Restore the reference to the 'handle' i.e. SP_EL3 */
mov x2, x20
+ /* x3 will point to a cookie (not used now) */
+ mov x3, xzr
+
/* Call the interrupt type handler */
blr x21
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 5117793..f79a122 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -37,6 +37,7 @@
#include <platform.h>
#include <runtime_svc.h>
#include <stdio.h>
+#include <string.h>
/*******************************************************************************
* This function pointer is used to initialise the BL32 image. It's initialized
@@ -154,6 +155,8 @@
{
entry_point_info_t *next_image_info;
uint32_t scr, image_type;
+ cpu_context_t *ctx;
+ gp_regs_t *gp_regs;
/* Determine which image to execute next */
image_type = bl31_get_next_image_type();
@@ -167,6 +170,7 @@
/* Program EL3 registers to enable entry into the next EL */
next_image_info = bl31_plat_get_next_image_ep_info(image_type);
assert(next_image_info);
+ assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr));
scr = read_scr();
scr &= ~SCR_NS_BIT;
@@ -182,13 +186,21 @@
* Tell the context mgmt. library to ensure that SP_EL3 points to
* the right context to exit from EL3 correctly.
*/
- cm_set_el3_eret_context(GET_SECURITY_STATE(next_image_info->h.attr),
+ cm_set_el3_eret_context(image_type,
next_image_info->pc,
next_image_info->spsr,
scr);
+ /*
+ * Save the args generated in BL2 for the image in the right context
+ * used on its entry
+ */
+ ctx = cm_get_context(read_mpidr(), image_type);
+ gp_regs = get_gpregs_ctx(ctx);
+ memcpy(gp_regs, (void *)&next_image_info->args, sizeof(aapcs64_params_t));
+
/* Finally set the next context */
- cm_set_next_eret_context(GET_SECURITY_STATE(next_image_info->h.attr));
+ cm_set_next_eret_context(image_type);
}
/*******************************************************************************
diff --git a/plat/fvp/bl2_fvp_setup.c b/plat/fvp/bl2_fvp_setup.c
index e18cf7d..72580f9 100644
--- a/plat/fvp/bl2_fvp_setup.c
+++ b/plat/fvp/bl2_fvp_setup.c
@@ -156,6 +156,9 @@
******************************************************************************/
struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
{
+#if DEBUG
+ bl31_ep_info->args.arg1 = FVP_BL31_PLAT_PARAM_VAL;
+#endif
return bl31_ep_info;
}
diff --git a/plat/fvp/bl31_fvp_setup.c b/plat/fvp/bl31_fvp_setup.c
index 5169bd7..6554ec3 100644
--- a/plat/fvp/bl31_fvp_setup.c
+++ b/plat/fvp/bl31_fvp_setup.c
@@ -159,6 +159,7 @@
assert(from_bl2->h.version >= VERSION_1);
bl2_to_bl31_params = from_bl2;
+ assert(((unsigned long)plat_params_from_bl2) == FVP_BL31_PLAT_PARAM_VAL);
#endif
}
diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h
index 9072a22..04ba611 100644
--- a/plat/fvp/fvp_def.h
+++ b/plat/fvp/fvp_def.h
@@ -115,6 +115,9 @@
/* Load address of BL33 in the FVP port */
#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
+/* Special value used to verify platform parameters from BL2 to BL3-1 */
+#define FVP_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
+
/*
* V2M sysled bit definitions. The values written to this
* register are defined in arch.h & runtime_svc.h. Only
diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c
index 4477fd7..1a6913a 100644
--- a/services/spd/tspd/tspd_main.c
+++ b/services/spd/tspd/tspd_main.c
@@ -90,7 +90,7 @@
#if IMF_READ_INTERRUPT_ID
/* Check the security status of the interrupt */
- assert(ic_get_interrupt_group(id) == SECURE);
+ assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1);
#endif
/* Sanity check the pointer to this cpu's context */