include: add U()/ULL() macros for constants
This patch uses the U() and ULL() macros for constants, to fix some
of the signed-ness defects flagged by the MISRA scanner.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h
index 66efa20..91f2f05 100644
--- a/include/lib/xlat_tables/xlat_tables.h
+++ b/include/lib/xlat_tables/xlat_tables.h
@@ -27,14 +27,14 @@
/*
* Shifts and masks to access fields of an mmap_attr_t
*/
-#define MT_TYPE_MASK 0x7
+#define MT_TYPE_MASK U(0x7)
#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK)
/* Access permissions (RO/RW) */
-#define MT_PERM_SHIFT 3
+#define MT_PERM_SHIFT U(3)
/* Security state (SECURE/NS) */
-#define MT_SEC_SHIFT 4
+#define MT_SEC_SHIFT U(4)
/* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */
-#define MT_EXECUTE_SHIFT 5
+#define MT_EXECUTE_SHIFT U(5)
/*
* Memory mapping attributes
@@ -51,11 +51,11 @@
MT_MEMORY,
/* Values up to 7 are reserved to add new memory types in the future */
- MT_RO = 0 << MT_PERM_SHIFT,
- MT_RW = 1 << MT_PERM_SHIFT,
+ MT_RO = U(0) << MT_PERM_SHIFT,
+ MT_RW = U(1) << MT_PERM_SHIFT,
- MT_SECURE = 0 << MT_SEC_SHIFT,
- MT_NS = 1 << MT_SEC_SHIFT,
+ MT_SECURE = U(0) << MT_SEC_SHIFT,
+ MT_NS = U(1) << MT_SEC_SHIFT,
/*
* Access permissions for instruction execution are only relevant for
@@ -64,8 +64,8 @@
* - Device memory is always marked as execute-never.
* - Read-write normal memory is always marked as execute-never.
*/
- MT_EXECUTE = 0 << MT_EXECUTE_SHIFT,
- MT_EXECUTE_NEVER = 1 << MT_EXECUTE_SHIFT,
+ MT_EXECUTE = U(0) << MT_EXECUTE_SHIFT,
+ MT_EXECUTE_NEVER = U(1) << MT_EXECUTE_SHIFT,
} mmap_attr_t;
#define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE)
diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index c54b729..4b993a0 100644
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h
@@ -10,23 +10,23 @@
#include <utils_def.h>
/* Miscellaneous MMU related constants */
-#define NUM_2MB_IN_GB (1 << 9)
-#define NUM_4K_IN_2MB (1 << 9)
-#define NUM_GB_IN_4GB (1 << 2)
+#define NUM_2MB_IN_GB (U(1) << 9)
+#define NUM_4K_IN_2MB (U(1) << 9)
+#define NUM_GB_IN_4GB (U(1) << 2)
-#define TWO_MB_SHIFT 21
-#define ONE_GB_SHIFT 30
-#define FOUR_KB_SHIFT 12
+#define TWO_MB_SHIFT U(21)
+#define ONE_GB_SHIFT U(30)
+#define FOUR_KB_SHIFT U(12)
#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
-#define INVALID_DESC 0x0
-#define BLOCK_DESC 0x1 /* Table levels 0-2 */
-#define TABLE_DESC 0x3 /* Table levels 0-2 */
-#define PAGE_DESC 0x3 /* Table level 3 */
-#define DESC_MASK 0x3
+#define INVALID_DESC U(0x0)
+#define BLOCK_DESC U(0x1) /* Table levels 0-2 */
+#define TABLE_DESC U(0x3) /* Table levels 0-2 */
+#define PAGE_DESC U(0x3) /* Table level 3 */
+#define DESC_MASK U(0x3)
#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
@@ -40,36 +40,36 @@
#define CONT_HINT (ULL(1) << 0)
#define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
-#define NON_GLOBAL (1 << 9)
-#define ACCESS_FLAG (1 << 8)
-#define NSH (0x0 << 6)
-#define OSH (0x2 << 6)
-#define ISH (0x3 << 6)
+#define NON_GLOBAL (U(1) << 9)
+#define ACCESS_FLAG (U(1) << 8)
+#define NSH (U(0x0) << 6)
+#define OSH (U(0x2) << 6)
+#define ISH (U(0x3) << 6)
#define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT /* 4, 16 or 64 KB */
-#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT)
+#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT)
#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
-#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */
-#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT)
+#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */
+#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT)
#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
-#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT)
#ifdef AARCH32
-#define XLAT_TABLE_LEVEL_MIN 1
+#define XLAT_TABLE_LEVEL_MIN U(1)
#else
-#define XLAT_TABLE_LEVEL_MIN 0
+#define XLAT_TABLE_LEVEL_MIN U(0)
#endif /* AARCH32 */
-#define XLAT_TABLE_LEVEL_MAX 3
+#define XLAT_TABLE_LEVEL_MAX U(3)
/* Values for number of entries in each MMU translation table */
#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
-#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT)
+#define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT)
#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
/* Values to convert a memory address to an index into a translation table */
@@ -90,34 +90,34 @@
* AP[1] bit is ignored by hardware and is
* treated as if it is One in EL2/EL3
*/
-#define AP_RO (0x1 << 5)
-#define AP_RW (0x0 << 5)
+#define AP_RO (U(0x1) << 5)
+#define AP_RW (U(0x0) << 5)
-#define NS (0x1 << 3)
-#define ATTR_NON_CACHEABLE_INDEX 0x2
-#define ATTR_DEVICE_INDEX 0x1
-#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
-#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
+#define NS (U(0x1) << 3)
+#define ATTR_NON_CACHEABLE_INDEX U(0x2)
+#define ATTR_DEVICE_INDEX U(0x1)
+#define ATTR_IWBWA_OWBWA_NTR_INDEX U(0x0)
+#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2)
/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
-#define ATTR_NON_CACHEABLE (0x44)
+#define ATTR_NON_CACHEABLE U(0x44)
/* Device-nGnRE */
-#define ATTR_DEVICE (0x4)
+#define ATTR_DEVICE U(0x4)
/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
-#define ATTR_IWBWA_OWBWA_NTR (0xff)
+#define ATTR_IWBWA_OWBWA_NTR U(0xff)
#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
-#define ATTR_INDEX_MASK 0x3
+#define ATTR_INDEX_MASK U(0x3)
#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK)
/*
* Flags to override default values used to program system registers while
* enabling the MMU.
*/
-#define DISABLE_DCACHE (1 << 0)
+#define DISABLE_DCACHE (U(1) << 0)
/*
* This flag marks the translation tables are Non-cacheable for MMU accesses.
* If the flag is not specified, by default the tables are cacheable.
*/
-#define XLAT_TABLE_NC (1 << 1)
+#define XLAT_TABLE_NC (U(1) << 1)
#endif /* __XLAT_TABLES_DEFS_H__ */
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h
index e7ed233..9db6719 100644
--- a/include/lib/xlat_tables/xlat_tables_v2.h
+++ b/include/lib/xlat_tables/xlat_tables_v2.h
@@ -27,14 +27,14 @@
/*
* Shifts and masks to access fields of an mmap_attr_t
*/
-#define MT_TYPE_MASK 0x7
+#define MT_TYPE_MASK U(0x7)
#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK)
/* Access permissions (RO/RW) */
-#define MT_PERM_SHIFT 3
+#define MT_PERM_SHIFT U(3)
/* Security state (SECURE/NS) */
-#define MT_SEC_SHIFT 4
+#define MT_SEC_SHIFT U(4)
/* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */
-#define MT_EXECUTE_SHIFT 5
+#define MT_EXECUTE_SHIFT U(5)
/* All other bits are reserved */
/*
@@ -52,11 +52,11 @@
MT_MEMORY,
/* Values up to 7 are reserved to add new memory types in the future */
- MT_RO = 0 << MT_PERM_SHIFT,
- MT_RW = 1 << MT_PERM_SHIFT,
+ MT_RO = U(0) << MT_PERM_SHIFT,
+ MT_RW = U(1) << MT_PERM_SHIFT,
- MT_SECURE = 0 << MT_SEC_SHIFT,
- MT_NS = 1 << MT_SEC_SHIFT,
+ MT_SECURE = U(0) << MT_SEC_SHIFT,
+ MT_NS = U(1) << MT_SEC_SHIFT,
/*
* Access permissions for instruction execution are only relevant for
@@ -65,8 +65,8 @@
* - Device memory is always marked as execute-never.
* - Read-write normal memory is always marked as execute-never.
*/
- MT_EXECUTE = 0 << MT_EXECUTE_SHIFT,
- MT_EXECUTE_NEVER = 1 << MT_EXECUTE_SHIFT,
+ MT_EXECUTE = U(0) << MT_EXECUTE_SHIFT,
+ MT_EXECUTE_NEVER = U(1) << MT_EXECUTE_SHIFT,
} mmap_attr_t;
#define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE)