diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index ce45076..905b016 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -783,6 +783,10 @@
   Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
   r1p1. It is fixed in r1p2.
 
+- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3
+  CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is
+  fixed in r1p2.
+
 - ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3
   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
   CPU. It is fixed in r1p2.
diff --git a/docs/process/code-review-guidelines.rst b/docs/process/code-review-guidelines.rst
index bd42811..5e9a667 100644
--- a/docs/process/code-review-guidelines.rst
+++ b/docs/process/code-review-guidelines.rst
@@ -242,4 +242,4 @@
 
 *Copyright (c) 2020-2023, Arm Limited. All rights reserved.*
 
-.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
+.. _Project Maintenance Process: https://trusted-firmware-docs.readthedocs.io/en/latest/generic_processes/project_maintenance_process.html
diff --git a/docs/process/maintenance.rst b/docs/process/maintenance.rst
index 45aada2..5ee435e 100644
--- a/docs/process/maintenance.rst
+++ b/docs/process/maintenance.rst
@@ -51,5 +51,5 @@
    and update the list of maintainers on the :ref:`Project
    Maintenance<maintainers>` page.
 
-.. _trustedfirmware.org Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
-.. _here: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/#how-to-become-a-maintainer
+.. _trustedfirmware.org Project Maintenance Process: https://trusted-firmware-docs.readthedocs.io/en/latest/generic_processes/project_maintenance_process.html
+.. _here: https://trusted-firmware-docs.readthedocs.io/en/latest/generic_processes/project_maintenance_process.html#how-to-become-a-maintainer
diff --git a/docs/process/security.rst b/docs/process/security.rst
index c6429ad..bbc939a 100644
--- a/docs/process/security.rst
+++ b/docs/process/security.rst
@@ -88,7 +88,7 @@
 .. |TFV-9| replace:: :ref:`Advisory TFV-9 (CVE-2022-23960)`
 .. |TFV-10| replace:: :ref:`Advisory TFV-10 (CVE-2022-47630)`
 
-.. _TrustedFirmware.org security incident process: https://developer.trustedfirmware.org/w/collaboration/security_center/
+.. _TrustedFirmware.org security incident process: https://trusted-firmware-docs.readthedocs.io/en/latest/security_center/
 
 --------------
 
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 95f3d10..7e9a7fc 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -57,6 +57,13 @@
 
 check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
 
+workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
+	/* dsb before isb of power down sequence */
+	dsb sy
+workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB
+
+check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1)
+
 workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509
 	/* Set CPUACTLR3_EL1 bit 47 */
 	sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47
@@ -82,12 +89,13 @@
 	 * ----------------------------------------------------
 	 */
 func cortex_x3_core_pwr_dwn
-apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+	apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
 	/* ---------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------------
 	 */
 	sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
 	isb
 	ret
 endfunc cortex_x3_core_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 302f697..0ad5e78 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -786,6 +786,10 @@
 # to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
 CPU_FLAG_LIST += ERRATA_X3_2742421
 
+# Flag to apply erratum 2743088 workaround on powerdown. This erratum applies
+# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_2743088
+
 # Flag to apply erratum 2779509 workaround on reset. This erratum applies
 # to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
 CPU_FLAG_LIST += ERRATA_X3_2779509
diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index 3912ba8..5c15148 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -86,6 +86,11 @@
 	/* Store magic number */
 	// TODO: Temp workaround to ungate testing
 	// mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ);
+
+	if (!intel_mailbox_is_fpga_not_ready()) {
+		socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
+					FPGA2SOC_MASK | F2SDRAM0_MASK);
+	}
 }
 
 void bl2_el3_plat_arch_setup(void)
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 8987a63..46596bf 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -142,6 +142,8 @@
 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7				0x274
 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8				0x278
 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9				0x27C
+#define SOCFPGA_SYSMGR_SDM_BE_AWADDR_REMAP				0x280
+#define SOCFPGA_SYSMGR_SDM_BE_ARADDR_REMAP				0x284
 
 /* QSPI ECC from SDM register */
 #define SOCFPGA_ECC_QSPI_CTRL						0x08
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index 29fbf92..3e44833 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -243,6 +243,10 @@
 int intel_mailbox_get_config_status(uint32_t cmd, bool init_done);
 int intel_mailbox_is_fpga_not_ready(void);
 
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+void intel_smmu_hps_remapper_init(uint64_t *mem);
+#endif
+
 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
 int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
 int mailbox_rsu_update(uint32_t *flash_offset);
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index cb98273..f68dc29 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -229,6 +229,10 @@
 		request_type = BITSTREAM_AUTH;
 	}
 
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	intel_smmu_hps_remapper_init(0U);
+#endif
+
 	mailbox_clear_response();
 
 	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
@@ -310,6 +314,10 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	intel_smmu_hps_remapper_init(&mem);
+#endif
+
 	for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
 		int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
 
@@ -730,6 +738,24 @@
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+/* SMMU HPS Remapper */
+void intel_smmu_hps_remapper_init(uint64_t *mem)
+{
+	/* Read out Bit 1 value */
+	uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02);
+
+	if (remap == 0x00) {
+		/* Update DRAM Base address for SDM SMMU */
+		mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE);
+		mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE);
+		*mem = *mem - DRAM_BASE;
+	} else {
+		*mem = *mem - DRAM_BASE;
+	}
+}
+#endif
+
 /*
  * This function is responsible for handling all SiP calls from the NS world
  */
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 8f1f1fe..537cb5c 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -449,8 +449,9 @@
 		[1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
 		[2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
 		[3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
-		[4] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
-		[5 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+		[4] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
+		[5] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
+		[6 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
 #endif /* CORTEX_X3_H_INC */