Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration
* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): support QSPI ECC Linux for Stratix10
feat(intel): add in QSPI ECC for Linux
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h
index cb9222d..20a62be 100644
--- a/plat/intel/soc/agilex/include/agilex_system_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_system_manager.h
@@ -143,6 +143,18 @@
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
+/* QSPI ECC from SDM register */
+#define SOCFPGA_ECC_QSPI_CTRL 0x08
+#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
+#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
+#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18
+#define SOCFPGA_ECC_QSPI_INTMODE 0x1C
+#define SOCFPGA_ECC_QSPI_INTSTAT 0x20
+#define SOCFPGA_ECC_QSPI_INTTEST 0x24
+#define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78
+#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
+#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
+
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
@@ -183,6 +195,9 @@
#define RMMUSECSID_REG_VAL BIT(5)
/* Macros */
+#define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \
+ + (SOCFPGA_ECC_QSPI_##_reg))
+
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg))
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index a9f6684..0895bf9 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -12,11 +12,11 @@
#include <platform_def.h>
/* Platform Setting */
-#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
-#define BOOT_SOURCE BOOT_SOURCE_SDMMC
-#define PLAT_PRIMARY_CPU 0
+#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
+#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
-#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
+#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
@@ -34,6 +34,7 @@
#define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100
#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
+#define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000
#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100
@@ -64,17 +65,17 @@
#define DEVICE4_BASE (0x2000000000)
#define DEVICE4_SIZE (0x0100000000)
-#define BL2_BASE (0xffe00000)
-#define BL2_LIMIT (0xffe2b000)
+#define BL2_BASE (0xffe00000)
+#define BL2_LIMIT (0xffe2b000)
-#define BL31_BASE (0x1000)
-#define BL31_LIMIT (0x81000)
+#define BL31_BASE (0x1000)
+#define BL31_LIMIT (0x81000)
/*******************************************************************************
* UART related constants
******************************************************************************/
-#define PLAT_UART0_BASE (0xFFC02000)
-#define PLAT_UART1_BASE (0xFFC02100)
+#define PLAT_UART0_BASE (0xFFC02000)
+#define PLAT_UART1_BASE (0xFFC02100)
/*******************************************************************************
* WDT related constants
@@ -84,10 +85,10 @@
/*******************************************************************************
* GIC related constants
******************************************************************************/
-#define PLAT_GIC_BASE (0xFFFC0000)
-#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
-#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
-#define PLAT_GICR_BASE 0
+#define PLAT_GIC_BASE (0xFFFC0000)
+#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
+#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
+#define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
@@ -95,8 +96,8 @@
/*******************************************************************************
* SDMMC related pointer function
******************************************************************************/
-#define SDMMC_READ_BLOCKS mmc_read_blocks
-#define SDMMC_WRITE_BLOCKS mmc_write_blocks
+#define SDMMC_READ_BLOCKS mmc_read_blocks
+#define SDMMC_WRITE_BLOCKS mmc_write_blocks
/*******************************************************************************
* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 582afc3..46596bf 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -145,6 +145,18 @@
#define SOCFPGA_SYSMGR_SDM_BE_AWADDR_REMAP 0x280
#define SOCFPGA_SYSMGR_SDM_BE_ARADDR_REMAP 0x284
+/* QSPI ECC from SDM register */
+#define SOCFPGA_ECC_QSPI_CTRL 0x08
+#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
+#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
+#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18
+#define SOCFPGA_ECC_QSPI_INTMODE 0x1C
+#define SOCFPGA_ECC_QSPI_INTSTAT 0x20
+#define SOCFPGA_ECC_QSPI_INTTEST 0x24
+#define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78
+#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
+#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
+
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
@@ -189,9 +201,10 @@
#define RMMUSECSID_REG_VAL BIT(5)
/* Macros */
+#define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \
+ + (SOCFPGA_ECC_QSPI_##_reg))
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg))
-
#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL \
| RSTREAMIDEN_REG_CTRL
#define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL \
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index 597612f..1ce1cff 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -48,6 +48,7 @@
#define SOCFPGA_SYSMGR_REG_BASE 0x10d12000
#define SOCFPGA_PINMUX_REG_BASE 0x10d13000
#define SOCFPGA_NAND_REG_BASE 0x10B80000
+#define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000
#define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000
#define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
index f860f57..1327b81 100644
--- a/plat/intel/soc/common/include/socfpga_system_manager.h
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -14,7 +14,6 @@
#define SOCFPGA_SYSMGR_SDMMC 0x28
/* Field Masking */
-
#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 8e279b8..f68dc29 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -431,8 +431,19 @@
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */
- return 0;
#endif
+ case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */
+ case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */
+ case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */
+ case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */
+ case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */
+ case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */
+ case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */
+ case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */
+ case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
+ case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
+ return 0;
+
default:
break;
}
@@ -459,7 +470,15 @@
return INTEL_SIP_SMC_STATUS_ERROR;
}
- mmio_write_32(reg_addr, val);
+ switch (reg_addr) {
+ case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
+ case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
+ mmio_write_16(reg_addr, val);
+ break;
+ default:
+ mmio_write_32(reg_addr, val);
+ break;
+ }
return intel_secure_reg_read(reg_addr, retval);
}
diff --git a/plat/intel/soc/n5x/include/n5x_system_manager.h b/plat/intel/soc/n5x/include/n5x_system_manager.h
index b628219..3610a6e 100644
--- a/plat/intel/soc/n5x/include/n5x_system_manager.h
+++ b/plat/intel/soc/n5x/include/n5x_system_manager.h
@@ -143,6 +143,18 @@
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
+/* QSPI ECC from SDM register */
+#define SOCFPGA_ECC_QSPI_CTRL 0x08
+#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
+#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
+#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18
+#define SOCFPGA_ECC_QSPI_INTMODE 0x1C
+#define SOCFPGA_ECC_QSPI_INTSTAT 0x20
+#define SOCFPGA_ECC_QSPI_INTTEST 0x24
+#define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78
+#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
+#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
+
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
@@ -186,6 +198,9 @@
#define RMMUSECSID_REG_VAL BIT(5)
/* Macros */
+#define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \
+ + (SOCFPGA_ECC_QSPI_##_reg))
+
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg))
#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL | \
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index 93b0c18..3568e3b 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -29,11 +29,10 @@
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000)
#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
-
#define SOCFPGA_MMC_REG_BASE U(0xff808000)
-
#define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000)
#define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000)
+#define SOCFPGA_ECC_QSPI_REG_BASE U(0xffa22000)
#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
index 88c0b46..e7bf730 100644
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@@ -142,6 +142,18 @@
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
+/* QSPI ECC from SDM register */
+#define SOCFPGA_ECC_QSPI_CTRL 0x08
+#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
+#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
+#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18
+#define SOCFPGA_ECC_QSPI_INTMODE 0x1C
+#define SOCFPGA_ECC_QSPI_INTSTAT 0x20
+#define SOCFPGA_ECC_QSPI_INTTEST 0x24
+#define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78
+#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
+#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
+
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
@@ -182,6 +194,8 @@
#define RMMUSECSID_REG_VAL BIT(5)
/* Macros */
+#define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \
+ + (SOCFPGA_ECC_QSPI_##_reg))
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg))
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index b766db0..84b7eec 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -33,6 +33,7 @@
#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
+#define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000
#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100