| commit | c5baddf6408f1d6e11e35ed98a6f07395271c250 | [log] [tgz] |
|---|---|---|
| author | Tien Hock Loh <tien.hock.loh@intel.com> | Mon May 11 01:11:48 2020 -0700 |
| committer | Manish Pandey <manish.pandey2@arm.com> | Mon Jun 08 22:03:41 2020 +0000 |
| tree | 2b00be35e84f6d4efe92af58a4b6be814cd7f98e | |
| parent | fcbc33d314094d8d28caa980aedb0253f0dc8066 [diff] [blame] |
plat: intel: Add FPGAINTF configuration to when configuring pinmux FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h index 93aa846..8b42d47 100644 --- a/plat/intel/soc/common/include/socfpga_system_manager.h +++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -13,6 +13,8 @@ #define SOCFPGA_SYSMGR_SDMMC 0x28 +#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c + #define SOCFPGA_SYSMGR_EMAC_0 0x44 #define SOCFPGA_SYSMGR_EMAC_1 0x48 #define SOCFPGA_SYSMGR_EMAC_2 0x4c