fix(cpus): workaround platforms non-arm interconnect
The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP. The ABI helps assist the Kernel
in the process of mitigation for the following errata:
Cortex-A715: erratum 2701951
Neoverse V2: erratum 2719103
Cortex-A710: erratum 2701952
Cortex-X2: erratum 2701952
Neoverse N2: erratum 2728475
Neoverse V1: erratum 2701953
Cortex-A78: erratum 2712571
Cortex-A78AE: erratum 2712574
Cortex-A78C: erratum 2712575
EL3 provides an appropriate return value via errata ABI when the
kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the
appropriate erratum ID.
Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index d473df6..bf9409d 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -200,10 +200,12 @@
[6] = {2242635, 0x10, 0x12, ERRATA_A78_2242635},
[7] = {2376745, 0x00, 0x12, ERRATA_A78_2376745},
[8] = {2395406, 0x00, 0x12, ERRATA_A78_2395406},
- [9] = {2742426, 0x00, 0x12, ERRATA_A78_2742426},
- [10] = {2772019, 0x00, 0x12, ERRATA_A78_2772019},
- [11] = {2779479, 0x00, 0x12, ERRATA_A78_2779479},
- [12 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [9] = {2712571, 0x00, 0x12, ERRATA_A78_2712571, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [10] = {2742426, 0x00, 0x12, ERRATA_A78_2742426},
+ [11] = {2772019, 0x00, 0x12, ERRATA_A78_2772019},
+ [12] = {2779479, 0x00, 0x12, ERRATA_A78_2779479},
+ [13 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A78_H_INC */
@@ -216,7 +218,9 @@
[1] = {1951502, 0x00, 0x01, ERRATA_A78_AE_1951502},
[2] = {2376748, 0x00, 0x01, ERRATA_A78_AE_2376748},
[3] = {2395408, 0x00, 0x01, ERRATA_A78_AE_2395408},
- [4 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [4] = {2712574, 0x00, 0x02, ERRATA_A78_AE_2712574, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [5 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A78_AE_H_INC */
@@ -229,9 +233,11 @@
[1] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638},
[2] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749},
[3] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
- [4] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
- [5] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
- [6 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [4] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [5] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
+ [6] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
+ [7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A78C_H_INC */
@@ -287,9 +293,11 @@
[9] = {2216392, 0x10, 0x11, ERRATA_V1_2216392},
[10] = {2294912, 0x00, 0x11, ERRATA_V1_2294912},
[11] = {2372203, 0x00, 0x11, ERRATA_V1_2372203},
- [12] = {2743093, 0x00, 0x12, ERRATA_V1_2743093},
- [13] = {2779461, 0x00, 0x12, ERRATA_V1_2779461},
- [14 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [12] = {2701953, 0x00, 0x11, ERRATA_V1_2701953, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [13] = {2743093, 0x00, 0x12, ERRATA_V1_2743093},
+ [14] = {2779461, 0x00, 0x12, ERRATA_V1_2779461},
+ [15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_V1_H_INC */
@@ -312,7 +320,9 @@
[11] = {2282622, 0x00, 0x21, ERRATA_A710_2282622},
[12] = {2291219, 0x00, 0x20, ERRATA_A710_2291219},
[13] = {2371105, 0x00, 0x20, ERRATA_A710_2371105},
- [14] = {2768515, 0x00, 0x21, ERRATA_A710_2768515}
+ [14] = {2701952, 0x00, 0x21, ERRATA_A710_2701952, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [15] = {2768515, 0x00, 0x21, ERRATA_A710_2768515}
}
},
#endif /* CORTEX_A710_H_INC */
@@ -334,8 +344,10 @@
[10] = {2326639, 0x00, 0x00, ERRATA_N2_2326639},
[11] = {2376738, 0x00, 0x00, ERRATA_N2_2376738},
[12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
- [13] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
- [14 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [13] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [14] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
+ [15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N2_H_INC */
@@ -353,8 +365,10 @@
[6] = {2216384, 0x00, 0x20, ERRATA_X2_2216384},
[7] = {2282622, 0x00, 0x21, ERRATA_X2_2282622},
[8] = {2371105, 0x00, 0x21, ERRATA_X2_2371105},
- [9] = {2768515, 0x00, 0x21, ERRATA_X2_2768515},
- [10 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [9] = {2701952, 0x00, 0x21, ERRATA_X2_2701952, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [10] = {2768515, 0x00, 0x21, ERRATA_X2_2768515},
+ [11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_X2_H_INC */
@@ -378,6 +392,28 @@
}
},
#endif /* CORTEX_A510_H_INC */
+
+#if NEOVERSE_V2_H_INC
+{
+ .cpu_partnumber = NEOVERSE_V2_MIDR,
+ .cpu_errata_list = {
+ [0] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* NEOVERSE_V2_H_INC */
+
+#if CORTEX_A715_H_INC
+{
+ .cpu_partnumber = CORTEX_MAKALU_MIDR,
+ .cpu_errata_list = {
+ [0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A715_H_INC */
};
/*