feat(imx8ulp): add a flag check for the ddr status
for some user case, the ddr may need to be controlled
by RTD side to save power, when APD resume from low
power mode, it should wait ddr is ready for access.
currently we use a GPR in SIM_RTD_SEC as a flag to
indicate when the DDR is for access, non-zero value
means the DDR can be access from APD.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6fb0cc17a040d803a597304620202423f646f294
diff --git a/plat/imx/imx8ulp/imx8ulp_psci.c b/plat/imx/imx8ulp/imx8ulp_psci.c
index 62cba2c..3a36332 100644
--- a/plat/imx/imx8ulp/imx8ulp_psci.c
+++ b/plat/imx/imx8ulp/imx8ulp_psci.c
@@ -25,6 +25,7 @@
extern bool is_lpav_owned_by_apd(void);
extern void apd_io_pad_off(void);
extern int upower_pmic_i2c_read(uint32_t reg_addr, uint32_t *reg_val);
+extern void imx8ulp_init_scmi_server(void);
static uintptr_t secure_entrypoint;
@@ -365,7 +366,7 @@
}
}
-extern void imx8ulp_init_scmi_server(void);
+#define DRAM_LPM_STATUS U(0x2802b004)
void imx_domain_suspend_finish(const psci_power_state_t *target_state)
{
unsigned int cpu = MPIDR_AFFLVL0_VAL(read_mpidr_el1());
@@ -395,6 +396,14 @@
imx8ulp_init_scmi_server();
}
+ /*
+ * wait for DDR is ready when DDR is under the RTD
+ * side control for power saving
+ */
+ while (mmio_read_32(DRAM_LPM_STATUS) != 0) {
+ ;
+ }
+
/* clear cluster's LPM setting. */
mmio_write_32(IMX_CMC1_BASE + 0x20, 0x0);
mmio_write_32(IMX_CMC1_BASE + 0x10, 0x0);