| commit | c549276059eb7191b8092d3aa870ed6986b85069 | [log] [tgz] |
|---|---|---|
| author | Sieu Mun Tang <sieu.mun.tang@intel.com> | Wed Sep 25 13:56:38 2024 +0800 |
| committer | Tang Sieu Mun <sieu.mun.tang@intel.com> | Wed Oct 16 23:39:09 2024 +0200 |
| tree | 3b0618ca56e2e33bdd1282d4796610aded656f40 | |
| parent | e12f4673c8fb8b480a81a75906b33b54b363a543 [diff] |
fix(intel): update the size with addition 0x8000 0000 base The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR Thus, we need to add in the DDR base address which is 0x8000 0000. Change-Id: I177596243e0616c6eadc2fa388e85e28692dc8f7 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>