nxp: ddr driver enablement for nxp layerscape soc
DDR driver for NXP layerscape SoC(s):
- lx2160aqds
- lx2162aqds
- lx2160ardb
- Other Board with SoC(s) like ls1046a, ls1043a etc;
-- These other boards are not verified yet.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic84a63cb30eba054f432d479862cd4d1097cbbaf
diff --git a/drivers/nxp/ddr/include/ddr.h b/drivers/nxp/ddr/include/ddr.h
new file mode 100644
index 0000000..0ef2870
--- /dev/null
+++ b/drivers/nxp/ddr/include/ddr.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_H
+#define DDR_H
+
+#include "ddr_io.h"
+#include "dimm.h"
+#include "immap.h"
+
+#ifndef DDRC_NUM_CS
+#define DDRC_NUM_CS 4
+#endif
+
+/*
+ * This is irrespective of what is the number of DDR controller,
+ * number of DIMM used. This is set to maximum
+ * Max controllers = 2
+ * Max num of DIMM per controlle = 2
+ * MAX NUM CS = 4
+ * Not to be changed.
+ */
+#define MAX_DDRC_NUM 2
+#define MAX_DIMM_NUM 2
+#define MAX_CS_NUM 4
+
+#include "opts.h"
+#include "regs.h"
+#include "utility.h"
+
+#ifdef DDR_DEBUG
+#define debug(...) INFO(__VA_ARGS__)
+#else
+#define debug(...) VERBOSE(__VA_ARGS__)
+#endif
+
+#ifndef DDRC_NUM_DIMM
+#define DDRC_NUM_DIMM 1
+#endif
+
+#define CONFIG_CS_PER_SLOT \
+ (DDRC_NUM_CS / DDRC_NUM_DIMM)
+
+/* Record of register values computed */
+struct ddr_cfg_regs {
+ struct {
+ unsigned int bnds;
+ unsigned int config;
+ unsigned int config_2;
+ } cs[MAX_CS_NUM];
+ unsigned int dec[10];
+ unsigned int timing_cfg[10];
+ unsigned int sdram_cfg[3];
+ unsigned int sdram_mode[16];
+ unsigned int md_cntl;
+ unsigned int interval;
+ unsigned int data_init;
+ unsigned int clk_cntl;
+ unsigned int init_addr;
+ unsigned int init_ext_addr;
+ unsigned int zq_cntl;
+ unsigned int wrlvl_cntl[3];
+ unsigned int ddr_sr_cntr;
+ unsigned int sdram_rcw[6];
+ unsigned int dq_map[4];
+ unsigned int eor;
+ unsigned int cdr[2];
+ unsigned int err_disable;
+ unsigned int err_int_en;
+ unsigned int tx_cfg[4];
+ unsigned int debug[64];
+};
+
+struct ddr_conf {
+ int dimm_in_use[MAX_DIMM_NUM];
+ int cs_in_use; /* bitmask, bit 0 for cs0, bit 1 for cs1, etc. */
+ int cs_on_dimm[MAX_DIMM_NUM]; /* bitmask */
+ unsigned long long cs_base_addr[MAX_CS_NUM];
+ unsigned long long cs_size[MAX_CS_NUM];
+ unsigned long long base_addr;
+ unsigned long long total_mem;
+};
+
+struct ddr_info {
+ unsigned long clk;
+ unsigned long long mem_base;
+ unsigned int num_ctlrs;
+ unsigned int dimm_on_ctlr;
+ struct dimm_params dimm;
+ struct memctl_opt opt;
+ struct ddr_conf conf;
+ struct ddr_cfg_regs ddr_reg;
+ struct ccsr_ddr *ddr[MAX_DDRC_NUM];
+ uint16_t *phy[MAX_DDRC_NUM];
+ int *spd_addr;
+ unsigned int ip_rev;
+ uintptr_t phy_gen2_fw_img_buf;
+ void *img_loadr;
+ int warm_boot_flag;
+};
+
+struct rc_timing {
+ unsigned int speed_bin;
+ unsigned int clk_adj;
+ unsigned int wrlvl;
+};
+
+struct board_timing {
+ unsigned int rc;
+ struct rc_timing const *p;
+ unsigned int add1;
+ unsigned int add2;
+};
+
+enum warm_boot {
+ DDR_COLD_BOOT = 0,
+ DDR_WARM_BOOT = 1,
+ DDR_WRM_BOOT_NT_SUPPORTED = -1,
+};
+
+int disable_unused_ddrc(struct ddr_info *priv, int mask,
+ uintptr_t nxp_ccn_hn_f0_addr);
+int ddr_board_options(struct ddr_info *priv);
+int compute_ddrc(const unsigned long clk,
+ const struct memctl_opt *popts,
+ const struct ddr_conf *conf,
+ struct ddr_cfg_regs *ddr,
+ const struct dimm_params *dimm_params,
+ const unsigned int ip_rev);
+int compute_ddr_phy(struct ddr_info *priv);
+int ddrc_set_regs(const unsigned long clk,
+ const struct ddr_cfg_regs *regs,
+ const struct ccsr_ddr *ddr,
+ int twopass);
+int cal_board_params(struct ddr_info *priv,
+ const struct board_timing *dimm,
+ int len);
+/* return bit mask of used DIMM(s) */
+int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf);
+long long dram_init(struct ddr_info *priv
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ , uintptr_t nxp_ccn_hn_f0_addr
+#endif
+ );
+long long board_static_ddr(struct ddr_info *info);
+
+#endif /* DDR_H */
diff --git a/drivers/nxp/ddr/include/ddr_io.h b/drivers/nxp/ddr/include/ddr_io.h
new file mode 100644
index 0000000..fbd7e97
--- /dev/null
+++ b/drivers/nxp/ddr/include/ddr_io.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_IO_H
+#define DDR_IO_H
+
+#include <endian.h>
+
+#include <lib/mmio.h>
+
+#define min(a, b) (((a) > (b)) ? (b) : (a))
+
+#define max(a, b) (((a) > (b)) ? (a) : (b))
+
+/* macro for memory barrier */
+#define mb() asm volatile("dsb sy" : : : "memory")
+
+#ifdef NXP_DDR_BE
+#define ddr_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a),\
+ bswap32(v))
+#elif defined(NXP_DDR_LE)
+#define ddr_in32(a) mmio_read_32((uintptr_t)(a))
+#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a), v)
+#else
+#error Please define CCSR DDR register endianness
+#endif
+
+#define ddr_setbits32(a, v) ddr_out32((a), ddr_in32(a) | (v))
+#define ddr_clrbits32(a, v) ddr_out32((a), ddr_in32(a) & ~(v))
+#define ddr_clrsetbits32(a, c, s) ddr_out32((a), (ddr_in32(a) & ~(c)) \
+ | (s))
+
+#endif /* DDR_IO_H */
diff --git a/drivers/nxp/ddr/include/dimm.h b/drivers/nxp/ddr/include/dimm.h
new file mode 100644
index 0000000..fcae179
--- /dev/null
+++ b/drivers/nxp/ddr/include/dimm.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DIMM_H
+#define DIMM_H
+
+#define SPD_MEMTYPE_DDR4 0x0C
+
+#define DDR4_SPD_MODULETYPE_MASK 0x0f
+#define DDR4_SPD_MODULETYPE_EXT 0x00
+#define DDR4_SPD_RDIMM 0x01
+#define DDR4_SPD_UDIMM 0x02
+#define DDR4_SPD_SO_DIMM 0x03
+#define DDR4_SPD_LRDIMM 0x04
+#define DDR4_SPD_MINI_RDIMM 0x05
+#define DDR4_SPD_MINI_UDIMM 0x06
+#define DDR4_SPD_72B_SO_RDIMM 0x08
+#define DDR4_SPD_72B_SO_UDIMM 0x09
+#define DDR4_SPD_16B_SO_DIMM 0x0c
+#define DDR4_SPD_32B_SO_DIMM 0x0d
+
+#define SPD_SPA0_ADDRESS 0x36
+#define SPD_SPA1_ADDRESS 0x37
+
+#define spd_to_ps(mtb, ftb) \
+ ((mtb) * pdimm->mtb_ps + ((ftb) * pdimm->ftb_10th_ps) / 10)
+
+#ifdef DDR_DEBUG
+#define dump_spd(spd, len) { \
+ register int i; \
+ register unsigned char *buf = (void *)(spd); \
+ \
+ for (i = 0; i < (len); i++) { \
+ print_uint(i); \
+ puts("\t: 0x"); \
+ print_hex(buf[i]); \
+ puts("\n"); \
+ } \
+}
+#else
+#define dump_spd(spd, len) {}
+#endif
+
+/* From JEEC Standard No. 21-C release 23A */
+struct ddr4_spd {
+ /* General Section: Bytes 0-127 */
+ unsigned char info_size_crc; /* 0 # bytes */
+ unsigned char spd_rev; /* 1 Total # bytes of SPD */
+ unsigned char mem_type; /* 2 Key Byte / mem type */
+ unsigned char module_type; /* 3 Key Byte / Module Type */
+ unsigned char density_banks; /* 4 Density and Banks */
+ unsigned char addressing; /* 5 Addressing */
+ unsigned char package_type; /* 6 Package type */
+ unsigned char opt_feature; /* 7 Optional features */
+ unsigned char thermal_ref; /* 8 Thermal and refresh */
+ unsigned char oth_opt_features; /* 9 Other optional features */
+ unsigned char res_10; /* 10 Reserved */
+ unsigned char module_vdd; /* 11 Module nominal voltage */
+ unsigned char organization; /* 12 Module Organization */
+ unsigned char bus_width; /* 13 Module Memory Bus Width */
+ unsigned char therm_sensor; /* 14 Module Thermal Sensor */
+ unsigned char ext_type; /* 15 Extended module type */
+ unsigned char res_16;
+ unsigned char timebases; /* 17 MTb and FTB */
+ unsigned char tck_min; /* 18 tCKAVGmin */
+ unsigned char tck_max; /* 19 TCKAVGmax */
+ unsigned char caslat_b1; /* 20 CAS latencies, 1st byte */
+ unsigned char caslat_b2; /* 21 CAS latencies, 2nd byte */
+ unsigned char caslat_b3; /* 22 CAS latencies, 3rd byte */
+ unsigned char caslat_b4; /* 23 CAS latencies, 4th byte */
+ unsigned char taa_min; /* 24 Min CAS Latency Time */
+ unsigned char trcd_min; /* 25 Min RAS# to CAS# Delay Time */
+ unsigned char trp_min; /* 26 Min Row Precharge Delay Time */
+ unsigned char tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
+ unsigned char tras_min_lsb; /* 28 tRASmin, lsb */
+ unsigned char trc_min_lsb; /* 29 tRCmin, lsb */
+ unsigned char trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
+ unsigned char trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
+ unsigned char trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
+ unsigned char trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
+ unsigned char trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
+ unsigned char trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
+ unsigned char tfaw_msb; /* 36 Upper Nibble for tFAW */
+ unsigned char tfaw_min; /* 37 tFAW, lsb */
+ unsigned char trrds_min; /* 38 tRRD_Smin, MTB */
+ unsigned char trrdl_min; /* 39 tRRD_Lmin, MTB */
+ unsigned char tccdl_min; /* 40 tCCS_Lmin, MTB */
+ unsigned char res_41[60-41]; /* 41 Rserved */
+ unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
+ unsigned char res_78[117-78]; /* 78~116, Reserved */
+ signed char fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
+ signed char fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
+ signed char fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
+ signed char fine_trc_min; /* 120 Fine offset for tRCmin */
+ signed char fine_trp_min; /* 121 Fine offset for tRPmin */
+ signed char fine_trcd_min; /* 122 Fine offset for tRCDmin */
+ signed char fine_taa_min; /* 123 Fine offset for tAAmin */
+ signed char fine_tck_max; /* 124 Fine offset for tCKAVGmax */
+ signed char fine_tck_min; /* 125 Fine offset for tCKAVGmin */
+ /* CRC: Bytes 126-127 */
+ unsigned char crc[2]; /* 126-127 SPD CRC */
+
+ /* Module-Specific Section: Bytes 128-255 */
+ union {
+ struct {
+ /* 128 (Unbuffered) Module Nominal Height */
+ unsigned char mod_height;
+ /* 129 (Unbuffered) Module Maximum Thickness */
+ unsigned char mod_thickness;
+ /* 130 (Unbuffered) Reference Raw Card Used */
+ unsigned char ref_raw_card;
+ /* 131 (Unbuffered) Address Mapping from
+ * Edge Connector to DRAM
+ */
+ unsigned char addr_mapping;
+ /* 132~253 (Unbuffered) Reserved */
+ unsigned char res_132[254-132];
+ /* 254~255 CRC */
+ unsigned char crc[2];
+ } unbuffered;
+ struct {
+ /* 128 (Registered) Module Nominal Height */
+ unsigned char mod_height;
+ /* 129 (Registered) Module Maximum Thickness */
+ unsigned char mod_thickness;
+ /* 130 (Registered) Reference Raw Card Used */
+ unsigned char ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ unsigned char modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ unsigned char thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ unsigned char reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ unsigned char reg_id_hi;
+ /* 135 Register Revision Number */
+ unsigned char reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ unsigned char reg_map;
+ unsigned char ca_stren;
+ unsigned char clk_stren;
+ /* 139~253 Reserved */
+ unsigned char res_139[254-139];
+ /* 254~255 CRC */
+ unsigned char crc[2];
+ } registered;
+ struct {
+ /* 128 (Loadreduced) Module Nominal Height */
+ unsigned char mod_height;
+ /* 129 (Loadreduced) Module Maximum Thickness */
+ unsigned char mod_thickness;
+ /* 130 (Loadreduced) Reference Raw Card Used */
+ unsigned char ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ unsigned char modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ unsigned char thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ unsigned char reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ unsigned char reg_id_hi;
+ /* 135 Register Revision Number */
+ unsigned char reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ unsigned char reg_map;
+ /* 137 Register Output Drive Strength for CMD/Add*/
+ unsigned char reg_drv;
+ /* 138 Register Output Drive Strength for CK */
+ unsigned char reg_drv_ck;
+ /* 139 Data Buffer Revision Number */
+ unsigned char data_buf_rev;
+ /* 140 DRAM VrefDQ for Package Rank 0 */
+ unsigned char vrefqe_r0;
+ /* 141 DRAM VrefDQ for Package Rank 1 */
+ unsigned char vrefqe_r1;
+ /* 142 DRAM VrefDQ for Package Rank 2 */
+ unsigned char vrefqe_r2;
+ /* 143 DRAM VrefDQ for Package Rank 3 */
+ unsigned char vrefqe_r3;
+ /* 144 Data Buffer VrefDQ for DRAM Interface */
+ unsigned char data_intf;
+ /*
+ * 145 Data Buffer MDQ Drive Strength and RTT
+ * for data rate <= 1866
+ */
+ unsigned char data_drv_1866;
+ /*
+ * 146 Data Buffer MDQ Drive Strength and RTT
+ * for 1866 < data rate <= 2400
+ */
+ unsigned char data_drv_2400;
+ /*
+ * 147 Data Buffer MDQ Drive Strength and RTT
+ * for 2400 < data rate <= 3200
+ */
+ unsigned char data_drv_3200;
+ /* 148 DRAM Drive Strength */
+ unsigned char dram_drv;
+ /*
+ * 149 DRAM ODT (RTT_WR, RTT_NOM)
+ * for data rate <= 1866
+ */
+ unsigned char dram_odt_1866;
+ /*
+ * 150 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 1866 < data rate <= 2400
+ */
+ unsigned char dram_odt_2400;
+ /*
+ * 151 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 2400 < data rate <= 3200
+ */
+ unsigned char dram_odt_3200;
+ /*
+ * 152 DRAM ODT (RTT_PARK)
+ * for data rate <= 1866
+ */
+ unsigned char dram_odt_park_1866;
+ /*
+ * 153 DRAM ODT (RTT_PARK)
+ * for 1866 < data rate <= 2400
+ */
+ unsigned char dram_odt_park_2400;
+ /*
+ * 154 DRAM ODT (RTT_PARK)
+ * for 2400 < data rate <= 3200
+ */
+ unsigned char dram_odt_park_3200;
+ unsigned char res_155[254-155]; /* Reserved */
+ /* 254~255 CRC */
+ unsigned char crc[2];
+ } loadreduced;
+ unsigned char uc[128]; /* 128-255 Module-Specific Section */
+ } mod_section;
+
+ unsigned char res_256[320-256]; /* 256~319 Reserved */
+
+ /* Module supplier's data: Byte 320~383 */
+ unsigned char mmid_lsb; /* 320 Module MfgID Code LSB */
+ unsigned char mmid_msb; /* 321 Module MfgID Code MSB */
+ unsigned char mloc; /* 322 Mfg Location */
+ unsigned char mdate[2]; /* 323~324 Mfg Date */
+ unsigned char sernum[4]; /* 325~328 Module Serial Number */
+ unsigned char mpart[20]; /* 329~348 Mfg's Module Part Number */
+ unsigned char mrev; /* 349 Module Revision Code */
+ unsigned char dmid_lsb; /* 350 DRAM MfgID Code LSB */
+ unsigned char dmid_msb; /* 351 DRAM MfgID Code MSB */
+ unsigned char stepping; /* 352 DRAM stepping */
+ unsigned char msd[29]; /* 353~381 Mfg's Specific Data */
+ unsigned char res_382[2]; /* 382~383 Reserved */
+};
+
+/* Parameters for a DDR dimm computed from the SPD */
+struct dimm_params {
+ /* DIMM organization parameters */
+ char mpart[19]; /* guaranteed null terminated */
+
+ unsigned int n_ranks;
+ unsigned int die_density;
+ unsigned long long rank_density;
+ unsigned long long capacity;
+ unsigned int primary_sdram_width;
+ unsigned int ec_sdram_width;
+ unsigned int rdimm;
+ unsigned int package_3ds; /* number of dies in 3DS */
+ unsigned int device_width; /* x4, x8, x16 components */
+ unsigned int rc;
+
+ /* SDRAM device parameters */
+ unsigned int n_row_addr;
+ unsigned int n_col_addr;
+ unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
+ unsigned int bank_addr_bits;
+ unsigned int bank_group_bits;
+ unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
+
+ /* mirrored DIMMs */
+ unsigned int mirrored_dimm; /* only for ddr3 */
+
+ /* DIMM timing parameters */
+
+ int mtb_ps; /* medium timebase ps */
+ int ftb_10th_ps; /* fine timebase, in 1/10 ps */
+ int taa_ps; /* minimum CAS latency time */
+ int tfaw_ps; /* four active window delay */
+
+ /*
+ * SDRAM clock periods
+ * The range for these are 1000-10000 so a short should be sufficient
+ */
+ int tckmin_x_ps;
+ int tckmax_ps;
+
+ /* SPD-defined CAS latencies */
+ unsigned int caslat_x;
+
+ /* basic timing parameters */
+ int trcd_ps;
+ int trp_ps;
+ int tras_ps;
+
+ int trfc1_ps;
+ int trfc2_ps;
+ int trfc4_ps;
+ int trrds_ps;
+ int trrdl_ps;
+ int tccdl_ps;
+ int trfc_slr_ps;
+
+ int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
+ int twr_ps; /* 15ns for all speed bins */
+
+ unsigned int refresh_rate_ps;
+ unsigned int extended_op_srt;
+
+ /* RDIMM */
+ unsigned char rcw[16]; /* Register Control Word 0-15 */
+ unsigned int dq_mapping[18];
+ unsigned int dq_mapping_ors;
+};
+
+int read_spd(unsigned char chip, void *buf, int len);
+int crc16(unsigned char *ptr, int count);
+int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm);
+
+#endif /* DIMM_H */
diff --git a/drivers/nxp/ddr/include/immap.h b/drivers/nxp/ddr/include/immap.h
new file mode 100644
index 0000000..83b4de6
--- /dev/null
+++ b/drivers/nxp/ddr/include/immap.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_IMMAP_H
+#define DDR_IMMAP_H
+
+#define DDR_DBUS_64 0
+#define DDR_DBUS_32 1
+#define DDR_DBUS_16 2
+
+/*
+ * DDRC register file for DDRC 5.0 and above
+ */
+struct ccsr_ddr {
+ struct {
+ unsigned int a; /* 0x0, 0x8, 0x10, 0x18 */
+ unsigned int res; /* 0x4, 0xc, 0x14, 0x1c */
+ } bnds[4];
+ unsigned char res_20[0x40 - 0x20];
+ unsigned int dec[10]; /* 0x40 */
+ unsigned char res_68[0x80 - 0x68];
+ unsigned int csn_cfg[4]; /* 0x80, 0x84, 0x88, 0x8c */
+ unsigned char res_90[48];
+ unsigned int csn_cfg_2[4]; /* 0xc0, 0xc4, 0xc8, 0xcc */
+ unsigned char res_d0[48];
+ unsigned int timing_cfg_3; /* SDRAM Timing Configuration 3 */
+ unsigned int timing_cfg_0; /* SDRAM Timing Configuration 0 */
+ unsigned int timing_cfg_1; /* SDRAM Timing Configuration 1 */
+ unsigned int timing_cfg_2; /* SDRAM Timing Configuration 2 */
+ unsigned int sdram_cfg; /* SDRAM Control Configuration */
+ unsigned int sdram_cfg_2; /* SDRAM Control Configuration 2 */
+ unsigned int sdram_mode; /* SDRAM Mode Configuration */
+ unsigned int sdram_mode_2; /* SDRAM Mode Configuration 2 */
+ unsigned int sdram_md_cntl; /* SDRAM Mode Control */
+ unsigned int sdram_interval; /* SDRAM Interval Configuration */
+ unsigned int sdram_data_init; /* SDRAM Data initialization */
+ unsigned char res_12c[4];
+ unsigned int sdram_clk_cntl; /* SDRAM Clock Control */
+ unsigned char res_134[20];
+ unsigned int init_addr; /* training init addr */
+ unsigned int init_ext_addr; /* training init extended addr */
+ unsigned char res_150[16];
+ unsigned int timing_cfg_4; /* SDRAM Timing Configuration 4 */
+ unsigned int timing_cfg_5; /* SDRAM Timing Configuration 5 */
+ unsigned int timing_cfg_6; /* SDRAM Timing Configuration 6 */
+ unsigned int timing_cfg_7; /* SDRAM Timing Configuration 7 */
+ unsigned int zq_cntl; /* ZQ calibration control*/
+ unsigned int wrlvl_cntl; /* write leveling control*/
+ unsigned char reg_178[4];
+ unsigned int ddr_sr_cntr; /* self refresh counter */
+ unsigned int ddr_sdram_rcw_1; /* Control Words 1 */
+ unsigned int ddr_sdram_rcw_2; /* Control Words 2 */
+ unsigned char reg_188[8];
+ unsigned int ddr_wrlvl_cntl_2; /* write leveling control 2 */
+ unsigned int ddr_wrlvl_cntl_3; /* write leveling control 3 */
+ unsigned char res_198[0x1a0-0x198];
+ unsigned int ddr_sdram_rcw_3;
+ unsigned int ddr_sdram_rcw_4;
+ unsigned int ddr_sdram_rcw_5;
+ unsigned int ddr_sdram_rcw_6;
+ unsigned char res_1b0[0x200-0x1b0];
+ unsigned int sdram_mode_3; /* SDRAM Mode Configuration 3 */
+ unsigned int sdram_mode_4; /* SDRAM Mode Configuration 4 */
+ unsigned int sdram_mode_5; /* SDRAM Mode Configuration 5 */
+ unsigned int sdram_mode_6; /* SDRAM Mode Configuration 6 */
+ unsigned int sdram_mode_7; /* SDRAM Mode Configuration 7 */
+ unsigned int sdram_mode_8; /* SDRAM Mode Configuration 8 */
+ unsigned char res_218[0x220-0x218];
+ unsigned int sdram_mode_9; /* SDRAM Mode Configuration 9 */
+ unsigned int sdram_mode_10; /* SDRAM Mode Configuration 10 */
+ unsigned int sdram_mode_11; /* SDRAM Mode Configuration 11 */
+ unsigned int sdram_mode_12; /* SDRAM Mode Configuration 12 */
+ unsigned int sdram_mode_13; /* SDRAM Mode Configuration 13 */
+ unsigned int sdram_mode_14; /* SDRAM Mode Configuration 14 */
+ unsigned int sdram_mode_15; /* SDRAM Mode Configuration 15 */
+ unsigned int sdram_mode_16; /* SDRAM Mode Configuration 16 */
+ unsigned char res_240[0x250-0x240];
+ unsigned int timing_cfg_8; /* SDRAM Timing Configuration 8 */
+ unsigned int timing_cfg_9; /* SDRAM Timing Configuration 9 */
+ unsigned int timing_cfg_10; /* SDRAM Timing COnfigurtion 10 */
+ unsigned char res_258[0x260-0x25c];
+ unsigned int sdram_cfg_3;
+ unsigned char res_264[0x270-0x264];
+ unsigned int sdram_md_cntl_2;
+ unsigned char res_274[0x400-0x274];
+ unsigned int dq_map[4];
+ unsigned char res_410[0x800-0x410];
+ unsigned int tx_cfg[4];
+ unsigned char res_810[0xb20-0x810];
+ unsigned int ddr_dsr1; /* Debug Status 1 */
+ unsigned int ddr_dsr2; /* Debug Status 2 */
+ unsigned int ddr_cdr1; /* Control Driver 1 */
+ unsigned int ddr_cdr2; /* Control Driver 2 */
+ unsigned char res_b30[200];
+ unsigned int ip_rev1; /* IP Block Revision 1 */
+ unsigned int ip_rev2; /* IP Block Revision 2 */
+ unsigned int eor; /* Enhanced Optimization Register */
+ unsigned char res_c04[252];
+ unsigned int mtcr; /* Memory Test Control Register */
+ unsigned char res_d04[28];
+ unsigned int mtp[10]; /* Memory Test Patterns */
+ unsigned char res_d48[184];
+ unsigned int data_err_inject_hi; /* Data Path Err Injection Mask Hi*/
+ unsigned int data_err_inject_lo;/* Data Path Err Injection Mask Lo*/
+ unsigned int ecc_err_inject; /* Data Path Err Injection Mask ECC */
+ unsigned char res_e0c[20];
+ unsigned int capture_data_hi; /* Data Path Read Capture High */
+ unsigned int capture_data_lo; /* Data Path Read Capture Low */
+ unsigned int capture_ecc; /* Data Path Read Capture ECC */
+ unsigned char res_e2c[20];
+ unsigned int err_detect; /* Error Detect */
+ unsigned int err_disable; /* Error Disable */
+ unsigned int err_int_en;
+ unsigned int capture_attributes; /* Error Attrs Capture */
+ unsigned int capture_address; /* Error Addr Capture */
+ unsigned int capture_ext_address; /* Error Extended Addr Capture */
+ unsigned int err_sbe; /* Single-Bit ECC Error Management */
+ unsigned char res_e5c[164];
+ unsigned int debug[64]; /* debug_1 to debug_64 */
+};
+#endif /* DDR_IMMAP_H */
diff --git a/drivers/nxp/ddr/include/opts.h b/drivers/nxp/ddr/include/opts.h
new file mode 100644
index 0000000..f32891b
--- /dev/null
+++ b/drivers/nxp/ddr/include/opts.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_OPTS_H
+#define DDR_OPTS_H
+
+#define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */
+
+#define DDR_BC4 4 /* burst chop */
+#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
+#define DDR_BL8 8 /* burst length 8 */
+
+#define DDR4_RTT_OFF 0
+#define DDR4_RTT_60_OHM 1 /* RZQ/4 */
+#define DDR4_RTT_120_OHM 2 /* RZQ/2 */
+#define DDR4_RTT_40_OHM 3 /* RZQ/6 */
+#define DDR4_RTT_240_OHM 4 /* RZQ/1 */
+#define DDR4_RTT_48_OHM 5 /* RZQ/5 */
+#define DDR4_RTT_80_OHM 6 /* RZQ/3 */
+#define DDR4_RTT_34_OHM 7 /* RZQ/7 */
+#define DDR4_RTT_WR_OFF 0
+#define DDR4_RTT_WR_120_OHM 1
+#define DDR4_RTT_WR_240_OHM 2
+#define DDR4_RTT_WR_HZ 3
+#define DDR4_RTT_WR_80_OHM 4
+#define DDR_ODT_NEVER 0x0
+#define DDR_ODT_CS 0x1
+#define DDR_ODT_ALL_OTHER_CS 0x2
+#define DDR_ODT_OTHER_DIMM 0x3
+#define DDR_ODT_ALL 0x4
+#define DDR_ODT_SAME_DIMM 0x5
+#define DDR_ODT_CS_AND_OTHER_DIMM 0x6
+#define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
+#define DDR_BA_INTLV_CS01 0x40
+#define DDR_BA_INTLV_CS0123 0x64
+#define DDR_BA_NONE 0
+#define DDR_256B_INTLV 0x8
+
+struct memctl_opt {
+ int rdimm;
+ unsigned int dbw_cap_shift;
+ struct local_opts_s {
+ unsigned int auto_precharge;
+ unsigned int odt_rd_cfg;
+ unsigned int odt_wr_cfg;
+ unsigned int odt_rtt_norm;
+ unsigned int odt_rtt_wr;
+ } cs_odt[DDRC_NUM_CS];
+ int ctlr_intlv;
+ unsigned int ctlr_intlv_mode;
+ unsigned int ba_intlv;
+ int addr_hash;
+ int ecc_mode;
+ int ctlr_init_ecc;
+ int self_refresh_in_sleep;
+ int self_refresh_irq_en;
+ int dynamic_power;
+ /* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
+ unsigned int data_bus_dimm;
+ unsigned int data_bus_used; /* on individual board */
+ unsigned int burst_length; /* BC4, OTF and BL8 */
+ int otf_burst_chop_en;
+ int mirrored_dimm;
+ int quad_rank_present;
+ int output_driver_impedance;
+ int ap_en;
+ int x4_en;
+
+ int caslat_override;
+ unsigned int caslat_override_value;
+ int addt_lat_override;
+ unsigned int addt_lat_override_value;
+
+ unsigned int clk_adj;
+ unsigned int cpo_sample;
+ unsigned int wr_data_delay;
+
+ unsigned int cswl_override;
+ unsigned int wrlvl_override;
+ unsigned int wrlvl_sample;
+ unsigned int wrlvl_start;
+ unsigned int wrlvl_ctl_2;
+ unsigned int wrlvl_ctl_3;
+
+ int half_strength_drive_en;
+ int twot_en;
+ int threet_en;
+ unsigned int bstopre;
+ unsigned int tfaw_ps;
+
+ int rtt_override;
+ unsigned int rtt_override_value;
+ unsigned int rtt_wr_override_value;
+ unsigned int rtt_park;
+
+ int auto_self_refresh_en;
+ unsigned int sr_it;
+ unsigned int ddr_cdr1;
+ unsigned int ddr_cdr2;
+
+ unsigned int trwt_override;
+ unsigned int trwt;
+ unsigned int twrt;
+ unsigned int trrt;
+ unsigned int twwt;
+
+ unsigned int vref_phy;
+ unsigned int vref_dimm;
+ unsigned int odt;
+ unsigned int phy_tx_impedance;
+ unsigned int phy_atx_impedance;
+ unsigned int skip2d;
+};
+
+#endif /* DDR_OPTS_H */
diff --git a/drivers/nxp/ddr/include/regs.h b/drivers/nxp/ddr/include/regs.h
new file mode 100644
index 0000000..e85fd8f
--- /dev/null
+++ b/drivers/nxp/ddr/include/regs.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_REG_H
+#define DDR_REG_H
+
+#define SDRAM_CS_CONFIG_EN 0x80000000
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG_SREN 0x40000000
+#define SDRAM_CFG_ECC_EN 0x20000000
+#define SDRAM_CFG_RD_EN 0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
+#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_DBW_MASK 0x00180000
+#define SDRAM_CFG_DBW_SHIFT 19
+#define SDRAM_CFG_32_BW 0x00080000
+#define SDRAM_CFG_16_BW 0x00100000
+#define SDRAM_CFG_8_BW 0x00180000
+#define SDRAM_CFG_8_BE 0x00040000
+#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_MEM_HLT 0x00000002
+#define SDRAM_CFG_BI 0x00000001
+
+#define SDRAM_CFG2_FRC_SR 0x80000000
+#define SDRAM_CFG2_FRC_SR_CLEAR ~(SDRAM_CFG2_FRC_SR)
+#define SDRAM_CFG2_D_INIT 0x00000010
+#define SDRAM_CFG2_AP_EN 0x00000020
+#define SDRAM_CFG2_ODT_ONLY_READ 2
+
+#define SDRAM_CFG3_DDRC_RST 0x80000000
+
+#define SDRAM_INTERVAL_REFINT 0xFFFF0000
+#define SDRAM_INTERVAL_REFINT_CLEAR ~(SDRAM_INTERVAL_REFINT)
+#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
+
+/* DDR_MD_CNTL */
+#define MD_CNTL_MD_EN 0x80000000
+#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
+#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
+#define MD_CNTL_CKE(x) (((x) & 0x3) << 20)
+
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN 0x80000000
+#define DDR_CDR1_ODT_SHIFT 17
+#define DDR_CDR1_ODT_MASK 0x6
+#define DDR_CDR2_ODT_MASK 0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
+#define DDR_CDR2_VREF_RANGE_2 0x00000040
+#define DDR_CDR_ODT_OFF 0x0
+#define DDR_CDR_ODT_100ohm 0x1
+#define DDR_CDR_ODT_120OHM 0x2
+#define DDR_CDR_ODT_80ohm 0x3
+#define DDR_CDR_ODT_60ohm 0x4
+#define DDR_CDR_ODT_40ohm 0x5
+#define DDR_CDR_ODT_50ohm 0x6
+#define DDR_CDR_ODT_30ohm 0x7
+
+
+/* DDR ERR_DISABLE */
+#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
+#define DDR_ERR_DISABLE_SBED (1 << 2) /* Address parity error disable */
+#define DDR_ERR_DISABLE_MBED (1 << 3) /* Address parity error disable */
+
+/* Mode Registers */
+#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
+#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
+
+/* DDR DSR2 register */
+#define DDR_DSR_2_PHY_INIT_CMPLT 0x4
+
+/* SDRAM TIMING_CFG_10 register */
+#define DDR_TIMING_CFG_10_T_STAB 0x7FFF
+
+/* DEBUG 2 register */
+#define DDR_DBG_2_MEM_IDLE 0x00000002
+
+/* DEBUG 26 register */
+#define DDR_DEBUG_26_BIT_6 (0x1 << 6)
+#define DDR_DEBUG_26_BIT_7 (0x1 << 7)
+#define DDR_DEBUG_26_BIT_12 (0x1 << 12)
+#define DDR_DEBUG_26_BIT_13 (0x1 << 13)
+#define DDR_DEBUG_26_BIT_14 (0x1 << 14)
+#define DDR_DEBUG_26_BIT_15 (0x1 << 15)
+#define DDR_DEBUG_26_BIT_16 (0x1 << 16)
+#define DDR_DEBUG_26_BIT_17 (0x1 << 17)
+#define DDR_DEBUG_26_BIT_18 (0x1 << 18)
+#define DDR_DEBUG_26_BIT_19 (0x1 << 19)
+#define DDR_DEBUG_26_BIT_24 (0x1 << 24)
+#define DDR_DEBUG_26_BIT_25 (0x1 << 25)
+
+#define DDR_DEBUG_26_BIT_24_CLEAR ~(DDR_DEBUG_26_BIT_24)
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
+
+#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
+
+#endif /* DDR_REG_H */
diff --git a/drivers/nxp/ddr/include/utility.h b/drivers/nxp/ddr/include/utility.h
new file mode 100644
index 0000000..2e22ad5
--- /dev/null
+++ b/drivers/nxp/ddr/include/utility.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef UTILITY_H
+#define UTILITY_H
+
+#include <dcfg.h>
+
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+#define CCN_HN_F_SAM_CTL 0x8
+#define CCN_HN_F_REGION_SIZE 0x10000
+#endif
+
+unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num);
+unsigned int get_memory_clk_ps(unsigned long clk);
+unsigned int picos_to_mclk(unsigned long data_rate, unsigned int picos);
+unsigned int get_ddrc_version(const struct ccsr_ddr *ddr);
+void print_ddr_info(struct ccsr_ddr *ddr);
+
+#endif