tree 60b2e156b4cf78088c48393d00839e9b215d6f7c
parent 5e1e48fb20454430e24caca51b24f066884fb487
author Xing Zheng <zhengxing@rock-chips.com> 1482402854 +0800
committer Xing Zheng <zhengxing@rock-chips.com> 1487938064 +0800

rockchip: rk3399: sperate the BL31 parameters for sharing

Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE
and TZRAM_SIZE for DDR secure regions), we can split them and don't have
to hardcode the range in two places.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>