diff --git a/Makefile b/Makefile
index 1baacf0..cac3e12 100644
--- a/Makefile
+++ b/Makefile
@@ -1360,7 +1360,7 @@
 	${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean
 endif
 	${Q}${MAKE} --no-print-directory -C ${SPTOOLPATH} clean
-	${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
+	${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean
 	${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean
 	${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
 
diff --git a/bl2/bl2_image_load_v2.c b/bl2/bl2_image_load_v2.c
index 48c9bec..dee3fc2 100644
--- a/bl2/bl2_image_load_v2.c
+++ b/bl2/bl2_image_load_v2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,17 +7,16 @@
 #include <assert.h>
 #include <stdint.h>
 
-#include <platform_def.h>
-
 #include <arch.h>
 #include <arch_helpers.h>
+#include "bl2_private.h"
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <common/desc_image_load.h>
 #include <drivers/auth/auth_mod.h>
 #include <plat/common/platform.h>
 
-#include "bl2_private.h"
+#include <platform_def.h>
 
 /*******************************************************************************
  * This function loads SCP_BL2/BL3x images and returns the ep_info for
@@ -66,16 +65,16 @@
 
 		if ((bl2_node_info->image_info->h.attr &
 		    IMAGE_ATTRIB_SKIP_LOADING) == 0U) {
-			INFO("BL2: Loading image id %d\n", bl2_node_info->image_id);
+			INFO("BL2: Loading image id %u\n", bl2_node_info->image_id);
 			err = load_auth_image(bl2_node_info->image_id,
 				bl2_node_info->image_info);
 			if (err != 0) {
-				ERROR("BL2: Failed to load image id %d (%i)\n",
+				ERROR("BL2: Failed to load image id %u (%i)\n",
 				      bl2_node_info->image_id, err);
 				plat_error_handler(err);
 			}
 		} else {
-			INFO("BL2: Skip loading image id %d\n", bl2_node_info->image_id);
+			INFO("BL2: Skip loading image id %u\n", bl2_node_info->image_id);
 		}
 
 		/* Allow platform to handle image information. */
diff --git a/changelog.yaml b/changelog.yaml
index 9a4a8a7..fa42e96 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -185,6 +185,13 @@
                 deprecated:
                   - plat/tc0
 
+      - title: Intel
+        scope: intel
+
+        subsections:
+          - title: SoC
+            scope: soc
+
       - title: Marvell
         scope: marvell
 
@@ -329,6 +336,19 @@
                         deprecated:
                           - plat/soc-lx2160
 
+              - title: LS1046A
+                scope: ls1046a
+
+                subsections:
+                  - title: LS1046ARDB
+                    scope: ls1046ardb
+
+                  - title: LS1046AFRWY
+                    scope: ls1046afrwy
+
+                  - title: LS1046AQDS
+                    scope: ls1046aqds
+
       - title: QEMU
         scope: qemu
 
@@ -722,6 +742,12 @@
             deprecated:
               - drivers/nxp/sfp
 
+          - title: QSPI
+            scope: nxp-qspi
+
+          - title: NXP Crypto
+            scope: nxp-crypto
+
       - title: Renesas
         scope: renesas-drivers
 
@@ -955,6 +981,9 @@
         deprecated:
           - tools/stm32image
 
+      - title: NXP Tools
+        scope: nxp-tools
+
   - title: Dependencies
     scope: deps
 
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 94c63f4..16c41bd 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -427,7 +427,7 @@
 :|G|: `vishnu-banavath`_
 :|F|: plat/arm/board/corstone700
 :|F|: plat/arm/board/a5ds
-:|F|: plat/arm/board/diphda
+:|F|: plat/arm/board/corstone1000
 
 Arm Reference Design platform ports
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -561,6 +561,15 @@
 :|F|: plat/nxp/soc-ls1043a
 :|F|: plat/nxp/soc-ls1043a/ls1043ardb
 
+NXP SoC Part LS1046A and its platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Jiafei Pan <jiafei.pan@nxp.com>
+:|G|: `JiafeiPan`_
+:|F|: plat/nxp/soc-ls1046a
+:|F|: plat/nxp/soc-ls1046a/ls1046ardb
+:|F|: plat/nxp/soc-ls1046a/ls1046afrwy
+:|F|: plat/nxp/soc-ls1046a/ls1046aqds
+
 QEMU platform port
 ^^^^^^^^^^^^^^^^^^
 :|M|: Jens Wiklander <jens.wiklander@linaro.org>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 7075ca6..7aa7384 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -409,6 +409,14 @@
    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
    of the CPU and is still open.
 
+-  ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is fixed in r2p1.
+
+-  ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is fixed in r2p1.
+
 For Neoverse N2, the following errata build flags are defined :
 
 -  ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
@@ -454,6 +462,50 @@
 -  ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
    CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
 
+-  ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to
+   Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+   r2p0 of the CPU, it is fixed in r2p1.
+
+-  ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to
+   Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+   r2p0 of the CPU, it is fixed in r2p1.
+
+-  ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to
+   Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+   r2p0 of the CPU, it is fixed in r2p1.
+
+For Cortex-A510, the following errata build flags are defined :
+
+-  ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is
+   fixed in r0p1.
+
+-  ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
+   r0p2, r0p3 and r1p0, it is fixed in r1p1.
+
+-  ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
+   r0p2, it is fixed in r0p3.
+
+-  ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
+   in r0p3. The issue is also present in r0p0 and r0p1 but there is no
+   workaround for those revisions.
+
+-  ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to
+   Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
+   r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
+   ENABLE_MPMM=1.
+
+-  ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to
+   Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
+   r0p3 and r1p0, it is fixed in r1p1.
+
+-  ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to
+   Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
+   r0p3 and r1p0, it is fixed in r1p1.
+
 DSU Errata Workarounds
 ----------------------
 
diff --git a/docs/design_documents/context_mgmt_rework.rst b/docs/design_documents/context_mgmt_rework.rst
new file mode 100644
index 0000000..59f9d4e
--- /dev/null
+++ b/docs/design_documents/context_mgmt_rework.rst
@@ -0,0 +1,197 @@
+Enhance Context Management library for EL3 firmware
+===================================================
+
+:Authors: Soby Mathew & Zelalem Aweke
+:Organization: Arm Limited
+:Contact: Soby Mathew <soby.mathew@arm.com> & Zelalem Aweke <zelalem.aweke@arm.com>
+:Status: RFC
+
+.. contents:: Table of Contents
+
+Introduction
+------------
+The context management library in TF-A provides the basic CPU context
+initialization and management routines for use by different components
+in EL3 firmware. The original design of the library was done keeping in
+mind the 2 world switch and hence this design pattern has been extended to
+keep up with growing requirements of EL3 firmware. With the introduction
+of a new Realm world and a separate Root world for EL3 firmware, it is clear
+that this library needs to be refactored to cater for future enhancements and
+reduce chances of introducing error in code. This also aligns with the overall
+goal of reducing EL3 firmware complexity and footprint.
+
+It is expected that the suggestions below could have legacy implications and
+hence we are mainly targeting SPM/RMM based systems. It is expected that these
+legacy issues will need to be sorted out as part of implementation on a case
+by case basis.
+
+Design Principles
+-----------------
+The below section lays down the design principles for re-factoring the context
+management library :
+
+(1) **Decentralized model for context mgmt**
+
+    Both the Secure and Realm worlds have associated dispatcher component in
+    EL3 firmware to allow management of their respective worlds. Allowing the
+    dispatcher to own the context for their respective world and moving away
+    from a centralized policy management by context management library will
+    remove the world differentiation code in the library. This also means that
+    the library will not be responsible for CPU feature enablement for
+    Secure and Realm worlds. See point 3 and 4 for more details.
+
+    The Non Secure world does not have a dispatcher component and hence EL3
+    firmware (BL31)/context management library needs to have routines to help
+    initialize the Non Secure world context.
+
+(2) **EL3 should only initialize immediate used lower EL**
+
+    Due to the way TF-A evolved, from EL3 interacting with an S-EL1 payload to
+    SPM in S-EL2, there is some code initializing S-EL1 registers which is
+    probably redundant when SPM is present in S-EL2. As a principle, EL3
+    firmware should only initialize the next immediate lower EL in use.
+    If EL2 needs to be skipped and is not to be used at runtime, then
+    EL3 can do the bare minimal EL2 init and init EL1 to prepare for EL3 exit.
+    It is expected that this skip EL2 configuration is only needed for NS
+    world to support legacy Android deployments. It is worth removing this
+    `skip EL2 for Non Secure` config support if this is no longer used.
+
+(3) **Maintain EL3 sysregs which affect lower EL within CPU context**
+
+    The CPU context contains some EL3 sysregs and gets applied on a per-world
+    basis (eg: cptr_el3, scr_el3, zcr_el3 is part of the context
+    because different settings need to be applied between each world).
+    But this design pattern is not enforced in TF-A. It is possible to directly
+    modify EL3 sysreg dynamically during the transition between NS and Secure
+    worlds. Having multiple ways of manipulating EL3 sysregs for different
+    values between the worlds is flaky and error prone. The proposal is to
+    enforce the rule that any EL3 sysreg which can be different between worlds
+    is maintained in the CPU Context. Once the context is initialized the
+    EL3 sysreg values corresponding to the world being entered will be restored.
+
+(4) **Allow more flexibility for Dispatchers to select feature set to save and restore**
+
+    The current functions for EL2 CPU context save and restore is a single
+    function which takes care of saving and restoring all the registers for
+    EL2. This method is inflexible and it does not allow to dynamically detect
+    CPU features to select registers to save and restore. It also assumes that
+    both Realm and Secure world will have the same feature set enabled from
+    EL3 at runtime and makes it hard to enable different features for each
+    world. The framework should cater for selective save and restore of CPU
+    registers which can be controlled by the dispatcher.
+
+    For the implementation, this could mean that there is a separate assembly
+    save and restore routine corresponding to Arch feature. The memory allocation
+    within the CPU Context for each set of registers will be controlled by a
+    FEAT_xxx build option. It is a valid configuration to have
+    context memory allocated but not used at runtime based on feature detection
+    at runtime or the platform owner has decided not to enable the feature
+    for the particular world.
+
+Context Allocation and Initialization
+-------------------------------------
+
+|context_mgmt_abs|
+
+.. |context_mgmt_abs| image::
+   ../resources/diagrams/context_management_abs.png
+
+The above figure shows how the CPU context is allocated within TF-A. The
+allocation for Secure and Realm world is by the respective dispatcher. In the case
+of NS world, the context is allocated by the PSCI lib. This scheme allows TF-A
+to be built in various configurations (with or without Secure/Realm worlds) and
+will result in optimal memory footprint. The Secure and Realm world contexts are
+initialized by invoking context management library APIs which then initialize
+each world based on conditional evaluation of the security state of the
+context. The proposal here is to move the conditional initialization
+of context for Secure and Realm worlds to their respective dispatchers and
+have the library do only the common init needed. The library can export
+helpers to initialize registers corresponding to certain features but
+should not try to do different initialization between the worlds. The library
+can also export helpers for initialization of NS CPU Context since there is no
+dispatcher for that world.
+
+This implies that any world specific code in context mgmt lib should now be
+migrated to the respective "owners". To maintain compatibility with legacy, the
+current functions can be retained in the lib and perhaps define new ones for
+use by SPMD and RMMD. The details of this can be worked out during
+implementation.
+
+Introducing Root Context
+------------------------
+Till now, we have been ignoring the fact that Root world (or EL3) itself could
+have some settings which are distinct from NS/S/Realm worlds. In this case,
+Root world itself would need to maintain some sysregs settings for its own
+execution and would need to use sysregs of lower EL (eg: PAuth, pmcr) to enable
+some functionalities in EL3. The current sequence for context save and restore
+in TF-A is as given below:
+
+|context_mgmt_existing|
+
+.. |context_mgmt_existing| image::
+   ../resources/diagrams/context_mgmt_existing.png
+
+Note1: The EL3 CPU context is not a homogenous collection of EL3 sysregs but
+a collection of EL3 and some other lower EL registers. The save and restore
+is also not done homogenously but based on the objective of using the
+particular register.
+
+Note2: The EL1 context save and restore can possibly be removed when switching
+to S-EL2 as SPM can take care of saving the incoming NS EL1 context.
+
+It can be seen that the EL3 sysreg values applied while the execution is in Root
+world corresponds to the world it came from (eg: if entering EL3 from NS world,
+the sysregs correspond to the values in NS context). There is a case that EL3
+itself may have some settings to apply for various reasons. A good example for
+this is the cptr_el3 regsiter. Although FPU traps need to be disabled for
+Non Secure, Secure and Realm worlds, the EL3 execution itself may keep the trap
+enabled for the sake of robustness. Another example is, if the MTE feature
+is enabled for a particular world, this feature will be enabled for Root world
+as well when entering EL3 from that world. The firmware at EL3 may not
+be expecting this feature to be enabled and may cause unwanted side-effects
+which could be problematic. Thus it would be more robust if Root world is not
+subject to EL3 sysreg values from other worlds but maintains its own values
+which is stable and predictable throughout root world execution.
+
+There is also the case that when EL3 would like to make use of some
+Architectural feature(s) or do some security hardening, it might need
+programming of some lower EL sysregs. For example, if EL3 needs to make
+use of Pointer Authentication (PAuth) feature, it needs to program
+its own PAuth Keys during execution at EL3. Hence EL3 needs its
+own copy of PAuth registers which needs to be restored on every
+entry to EL3. A similar case can be made for DIT bit in PSTATE,
+or use of SP_EL0 for C Runtime Stack at EL3.
+
+The proposal here is to maintain a separate root world CPU context
+which gets applied for Root world execution. This is not the full
+CPU_Context, but subset of EL3 sysregs (`el3_sysreg`) and lower EL
+sysregs (`root_exc_context`) used by EL3. The save and restore
+sequence for this Root context would need to be done in
+an optimal way. The `el3_sysreg` does not need to be saved
+on EL3 Exit and possibly only some registers in `root_exc_context`
+of Root world context would need to be saved on EL3 exit (eg: SP_EL0).
+
+The new sequence for world switch including Root world context would
+be as given below :
+
+|context_mgmt_proposed|
+
+.. |context_mgmt_proposed| image::
+   ../resources/diagrams/context_mgmt_proposed.png
+
+Having this framework in place will allow Root world to make use of lower EL
+registers easily for its own purposes and also have a fixed EL3 sysreg setting
+which is not affected by the settings of other worlds. This will unify the
+Root world register usage pattern for its own execution and remove some
+of the adhoc usages in code.
+
+Conclusion
+----------
+Of all the proposals, the introduction of Root world context would likely need
+further prototyping to confirm the design and we will need to measure the
+performance and memory impact of this change. Other changes are incremental
+improvements which are thought to have negligible impact on EL3 performance.
+
+--------------
+
+*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/design_documents/index.rst b/docs/design_documents/index.rst
index c82d2ee..257a510 100644
--- a/docs/design_documents/index.rst
+++ b/docs/design_documents/index.rst
@@ -7,6 +7,7 @@
    :numbered:
 
    cmake_framework
+   context_mgmt_rework
    measured_boot_poc
 
 --------------
diff --git a/docs/plat/arm/diphda/index.rst b/docs/plat/arm/corstone1000/index.rst
similarity index 92%
rename from docs/plat/arm/diphda/index.rst
rename to docs/plat/arm/corstone1000/index.rst
index 27afda4..b889b7f 100644
--- a/docs/plat/arm/diphda/index.rst
+++ b/docs/plat/arm/corstone1000/index.rst
@@ -1,7 +1,7 @@
-Diphda Platform
+Corstone1000 Platform
 ==========================
 
-Some of the features of the Diphda platform referenced in TF-A include:
+Some of the features of the Corstone1000 platform referenced in TF-A include:
 
 - Cortex-A35 application processor (64-bit mode)
 - Secure Enclave
@@ -37,7 +37,7 @@
       CC=aarch64-none-elf-gcc \
       V=1 \
       BUILD_BASE=<path to the build folder> \
-      PLAT=diphda \
+      PLAT=corstone1000 \
       SPD=spmd \
       SPMD_SPM_AT_SEL2=0 \
       DEBUG=1 \
diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst
index f262dc0..2f68522 100644
--- a/docs/plat/arm/index.rst
+++ b/docs/plat/arm/index.rst
@@ -13,7 +13,7 @@
    arm_fpga/index
    arm-build-options
    morello/index
-   diphda/index
+   corstone1000/index
 
 This chapter holds documentation related to Arm's development platforms,
 including both software models (FVPs) and hardware development boards
diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst
index 0fe15c9..101d52b 100644
--- a/docs/plat/imx8m.rst
+++ b/docs/plat/imx8m.rst
@@ -60,3 +60,11 @@
 All of the BL3x will be put in the FIP image. BL2 will verify them.
 In U-boot we turn on the UEFI secure boot features so it can verify
 grub. And we use grub to verify linux kernel.
+
+Measured Boot
+-------------
+
+When setting MEASURED_BOOT=1 on imx8mm we can let TF-A generate event logs
+with a DTB overlay. The overlay will be put at PLAT_IMX8M_DTO_BASE with
+maximum size PLAT_IMX8M_DTO_MAX_SIZE. Then in U-boot we can apply the DTB
+overlay and let U-boot to parse the event log and update the PCRs.
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index 6872f56..5147cf2 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -258,7 +258,7 @@
 
                 Image needs to be stored at disk LBA 0 or at disk partition with
                 MBR type 0x4d (ASCII 'M' as in Marvell) or at disk partition with
-                GPT name ``MARVELL BOOT PARTITION``.
+                GPT partition type GUID ``6828311A-BA55-42A4-BCDE-A89BB5EDECAE``.
 
 - PARTNUM
 
@@ -317,11 +317,19 @@
         Use this parameter to point to the directory with
         compiled Crypto++ library. By default it points to the CRYPTOPP_PATH.
 
+        On Debian systems it is possible to install system-wide Crypto++ library
+        via command ``apt install libcrypto++-dev`` and specify CRYPTOPP_LIBDIR
+        to ``/usr/lib/``.
+
 - CRYPTOPP_INCDIR
 
         Use this parameter to point to the directory with
         header files of Crypto++ library. By default it points to the CRYPTOPP_PATH.
 
+        On Debian systems it is possible to install system-wide Crypto++ library
+        via command ``apt install libcrypto++-dev`` and specify CRYPTOPP_INCDIR
+        to ``/usr/include/crypto++/``.
+
 
 For example, in order to build the image in debug mode with log level up to 'notice' level run
 
diff --git a/docs/plat/nxp/nxp-layerscape.rst b/docs/plat/nxp/nxp-layerscape.rst
index bae779c..6cbd7f9 100644
--- a/docs/plat/nxp/nxp-layerscape.rst
+++ b/docs/plat/nxp/nxp-layerscape.rst
@@ -93,6 +93,39 @@
 
 Details about LS1043A RDB board can be found at `ls1043ardb`_.
 
+4. LS1046A
+
+- SoC Overview:
+
+The LS1046A is a cost-effective, power-efficient, and highly integrated
+system-on-chip (SoC) design that extends the reach of the NXP value-performance
+line of QorIQ communications processors. Featuring power-efficient 64-bit
+Arm Cortex-A72 cores with ECC-protected L1 and L2 cache memories for high
+reliability, running up to 1.8 GHz.
+
+Details about LS1043A can be found at `ls1046a`_.
+
+- LS1046ARDB Board:
+
+The LS1046A reference design board (RDB) is a high-performance computing,
+evaluation, and development platform that supports the Layerscape LS1046A
+architecture processor. The LS1046ARDB board supports the Layerscape LS1046A
+processor and is optimized to support the DDR4 memory and a full complement
+of high-speed SerDes ports.
+
+Details about LS1043A RDB board can be found at `ls1046ardb`_.
+
+- LS1046AFRWY Board:
+
+The LS1046A Freeway board (FRWY) is a high-performance computing, evaluation,
+and development platform that supports the LS1046A architecture processor
+capable of support more than 32,000 CoreMark performance. The FRWY-LS1046A
+board supports the LS1046A processor, onboard DDR4 memory, multiple Gigabit
+Ethernet, USB3.0 and M2_Type_E interfaces for Wi-Fi, FRWY-LS1046A-AC includes
+the Wi-Fi card.
+
+Details about LS1043A RDB board can be found at `ls1046afrwy`_.
+
 Table of supported boot-modes by each platform & platform that needs FIP-DDR:
 -----------------------------------------------------------------------------
 
@@ -107,6 +140,10 @@
 +---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
 |     ls1043ardb      |  yes  |        |  yes  |  yes  |       |             |              |       no        |
 +---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
+|     ls1046ardb      |  yes  |  yes   |       |       |  yes  |             |              |       no        |
++---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
+|     ls1046afrwy     |  yes  |  yes   |       |       |       |             |              |       no        |
++---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
 
 
 Boot Sequence
@@ -275,32 +312,42 @@
 Note: The size in the standard uboot commands for copy to nor, qspi, nand or sd
 should be modified based on the binary size of the image to be copied.
 
+-  Deploy ATF images on flexspi-Nor or QSPI flash Alt Bank from U-Boot prompt.
+
+   --  Commands to flash images for bl2_xxx.pbl and fip.bin
+
--  Deploy ATF images on flexspi-Nor flash Alt Bank from U-Boot prompt.
-   --  Commands to flash images for bl2_xxx.pbl and fip.bin.
+   Notes: ls1028ardb has no flexspi-Nor Alt Bank, so use "sf probe 0:0" for current bank.
 
    .. code:: shell
 
-        tftp 82000000  $path/bl2_flexspi_nor.pbl;
-        i2c mw 66 50 20;sf probe 0:0; sf erase 0 +$filesize; sf write 0x82000000 0x0 $filesize;
+        tftp 82000000  $path/bl2_xxx.pbl;
+
+        i2c mw 66 50 20;sf probe 0:1; sf erase 0 +$filesize; sf write 0x82000000 0x0 $filesize;
 
         tftp 82000000  $path/fip.bin;
-        i2c mw 66 50 20;sf probe 0:0; sf erase 0x100000 +$filesize; sf write 0x82000000 0x100000 $filesize;
+        i2c mw 66 50 20;sf probe 0:1; sf erase 0x100000 +$filesize; sf write 0x82000000 0x100000 $filesize;
 
    --  Next step is valid for platform where FIP-DDR is needed.
 
    .. code:: shell
 
         tftp 82000000  $path/ddr_fip.bin;
-        i2c mw 66 50 20;sf probe 0:0; sf erase 0x800000 +$filesize; sf write 0x82000000 0x800000 $filesize;
+        i2c mw 66 50 20;sf probe 0:1; sf erase 0x800000 +$filesize; sf write 0x82000000 0x800000 $filesize;
 
    --  Then reset to alternate bank to boot up ATF.
 
-   Command for lx2160A and ls1028a platforms:
+   Command for lx2160a and ls1028a platforms:
 
    .. code:: shell
 
         qixisreset altbank;
 
+   Command for ls1046a platforms:
+
+   .. code:: shell
+
+        cpld reset altbank;
+
 -  Deploy ATF images on SD/eMMC from U-Boot prompt.
    -- file_size_in_block_sizeof_512 = (Size_of_bytes_tftp / 512)
 
@@ -329,7 +376,7 @@
 
         qixisreset <sd or emmc>;
 
-   Command for ls1043a platform:
+   Command for ls1043a and ls1046a platform:
 
    .. code:: shell
 
@@ -395,4 +442,7 @@
 .. _ls1028ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB
 .. _ls1043a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1043a-and-1023a-processors:LS1043A
 .. _ls1043ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1043a-reference-design-board:LS1043A-RDB
+.. _ls1046a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1046a-and-1026a-processors:LS1046A
+.. _ls1046ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1046a-reference-design-board:LS1046A-RDB
+.. _ls1046afrwy: https://www.nxp.com/design/qoriq-developer-resources/ls1046a-freeway-board:FRWY-LS1046A
 .. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst
diff --git a/docs/resources/diagrams/context_management_abs.png b/docs/resources/diagrams/context_management_abs.png
new file mode 100644
index 0000000..717ecec
--- /dev/null
+++ b/docs/resources/diagrams/context_management_abs.png
Binary files differ
diff --git a/docs/resources/diagrams/context_mgmt_existing.png b/docs/resources/diagrams/context_mgmt_existing.png
new file mode 100644
index 0000000..5170960
--- /dev/null
+++ b/docs/resources/diagrams/context_mgmt_existing.png
Binary files differ
diff --git a/docs/resources/diagrams/context_mgmt_proposed.png b/docs/resources/diagrams/context_mgmt_proposed.png
new file mode 100644
index 0000000..41ae92f
--- /dev/null
+++ b/docs/resources/diagrams/context_mgmt_proposed.png
Binary files differ
diff --git a/drivers/allwinner/axp/axp803.c b/drivers/allwinner/axp/axp803.c
index 7050818..19a9549 100644
--- a/drivers/allwinner/axp/axp803.c
+++ b/drivers/allwinner/axp/axp803.c
@@ -11,6 +11,7 @@
 
 #if SUNXI_SETUP_REGULATORS == 1
 const struct axp_regulator axp_regulators[] = {
+	{"aldo1",  700, 3300, 100, NA, 0x28, 0x13, 5},
 	{"dcdc1", 1600, 3400, 100, NA, 0x20, 0x10, 0},
 	{"dcdc5",  800, 1840,  10, 32, 0x24, 0x10, 4},
 	{"dcdc6",  600, 1520,  10, 50, 0x25, 0x10, 5},
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index e4fc8c9..759824d 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -306,8 +306,8 @@
 			 * See the 'ARM (R) CoreLink TM TZC-400 TrustZone (R)
 			 * Address Space Controller' Technical Reference Manual.
 			 */
-			ERROR("TZC-400 : Filter %d Gatekeeper already"
-				" enabled.\n", filter);
+			ERROR("TZC-400 : Filter %u Gatekeeper already enabled.\n",
+			      filter);
 			panic();
 		}
 		_tzc400_set_gate_keeper(tzc400.base, filter, 1);
diff --git a/drivers/io/io_mtd.c b/drivers/io/io_mtd.c
index ba8cecd..5d86592 100644
--- a/drivers/io/io_mtd.c
+++ b/drivers/io/io_mtd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,13 +8,13 @@
 #include <errno.h>
 #include <string.h>
 
-#include <platform_def.h>
-
 #include <common/debug.h>
 #include <drivers/io/io_driver.h>
 #include <drivers/io/io_mtd.h>
 #include <lib/utils.h>
 
+#include <platform_def.h>
+
 typedef struct {
 	io_mtd_dev_spec_t	*dev_spec;
 	uintptr_t		base;
@@ -214,7 +214,7 @@
 	ops = &cur->dev_spec->ops;
 	assert(ops->read != NULL);
 
-	VERBOSE("Read at %llx into %lx, length %zi\n",
+	VERBOSE("Read at %llx into %lx, length %zu\n",
 		cur->base + cur->pos, buffer, length);
 	if ((cur->base + cur->pos + length) > cur->dev_spec->device_size) {
 		return -EINVAL;
diff --git a/drivers/mtd/nand/spi_nand.c b/drivers/mtd/nand/spi_nand.c
index abb524d..542b614 100644
--- a/drivers/mtd/nand/spi_nand.c
+++ b/drivers/mtd/nand/spi_nand.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021,  STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022,  STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,13 +8,13 @@
 #include <errno.h>
 #include <stddef.h>
 
-#include <platform_def.h>
-
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
 #include <drivers/spi_nand.h>
 #include <lib/utils.h>
 
+#include <platform_def.h>
+
 #define SPI_NAND_MAX_ID_LEN		4U
 #define DELAY_US_400MS			400000U
 #define MACRONIX_ID			0xC2U
@@ -246,7 +246,7 @@
 
 	if ((bbm_marker[0] != GENMASK_32(7, 0)) ||
 	    (bbm_marker[1] != GENMASK_32(7, 0))) {
-		WARN("Block %i is bad\n", block);
+		WARN("Block %u is bad\n", block);
 		return 1;
 	}
 
@@ -312,7 +312,7 @@
 
 	VERBOSE("SPI_NAND Detected ID 0x%x\n", id[1]);
 
-	VERBOSE("Page size %i, Block size %i, size %lli\n",
+	VERBOSE("Page size %u, Block size %u, size %llu\n",
 		spinand_dev.nand_dev->page_size,
 		spinand_dev.nand_dev->block_size,
 		spinand_dev.nand_dev->size);
diff --git a/drivers/mtd/nor/spi_nor.c b/drivers/mtd/nor/spi_nor.c
index 6b4643e..2e34344 100644
--- a/drivers/mtd/nor/spi_nor.c
+++ b/drivers/mtd/nor/spi_nor.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -284,7 +284,7 @@
 	nor_dev.read_op.addr.val = offset;
 	nor_dev.read_op.data.buf = (void *)buffer;
 
-	VERBOSE("%s offset %i length %zu\n", __func__, offset, length);
+	VERBOSE("%s offset %u length %zu\n", __func__, offset, length);
 
 	while (length != 0U) {
 		if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
diff --git a/drivers/mtd/spi-mem/spi_mem.c b/drivers/mtd/spi-mem/spi_mem.c
index 010e8b6..c43d519 100644
--- a/drivers/mtd/spi-mem/spi_mem.c
+++ b/drivers/mtd/spi-mem/spi_mem.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,10 +8,9 @@
 #include <inttypes.h>
 #include <stdint.h>
 
-#include <libfdt.h>
-
 #include <drivers/spi_mem.h>
 #include <lib/utils_def.h>
+#include <libfdt.h>
 
 #define SPI_MEM_DEFAULT_SPEED_HZ 100000U
 
@@ -258,7 +257,7 @@
 				mode |= SPI_TX_QUAD;
 				break;
 			default:
-				WARN("spi-tx-bus-width %d not supported\n",
+				WARN("spi-tx-bus-width %u not supported\n",
 				     fdt32_to_cpu(*cuint));
 				return -EINVAL;
 			}
@@ -276,7 +275,7 @@
 				mode |= SPI_RX_QUAD;
 				break;
 			default:
-				WARN("spi-rx-bus-width %d not supported\n",
+				WARN("spi-rx-bus-width %u not supported\n",
 				     fdt32_to_cpu(*cuint));
 				return -EINVAL;
 			}
diff --git a/drivers/nxp/crypto/caam/src/jobdesc.c b/drivers/nxp/crypto/caam/src/jobdesc.c
index 9c235af..f559c4b 100644
--- a/drivers/nxp/crypto/caam/src/jobdesc.c
+++ b/drivers/nxp/crypto/caam/src/jobdesc.c
@@ -60,8 +60,8 @@
 #ifdef CONFIG_PHYS_64BIT
 	ptr_addr_t *ptr_addr = (ptr_addr_t *) last;
 
-	ptr_addr->m_halves.high = PHYS_ADDR_HI(ptr);
-	ptr_addr->m_halves.low = PHYS_ADDR_LO(ptr);
+	ptr_addr->high = PHYS_ADDR_HI(ptr);
+	ptr_addr->low = PHYS_ADDR_LO(ptr);
 #else
 	*last = ptr;
 #endif
diff --git a/drivers/nxp/qspi/qspi.mk b/drivers/nxp/qspi/qspi.mk
index b83dee2..450aeca 100644
--- a/drivers/nxp/qspi/qspi.mk
+++ b/drivers/nxp/qspi/qspi.mk
@@ -10,7 +10,7 @@
 
 QSPI_SOURCES		:= $(PLAT_DRIVERS_PATH)/qspi/qspi.c
 
-PLAT_INCLUDES		+= -I$(PLAT_DRIVERS_PATH)/qspi
+PLAT_INCLUDES		+= -I$(PLAT_DRIVERS_INCLUDE_PATH)/qspi
 
 ifeq (${BL_COMM_QSPI_NEEDED},yes)
 BL_COMMON_SOURCES	+= ${QSPI_SOURCES}
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index f525741..2288348 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1564,7 +1564,7 @@
 	/* Wait PLL lock */
 	while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
 		if (timeout_elapsed(timeout)) {
-			ERROR("PLL%d start failed @ 0x%lx: 0x%x\n",
+			ERROR("PLL%u start failed @ 0x%lx: 0x%x\n",
 			      pll_id, pllxcr, mmio_read_32(pllxcr));
 			return -ETIMEDOUT;
 		}
@@ -1593,7 +1593,7 @@
 	/* Wait PLL stopped */
 	while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
 		if (timeout_elapsed(timeout)) {
-			ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n",
+			ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n",
 			      pll_id, pllxcr, mmio_read_32(pllxcr));
 			return -ETIMEDOUT;
 		}
@@ -1852,7 +1852,7 @@
 	for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
 		char name[12];
 
-		snprintf(name, sizeof(name), "st,pll@%d", i);
+		snprintf(name, sizeof(name), "st,pll@%u", i);
 		plloff[i] = fdt_rcc_subnode_offset(name);
 
 		pllcfg_valid[i] = fdt_check_node(plloff[i]);
diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c
index e9ab6da..9bdc854 100644
--- a/drivers/st/fmc/stm32_fmc2_nand.c
+++ b/drivers/st/fmc/stm32_fmc2_nand.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -9,10 +9,6 @@
 #include <limits.h>
 #include <stdint.h>
 
-#include <libfdt.h>
-
-#include <platform_def.h>
-
 #include <common/debug.h>
 #include <drivers/clk.h>
 #include <drivers/delay_timer.h>
@@ -22,6 +18,9 @@
 #include <drivers/st/stm32mp_reset.h>
 #include <lib/mmio.h>
 #include <lib/utils_def.h>
+#include <libfdt.h>
+
+#include <platform_def.h>
 
 /* Timeout for device interface reset */
 #define TIMEOUT_US_1_MS			1000U
@@ -516,7 +515,7 @@
 	unsigned int s;
 	int ret;
 
-	VERBOSE(">%s page %i buffer %lx\n", __func__, page, buffer);
+	VERBOSE(">%s page %u buffer %lx\n", __func__, page, buffer);
 
 	ret = nand_read_page_cmd(page, 0U, 0U, 0U);
 	if (ret != 0) {
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index dbdaa54..3f709a7 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -319,7 +319,7 @@
 	while ((status & flags_cmd) == 0U) {
 		if (timeout_elapsed(timeout)) {
 			err = -ETIMEDOUT;
-			ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
+			ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n",
 			      __func__, cmd->cmd_idx, status);
 			goto err_exit;
 		}
@@ -339,12 +339,12 @@
 			      (cmd->cmd_idx == MMC_CMD(13)) ||
 			      ((cmd->cmd_idx == MMC_CMD(8)) &&
 			       (cmd->resp_type == MMC_RESPONSE_R7)))) {
-				ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n",
+				ERROR("%s: CTIMEOUT (cmd = %u,status = %x)\n",
 				      __func__, cmd->cmd_idx, status);
 			}
 		} else {
 			err = -EIO;
-			ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n",
+			ERROR("%s: CRCFAIL (cmd = %u,status = %x)\n",
 			      __func__, cmd->cmd_idx, status);
 		}
 
@@ -385,7 +385,7 @@
 
 	while ((status & flags_data) == 0U) {
 		if (timeout_elapsed(timeout)) {
-			ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
+			ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n",
 			      __func__, cmd->cmd_idx, status);
 			err = -ETIMEDOUT;
 			goto err_exit;
@@ -397,7 +397,7 @@
 	if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL |
 		       SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR |
 		       SDMMC_STAR_IDMATE)) != 0U) {
-		ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__,
+		ERROR("%s: Error flag (cmd = %u,status = %x)\n", __func__,
 		      cmd->cmd_idx, status);
 		err = -EIO;
 	}
diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c
index 6a30dce..0139661 100644
--- a/drivers/st/pmic/stm32mp_pmic.c
+++ b/drivers/st/pmic/stm32mp_pmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -337,7 +337,7 @@
 
 static int pmic_set_state(const struct regul_description *desc, bool enable)
 {
-	VERBOSE("%s: set state to %u\n", desc->node_name, enable);
+	VERBOSE("%s: set state to %d\n", desc->node_name, enable);
 
 	if (enable == STATE_ENABLE) {
 		return stpmic1_regulator_enable(desc->node_name);
diff --git a/drivers/usb/usb_device.c b/drivers/usb/usb_device.c
index 031e678..701f301 100644
--- a/drivers/usb/usb_device.c
+++ b/drivers/usb/usb_device.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -362,7 +362,7 @@
 
 	case USB_REQ_RECIPIENT_ENDPOINT:
 	default:
-		ERROR("receive unsupported request %i",
+		ERROR("receive unsupported request %u",
 		      pdev->request.bm_request & USB_REQ_RECIPIENT_MASK);
 		usb_core_set_stall(pdev, pdev->request.bm_request & USB_REQ_DIRECTION);
 		return USBD_FAIL;
diff --git a/include/drivers/measured_boot/event_log/event_log.h b/include/drivers/measured_boot/event_log/event_log.h
index a687d41..0a19f8a 100644
--- a/include/drivers/measured_boot/event_log/event_log.h
+++ b/include/drivers/measured_boot/event_log/event_log.h
@@ -77,6 +77,7 @@
 #define EVLOG_STM32_STRING		"STM32"
 #define EVLOG_TB_FW_CONFIG_STRING	"TB_FW_CONFIG"
 #define	EVLOG_TOS_FW_CONFIG_STRING	"TOS_FW_CONFIG"
+#define EVLOG_RMM_STRING 		"RMM"
 
 typedef struct {
 	unsigned int id;
diff --git a/include/drivers/nxp/crypto/caam/sec_hw_specific.h b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
index a4fc022..9800793 100644
--- a/include/drivers/nxp/crypto/caam/sec_hw_specific.h
+++ b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
@@ -187,9 +187,7 @@
 				((value) & JRINT_JRE)
 
  /* Macros for manipulating JR registers */
-typedef union {
-	uint64_t m_whole;
-	struct {
+typedef struct {
 #ifdef NXP_SEC_BE
 		uint32_t high;
 		uint32_t low;
@@ -197,7 +195,6 @@
 		uint32_t low;
 		uint32_t high;
 #endif
-	} m_halves;
 } ptr_addr_t;
 
 #if defined(CONFIG_PHYS_64BIT)
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h
index 6a4cfdf..2b8db14 100644
--- a/include/lib/cpus/aarch64/cortex_a510.h
+++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2022, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,6 +13,10 @@
  * CPU Extended Control register specific definitions
  ******************************************************************************/
 #define CORTEX_A510_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT		U(19)
+#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE	U(1)
+#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT			U(23)
+#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT			U(46)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions
@@ -20,4 +24,14 @@
 #define CORTEX_A510_CPUPWRCTLR_EL1				S3_0_C15_C2_7
 #define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
 
+/*******************************************************************************
+ * Complex auxiliary control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A510_CMPXACTLR_EL1				S3_0_C15_C1_3
+
+/*******************************************************************************
+ * Auxiliary control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A510_CPUACTLR_EL1				S3_0_C15_C1_0
+
 #endif /* CORTEX_A510_H */
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
index d2bc146..dc56b62 100644
--- a/include/lib/cpus/aarch64/cortex_a710.h
+++ b/include/lib/cpus/aarch64/cortex_a710.h
@@ -26,12 +26,14 @@
  ******************************************************************************/
 #define CORTEX_A710_CPUACTLR_EL1 				S3_0_C15_C1_0
 #define CORTEX_A710_CPUACTLR_EL1_BIT_46				(ULL(1) << 46)
+#define CORTEX_A710_CPUACTLR_EL1_BIT_22				(ULL(1) << 22)
 
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
 #define CORTEX_A710_CPUACTLR5_EL1				S3_0_C15_C8_0
 #define CORTEX_A710_CPUACTLR5_EL1_BIT_13			(ULL(1) << 13)
+#define CORTEX_A710_CPUACTLR5_EL1_BIT_44			(ULL(1) << 44)
 
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h
index bf1b460..e3d0fa9 100644
--- a/include/lib/cpus/aarch64/cortex_x2.h
+++ b/include/lib/cpus/aarch64/cortex_x2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,6 +13,7 @@
  * CPU Extended Control register specific definitions
  ******************************************************************************/
 #define CORTEX_X2_CPUECTLR_EL1					S3_0_C15_C1_4
+#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT			(ULL(1) << 8)
 
 /*******************************************************************************
  * CPU Extended Control register 2 specific definitions
@@ -33,5 +34,14 @@
  * CPU Auxiliary Control Register 5 definitions
  ******************************************************************************/
 #define CORTEX_X2_CPUACTLR5_EL1					S3_0_C15_C8_0
+#define CORTEX_X2_CPUACTLR5_EL1_BIT_17				(ULL(1) << 17)
+
+/*******************************************************************************
+ * CPU Implementation Specific Selected Instruction registers
+ ******************************************************************************/
+#define CORTEX_X2_IMP_CPUPSELR_EL3				S3_6_C15_C8_0
+#define CORTEX_X2_IMP_CPUPCR_EL3				S3_6_C15_C8_1
+#define CORTEX_X2_IMP_CPUPOR_EL3				S3_6_C15_C8_2
+#define CORTEX_X2_IMP_CPUPMR_EL3				S3_6_C15_C8_3
 
 #endif /* CORTEX_X2_H */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 1993cb4..2af8c11 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -381,7 +381,7 @@
  * The max number of regions like RO(code), coherent and data required by
  * different BL stages which need to be mapped in the MMU.
  */
-#define ARM_BL_REGIONS			6
+#define ARM_BL_REGIONS			7
 
 #define MAX_MMAP_REGIONS		(PLAT_ARM_MMAP_ENTRIES +	\
 					 ARM_BL_REGIONS)
diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h
index 4c049c5..9a7c489 100644
--- a/include/services/ffa_svc.h
+++ b/include/services/ffa_svc.h
@@ -116,6 +116,7 @@
 #define FFA_MSG_YIELD		FFA_FID(SMC_32, FFA_FNUM_MSG_YIELD)
 #define FFA_MSG_RUN		FFA_FID(SMC_32, FFA_FNUM_MSG_RUN)
 #define FFA_MSG_SEND		FFA_FID(SMC_32, FFA_FNUM_MSG_SEND)
+#define FFA_MSG_SEND2		FFA_FID(SMC_32, FFA_FNUM_MSG_SEND2)
 #define FFA_MSG_SEND_DIRECT_REQ_SMC32 \
 	FFA_FID(SMC_32, FFA_FNUM_MSG_SEND_DIRECT_REQ)
 #define FFA_MSG_SEND_DIRECT_RESP_SMC32	\
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 3310322..34e1082 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2022, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,14 +13,257 @@
 
 /* Hardware handled coherency */
 #if HW_ASSISTED_COHERENCY == 0
-#error "Cortex A510 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled"
 #endif
 
 /* 64-bit only core */
 #if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #1922240.
+	 * This applies only to revision r0p0 (fixed in r0p1)
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_1922240_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_1922240
+	cbz	x0, 1f
+
+	/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
+	mrs	x0, CORTEX_A510_CMPXACTLR_EL1
+	mov	x1, #3
+	bfi	x0, x1, #10, #2
+	msr	CORTEX_A510_CMPXACTLR_EL1, x0
+
+1:
+	ret	x17
+endfunc errata_cortex_a510_1922240_wa
+
+func check_errata_1922240
+	/* Applies to r0p0 only */
+	mov	x1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_1922240
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #2288014.
+	 * This applies only to revisions r0p0, r0p1, r0p2,
+	 * r0p3 and r1p0. (fixed in r1p1)
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_2288014_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2288014
+	cbz	x0, 1f
+
+	/* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
+	mrs	x0, CORTEX_A510_CPUACTLR_EL1
+	mov	x1, #1
+	bfi	x0, x1, #18, #1
+	msr	CORTEX_A510_CPUACTLR_EL1, x0
+
+1:
+	ret	x17
+endfunc errata_cortex_a510_2288014_wa
+
+func check_errata_2288014
+	/* Applies to r1p0 and below */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_2288014
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #2042739.
+	 * This applies only to revisions r0p0, r0p1 and r0p2.
+	 * (fixed in r0p3)
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_2042739_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2042739
+	cbz	x0, 1f
+
+	/* Apply the workaround by disabling ReadPreferUnique. */
+	mrs	x0, CORTEX_A510_CPUECTLR_EL1
+	mov	x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
+	bfi	x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
+	msr	CORTEX_A510_CPUECTLR_EL1, x0
+
+1:
+	ret	x17
+endfunc errata_cortex_a510_2042739_wa
+
+func check_errata_2042739
+	/* Applies to revisions r0p0 - r0p2 */
+	mov	x1, #0x02
+	b	cpu_rev_var_ls
+endfunc check_errata_2042739
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #2041909.
+	 * This applies only to revision r0p2 and it is fixed in
+	 * r0p3. The issue is also present in r0p0 and r0p1 but
+	 * there is no workaround in those revisions.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x2, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_2041909_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2041909
+	cbz	x0, 1f
+
+	/* Apply workaround */
+	mov	x0, xzr
+	msr	S3_6_C15_C4_0, x0
+	isb
+
+	mov	x0, #0x8500000
+	msr	S3_6_C15_C4_2, x0
+
+	mov	x0, #0x1F700000
+	movk	x0, #0x8, lsl #32
+	msr	S3_6_C15_C4_3, x0
+
+	mov	x0, #0x3F1
+	movk	x0, #0x110, lsl #16
+	msr	S3_6_C15_C4_1, x0
+	isb
+
+1:
+	ret	x17
+endfunc errata_cortex_a510_2041909_wa
+
+func check_errata_2041909
+	/* Applies only to revision r0p2 */
+	mov	x1, #0x02
+	mov	x2, #0x02
+	b	cpu_rev_var_range
+endfunc check_errata_2041909
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #2250311.
+	 * This applies only to revisions r0p0, r0p1, r0p2,
+	 * r0p3 and r1p0, and is fixed in r1p1.
+	 * This workaround is not a typical errata fix. MPMM
+	 * is disabled here, but this conflicts with the BL31
+	 * MPMM support. So in addition to simply disabling
+	 * the feature, a flag is set in the MPMM library
+	 * indicating that it should not be enabled even if
+	 * ENABLE_MPMM=1.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_2250311_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2250311
+	cbz	x0, 1f
+
+	/* Disable MPMM */
+	mrs	x0, CPUMPMMCR_EL3
+	bfm	x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
+	msr	CPUMPMMCR_EL3, x0
+
+#if ENABLE_MPMM && IMAGE_BL31
+	/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
+	bl mpmm_errata_disable
+#endif
+
+1:
+	ret x17
+endfunc errata_cortex_a510_2250311_wa
+
+func check_errata_2250311
+	/* Applies to r1p0 and lower */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_2250311
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #2218950.
+	 * This applies only to revisions r0p0, r0p1, r0p2,
+	 * r0p3 and r1p0, and is fixed in r1p1.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_2218950_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2218950
+	cbz	x0, 1f
+
+	/* Source register for BFI */
+	mov	x1, #1
+
+	/* Set bit 18 in CPUACTLR_EL1 */
+	mrs	x0, CORTEX_A510_CPUACTLR_EL1
+	bfi	x0, x1, #18, #1
+	msr	CORTEX_A510_CPUACTLR_EL1, x0
+
+	/* Set bit 25 in CMPXACTLR_EL1 */
+	mrs	x0, CORTEX_A510_CMPXACTLR_EL1
+	bfi	x0, x1, #25, #1
+	msr	CORTEX_A510_CMPXACTLR_EL1, x0
+
+1:
+	ret x17
+endfunc errata_cortex_a510_2218950_wa
+
+func check_errata_2218950
+	/* Applies to r1p0 and lower */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_2218950
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #2172148.
+	 * This applies only to revisions r0p0, r0p1, r0p2,
+	 * r0p3 and r1p0, and is fixed in r1p1.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_2172148_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2172148
+	cbz	x0, 1f
+
+	/*
+	 * Force L2 allocation of transient lines by setting
+	 * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
+	 */
+	mrs	x0, CORTEX_A510_CPUECTLR_EL1
+	mov	x1, #1
+	bfi	x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
+	bfi	x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
+	msr	CORTEX_A510_CPUECTLR_EL1, x0
+
+1:
+	ret x17
+endfunc errata_cortex_a510_2172148_wa
+
+func check_errata_2172148
+	/* Applies to r1p0 and lower */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_2172148
+
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
@@ -38,19 +281,79 @@
 endfunc cortex_a510_core_pwr_dwn
 
 	/*
-	 * Errata printing function for Cortex A510. Must follow AAPCS.
+	 * Errata printing function for Cortex-A510. Must follow AAPCS.
 	 */
 #if REPORT_ERRATA
 func cortex_a510_errata_report
+	stp	x8, x30, [sp, #-16]!
+
+	bl	cpu_get_rev_var
+	mov	x8, x0
+
+	/*
+	 * Report all errata. The revision-variant information is passed to
+	 * checking functions of each errata.
+	 */
+	report_errata ERRATA_A510_1922240, cortex_a510, 1922240
+	report_errata ERRATA_A510_2288014, cortex_a510, 2288014
+	report_errata ERRATA_A510_2042739, cortex_a510, 2042739
+	report_errata ERRATA_A510_2041909, cortex_a510, 2041909
+	report_errata ERRATA_A510_2250311, cortex_a510, 2250311
+	report_errata ERRATA_A510_2218950, cortex_a510, 2218950
+	report_errata ERRATA_A510_2172148, cortex_a510, 2172148
+
+	ldp	x8, x30, [sp], #16
 	ret
 endfunc cortex_a510_errata_report
 #endif
 
 func cortex_a510_reset_func
+	mov	x19, x30
+
 	/* Disable speculative loads */
 	msr	SSBS, xzr
 	isb
-	ret
+
+	/* Get the CPU revision and stash it in x18. */
+	bl	cpu_get_rev_var
+	mov	x18, x0
+
+#if ERRATA_A510_1922240
+	mov	x0, x18
+	bl	errata_cortex_a510_1922240_wa
+#endif
+
+#if ERRATA_A510_2288014
+	mov	x0, x18
+	bl	errata_cortex_a510_2288014_wa
+#endif
+
+#if ERRATA_A510_2042739
+	mov	x0, x18
+	bl	errata_cortex_a510_2042739_wa
+#endif
+
+#if ERRATA_A510_2041909
+	mov	x0, x18
+	bl	errata_cortex_a510_2041909_wa
+#endif
+
+#if ERRATA_A510_2250311
+	mov	x0, x18
+	bl	errata_cortex_a510_2250311_wa
+#endif
+
+#if ERRATA_A510_2218950
+	mov	x0, x18
+	bl	errata_cortex_a510_2218950_wa
+#endif
+
+#if ERRATA_A510_2172148
+	mov	x0, x18
+	bl	errata_cortex_a510_2172148_wa
+#endif
+
+	ret	x19
 endfunc cortex_a510_reset_func
 
 	/* ---------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 7d7fbd8..92f7363 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -216,6 +216,65 @@
 	b	cpu_rev_var_ls
 endfunc check_errata_2058056
 
+/* --------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2267065.
+ * This applies to revisions r0p0, r1p0 and r2p0.
+ * It is fixed in r2p1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * --------------------------------------------------
+ */
+func errata_a710_2267065_wa
+	/* Compare x0 against revision r2p0 */
+	mov	x17, x30
+	bl	check_errata_2267065
+	cbz	x0, 1f
+
+	/* Apply instruction patching sequence */
+	mrs	x1, CORTEX_A710_CPUACTLR_EL1
+	orr	x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
+	msr	CORTEX_A710_CPUACTLR_EL1, x1
+1:
+	ret	x17
+endfunc errata_a710_2267065_wa
+
+func check_errata_2267065
+	/* Applies to r0p0, r1p0 and r2p0 */
+	mov	x1, #0x20
+	b	cpu_rev_var_ls
+endfunc check_errata_2267065
+
+/* ---------------------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2136059.
+ * This applies to revision r0p0, r1p0 and r2p0.
+ * It is fixed in r2p1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ---------------------------------------------------------------
+ */
+func errata_a710_2136059_wa
+	/* Compare x0 against revision r2p0 */
+	mov     x17, x30
+	bl      check_errata_2136059
+	cbz     x0, 1f
+
+	/* Apply the workaround */
+	mrs     x1, CORTEX_A710_CPUACTLR5_EL1
+	orr     x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
+	msr     CORTEX_A710_CPUACTLR5_EL1, x1
+
+1:
+	ret     x17
+endfunc errata_a710_2136059_wa
+
+func check_errata_2136059
+	/* Applies to r0p0, r1p0 and r2p0 */
+	mov     x1, #0x20
+	b       cpu_rev_var_ls
+endfunc check_errata_2136059
+
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
@@ -252,6 +311,8 @@
 	report_errata ERRATA_A710_2017096, cortex_a710, 2017096
 	report_errata ERRATA_A710_2083908, cortex_a710, 2083908
 	report_errata ERRATA_A710_2058056, cortex_a710, 2058056
+	report_errata ERRATA_A710_2267065, cortex_a710, 2267065
+	report_errata ERRATA_A710_2136059, cortex_a710, 2136059
 
 	ldp	x8, x30, [sp], #16
 	ret
@@ -296,6 +357,17 @@
 	mov	x0, x18
 	bl	errata_a710_2058056_wa
 #endif
+
+#if ERRATA_A710_2267065
+	mov	x0, x18
+	bl	errata_a710_2267065_wa
+#endif
+
+#if ERRATA_A710_2136059
+	mov	x0, x18
+	bl	errata_a710_2136059_wa
+#endif
+
 	isb
 	ret	x19
 endfunc cortex_a710_reset_func
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index 88116c3..2ecfbbb 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -113,6 +113,115 @@
 	b	cpu_rev_var_range
 endfunc check_errata_2083908
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-X2 Errata 2017096.
+	 * This applies only to revisions r0p0, r1p0 and r2p0
+	 * and is fixed in r2p1.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_x2_2017096_wa
+	/* Compare x0 against revision r0p0 to r2p0 */
+	mov     x17, x30
+	bl      check_errata_2017096
+	cbz     x0, 1f
+	mrs     x1, CORTEX_X2_CPUECTLR_EL1
+	orr     x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
+	msr     CORTEX_X2_CPUECTLR_EL1, x1
+
+1:
+	ret     x17
+endfunc errata_x2_2017096_wa
+
+func check_errata_2017096
+	/* Applies to r0p0, r1p0, r2p0 */
+	mov     x1, #0x20
+	b       cpu_rev_var_ls
+endfunc check_errata_2017096
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-X2 Errata 2081180.
+	 * This applies to revision r0p0, r1p0 and r2p0
+	 * and is fixed in r2p1.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_x2_2081180_wa
+	/* Check revision. */
+	mov	x17, x30
+	bl	check_errata_2081180
+	cbz	x0, 1f
+
+	/* Apply instruction patching sequence */
+	ldr	x0, =0x3
+	msr	CORTEX_X2_IMP_CPUPSELR_EL3, x0
+	ldr	x0, =0xF3A08002
+	msr	CORTEX_X2_IMP_CPUPOR_EL3, x0
+	ldr	x0, =0xFFF0F7FE
+	msr	CORTEX_X2_IMP_CPUPMR_EL3, x0
+	ldr	x0, =0x10002001003FF
+	msr	CORTEX_X2_IMP_CPUPCR_EL3, x0
+	ldr	x0, =0x4
+	msr	CORTEX_X2_IMP_CPUPSELR_EL3, x0
+	ldr	x0, =0xBF200000
+	msr	CORTEX_X2_IMP_CPUPOR_EL3, x0
+	ldr	x0, =0xFFEF0000
+	msr	CORTEX_X2_IMP_CPUPMR_EL3, x0
+	ldr	x0, =0x10002001003F3
+	msr	CORTEX_X2_IMP_CPUPCR_EL3, x0
+	isb
+1:
+	ret	x17
+endfunc errata_x2_2081180_wa
+
+func check_errata_2081180
+	/* Applies to r0p0, r1p0 and r2p0 */
+	mov	x1, #0x20
+	b	cpu_rev_var_ls
+endfunc check_errata_2081180
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex X2 Errata 2216384.
+	 * This applies to revisions r0p0, r1p0, and r2p0
+	 * and is fixed in r2p1.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_x2_2216384_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2216384
+	cbz	x0, 1f
+
+	mrs	x1, CORTEX_X2_CPUACTLR5_EL1
+	orr	x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
+	msr	CORTEX_X2_CPUACTLR5_EL1, x1
+
+	/* Apply instruction patching sequence */
+	ldr	x0, =0x5
+	msr	CORTEX_X2_IMP_CPUPSELR_EL3, x0
+	ldr	x0, =0x10F600E000
+	msr	CORTEX_X2_IMP_CPUPOR_EL3, x0
+	ldr	x0, =0x10FF80E000
+	msr	CORTEX_X2_IMP_CPUPMR_EL3, x0
+	ldr	x0, =0x80000000003FF
+	msr	CORTEX_X2_IMP_CPUPCR_EL3, x0
+	isb
+
+1:
+	ret	x17
+endfunc errata_x2_2216384_wa
+
+func check_errata_2216384
+	/* Applies to r0p0 - r2p0 */
+	mov	x1, #0x20
+	b	cpu_rev_var_ls
+endfunc check_errata_2216384
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
@@ -146,6 +255,9 @@
 	report_errata ERRATA_X2_2002765, cortex_x2, 2002765
 	report_errata ERRATA_X2_2058056, cortex_x2, 2058056
 	report_errata ERRATA_X2_2083908, cortex_x2, 2083908
+	report_errata ERRATA_X2_2017096, cortex_x2, 2017096
+	report_errata ERRATA_X2_2081180, cortex_x2, 2081180
+	report_errata ERRATA_X2_2216384, cortex_x2, 2216384
 
 	ldp	x8, x30, [sp], #16
 	ret
@@ -178,6 +290,21 @@
 	bl	errata_cortex_x2_2083908_wa
 #endif
 
+#if ERRATA_X2_2017096
+	mov	x0, x18
+	bl	errata_x2_2017096_wa
+#endif
+
+#if ERRATA_X2_2081180
+	mov	x0, x18
+	bl	errata_x2_2081180_wa
+#endif
+
+#if ERRATA_X2_2216384
+	mov	x0, x18
+	bl	errata_x2_2216384_wa
+#endif
+
 	ret x19
 endfunc cortex_x2_reset_func
 
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index dd06cb8..62b67b6 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
 # Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
@@ -7,27 +7,27 @@
 
 # Cortex A57 specific optimisation to skip L1 cache flush when
 # cluster is powered down.
-SKIP_A57_L1_FLUSH_PWR_DWN	?=0
+SKIP_A57_L1_FLUSH_PWR_DWN		?=0
 
 # Flag to disable the cache non-temporal hint.
 # It is enabled by default.
-A53_DISABLE_NON_TEMPORAL_HINT	?=1
+A53_DISABLE_NON_TEMPORAL_HINT		?=1
 
 # Flag to disable the cache non-temporal hint.
 # It is enabled by default.
-A57_DISABLE_NON_TEMPORAL_HINT	?=1
+A57_DISABLE_NON_TEMPORAL_HINT		?=1
 
 # Flag to enable higher performance non-cacheable load forwarding.
 # It is disabled by default.
 A57_ENABLE_NONCACHEABLE_LOAD_FWD	?= 0
 
-WORKAROUND_CVE_2017_5715	?=1
-WORKAROUND_CVE_2018_3639	?=1
+WORKAROUND_CVE_2017_5715		?=1
+WORKAROUND_CVE_2018_3639		?=1
 DYNAMIC_WORKAROUND_CVE_2018_3639	?=0
 
 # Flags to indicate internal or external Last level cache
 # By default internal
-NEOVERSE_Nx_EXTERNAL_LLC	?=0
+NEOVERSE_Nx_EXTERNAL_LLC		?=0
 
 # Process A57_ENABLE_NONCACHEABLE_LOAD_FWD flag
 $(eval $(call assert_boolean,A57_ENABLE_NONCACHEABLE_LOAD_FWD))
@@ -60,9 +60,9 @@
 $(eval $(call add_define,NEOVERSE_Nx_EXTERNAL_LLC))
 
 ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
-    ifeq (${WORKAROUND_CVE_2018_3639},0)
-        $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
-    endif
+	ifeq (${WORKAROUND_CVE_2018_3639},0)
+		$(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
+	endif
 endif
 
 # CPU Errata Build flags.
@@ -108,7 +108,7 @@
 # only to revision <= r0p2 of the Cortex A53 cpu.
 ERRATA_A53_827319	?=0
 
-# Flag to apply erratum 835769 workaround at compile and link time.  This
+# Flag to apply erratum 835769 workaround at compile and link time. This
 # erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
 # workaround can lead the linker to create "*.stub" sections.
 ERRATA_A53_835769	?=0
@@ -170,11 +170,11 @@
 # only to revision r0p0 of the Cortex A57 cpu.
 ERRATA_A57_813419	?=0
 
-# Flag to apply erratum 813420  workaround during reset. This erratum applies
+# Flag to apply erratum 813420 workaround during reset. This erratum applies
 # only to revision r0p0 of the Cortex A57 cpu.
 ERRATA_A57_813420	?=0
 
-# Flag to apply erratum 814670  workaround during reset. This erratum applies
+# Flag to apply erratum 814670 workaround during reset. This erratum applies
 # only to revision r0p0 of the Cortex A57 cpu.
 ERRATA_A57_814670	?=0
 
@@ -307,7 +307,7 @@
 ERRATA_A78_1941498	?=0
 
 # Flag to apply erratum 1951500 workaround during reset. This erratum applies
-# to revisions r1p0 and r1p1 of the A78 cpu.  The issue is present in r0p0 as
+# to revisions r1p0 and r1p1 of the A78 cpu. The issue is present in r0p0 as
 # well but there is no workaround for that revision.
 ERRATA_A78_1951500	?=0
 
@@ -317,11 +317,11 @@
 
 # Flag to apply erratum 1952683 workaround during reset. This erratum applies
 # to revision r0p0 of the A78 cpu and was fixed in the revision r1p0.
-ERRATA_A78_1952683  ?=0
+ERRATA_A78_1952683	?=0
 
 # Flag to apply erratum 2132060 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
-ERRATA_A78_2132060  ?=0
+ERRATA_A78_2132060	?=0
 
 # Flag to apply erratum 2242635 workaround during reset. This erratum applies
 # to revisions r1p0, r1p1, and r1p2 of the A78 cpu and is open. The issue is
@@ -389,7 +389,7 @@
 ERRATA_N1_1868343	?=0
 
 # Flag to apply erratum 1946160 workaround during reset. This erratum applies
-# to revisions r3p0, r3p1, r4p0, and r4p1 of the Neoverse N1 cpu.  The issue
+# to revisions r3p0, r3p1, r4p0, and r4p1 of the Neoverse N1 cpu. The issue
 # exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround.
 ERRATA_N1_1946160	?=0
 
@@ -397,19 +397,19 @@
 # to revisions r0p0 of the Neoverse-N2 cpu, it is still open.
 ERRATA_N2_2002655	?=0
 
-# Flag to apply erratum 1774420 workaround during reset.  This erratum applies
+# Flag to apply erratum 1774420 workaround during reset. This erratum applies
 # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
 ERRATA_V1_1774420	?=0
 
-# Flag to apply erratum 1791573 workaround during reset.  This erratum applies
+# Flag to apply erratum 1791573 workaround during reset. This erratum applies
 # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
 ERRATA_V1_1791573	?=0
 
-# Flag to apply erratum 1852267 workaround during reset.  This erratum applies
+# Flag to apply erratum 1852267 workaround during reset. This erratum applies
 # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
 ERRATA_V1_1852267	?=0
 
-# Flag to apply erratum 1925756 workaround during reset.  This needs to be
+# Flag to apply erratum 1925756 workaround during reset. This needs to be
 # enabled for r0p0, r1p0, and r1p1 of the Neoverse V1 core, it is still open.
 ERRATA_V1_1925756	?=0
 
@@ -418,7 +418,7 @@
 ERRATA_V1_1940577	?=0
 
 # Flag to apply erratum 1966096 workaround during reset. This erratum applies
-# to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open.  This issue
+# to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open. This issue
 # exists in r0p0 as well but there is no workaround for that revision.
 ERRATA_V1_1966096	?=0
 
@@ -451,6 +451,22 @@
 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
 ERRATA_A710_2058056	?=0
 
+# Flag to apply erratum 2055002 workaround during reset. This erratum applies
+# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
+ERRATA_A710_2055002	?=0
+
+# Flag to apply erratum 2017096 workaround during reset. This erratum applies
+# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
+ERRATA_A710_2017096	?=0
+
+# Flag to apply erratum 2267065 workaround during reset. This erratum applies
+# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
+ERRATA_A710_2267065	?=0
+
+# Flag to apply erratum 2136059 workaround during reset. This erratum applies
+# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
+ERRATA_A710_2136059	?=0
+
 # Flag to apply erratum 2067956 workaround during reset. This erratum applies
 # to revision r0p0 of the Neoverse N2 cpu and is still open.
 ERRATA_N2_2067956	?=0
@@ -487,25 +503,62 @@
 # to revision r0p0 of the Neoverse N2 cpu and is still open.
 ERRATA_N2_2280757	?=0
 
-# Flag to apply erratum 2055002 workaround during reset. This erratum applies
-# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
-ERRATA_A710_2055002	?=0
-
-# Flag to apply erratum 2017096 workaround during reset. This erratum applies
-# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
-ERRATA_A710_2017096	?=0
-
 # Flag to apply erratum 2002765 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
-ERRATA_X2_2002765   ?=0
+ERRATA_X2_2002765	?=0
 
 # Flag to apply erratum 2058056 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
-ERRATA_X2_2058056   ?=0
+ERRATA_X2_2058056	?=0
 
 # Flag to apply erratum 2083908 workaround during reset. This erratum applies
 # to revision r2p0 of the Cortex-X2 cpu and is still open.
-ERRATA_X2_2083908   ?=0
+ERRATA_X2_2083908	?=0
+
+# Flag to apply erratum 2017096 workaround during reset. This erratum applies
+# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
+# r2p1.
+ERRATA_X2_2017096	?=0
+
+# Flag to apply erratum 2081180 workaround during reset. This erratum applies
+# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
+# r2p1.
+ERRATA_X2_2081180	?=0
+
+# Flag to apply erratum 2216384 workaround during reset. This erratum applies
+# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
+# r2p1.
+ERRATA_X2_2216384	?=0
+
+# Flag to apply erratum 1922240 workaround during reset. This erratum applies
+# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
+ERRATA_A510_1922240	?=0
+
+# Flag to apply erratum 2288014 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0 of the Cortex-A510 cpu and is
+# fixed in r1p1.
+ERRATA_A510_2288014	?=0
+
+# Flag to apply erratum 2042739 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1 and r0p2 of the Cortex-A510 cpu and is fixed in r0p3.
+ERRATA_A510_2042739	?=0
+
+# Flag to apply erratum 2041909 workaround during reset. This erratum applies
+# to revision r0p2 of the Cortex-A510 cpu and is fixed in r0p3. The issue is
+# present in r0p0 and r0p1 but there is no workaround for those revisions.
+ERRATA_A510_2041909	?=0
+
+# Flag to apply erratum 2250311 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
+ERRATA_A510_2250311	?=0
+
+# Flag to apply erratum 2218950 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
+ERRATA_A510_2218950	?=0
+
+# Flag to apply erratum 2172148 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
+ERRATA_A510_2172148	?=0
 
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
@@ -888,6 +941,22 @@
 $(eval $(call assert_boolean,ERRATA_A710_2058056))
 $(eval $(call add_define,ERRATA_A710_2058056))
 
+# Process ERRATA_A710_2055002 flag
+$(eval $(call assert_boolean,ERRATA_A710_2055002))
+$(eval $(call add_define,ERRATA_A710_2055002))
+
+# Process ERRATA_A710_2017096 flag
+$(eval $(call assert_boolean,ERRATA_A710_2017096))
+$(eval $(call add_define,ERRATA_A710_2017096))
+
+# Process ERRATA_A710_2267065 flag
+$(eval $(call assert_boolean,ERRATA_A710_2267065))
+$(eval $(call add_define,ERRATA_A710_2267065))
+
+# Process ERRATA_A710_2136059 flag
+$(eval $(call assert_boolean,ERRATA_A710_2136059))
+$(eval $(call add_define,ERRATA_A710_2136059))
+
 # Process ERRATA_N2_2067956 flag
 $(eval $(call assert_boolean,ERRATA_N2_2067956))
 $(eval $(call add_define,ERRATA_N2_2067956))
@@ -924,14 +993,6 @@
 $(eval $(call assert_boolean,ERRATA_N2_2280757))
 $(eval $(call add_define,ERRATA_N2_2280757))
 
-# Process ERRATA_A710_2055002 flag
-$(eval $(call assert_boolean,ERRATA_A710_2055002))
-$(eval $(call add_define,ERRATA_A710_2055002))
-
-# Process ERRATA_A710_2017096 flag
-$(eval $(call assert_boolean,ERRATA_A710_2017096))
-$(eval $(call add_define,ERRATA_A710_2017096))
-
 # Process ERRATA_X2_2002765 flag
 $(eval $(call assert_boolean,ERRATA_X2_2002765))
 $(eval $(call add_define,ERRATA_X2_2002765))
@@ -944,6 +1005,46 @@
 $(eval $(call assert_boolean,ERRATA_X2_2083908))
 $(eval $(call add_define,ERRATA_X2_2083908))
 
+# Process ERRATA_X2_2017096 flag
+$(eval $(call assert_boolean,ERRATA_X2_2017096))
+$(eval $(call add_define,ERRATA_X2_2017096))
+
+# Process ERRATA_X2_2081180 flag
+$(eval $(call assert_boolean,ERRATA_X2_2081180))
+$(eval $(call add_define,ERRATA_X2_2081180))
+
+# Process ERRATA_X2_2216384 flag
+$(eval $(call assert_boolean,ERRATA_X2_2216384))
+$(eval $(call add_define,ERRATA_X2_2216384))
+
+# Process ERRATA_A510_1922240 flag
+$(eval $(call assert_boolean,ERRATA_A510_1922240))
+$(eval $(call add_define,ERRATA_A510_1922240))
+
+# Process ERRATA_A510_2288014 flag
+$(eval $(call assert_boolean,ERRATA_A510_2288014))
+$(eval $(call add_define,ERRATA_A510_2288014))
+
+# Process ERRATA_A510_2042739 flag
+$(eval $(call assert_boolean,ERRATA_A510_2042739))
+$(eval $(call add_define,ERRATA_A510_2042739))
+
+# Process ERRATA_A510_2041909 flag
+$(eval $(call assert_boolean,ERRATA_A510_2041909))
+$(eval $(call add_define,ERRATA_A510_2041909))
+
+# Process ERRATA_A510_2250311 flag
+$(eval $(call assert_boolean,ERRATA_A510_2250311))
+$(eval $(call add_define,ERRATA_A510_2250311))
+
+# Process ERRATA_A510_2218950 flag
+$(eval $(call assert_boolean,ERRATA_A510_2218950))
+$(eval $(call add_define,ERRATA_A510_2218950))
+
+# Process ERRATA_A510_2172148 flag
+$(eval $(call assert_boolean,ERRATA_A510_2172148))
+$(eval $(call add_define,ERRATA_A510_2172148))
+
 # Process ERRATA_DSU_798953 flag
 $(eval $(call assert_boolean,ERRATA_DSU_798953))
 $(eval $(call add_define,ERRATA_DSU_798953))
diff --git a/lib/fconf/fconf.c b/lib/fconf/fconf.c
index 24b6bcc..b1d6eaa 100644
--- a/lib/fconf/fconf.c
+++ b/lib/fconf/fconf.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,15 +34,15 @@
 	config_image_info.image_base = config_info->config_addr;
 	config_image_info.image_max_size = config_info->config_max_size;
 
-	VERBOSE("FCONF: Loading config with image ID: %d\n", image_id);
+	VERBOSE("FCONF: Loading config with image ID: %u\n", image_id);
 	err = load_auth_image(image_id, &config_image_info);
 	if (err != 0) {
-		VERBOSE("Failed to load config %d\n", image_id);
+		VERBOSE("Failed to load config %u\n", image_id);
 		return err;
 	}
 
-	INFO("FCONF: Config file with image ID:%d loaded at address = 0x%lx\n",
-		image_id, config_image_info.image_base);
+	INFO("FCONF: Config file with image ID:%u loaded at address = 0x%lx\n",
+	     image_id, config_image_info.image_base);
 
 	return 0;
 }
diff --git a/lib/libc/assert.c b/lib/libc/assert.c
index ff987b3..c199de6 100644
--- a/lib/libc/assert.c
+++ b/lib/libc/assert.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,7 +21,7 @@
 void __dead2 __assert(const char *file, unsigned int line,
 		      const char *assertion)
 {
-	printf("ASSERT: %s:%d:%s\n", file, line, assertion);
+	printf("ASSERT: %s:%u:%s\n", file, line, assertion);
 	backtrace("assert");
 	console_flush();
 	plat_panic_handler();
@@ -29,7 +29,7 @@
 #elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
 void __dead2 __assert(const char *file, unsigned int line)
 {
-	printf("ASSERT: %s:%d\n", file, line);
+	printf("ASSERT: %s:%u\n", file, line);
 	backtrace("assert");
 	console_flush();
 	plat_panic_handler();
diff --git a/lib/libc/snprintf.c b/lib/libc/snprintf.c
index f34cefd..675d243 100644
--- a/lib/libc/snprintf.c
+++ b/lib/libc/snprintf.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -42,7 +42,7 @@
 	char ascii_a = capitalise ? 'A' : 'a';
 
 	if (radix < 10) {
-		ERROR("snprintf: unsupported radix '%d'.", radix);
+		ERROR("snprintf: unsupported radix '%u'.", radix);
 		plat_panic_handler();
 		assert(0); /* Unreachable */
 	}
diff --git a/lib/mpmm/mpmm.c b/lib/mpmm/mpmm.c
index a66f2aa..dc61cf6 100644
--- a/lib/mpmm/mpmm.c
+++ b/lib/mpmm/mpmm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -62,11 +62,25 @@
 	return supported;
 }
 
+/* Defaults to false */
+static bool mpmm_disable_for_errata;
+
 void mpmm_enable(void)
 {
-	bool supported = mpmm_supported();
-
-	if (supported) {
+	if (mpmm_supported()) {
+		if (mpmm_disable_for_errata) {
+			WARN("MPMM: disabled by errata workaround\n");
+			return;
+		}
 		write_cpumpmmcr_el3_mpmm_en(1U);
 	}
 }
+
+/*
+ * This function is called from assembly code very early in BL31 so it must be
+ * small and simple.
+ */
+void mpmm_errata_disable(void)
+{
+	mpmm_disable_for_errata = true;
+}
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 9f8a08a..170777f 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -908,7 +908,7 @@
 							idx++) {
 		state_type = find_local_state_type(
 				psci_non_cpu_pd_nodes[idx].local_state);
-		INFO("  Domain Node : Level %u, parent_node %d,"
+		INFO("  Domain Node : Level %u, parent_node %u,"
 				" State %s (0x%x)\n",
 				psci_non_cpu_pd_nodes[idx].level,
 				psci_non_cpu_pd_nodes[idx].parent_node,
@@ -919,7 +919,7 @@
 	for (idx = 0; idx < psci_plat_core_count; idx++) {
 		state = psci_get_cpu_local_state_by_idx(idx);
 		state_type = find_local_state_type(state);
-		INFO("  CPU Node : MPID 0x%llx, parent_node %d,"
+		INFO("  CPU Node : MPID 0x%llx, parent_node %u,"
 				" State %s (0x%x)\n",
 				(unsigned long long)psci_cpu_pd_nodes[idx].mpidr,
 				psci_cpu_pd_nodes[idx].parent_node,
diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
index 38f91fe..06e2a06 100644
--- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S
+++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-/* diphda platform provides custom values for the macros defined in
+/* corstone1000 platform provides custom values for the macros defined in
  * arm_def.h , so only platform_def.h needs to be included
  */
 #if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)
diff --git a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
similarity index 83%
rename from plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
rename to plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
index 916c868..3ee396c 100644
--- a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -44,7 +44,7 @@
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
 			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
 		.ep_info.pc = BL32_BASE,
-			.ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE,
+			.ep_info.args.arg0 = CORSTONE1000_TOS_FW_CONFIG_BASE,
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 			VERSION_2, image_info_t, 0),
 		.image_info.image_base = BL32_BASE,
@@ -56,9 +56,9 @@
 	/* Fill TOS_FW_CONFIG related information */
 	{
 		.image_id = TOS_FW_CONFIG_ID,
-		.image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE,
-		.image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \
-			DIPHDA_TOS_FW_CONFIG_BASE,
+		.image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE,
+		.image_info.image_max_size = CORSTONE1000_TOS_FW_CONFIG_LIMIT - \
+			CORSTONE1000_TOS_FW_CONFIG_BASE,
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
 			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
@@ -71,13 +71,12 @@
 		.image_id = BL33_IMAGE_ID,
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
 			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
-		.ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
+		.ep_info.pc = BL33_BASE,
 
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 			VERSION_2, image_info_t, 0),
-		.image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
-		.image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
-			- PLAT_ARM_NS_IMAGE_BASE,
+		.image_info.image_base = BL33_BASE,
+		.image_info.image_max_size = BL33_LIMIT - BL33_BASE,
 
 		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
diff --git a/plat/arm/board/diphda/common/diphda_err.c b/plat/arm/board/corstone1000/common/corstone1000_err.c
similarity index 60%
rename from plat/arm/board/diphda/common/diphda_err.c
rename to plat/arm/board/corstone1000/common/corstone1000_err.c
index 89a3b82..376799f 100644
--- a/plat/arm/board/diphda/common/diphda_err.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_err.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +7,7 @@
 #include <plat/arm/common/plat_arm.h>
 
 /*
- * diphda error handler
+ * corstone1000 error handler
  */
 void __dead2 plat_arm_error_handler(int err)
 {
diff --git a/plat/arm/board/diphda/common/diphda_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
similarity index 90%
rename from plat/arm/board/diphda/common/diphda_helpers.S
rename to plat/arm/board/corstone1000/common/corstone1000_helpers.S
index c9d2a88..cbe27c3 100644
--- a/plat/arm/board/diphda/common/diphda_helpers.S
+++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,7 +29,7 @@
 	 * unsigned long plat_get_my_entrypoint (void);
 	 *
 	 * Main job of this routine is to distinguish between a cold and warm
-	 * boot. On diphda, this information can be queried from the power
+	 * boot. On corstone1000, this information can be queried from the power
 	 * controller. The Power Control SYS Status Register (PSYSR) indicates
 	 * the wake-up reason for the CPU.
 	 *
@@ -61,7 +61,7 @@
 	mrs	x0, mpidr_el1
 	mov_imm	x1, MPIDR_AFFINITY_MASK
 	and	x0, x0, x1
-	cmp	x0, #DIPHDA_PRIMARY_CPU
+	cmp	x0, #CORSTONE1000_PRIMARY_CPU
 	cset	w0, eq
 	ret
 endfunc plat_is_my_cpu_primary
diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
new file mode 100644
index 0000000..a96baae
--- /dev/null
+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/bl_common.h>
+
+#include <drivers/generic_delay_timer.h>
+#include <drivers/io/io_storage.h>
+#include <plat/common/platform.h>
+#include <plat/arm/common/arm_fconf_getter.h>
+#include <plat/arm/common/arm_fconf_io_storage.h>
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+
+/*
+ * Table of regions to map using the MMU.
+ * Replace or extend the below regions as required
+ */
+
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	ARM_MAP_NS_SHARED_RAM,
+	ARM_MAP_NS_DRAM1,
+	CORSTONE1000_MAP_DEVICE,
+	CORSTONE1000_EXTERNAL_FLASH,
+	{0}
+};
+
+static void set_fip_image_source(void)
+{
+	const struct plat_io_policy *policy;
+	/*
+	* metadata for firmware update is written at 0x0000 offset of the flash.
+	* PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted.
+	* As per firmware update spec, at a given point of time, only one bank is active.
+	* This means, TF-A should boot from the same bank as TF-M.
+	*/
+	volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG);
+	if (*boot_bank_flag > 1) {
+		VERBOSE("Boot_bank is set higher than possible values");
+	}
+
+	VERBOSE("Boot bank flag = %u.\n\r", *boot_bank_flag);
+
+	policy = FCONF_GET_PROPERTY(arm, io_policies, FIP_IMAGE_ID);
+
+	assert(policy != NULL);
+	assert(policy->image_spec != 0UL);
+
+	io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec;
+
+	if ((*boot_bank_flag) == 0) {
+		VERBOSE("Booting from bank 0: fip offset = 0x%lx\n\r",
+						PLAT_ARM_FIP_BASE_BANK0);
+		spec->offset = PLAT_ARM_FIP_BASE_BANK0;
+	} else {
+		VERBOSE("Booting from bank 1: fip offset = 0x%lx\n\r",
+						PLAT_ARM_FIP_BASE_BANK1);
+		spec->offset = PLAT_ARM_FIP_BASE_BANK1;
+	}
+}
+
+void bl2_platform_setup(void)
+{
+	arm_bl2_platform_setup();
+	/*
+	 * Identify the start address of the FIP by reading the boot
+	 * index flag from the flash.
+	 */
+	set_fip_image_source();
+}
+
+/* corstone1000 only has one always-on power domain and there
+ * is no power control present
+ */
+void __init plat_arm_pwrc_setup(void)
+{
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	/* Returning the Generic Timer Frequency */
+	return SYS_COUNTER_FREQ_IN_TICKS;
+}
+
+
+/*
+ * Helper function to initialize ARM interconnect driver.
+ */
+void plat_arm_interconnect_init(void)
+{
+}
+
+/*
+ * Helper function to place current master into coherency
+ */
+void plat_arm_interconnect_enter_coherency(void)
+{
+}
+
+/*
+ * Helper function to remove current master from coherency
+ */
+void plat_arm_interconnect_exit_coherency(void)
+{
+}
+
+/*
+ * This function is invoked during Mbed TLS library initialisation to get a heap
+ * The function simply returns the default allocated heap.
+ */
+
+#if TRUSTED_BOARD_BOOT
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+	assert(heap_addr != NULL);
+	assert(heap_size != NULL);
+
+	return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
new file mode 100644
index 0000000..98dea79
--- /dev/null
+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+/*******************************************************************************
+ * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
+ * platform layer will take care of registering the handlers with PSCI.
+ ******************************************************************************/
+
+static void __dead2 corstone1000_system_reset(void)
+{
+
+	uint32_t volatile * const watchdog_ctrl_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_CTRL_REG;
+	uint32_t volatile * const watchdog_val_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_VAL_REG;
+
+	*(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL;
+	*watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE;
+	while (1) {
+		 wfi();
+	 }
+}
+
+plat_psci_ops_t plat_arm_psci_pm_ops = {
+	.system_reset = corstone1000_system_reset,
+	.validate_ns_entrypoint = NULL
+};
+
+const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
+{
+	ops = &plat_arm_psci_pm_ops;
+	return ops;
+}
diff --git a/plat/arm/board/diphda/common/diphda_security.c b/plat/arm/board/corstone1000/common/corstone1000_security.c
similarity index 78%
rename from plat/arm/board/diphda/common/diphda_security.c
rename to plat/arm/board/corstone1000/common/corstone1000_security.c
index bf172af..c88201b 100644
--- a/plat/arm/board/diphda/common/diphda_security.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_security.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/arm/board/diphda/common/diphda_stack_protector.c b/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
similarity index 90%
rename from plat/arm/board/diphda/common/diphda_stack_protector.c
rename to plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
index 6228b63..393235e 100644
--- a/plat/arm/board/diphda/common/diphda_stack_protector.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/arm/board/diphda/common/diphda_topology.c b/plat/arm/board/corstone1000/common/corstone1000_topology.c
similarity index 72%
rename from plat/arm/board/diphda/common/diphda_topology.c
rename to plat/arm/board/corstone1000/common/corstone1000_topology.c
index 9dfd05d..5351896 100644
--- a/plat/arm/board/diphda/common/diphda_topology.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_topology.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,8 +7,8 @@
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 
-/* The diphda power domain tree descriptor */
-static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
+/* The corstone1000 power domain tree descriptor */
+static unsigned char corstone1000_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
 							+ 2];
 /*******************************************************************************
  * This function dynamically constructs the topology according to
@@ -22,13 +22,13 @@
 	 * The highest level is the system level. The next level is constituted
 	 * by clusters and then cores in clusters.
 	 */
-	diphda_power_domain_tree_desc[0] = 1;
-	diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
+	corstone1000_power_domain_tree_desc[0] = 1;
+	corstone1000_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
 
 	for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
-		diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
+		corstone1000_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
 
-	return diphda_power_domain_tree_desc;
+	return corstone1000_power_domain_tree_desc;
 }
 
 /******************************************************************************
diff --git a/plat/arm/board/diphda/common/diphda_trusted_boot.c b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
similarity index 91%
rename from plat/arm/board/diphda/common/diphda_trusted_boot.c
rename to plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
index ddb41fa..cec7332 100644
--- a/plat/arm/board/diphda/common/diphda_trusted_boot.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -38,7 +38,7 @@
  */
 int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
 {
-    *nv_ctr = DIPHDA_FW_NVCTR_VAL;
+    *nv_ctr = CORSTONE1000_FW_NVCTR_VAL;
     return 0;
 }
 
diff --git a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
similarity index 87%
rename from plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
rename to plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
index 536bdc3..8e49ab8 100644
--- a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
+++ b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
new file mode 100644
index 0000000..2523d72
--- /dev/null
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -0,0 +1,436 @@
+/*
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <common/tbbr/tbbr_img_def.h>
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/arm/common/smccc_def.h>
+#include <plat/common/common_def.h>
+#include <plat/arm/soc/common/soc_css_def.h>
+
+#define ARM_ROTPK_HEADER_LEN					19
+#define ARM_ROTPK_HASH_LEN					32
+
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define ARM_BL31_PLAT_PARAM_VAL					ULL(0x0f1e2d3c4b5a6978)
+
+/* PL011 UART related constants */
+#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ
+#undef V2M_IOFPGA_UART0_CLK_IN_HZ
+#endif
+
+#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ
+#undef V2M_IOFPGA_UART1_CLK_IN_HZ
+#endif
+
+#define V2M_IOFPGA_UART0_CLK_IN_HZ				50000000
+#define V2M_IOFPGA_UART1_CLK_IN_HZ				50000000
+
+/* Core/Cluster/Thread counts for corstone1000 */
+#define CORSTONE1000_CLUSTER_COUNT				U(1)
+#define CORSTONE1000_MAX_CPUS_PER_CLUSTER			U(4)
+#define CORSTONE1000_MAX_PE_PER_CPU				U(1)
+#define CORSTONE1000_PRIMARY_CPU				U(0)
+
+#define PLAT_ARM_CLUSTER_COUNT					CORSTONE1000_CLUSTER_COUNT
+
+#define PLATFORM_CORE_COUNT					(PLAT_ARM_CLUSTER_COUNT *      \
+								CORSTONE1000_MAX_CPUS_PER_CLUSTER *  \
+								CORSTONE1000_MAX_PE_PER_CPU)
+
+/* UART related constants */
+#define PLAT_ARM_BOOT_UART_BASE					0x1a510000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ				V2M_IOFPGA_UART0_CLK_IN_HZ
+#define PLAT_ARM_RUN_UART_BASE					0x1a520000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ				V2M_IOFPGA_UART1_CLK_IN_HZ
+#define ARM_CONSOLE_BAUDRATE					115200
+#define PLAT_ARM_CRASH_UART_BASE				PLAT_ARM_RUN_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ				PLAT_ARM_RUN_UART_CLK_IN_HZ
+
+/* Memory related constants */
+
+/* SRAM (CVM) memory layout
+ *
+ * <ARM_TRUSTED_SRAM_BASE>
+ *
+ *         partition size: sizeof(meminfo_t) = 16 bytes
+ *
+ *         content: memory info area used by the next BL
+ *
+ * <ARM_FW_CONFIG_BASE>
+ *
+ *         partition size: 4080 bytes
+ *
+ * <ARM_BL2_MEM_DESC_BASE>
+ *
+ *         partition size: 4 KB
+ *
+ *         content:
+ *
+ *             Area where BL2 copies the images descriptors
+ *
+ * <ARM_BL_RAM_BASE> = <BL32_BASE>
+ *
+ *         partition size: 688 KB
+ *
+ *         content:
+ *
+ *             BL32 (optee-os)
+ *
+ * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
+ *
+ *         partition size: 8 KB
+ *
+ *         content:
+ *
+ *             BL32 config (TOS_FW_CONFIG)
+ *
+ * <BL31_BASE>
+ *
+ *         partition size: 140 KB
+ *
+ *         content:
+ *
+ *             BL31
+ *
+ * <BL2_SIGNATURE_BASE>
+ *
+ *     partition size: 4 KB
+ *
+ *     content:
+ *
+ *         MCUBOOT data needed to verify TF-A BL2
+ *
+ * <BL2_BASE>
+ *
+ *     partition size: 176 KB
+ *
+ *         content:
+ *
+ *             BL2
+ *
+ * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
+ *
+ *         partition size: 512 KB
+ *
+ *         content:
+ *
+ *             BL33 (u-boot)
+ */
+
+/* DDR memory */
+#define ARM_DRAM1_BASE						UL(0x80000000)
+#define ARM_DRAM1_SIZE                 				(SZ_2G) /* 2GB*/
+#define ARM_DRAM1_END						(ARM_DRAM1_BASE +	\
+								ARM_DRAM1_SIZE - 1)
+
+/* DRAM1 and DRAM2 are the same for corstone1000 */
+#define ARM_DRAM2_BASE						ARM_DRAM1_BASE
+#define ARM_DRAM2_SIZE						ARM_DRAM1_SIZE
+#define ARM_DRAM2_END						ARM_DRAM1_END
+
+#define ARM_NS_DRAM1_BASE					ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE					ARM_DRAM1_SIZE
+#define ARM_NS_DRAM1_END					(ARM_NS_DRAM1_BASE +\
+								ARM_NS_DRAM1_SIZE - 1)
+
+/* The first 8 KB of Trusted SRAM are used as shared memory */
+#define ARM_TRUSTED_SRAM_BASE					UL(0x02000000)
+#define ARM_SHARED_RAM_SIZE					(SZ_8K)  /* 8 KB */
+#define ARM_SHARED_RAM_BASE					ARM_TRUSTED_SRAM_BASE
+
+/* The remaining Trusted SRAM is used to load the BL images */
+#define TOTAL_SRAM_SIZE						(SZ_4M) /* 4 MB */
+
+/* Last 512KB of CVM is allocated for shared RAM
+ * as an example openAMP */
+#define ARM_NS_SHARED_RAM_SIZE					(512 * SZ_1K)
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE				(TOTAL_SRAM_SIZE - \
+								ARM_NS_SHARED_RAM_SIZE - \
+								ARM_SHARED_RAM_SIZE)
+
+#define PLAT_ARM_MAX_BL2_SIZE					(180 * SZ_1K)  /* 180 KB */
+
+#define PLAT_ARM_MAX_BL31_SIZE					(140 * SZ_1K)  /* 140 KB */
+
+#define ARM_BL_RAM_BASE						(ARM_SHARED_RAM_BASE +  \
+								ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE						(PLAT_ARM_TRUSTED_SRAM_SIZE - \
+								ARM_SHARED_RAM_SIZE)
+
+#define BL2_SIGNATURE_SIZE					(SZ_4K)  /* 4 KB */
+
+#define BL2_SIGNATURE_BASE					(BL2_LIMIT - \
+								PLAT_ARM_MAX_BL2_SIZE)
+#define BL2_BASE						(BL2_LIMIT - \
+								PLAT_ARM_MAX_BL2_SIZE + \
+								BL2_SIGNATURE_SIZE)
+#define BL2_LIMIT						(ARM_BL_RAM_BASE + \
+								ARM_BL_RAM_SIZE)
+
+#define BL31_BASE						(BL2_SIGNATURE_BASE - \
+								PLAT_ARM_MAX_BL31_SIZE)
+#define BL31_LIMIT						BL2_SIGNATURE_BASE
+
+#define CORSTONE1000_TOS_FW_CONFIG_BASE				(BL31_BASE - \
+								CORSTONE1000_TOS_FW_CONFIG_SIZE)
+#define CORSTONE1000_TOS_FW_CONFIG_SIZE				(SZ_8K)  /* 8 KB */
+#define CORSTONE1000_TOS_FW_CONFIG_LIMIT			BL31_BASE
+
+#define BL32_BASE						ARM_BL_RAM_BASE
+#define PLAT_ARM_MAX_BL32_SIZE					(CORSTONE1000_TOS_FW_CONFIG_BASE - \
+								BL32_BASE)
+
+#define BL32_LIMIT						(BL32_BASE + \
+								PLAT_ARM_MAX_BL32_SIZE)
+
+/* SPD_spmd settings */
+
+#define PLAT_ARM_SPMC_BASE					BL32_BASE
+#define PLAT_ARM_SPMC_SIZE					PLAT_ARM_MAX_BL32_SIZE
+
+/* NS memory */
+
+/* The last 512KB of the SRAM is allocated as shared memory */
+#define ARM_NS_SHARED_RAM_BASE					(ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \
+								(PLAT_ARM_MAX_BL31_SIZE + \
+								PLAT_ARM_MAX_BL32_SIZE))
+
+#define BL33_BASE						ARM_DRAM1_BASE
+#define PLAT_ARM_MAX_BL33_SIZE					(12 * SZ_1M) /* 12 MB*/
+#define BL33_LIMIT						(ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
+
+/* end of the definition of SRAM memory layout */
+
+/* NOR Flash */
+
+#define PLAT_ARM_BOOT_BANK_FLAG					UL(0x08002000)
+#define PLAT_ARM_FIP_BASE_BANK0					UL(0x081EF000)
+#define PLAT_ARM_FIP_BASE_BANK1					UL(0x0916F000)
+#define PLAT_ARM_FIP_MAX_SIZE					UL(0x1ff000)  /* 1.996 MB */
+
+#define PLAT_ARM_NVM_BASE					V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE					(SZ_32M)  /* 32 MB */
+
+#define PLAT_ARM_FLASH_IMAGE_BASE				PLAT_ARM_FIP_BASE_BANK0
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE				PLAT_ARM_FIP_MAX_SIZE
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE					(U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+#define ARM_CACHE_WRITEBACK_SHIFT				6
+
+/*
+ * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
+ * FW_CONFIG is intended to host the device tree. Currently, This area is not
+ * used because corstone1000 platform doesn't use a device tree at TF-A level.
+ */
+#define ARM_FW_CONFIG_BASE					(ARM_SHARED_RAM_BASE \
+								+ sizeof(meminfo_t))
+#define ARM_FW_CONFIG_LIMIT					(ARM_SHARED_RAM_BASE \
+								+ (ARM_SHARED_RAM_SIZE >> 1))
+
+/*
+ * Boot parameters passed from BL2 to BL31/BL32 are stored here
+ */
+#define ARM_BL2_MEM_DESC_BASE					ARM_FW_CONFIG_LIMIT
+#define ARM_BL2_MEM_DESC_LIMIT					ARM_BL_RAM_BASE
+
+/*
+ * The max number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#define ARM_BL_REGIONS						3
+#define PLAT_ARM_MMAP_ENTRIES					8
+#define MAX_XLAT_TABLES						5
+#define MAX_MMAP_REGIONS					(PLAT_ARM_MMAP_ENTRIES + \
+								ARM_BL_REGIONS)
+#define MAX_IO_DEVICES						2
+#define MAX_IO_HANDLES						3
+#define MAX_IO_BLOCK_DEVICES					1
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE					0x1C010000
+#define PLAT_ARM_GICC_BASE					0x1C02F000
+
+/* MHUv2 Secure Channel receiver and sender */
+#define PLAT_SDK700_MHU0_SEND					0x1B800000
+#define PLAT_SDK700_MHU0_RECV					0x1B810000
+
+/* Timer/watchdog related constants */
+#define ARM_SYS_CNTCTL_BASE					UL(0x1a200000)
+#define ARM_SYS_CNTREAD_BASE					UL(0x1a210000)
+#define ARM_SYS_TIMCTL_BASE					UL(0x1a220000)
+
+#define SECURE_WATCHDOG_ADDR_CTRL_REG				0x1A320000
+#define SECURE_WATCHDOG_ADDR_VAL_REG      			0x1A320008
+#define SECURE_WATCHDOG_MASK_ENABLE       			0x01
+#define SECURE_WATCHDOG_COUNTDOWN_VAL     			0x1000
+
+#define SYS_COUNTER_FREQ_IN_TICKS				UL(50000000) /* 50MHz */
+
+#define CORSTONE1000_IRQ_TZ_WDOG				32
+#define CORSTONE1000_IRQ_SEC_SYS_TIMER				34
+
+#define PLAT_MAX_PWR_LVL					2
+/*
+ * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
+ * power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+#define ARM_PWR_LVL0						MPIDR_AFFLVL0
+#define ARM_PWR_LVL1						MPIDR_AFFLVL1
+#define ARM_PWR_LVL2						MPIDR_AFFLVL2
+
+/*
+ *  Macros for local power states in ARM platforms encoded by State-ID field
+ *  within the power-state parameter.
+ */
+/* Local power state for power domains in Run state. */
+#define ARM_LOCAL_STATE_RUN					U(0)
+/* Local power state for retention. Valid only for CPU power domains */
+#define ARM_LOCAL_STATE_RET					U(1)
+/* Local power state for OFF/power-down. Valid for CPU and cluster
+ * power domains
+ */
+#define ARM_LOCAL_STATE_OFF					U(2)
+
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE				ARM_TRUSTED_SRAM_BASE
+#define PLAT_ARM_NSTIMER_FRAME_ID				U(1)
+
+#define PLAT_ARM_NS_IMAGE_BASE					(ARM_NS_SHARED_RAM_BASE)
+
+#define PLAT_PHY_ADDR_SPACE_SIZE				(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE				(1ULL << 32)
+
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * ID will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE					1
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE					2
+
+#define PLATFORM_STACK_SIZE					UL(0x440)
+
+#define CORSTONE1000_EXTERNAL_FLASH				MAP_REGION_FLAT(		\
+								PLAT_ARM_NVM_BASE,		\
+								PLAT_ARM_NVM_SIZE,		\
+								MT_DEVICE | MT_RO | MT_SECURE)
+
+#define ARM_MAP_SHARED_RAM					MAP_REGION_FLAT(		\
+								ARM_SHARED_RAM_BASE,	\
+								ARM_SHARED_RAM_SIZE,	\
+								MT_MEMORY | MT_RW | MT_SECURE)
+
+#define ARM_MAP_NS_SHARED_RAM					MAP_REGION_FLAT(	\
+								ARM_NS_SHARED_RAM_BASE, \
+								ARM_NS_SHARED_RAM_SIZE, \
+								MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_NS_DRAM1					MAP_REGION_FLAT(	\
+								ARM_NS_DRAM1_BASE,	\
+								ARM_NS_DRAM1_SIZE,	\
+								MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_BL_RO						MAP_REGION_FLAT(	\
+								BL_CODE_BASE,		\
+								BL_CODE_END		\
+								- BL_CODE_BASE, \
+								MT_CODE | MT_SECURE),	\
+								MAP_REGION_FLAT(	\
+								BL_RO_DATA_BASE,	\
+								BL_RO_DATA_END	\
+								- BL_RO_DATA_BASE,	\
+								MT_RO_DATA | MT_SECURE)
+#if USE_COHERENT_MEM
+#define ARM_MAP_BL_COHERENT_RAM					MAP_REGION_FLAT(	\
+								BL_COHERENT_RAM_BASE,	\
+								BL_COHERENT_RAM_END	\
+								- BL_COHERENT_RAM_BASE, \
+								MT_DEVICE | MT_RW | MT_SECURE)
+#endif
+
+/*
+ * Map the region for the optional device tree configuration with read and
+ * write permissions
+ */
+#define ARM_MAP_BL_CONFIG_REGION				MAP_REGION_FLAT(	\
+								ARM_FW_CONFIG_BASE,	\
+								(ARM_FW_CONFIG_LIMIT-   \
+								ARM_FW_CONFIG_BASE),   \
+								MT_MEMORY | MT_RW | MT_SECURE)
+
+#define CORSTONE1000_DEVICE_BASE				(0x1A000000)
+#define CORSTONE1000_DEVICE_SIZE				(0x26000000)
+#define CORSTONE1000_MAP_DEVICE					MAP_REGION_FLAT(	\
+								CORSTONE1000_DEVICE_BASE,	\
+								CORSTONE1000_DEVICE_SIZE,	\
+								MT_DEVICE | MT_RW | MT_SECURE)
+
+#define ARM_IRQ_SEC_PHY_TIMER					29
+
+#define ARM_IRQ_SEC_SGI_0					8
+#define ARM_IRQ_SEC_SGI_1					9
+#define ARM_IRQ_SEC_SGI_2					10
+#define ARM_IRQ_SEC_SGI_3					11
+#define ARM_IRQ_SEC_SGI_4					12
+#define ARM_IRQ_SEC_SGI_5					13
+#define ARM_IRQ_SEC_SGI_6					14
+#define ARM_IRQ_SEC_SGI_7					15
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define ARM_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+		(grp), GIC_INTR_CFG_LEVEL), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+		GIC_INTR_CFG_EDGE)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_ARM_G1S_IRQ_PROPS(grp)	\
+	ARM_G1S_IRQ_PROPS(grp), \
+	INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
+		(grp), GIC_INTR_CFG_LEVEL), \
+	INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \
+		GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/diphda/include/plat_macros.S b/plat/arm/board/corstone1000/include/plat_macros.S
similarity index 84%
rename from plat/arm/board/diphda/include/plat_macros.S
rename to plat/arm/board/corstone1000/include/plat_macros.S
index 4de8f95..9334201 100644
--- a/plat/arm/board/diphda/include/plat_macros.S
+++ b/plat/arm/board/corstone1000/include/plat_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
new file mode 100644
index 0000000..d891691
--- /dev/null
+++ b/plat/arm/board/corstone1000/platform.mk
@@ -0,0 +1,83 @@
+#
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Making sure the corstone1000 platform type is specified
+ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
+	$(error TARGET_PLATFORM must be fpga or fvp)
+endif
+
+CORSTONE1000_CPU_LIBS	+=lib/cpus/aarch64/cortex_a35.S
+
+PLAT_INCLUDES		:=	-Iplat/arm/board/corstone1000/common/include	\
+				-Iplat/arm/board/corstone1000/include		\
+				-Iinclude/plat/arm/common			\
+				-Iinclude/plat/arm/css/common/aarch64
+
+
+CORSTONE1000_FW_NVCTR_VAL	:=	255
+TFW_NVCTR_VAL		:=	${CORSTONE1000_FW_NVCTR_VAL}
+NTFW_NVCTR_VAL		:=	${CORSTONE1000_FW_NVCTR_VAL}
+
+override NEED_BL1	:=	no
+
+override NEED_BL2	:=	yes
+FIP_BL2_ARGS := tb-fw
+
+override NEED_BL2U	:=	no
+override NEED_BL31	:=	yes
+NEED_BL32		:=	yes
+override NEED_BL33	:=	yes
+
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+
+CORSTONE1000_GIC_SOURCES	:=	${GICV2_SOURCES}			\
+				plat/common/plat_gicv2.c		\
+				plat/arm/common/arm_gicv2.c
+
+
+BL2_SOURCES		+=	plat/arm/board/corstone1000/common/corstone1000_security.c		\
+				plat/arm/board/corstone1000/common/corstone1000_err.c		\
+				plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c	\
+				lib/utils/mem_region.c					\
+				plat/arm/board/corstone1000/common/corstone1000_helpers.S		\
+				plat/arm/board/corstone1000/common/corstone1000_plat.c		\
+				plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \
+				${CORSTONE1000_CPU_LIBS}					\
+
+
+BL31_SOURCES	+=	drivers/cfi/v2m/v2m_flash.c				\
+			lib/utils/mem_region.c					\
+			plat/arm/board/corstone1000/common/corstone1000_helpers.S		\
+			plat/arm/board/corstone1000/common/corstone1000_topology.c		\
+			plat/arm/board/corstone1000/common/corstone1000_security.c		\
+			plat/arm/board/corstone1000/common/corstone1000_plat.c		\
+			plat/arm/board/corstone1000/common/corstone1000_pm.c		\
+			${CORSTONE1000_CPU_LIBS}					\
+			${CORSTONE1000_GIC_SOURCES}
+
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+	ifneq (${ENABLE_STACK_PROTECTOR},none)
+		CORSTONE1000_SECURITY_SOURCES := plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
+		BL2_SOURCES += ${CORSTONE1000_SECURITY_SOURCES}
+		BL31_SOURCES += ${CORSTONE1000_SECURITY_SOURCES}
+	endif
+endif
+
+FDT_SOURCES		+=	plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
+CORSTONE1000_TOS_FW_CONFIG	:=	${BUILD_PLAT}/fdts/corstone1000_spmc_manifest.dtb
+
+# Add the SPMC manifest to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE1000_TOS_FW_CONFIG},--tos-fw-config,${CORSTONE1000_TOS_FW_CONFIG}))
+
+# Adding TARGET_PLATFORM as a GCC define (-D option)
+$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
+
+# Adding CORSTONE1000_FW_NVCTR_VAL as a GCC define (-D option)
+$(eval $(call add_define,CORSTONE1000_FW_NVCTR_VAL))
+
+include plat/arm/common/arm_common.mk
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/diphda/common/diphda_plat.c b/plat/arm/board/diphda/common/diphda_plat.c
deleted file mode 100644
index 28d15a5..0000000
--- a/plat/arm/board/diphda/common/diphda_plat.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/bl_common.h>
-
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-
-/*
- * Table of regions to map using the MMU.
- * Replace or extend the below regions as required
- */
-
-const mmap_region_t plat_arm_mmap[] = {
-	ARM_MAP_SHARED_RAM,
-	ARM_MAP_NS_SHARED_RAM,
-	ARM_MAP_NS_DRAM1,
-	DIPHDA_MAP_DEVICE,
-	DIPHDA_EXTERNAL_FLASH,
-	{0}
-};
-
-/* diphda only has one always-on power domain and there
- * is no power control present
- */
-void __init plat_arm_pwrc_setup(void)
-{
-}
-
-unsigned int plat_get_syscnt_freq2(void)
-{
-	/* Returning the Generic Timer Frequency */
-	return SYS_COUNTER_FREQ_IN_TICKS;
-}
-
-
-/*
- * Helper function to initialize ARM interconnect driver.
- */
-void plat_arm_interconnect_init(void)
-{
-}
-
-/*
- * Helper function to place current master into coherency
- */
-void plat_arm_interconnect_enter_coherency(void)
-{
-}
-
-/*
- * Helper function to remove current master from coherency
- */
-void plat_arm_interconnect_exit_coherency(void)
-{
-}
-
-/*
- * This function is invoked during Mbed TLS library initialisation to get a heap
- * The function simply returns the default allocated heap.
- */
-
-#if TRUSTED_BOARD_BOOT
-int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
-{
-	assert(heap_addr != NULL);
-	assert(heap_size != NULL);
-
-	return arm_get_mbedtls_heap(heap_addr, heap_size);
-}
-#endif
diff --git a/plat/arm/board/diphda/common/diphda_pm.c b/plat/arm/board/diphda/common/diphda_pm.c
deleted file mode 100644
index 12b322e..0000000
--- a/plat/arm/board/diphda/common/diphda_pm.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/psci/psci.h>
-#include <plat/arm/common/plat_arm.h>
-
-/*******************************************************************************
- * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
- * platform layer will take care of registering the handlers with PSCI.
- ******************************************************************************/
-plat_psci_ops_t plat_arm_psci_pm_ops = {
-	/* dummy struct */
-	.validate_ns_entrypoint = NULL
-};
-
-const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
-{
-	return ops;
-}
diff --git a/plat/arm/board/diphda/common/include/platform_def.h b/plat/arm/board/diphda/common/include/platform_def.h
deleted file mode 100644
index 37fd71b..0000000
--- a/plat/arm/board/diphda/common/include/platform_def.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <common/tbbr/tbbr_img_def.h>
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <plat/arm/board/common/v2m_def.h>
-#include <plat/arm/common/arm_spm_def.h>
-#include <plat/arm/common/smccc_def.h>
-#include <plat/common/common_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
-
-#define ARM_ROTPK_HEADER_LEN			19
-#define ARM_ROTPK_HASH_LEN			32
-
-/* Special value used to verify platform parameters from BL2 to BL31 */
-#define ARM_BL31_PLAT_PARAM_VAL		ULL(0x0f1e2d3c4b5a6978)
-
-/* PL011 UART related constants */
-#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ
-#undef V2M_IOFPGA_UART0_CLK_IN_HZ
-#endif
-
-#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ
-#undef V2M_IOFPGA_UART1_CLK_IN_HZ
-#endif
-
-#define V2M_IOFPGA_UART0_CLK_IN_HZ		50000000
-#define V2M_IOFPGA_UART1_CLK_IN_HZ		50000000
-
-/* Core/Cluster/Thread counts for diphda */
-#define DIPHDA_CLUSTER_COUNT			U(1)
-#define DIPHDA_MAX_CPUS_PER_CLUSTER		U(4)
-#define DIPHDA_MAX_PE_PER_CPU			U(1)
-#define DIPHDA_PRIMARY_CPU			U(0)
-
-#define PLAT_ARM_CLUSTER_COUNT		DIPHDA_CLUSTER_COUNT
-
-#define PLATFORM_CORE_COUNT			(PLAT_ARM_CLUSTER_COUNT *      \
-						DIPHDA_MAX_CPUS_PER_CLUSTER *  \
-						DIPHDA_MAX_PE_PER_CPU)
-
-/* UART related constants */
-#define PLAT_ARM_BOOT_UART_BASE		0x1a510000
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ		V2M_IOFPGA_UART0_CLK_IN_HZ
-#define PLAT_ARM_RUN_UART_BASE		0x1a520000
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ		V2M_IOFPGA_UART1_CLK_IN_HZ
-#define ARM_CONSOLE_BAUDRATE			115200
-#define PLAT_ARM_CRASH_UART_BASE		PLAT_ARM_RUN_UART_BASE
-#define PLAT_ARM_CRASH_UART_CLK_IN_HZ		PLAT_ARM_RUN_UART_CLK_IN_HZ
-
-/* Memory related constants */
-
-/* SRAM (CVM) memory layout
- *
- * <ARM_TRUSTED_SRAM_BASE>
- *
- *         partition size: sizeof(meminfo_t) = 16 bytes
- *
- *         content: memory info area used by the next BL
- *
- * <ARM_FW_CONFIG_BASE>
- *
- *         partition size: 4080 bytes
- *
- * <ARM_BL2_MEM_DESC_BASE>
- *
- *         partition size: 4 KB
- *
- *         content:
- *
- *             Area where BL2 copies the images descriptors
- *
- * <ARM_BL_RAM_BASE> = <BL32_BASE>
- *
- *         partition size: 688 KB
- *
- *         content:
- *
- *             BL32 (optee-os)
- *
- * <DIPHDA_TOS_FW_CONFIG_BASE> = 0x20ae000
- *
- *         partition size: 8 KB
- *
- *         content:
- *
- *             BL32 config (TOS_FW_CONFIG)
- *
- * <BL31_BASE>
- *
- *         partition size: 140 KB
- *
- *         content:
- *
- *             BL31
- *
- * <BL2_SIGNATURE_BASE>
- *
- *     partition size: 4 KB
- *
- *     content:
- *
- *         MCUBOOT data needed to verify TF-A BL2
- *
- * <BL2_BASE>
- *
- *     partition size: 176 KB
- *
- *         content:
- *
- *             BL2
- *
- * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
- *
- *         partition size: 3 MB
- *
- *         content:
- *
- *             BL33 (u-boot)
- */
-
-/* DDR memory */
-#define ARM_DRAM1_BASE			UL(0x80000000)
-#define ARM_DRAM1_SIZE			UL(0x80000000)
-#define ARM_DRAM1_END				(ARM_DRAM1_BASE +	\
-						ARM_DRAM1_SIZE - 1)
-
-/* DRAM1 and DRAM2 are the same for diphda */
-#define ARM_DRAM2_BASE			ARM_DRAM1_BASE
-#define ARM_DRAM2_SIZE			ARM_DRAM1_SIZE
-#define ARM_DRAM2_END				ARM_DRAM1_END
-
-#define ARM_NS_DRAM1_BASE			ARM_DRAM1_BASE
-#define ARM_NS_DRAM1_SIZE			ARM_DRAM1_SIZE
-#define ARM_NS_DRAM1_END			(ARM_NS_DRAM1_BASE +	\
-						ARM_NS_DRAM1_SIZE - 1)
-
-/* The first 8 KB of Trusted SRAM are used as shared memory */
-#define ARM_TRUSTED_SRAM_BASE			UL(0x02000000)
-#define ARM_SHARED_RAM_SIZE			UL(0x00002000)  /* 8 KB */
-#define ARM_SHARED_RAM_BASE			ARM_TRUSTED_SRAM_BASE
-
-/* The remaining Trusted SRAM is used to load the BL images */
-
-#define PLAT_ARM_TRUSTED_SRAM_SIZE		UL(0x00100000)  /* 1 MB */
-
-#define PLAT_ARM_MAX_BL2_SIZE			UL(0x0002d000)  /* 180 KB */
-
-#define PLAT_ARM_MAX_BL31_SIZE		UL(0x00023000)  /* 140 KB */
-
-#define ARM_BL_RAM_BASE			(ARM_SHARED_RAM_BASE +	\
-						ARM_SHARED_RAM_SIZE)
-#define ARM_BL_RAM_SIZE			(PLAT_ARM_TRUSTED_SRAM_SIZE -	\
-						ARM_SHARED_RAM_SIZE)
-
-#define BL2_SIGNATURE_SIZE			UL(0x00001000)  /* 4 KB */
-#define BL2_SIGNATURE_BASE			(BL2_LIMIT - \
-						PLAT_ARM_MAX_BL2_SIZE)
-#define BL2_BASE				(BL2_LIMIT - \
-						PLAT_ARM_MAX_BL2_SIZE + \
-						BL2_SIGNATURE_SIZE)
-#define BL2_LIMIT				(ARM_BL_RAM_BASE + \
-						ARM_BL_RAM_SIZE)
-
-#define BL31_BASE				(BL2_SIGNATURE_BASE - \
-						PLAT_ARM_MAX_BL31_SIZE)
-#define BL31_LIMIT				BL2_SIGNATURE_BASE
-
-#define DIPHDA_TOS_FW_CONFIG_BASE		(BL31_BASE - \
-						DIPHDA_TOS_FW_CONFIG_SIZE)
-#define DIPHDA_TOS_FW_CONFIG_SIZE		UL(0x00002000)  /* 8 KB */
-#define DIPHDA_TOS_FW_CONFIG_LIMIT		BL31_BASE
-
-#define BL32_BASE				ARM_BL_RAM_BASE
-#define PLAT_ARM_MAX_BL32_SIZE		(DIPHDA_TOS_FW_CONFIG_BASE - \
-						BL32_BASE)     /* 688 KB */
-#define BL32_LIMIT				(BL32_BASE + \
-						PLAT_ARM_MAX_BL32_SIZE)
-
-/* SPD_spmd settings */
-
-#define PLAT_ARM_SPMC_BASE			BL32_BASE
-#define PLAT_ARM_SPMC_SIZE			PLAT_ARM_MAX_BL32_SIZE
-
-/* NS memory */
-
-/* The last 3 MB of the SRAM is allocated to the non secure area */
-#define ARM_NS_SHARED_RAM_BASE		(ARM_TRUSTED_SRAM_BASE + \
-						PLAT_ARM_TRUSTED_SRAM_SIZE)
-#define ARM_NS_SHARED_RAM_SIZE		UL(0x00300000)  /* 3 MB */
-
-/* end of the definition of SRAM memory layout */
-
-/* NOR Flash */
-
-#define PLAT_ARM_FIP_BASE			UL(0x08131000)
-#define PLAT_ARM_FIP_MAX_SIZE			UL(0x1ff000)  /* 1.996 MB */
-
-#define PLAT_ARM_NVM_BASE			V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE			UL(0x02000000)  /* 32 MB */
-
-#define PLAT_ARM_FLASH_IMAGE_BASE		PLAT_ARM_FIP_BASE
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE		PLAT_ARM_FIP_MAX_SIZE
-
-/*
- * Some data must be aligned on the biggest cache line size in the platform.
- * This is known only to the platform as it might have a combination of
- * integrated and external caches.
- */
-#define CACHE_WRITEBACK_GRANULE		(U(1) << ARM_CACHE_WRITEBACK_SHIFT)
-#define ARM_CACHE_WRITEBACK_SHIFT		6
-
-/*
- * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
- * FW_CONFIG is intended to host the device tree. Currently, This area is not
- * used because diphda platform doesn't use a device tree at TF-A level.
- */
-#define ARM_FW_CONFIG_BASE			(ARM_SHARED_RAM_BASE \
-						+ sizeof(meminfo_t))
-#define ARM_FW_CONFIG_LIMIT			(ARM_SHARED_RAM_BASE \
-						+ (ARM_SHARED_RAM_SIZE >> 1))
-
-/*
- * Boot parameters passed from BL2 to BL31/BL32 are stored here
- */
-#define ARM_BL2_MEM_DESC_BASE			ARM_FW_CONFIG_LIMIT
-#define ARM_BL2_MEM_DESC_LIMIT		ARM_BL_RAM_BASE
-
-/*
- * The max number of regions like RO(code), coherent and data required by
- * different BL stages which need to be mapped in the MMU.
- */
-#define ARM_BL_REGIONS			3
-#define PLAT_ARM_MMAP_ENTRIES			8
-#define MAX_XLAT_TABLES			5
-#define MAX_MMAP_REGIONS			(PLAT_ARM_MMAP_ENTRIES + \
-						ARM_BL_REGIONS)
-#define MAX_IO_DEVICES			2
-#define MAX_IO_HANDLES			3
-#define MAX_IO_BLOCK_DEVICES			1
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE			0x1C010000
-#define PLAT_ARM_GICC_BASE			0x1C02F000
-
-/* MHUv2 Secure Channel receiver and sender */
-#define PLAT_SDK700_MHU0_SEND			0x1B800000
-#define PLAT_SDK700_MHU0_RECV			0x1B810000
-
-/* Timer/watchdog related constants */
-#define ARM_SYS_CNTCTL_BASE			UL(0x1a200000)
-#define ARM_SYS_CNTREAD_BASE			UL(0x1a210000)
-#define ARM_SYS_TIMCTL_BASE			UL(0x1a220000)
-
-#define SYS_COUNTER_FREQ_IN_TICKS	UL(50000000) /* 50MHz */
-
-#define DIPHDA_IRQ_TZ_WDOG			32
-#define DIPHDA_IRQ_SEC_SYS_TIMER		34
-
-#define PLAT_MAX_PWR_LVL			2
-/*
- * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
- * power levels have a 1:1 mapping with the MPIDR affinity levels.
- */
-#define ARM_PWR_LVL0				MPIDR_AFFLVL0
-#define ARM_PWR_LVL1				MPIDR_AFFLVL1
-#define ARM_PWR_LVL2				MPIDR_AFFLVL2
-
-/*
- *  Macros for local power states in ARM platforms encoded by State-ID field
- *  within the power-state parameter.
- */
-/* Local power state for power domains in Run state. */
-#define ARM_LOCAL_STATE_RUN			U(0)
-/* Local power state for retention. Valid only for CPU power domains */
-#define ARM_LOCAL_STATE_RET			U(1)
-/* Local power state for OFF/power-down. Valid for CPU and cluster
- * power domains
- */
-#define ARM_LOCAL_STATE_OFF			U(2)
-
-#define PLAT_ARM_TRUSTED_MAILBOX_BASE		ARM_TRUSTED_SRAM_BASE
-#define PLAT_ARM_NSTIMER_FRAME_ID		U(1)
-
-#define PLAT_ARM_NS_IMAGE_BASE		(ARM_NS_SHARED_RAM_BASE)
-
-#define PLAT_PHY_ADDR_SPACE_SIZE		(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE		(1ULL << 32)
-
-/*
- * This macro defines the deepest retention state possible. A higher state
- * ID will represent an invalid or a power down state.
- */
-#define PLAT_MAX_RET_STATE			1
-
-/*
- * This macro defines the deepest power down states possible. Any state ID
- * higher than this is invalid.
- */
-#define PLAT_MAX_OFF_STATE			2
-
-#define PLATFORM_STACK_SIZE			UL(0x440)
-
-#define DIPHDA_EXTERNAL_FLASH			MAP_REGION_FLAT(	\
-						PLAT_ARM_NVM_BASE,	\
-						PLAT_ARM_NVM_SIZE,	\
-						MT_DEVICE | MT_RO | MT_SECURE)
-
-#define ARM_MAP_SHARED_RAM			MAP_REGION_FLAT(	\
-						ARM_SHARED_RAM_BASE,	\
-						ARM_SHARED_RAM_SIZE,	\
-						MT_MEMORY | MT_RW | MT_SECURE)
-
-#define ARM_MAP_NS_SHARED_RAM			MAP_REGION_FLAT(	\
-						ARM_NS_SHARED_RAM_BASE, \
-						ARM_NS_SHARED_RAM_SIZE, \
-						MT_MEMORY | MT_RW | MT_NS)
-
-#define ARM_MAP_NS_DRAM1			MAP_REGION_FLAT(	\
-						ARM_NS_DRAM1_BASE,	\
-						ARM_NS_DRAM1_SIZE,	\
-						MT_MEMORY | MT_RW | MT_NS)
-
-#define ARM_MAP_BL_RO				MAP_REGION_FLAT(	\
-						BL_CODE_BASE,		\
-						BL_CODE_END		\
-							- BL_CODE_BASE, \
-						MT_CODE | MT_SECURE),	\
-						MAP_REGION_FLAT(	\
-						BL_RO_DATA_BASE,	\
-						BL_RO_DATA_END	\
-						- BL_RO_DATA_BASE,	\
-						MT_RO_DATA | MT_SECURE)
-#if USE_COHERENT_MEM
-#define ARM_MAP_BL_COHERENT_RAM		MAP_REGION_FLAT(	\
-						BL_COHERENT_RAM_BASE,	\
-						BL_COHERENT_RAM_END	\
-						- BL_COHERENT_RAM_BASE, \
-						MT_DEVICE | MT_RW | MT_SECURE)
-#endif
-
-/*
- * Map the region for the optional device tree configuration with read and
- * write permissions
- */
-#define ARM_MAP_BL_CONFIG_REGION		MAP_REGION_FLAT(	\
-						ARM_FW_CONFIG_BASE,	\
-						(ARM_FW_CONFIG_LIMIT-   \
-						ARM_FW_CONFIG_BASE),   \
-						MT_MEMORY | MT_RW | MT_SECURE)
-
-#define DIPHDA_DEVICE_BASE			(0x1A000000)
-#define DIPHDA_DEVICE_SIZE			(0x26000000)
-#define DIPHDA_MAP_DEVICE			MAP_REGION_FLAT(	\
-						DIPHDA_DEVICE_BASE,	\
-						DIPHDA_DEVICE_SIZE,	\
-						MT_DEVICE | MT_RW | MT_SECURE)
-
-#define ARM_IRQ_SEC_PHY_TIMER			29
-
-#define ARM_IRQ_SEC_SGI_0			8
-#define ARM_IRQ_SEC_SGI_1			9
-#define ARM_IRQ_SEC_SGI_2			10
-#define ARM_IRQ_SEC_SGI_3			11
-#define ARM_IRQ_SEC_SGI_4			12
-#define ARM_IRQ_SEC_SGI_5			13
-#define ARM_IRQ_SEC_SGI_6			14
-#define ARM_IRQ_SEC_SGI_7			15
-
-/*
- * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define ARM_G1S_IRQ_PROPS(grp) \
-	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
-		(grp), GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,	\
-		(grp), GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,	\
-		(grp), GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,	\
-		(grp), GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,	\
-		(grp), GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,	\
-		(grp), GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,	\
-		(grp), GIC_INTR_CFG_EDGE)
-
-#define ARM_G0_IRQ_PROPS(grp) \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
-		GIC_INTR_CFG_EDGE)
-
-/*
- * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_ARM_G1S_IRQ_PROPS(grp)	\
-	ARM_G1S_IRQ_PROPS(grp), \
-	INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
-		(grp), GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \
-		GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
-
-#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/diphda/platform.mk b/plat/arm/board/diphda/platform.mk
deleted file mode 100644
index 8b89cee..0000000
--- a/plat/arm/board/diphda/platform.mk
+++ /dev/null
@@ -1,83 +0,0 @@
-#
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Making sure the diphda platform type is specified
-ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
-	$(error TARGET_PLATFORM must be fpga or fvp)
-endif
-
-DIPHDA_CPU_LIBS	+=lib/cpus/aarch64/cortex_a35.S
-
-PLAT_INCLUDES		:=	-Iplat/arm/board/diphda/common/include	\
-				-Iplat/arm/board/diphda/include		\
-				-Iinclude/plat/arm/common			\
-				-Iinclude/plat/arm/css/common/aarch64
-
-
-DIPHDA_FW_NVCTR_VAL	:=	255
-TFW_NVCTR_VAL		:=	${DIPHDA_FW_NVCTR_VAL}
-NTFW_NVCTR_VAL		:=	${DIPHDA_FW_NVCTR_VAL}
-
-override NEED_BL1	:=	no
-
-override NEED_BL2	:=	yes
-FIP_BL2_ARGS := tb-fw
-
-override NEED_BL2U	:=	no
-override NEED_BL31	:=	yes
-NEED_BL32		:=	yes
-override NEED_BL33	:=	yes
-
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-DIPHDA_GIC_SOURCES	:=	${GICV2_SOURCES}			\
-				plat/common/plat_gicv2.c		\
-				plat/arm/common/arm_gicv2.c
-
-
-BL2_SOURCES		+=	plat/arm/board/diphda/common/diphda_security.c		\
-				plat/arm/board/diphda/common/diphda_err.c		\
-				plat/arm/board/diphda/common/diphda_trusted_boot.c	\
-				lib/utils/mem_region.c					\
-				plat/arm/board/diphda/common/diphda_helpers.S		\
-				plat/arm/board/diphda/common/diphda_plat.c		\
-				plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \
-				${DIPHDA_CPU_LIBS}					\
-
-
-BL31_SOURCES	+=	drivers/cfi/v2m/v2m_flash.c				\
-			lib/utils/mem_region.c					\
-			plat/arm/board/diphda/common/diphda_helpers.S		\
-			plat/arm/board/diphda/common/diphda_topology.c		\
-			plat/arm/board/diphda/common/diphda_security.c		\
-			plat/arm/board/diphda/common/diphda_plat.c		\
-			plat/arm/board/diphda/common/diphda_pm.c		\
-			${DIPHDA_CPU_LIBS}					\
-			${DIPHDA_GIC_SOURCES}
-
-ifneq (${ENABLE_STACK_PROTECTOR},0)
-	ifneq (${ENABLE_STACK_PROTECTOR},none)
-		DIPHDA_SECURITY_SOURCES := plat/arm/board/diphda/common/diphda_stack_protector.c
-		BL2_SOURCES += ${DIPHDA_SECURITY_SOURCES}
-		BL31_SOURCES += ${DIPHDA_SECURITY_SOURCES}
-	endif
-endif
-
-FDT_SOURCES		+=	plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
-DIPHDA_TOS_FW_CONFIG	:=	${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb
-
-# Add the SPMC manifest to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG}))
-
-# Adding TARGET_PLATFORM as a GCC define (-D option)
-$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
-
-# Adding DIPHDA_FW_NVCTR_VAL as a GCC define (-D option)
-$(eval $(call add_define,DIPHDA_FW_NVCTR_VAL))
-
-include plat/arm/common/arm_common.mk
-include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
index af43065..1f38278 100644
--- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
@@ -28,6 +28,7 @@
 	{ SCP_BL2_IMAGE_ID, EVLOG_SCP_BL2_STRING, PCR_0 },
 	{ SOC_FW_CONFIG_ID, EVLOG_SOC_FW_CONFIG_STRING, PCR_0 },
 	{ TOS_FW_CONFIG_ID, EVLOG_TOS_FW_CONFIG_STRING, PCR_0 },
+	{ RMM_IMAGE_ID, EVLOG_RMM_STRING, PCR_0},
 
 	{ CRITICAL_DATA_ID, EVLOG_CRITICAL_DATA_STRING, PCR_1 },
 
diff --git a/plat/arm/board/fvp/fvp_security.c b/plat/arm/board/fvp/fvp_security.c
index 937f09f..573d92e 100644
--- a/plat/arm/board/fvp/fvp_security.c
+++ b/plat/arm/board/fvp/fvp_security.c
@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <plat/arm/common/arm_config.h>
 #include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
 
 /*
  * We assume that all security programming is done by the primary core.
@@ -21,6 +22,21 @@
 	 * configurations, those would be configured here.
 	 */
 
+	const arm_tzc_regions_info_t fvp_tzc_regions[] = {
+		ARM_TZC_REGIONS_DEF,
+#if !SPM_MM && !ENABLE_RME
+		{FVP_DRAM3_BASE, FVP_DRAM3_END,
+		 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
+		{FVP_DRAM4_BASE, FVP_DRAM4_END,
+		 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
+		{FVP_DRAM5_BASE, FVP_DRAM5_END,
+		 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
+		{FVP_DRAM6_BASE, FVP_DRAM6_END,
+		 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
+#endif
+		{0}
+	};
+
 	if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U)
-		arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
+		arm_tzc400_setup(PLAT_ARM_TZC_BASE, fvp_tzc_regions);
 }
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index fcc4a0a..77df610 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -63,8 +63,24 @@
 /* No SCP in FVP */
 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE	UL(0x0)
 
-#define PLAT_ARM_DRAM2_BASE		ULL(0x880000000)
-#define PLAT_ARM_DRAM2_SIZE		UL(0x80000000)
+#define PLAT_ARM_DRAM2_BASE	ULL(0x880000000) /* 36-bit range */
+#define PLAT_ARM_DRAM2_SIZE	ULL(0x780000000) /* 30 GB */
+
+#define FVP_DRAM3_BASE	ULL(0x8800000000) /* 40-bit range */
+#define FVP_DRAM3_SIZE	ULL(0x7800000000) /* 480 GB */
+#define FVP_DRAM3_END	(FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U)
+
+#define FVP_DRAM4_BASE	ULL(0x88000000000) /* 44-bit range */
+#define FVP_DRAM4_SIZE	ULL(0x78000000000) /* 7.5 TB */
+#define FVP_DRAM4_END	(FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U)
+
+#define FVP_DRAM5_BASE	ULL(0x880000000000) /* 48-bit range */
+#define FVP_DRAM5_SIZE	ULL(0x780000000000) /* 120 TB */
+#define FVP_DRAM5_END	(FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U)
+
+#define FVP_DRAM6_BASE	ULL(0x8800000000000) /* 52-bit range */
+#define FVP_DRAM6_SIZE	ULL(0x7800000000000) /* 1920 TB */
+#define FVP_DRAM6_END	(FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U)
 
 /* Range of kernel DTB load address */
 #define FVP_DTB_DRAM_MAP_START		ULL(0x82000000)
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index 753ba32..b882dc8 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -30,7 +30,8 @@
 
 PLAT_INCLUDES		+=	-I${RDN2_BASE}/include/
 
-SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_n2.S
+SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_n2.S \
+				lib/cpus/aarch64/neoverse_demeter.S
 
 PLAT_BL_COMMON_SOURCES	+=	${CSS_ENT_BASE}/sgi_plat_v2.c
 
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index c45e045..6d7aa2d 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -282,7 +282,7 @@
 ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
 BL2_SOURCES		+=	plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
 else
-ifneq (${PLAT}, diphda)
+ifneq (${PLAT}, corstone1000)
 BL2_SOURCES		+=	plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
 endif
 endif
diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h
index 0062b97..41467f7 100644
--- a/plat/arm/css/sgi/include/sgi_variant.h
+++ b/plat/arm/css/sgi/include/sgi_variant.h
@@ -23,6 +23,10 @@
 /* SID Version values for RD-N2 variants */
 #define RD_N2_CFG1_SID_VER_PART_NUM		0x07B6
 
+/* SID Version values for RD-Edmunds */
+#define RD_EDMUNDS_SID_VER_PART_NUM		0x07F2
+#define RD_EDMUNDS_CONFIG_ID			0x1
+
 /* Structure containing SGI platform variant information */
 typedef struct sgi_platform_info {
 	unsigned int platform_id;	/* Part Number of the platform */
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index 541689b..99f2f20 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -76,6 +76,7 @@
 	if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
 		sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
 		sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
+		sgi_plat_info.platform_id == RD_EDMUNDS_SID_VER_PART_NUM ||
 		sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
 		if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
 			panic();
diff --git a/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c b/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c
new file mode 100644
index 0000000..8b2fdd6
--- /dev/null
+++ b/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022, Linaro.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch_helpers.h>
+#if MEASURED_BOOT
+#include <common/desc_image_load.h>
+#endif
+#include <common/fdt_wrappers.h>
+#include <libfdt.h>
+
+#define DTB_PROP_HW_LOG_ADDR	"tpm_event_log_addr"
+#define DTB_PROP_HW_LOG_SIZE	"tpm_event_log_size"
+
+#if MEASURED_BOOT
+
+static int imx8m_event_log_fdt_init_overlay(uintptr_t dt_base, int dt_size)
+{
+	int ret;
+	int offset;
+	void *dtb = (void *)dt_base;
+
+	ret = fdt_create_empty_tree(dtb, dt_size);
+	if (ret < 0) {
+		ERROR("cannot create empty dtb tree: %s\n",
+		       fdt_strerror(ret));
+		return ret;
+	}
+
+	offset = fdt_path_offset(dtb, "/");
+	if (offset < 0) {
+		ERROR("cannot find root of the tree: %s\n",
+		       fdt_strerror(offset));
+		return offset;
+	}
+
+	offset = fdt_add_subnode(dtb, offset, "fragment@0");
+	if (offset < 0) {
+		ERROR("cannot add fragment node: %s\n",
+		       fdt_strerror(offset));
+		return offset;
+	}
+
+	ret = fdt_setprop_string(dtb, offset, "target-path", "/");
+	if (ret < 0) {
+		ERROR("cannot set target-path property: %s\n",
+		       fdt_strerror(ret));
+		return ret;
+	}
+
+	offset = fdt_add_subnode(dtb, offset, "__overlay__");
+	if (offset < 0) {
+		ERROR("cannot add __overlay__ node: %s\n",
+		       fdt_strerror(offset));
+		return ret;
+	}
+
+	offset = fdt_add_subnode(dtb, offset, "tpm_event_log");
+	if (offset < 0) {
+		ERROR("cannot add tpm_event_log node: %s\n",
+		       fdt_strerror(offset));
+		return offset;
+	}
+
+	ret = fdt_setprop_string(dtb, offset, "compatible",
+				 "arm,tpm_event_log");
+	if (ret < 0) {
+		ERROR("cannot set compatible property: %s\n",
+		       fdt_strerror(ret));
+		return ret;
+	}
+
+	ret = fdt_setprop_u64(dtb, offset, "tpm_event_log_addr", 0);
+	if (ret < 0) {
+		ERROR("cannot set tpm_event_log_addr property: %s\n",
+		       fdt_strerror(ret));
+		return ret;
+	}
+
+	ret = fdt_setprop_u32(dtb, offset, "tpm_event_log_size", 0);
+	if (ret < 0) {
+		ERROR("cannot set tpm_event_log_size property: %s\n",
+		       fdt_strerror(ret));
+		return ret;
+	}
+
+	return ret;
+}
+
+/*
+ * Write the Event Log address and its size in the DTB.
+ *
+ * This function is supposed to be called only by BL2.
+ *
+ * Returns:
+ *	0 = success
+ *    < 0 = error
+ */
+static int imx8m_set_event_log_info(uintptr_t config_base,
+				  uintptr_t log_addr, size_t log_size)
+{
+	/* As libfdt uses void *, we can't avoid this cast */
+	void *dtb = (void *)config_base;
+	const char *compatible_tpm = "arm,tpm_event_log";
+	uint64_t base = cpu_to_fdt64(log_addr);
+	uint32_t sz = cpu_to_fdt32(log_size);
+	int err, node;
+
+	err = fdt_open_into(dtb, dtb, PLAT_IMX8M_DTO_MAX_SIZE);
+	if (err < 0) {
+		ERROR("Invalid Device Tree at %p: error %d\n", dtb, err);
+		return err;
+	}
+
+	/*
+	 * Verify that the DTB is valid, before attempting to write to it,
+	 * and get the DTB root node.
+	 */
+
+	/* Check if the pointer to DT is correct */
+	err = fdt_check_header(dtb);
+	if (err < 0) {
+		WARN("Invalid DTB file passed\n");
+		return err;
+	}
+
+	/*
+	 * Find the TPM node in device tree.
+	 */
+	node = fdt_node_offset_by_compatible(dtb, -1, compatible_tpm);
+	if (node < 0) {
+		ERROR("The compatible property '%s' not%s", compatible_tpm,
+			" found in the config\n");
+		return node;
+	}
+
+	err = fdt_setprop(dtb, node, DTB_PROP_HW_LOG_ADDR, &base, 8);
+	if (err < 0) {
+		ERROR("Failed to add log addr err %d\n", err);
+		return err;
+	}
+
+	err = fdt_setprop(dtb, node, DTB_PROP_HW_LOG_SIZE, &sz, 4);
+	if (err < 0) {
+		ERROR("Failed to add log addr err %d\n", err);
+		return err;
+	}
+
+	err = fdt_pack(dtb);
+	if (err < 0) {
+		ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, err);
+		return err;
+	}
+
+	/*
+	 * Ensure that the info written to the DTB is visible
+	 * to other images.
+	 */
+	flush_dcache_range(config_base, fdt_totalsize(dtb));
+
+	return err;
+}
+
+/*
+ * This function writes the Event Log address and its size
+ * in the QEMU DTB.
+ *
+ * This function is supposed to be called only by BL2.
+ *
+ * Returns:
+ *	0 = success
+ *    < 0 = error
+ */
+int imx8m_set_nt_fw_info(size_t log_size, uintptr_t *ns_log_addr)
+{
+	uintptr_t ns_addr;
+	int err;
+
+	assert(ns_log_addr != NULL);
+
+	ns_addr = PLAT_IMX8M_DTO_BASE + PLAT_IMX8M_DTO_MAX_SIZE;
+
+	imx8m_event_log_fdt_init_overlay(PLAT_IMX8M_DTO_BASE,
+					  PLAT_IMX8M_DTO_MAX_SIZE);
+
+	/* Write the Event Log address and its size in the DTB */
+	err = imx8m_set_event_log_info(PLAT_IMX8M_DTO_BASE,
+					ns_addr, log_size);
+
+	/* Return Event Log address in Non-secure memory */
+	*ns_log_addr = (err < 0) ? 0UL : ns_addr;
+	return err;
+}
+
+#endif /* MEASURED_BOOT */
diff --git a/plat/imx/imx8m/imx8m_measured_boot.c b/plat/imx/imx8m/imx8m_measured_boot.c
new file mode 100644
index 0000000..ec61606
--- /dev/null
+++ b/plat/imx/imx8m/imx8m_measured_boot.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include "./include/imx8m_measured_boot.h"
+#include <drivers/measured_boot/event_log/event_log.h>
+#include <plat/arm/common/plat_arm.h>
+
+/* Event Log data */
+static uint8_t event_log[PLAT_IMX_EVENT_LOG_MAX_SIZE];
+
+/* FVP table with platform specific image IDs, names and PCRs */
+static const event_log_metadata_t imx8m_event_log_metadata[] = {
+	{ BL31_IMAGE_ID, EVLOG_BL31_STRING, PCR_0 },
+	{ BL32_IMAGE_ID, EVLOG_BL32_STRING, PCR_0 },
+	{ BL32_EXTRA1_IMAGE_ID, EVLOG_BL32_EXTRA1_STRING, PCR_0 },
+	{ BL32_EXTRA2_IMAGE_ID, EVLOG_BL32_EXTRA2_STRING, PCR_0 },
+	{ BL33_IMAGE_ID, EVLOG_BL33_STRING, PCR_0 },
+	{ EVLOG_INVALID_ID, NULL, (unsigned int)(-1) }	/* Terminator */
+};
+
+const event_log_metadata_t *plat_event_log_get_metadata(void)
+{
+	return imx8m_event_log_metadata;
+}
+
+int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
+{
+	/* Calculate image hash and record data in Event Log */
+	int err = event_log_measure_and_record(image_data->image_base,
+					       image_data->image_size,
+					       image_id);
+	if (err != 0) {
+		ERROR("%s%s image id %u (%i)\n",
+		      "Failed to ", "record", image_id, err);
+		return err;
+	}
+
+	return 0;
+}
+
+void bl2_plat_mboot_init(void)
+{
+	event_log_init(event_log, event_log + sizeof(event_log));
+	event_log_write_header();
+}
+
+void bl2_plat_mboot_finish(void)
+{
+	int rc = 0;
+
+	/* Event Log address in Non-Secure memory */
+	uintptr_t ns_log_addr;
+
+	/* Event Log filled size */
+	size_t event_log_cur_size;
+
+	event_log_cur_size = event_log_get_cur_size(event_log);
+
+	rc = imx8m_set_nt_fw_info(event_log_cur_size, &ns_log_addr);
+	if (rc != 0) {
+		ERROR("%s(): Unable to update %s_FW_CONFIG\n",
+		      __func__, "NT");
+		/*
+		 * It is a fatal error because on i.MX U-boot assumes that
+		 * a valid event log exists and will use it to record the
+		 * measurements into the fTPM.
+		 */
+		panic();
+	}
+
+	/* Copy Event Log to Non-secure memory */
+	(void)memcpy((void *)ns_log_addr, (const void *)event_log,
+		     event_log_cur_size);
+
+	/* Ensure that the Event Log is visible in Non-secure memory */
+	flush_dcache_range(ns_log_addr, event_log_cur_size);
+
+	dump_event_log((uint8_t *)event_log, event_log_cur_size);
+}
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index 6709678..300ef9e 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -152,3 +152,7 @@
 #define MAX_IO_HANDLES			3U
 #define MAX_IO_DEVICES			2U
 #define MAX_IO_BLOCK_DEVICES		1U
+
+#define PLAT_IMX8M_DTO_BASE		0x53000000
+#define PLAT_IMX8M_DTO_MAX_SIZE		0x1000
+#define PLAT_IMX_EVENT_LOG_MAX_SIZE	UL(0x400)
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index ac5a809..cd8de89 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -8,11 +8,14 @@
 				-Iplat/imx/imx8m/include		\
 				-Iplat/imx/imx8m/imx8mm/include		\
 				-Idrivers/imx/usdhc			\
-				-Iinclude/common/tbbr
+				-Iinclude/common/tbbr			\
+				-Iinclude/lib/libfdt
 
 # Include GICv3 driver files
 include drivers/arm/gic/v3/gicv3.mk
 
+include lib/libfdt/libfdt.mk
+
 IMX_GIC_SOURCES		:=	${GICV3_SOURCES}			\
 				plat/common/plat_gicv3.c		\
 				plat/common/plat_psci_common.c		\
@@ -43,6 +46,7 @@
 
 ifeq (${NEED_BL2},yes)
 BL2_SOURCES		+=	common/desc_image_load.c			\
+				common/fdt_wrappers.c				\
 				plat/imx/common/imx8_helpers.S			\
 				plat/imx/common/imx_uart_console.S		\
 				plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c	\
@@ -148,3 +152,14 @@
 
 EL3_EXCEPTION_HANDLING := 1
 SDEI_SUPPORT := 1
+
+ifeq (${MEASURED_BOOT},1)
+    MEASURED_BOOT_MK := drivers/measured_boot/event_log/event_log.mk
+    $(info Including ${MEASURED_BOOT_MK})
+    include ${MEASURED_BOOT_MK}
+
+BL2_SOURCES		+=	plat/imx/imx8m/imx8m_measured_boot.c	\
+				plat/imx/imx8m/imx8m_dyn_cfg_helpers.c	\
+				${EVENT_LOG_SOURCES}
+
+endif
diff --git a/plat/imx/imx8m/include/imx8m_measured_boot.h b/plat/imx/imx8m/include/imx8m_measured_boot.h
new file mode 100644
index 0000000..2ec0c46
--- /dev/null
+++ b/plat/imx/imx8m/include/imx8m_measured_boot.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2022, Linaro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX8M_MEASURED_BOOT_H
+#define IMX8M_MEASURED_BOOT_H
+
+#include <stdint.h>
+
+#include <arch_helpers.h>
+
+int imx8m_set_nt_fw_info(size_t log_size, uintptr_t *ns_log_addr);
+
+#endif /* IMX8M_MEASURED_BOOT_H */
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index 7b4d62f..6e67502 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -114,6 +114,9 @@
 	mmc_info.mmc_dev_type = MMC_IS_SD;
 	mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
 
+	/* Request ownership and direct access to QSPI */
+	mailbox_hps_qspi_enable();
+
 	switch (boot_source) {
 	case BOOT_SOURCE_SDMMC:
 		dw_mmc_init(&params, &mmc_info);
@@ -121,8 +124,6 @@
 		break;
 
 	case BOOT_SOURCE_QSPI:
-		mailbox_set_qspi_open();
-		mailbox_set_qspi_direct();
 		cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
 			QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
 			QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index 923c4f1..bc10dd8 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -69,6 +69,7 @@
 #define CMD_CASUAL			0
 #define CMD_URGENT			1
 
+#define MBOX_WORD_BYTE			4U
 #define MBOX_RESP_BUFFER_SIZE		16
 #define MBOX_CMD_BUFFER_SIZE		32
 
@@ -108,6 +109,9 @@
 
 /* Mailbox Macros */
 
+#define MBOX_ENTRY_TO_ADDR(_buf, ptr)	(MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \
+						+ MBOX_WORD_BYTE * (ptr))
+
 /* Mailbox interrupt flags and masks */
 #define MBOX_INT_FLAG_COE		0x1
 #define MBOX_INT_FLAG_RIE		0x2
@@ -139,23 +143,22 @@
 void mailbox_set_int(uint32_t interrupt_input);
 int mailbox_init(void);
 void mailbox_set_qspi_close(void);
-void mailbox_set_qspi_open(void);
-void mailbox_set_qspi_direct(void);
+void mailbox_hps_qspi_enable(void);
 
 int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args,
 			unsigned int len, uint32_t urgent, uint32_t *response,
-			unsigned int resp_len);
+			unsigned int *resp_len);
 int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args,
 			unsigned int len, unsigned int indirect);
 int mailbox_read_response(uint32_t *job_id, uint32_t *response,
-			unsigned int resp_len);
-unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
-			unsigned int resp_len);
+			unsigned int *resp_len);
+int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
+			unsigned int *resp_len);
 
 void mailbox_reset_cold(void);
 void mailbox_clear_response(void);
 
-int intel_mailbox_get_config_status(uint32_t cmd);
+int intel_mailbox_get_config_status(uint32_t cmd, bool init_done);
 int intel_mailbox_is_fpga_not_ready(void);
 
 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index aec94af..be900c9 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -59,9 +59,7 @@
 			}
 			mdelay(10U);
 		} else {
-			mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER +
-				      (*cin * 4), data);
-			(*cin)++;
+			mmio_write_32(MBOX_ENTRY_TO_ADDR(CMD, (*cin)++), data);
 			*cin %= MBOX_CMD_BUFFER_SIZE;
 			mmio_write_32(MBOX_OFFSET + MBOX_CIN, *cin);
 			break;
@@ -107,9 +105,7 @@
 		}
 	}
 
-	if (!is_doorbell_triggered) {
-		mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
-	}
+	mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
 
 	return MBOX_RET_OK;
 
@@ -131,7 +127,7 @@
 }
 
 int mailbox_read_response(unsigned int *job_id, uint32_t *response,
-				unsigned int resp_len)
+				unsigned int *resp_len)
 {
 	uint32_t rin;
 	uint32_t rout;
@@ -146,8 +142,7 @@
 	rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
 
 	if (rout != rin) {
-		resp_data = mmio_read_32(MBOX_OFFSET +
-				    MBOX_RESP_BUFFER + ((rout++)*4U));
+		resp_data = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++));
 
 		rout %= MBOX_RESP_BUFFER_SIZE;
 		mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
@@ -161,9 +156,9 @@
 
 		ret_resp_len = MBOX_RESP_LEN(resp_data);
 
-		if (ret_resp_len != 0U) {
-			ret_resp_len = iterate_resp(ret_resp_len, response,
-						    resp_len);
+		if (iterate_resp(ret_resp_len, response, resp_len)
+			!= MBOX_RET_OK) {
+			return MBOX_TIMEOUT;
 		}
 
 		if (MBOX_RESP_ERR(resp_data) > 0U) {
@@ -171,14 +166,14 @@
 			return -MBOX_RESP_ERR(resp_data);
 		}
 
-		return ret_resp_len;
+		return MBOX_RET_OK;
 	}
 	return MBOX_NO_RESPONSE;
 }
 
 
 int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response,
-				unsigned int resp_len)
+				unsigned int *resp_len)
 {
 	unsigned int timeout = 40U;
 	unsigned int sdm_loop = 255U;
@@ -221,8 +216,8 @@
 		rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
 
 		while (rout != rin) {
-			resp_data = mmio_read_32(MBOX_OFFSET +
-					    MBOX_RESP_BUFFER + ((rout++)*4U));
+			resp_data = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP,
+								(rout)++));
 
 			rout %= MBOX_RESP_BUFFER_SIZE;
 			mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
@@ -234,10 +229,9 @@
 
 			ret_resp_len = MBOX_RESP_LEN(resp_data);
 
-			if (ret_resp_len != 0U) {
-				ret_resp_len = iterate_resp(ret_resp_len,
-							    response,
-							    resp_len);
+			if (iterate_resp(ret_resp_len, response, resp_len)
+				!= MBOX_RET_OK) {
+				return MBOX_TIMEOUT;
 			}
 
 			if (MBOX_RESP_ERR(resp_data) > 0U) {
@@ -245,7 +239,7 @@
 				return -MBOX_RESP_ERR(resp_data);
 			}
 
-			return ret_resp_len;
+			return MBOX_RET_OK;
 		}
 
 	sdm_loop--;
@@ -255,8 +249,8 @@
 	return MBOX_TIMEOUT;
 }
 
-unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
-			unsigned int resp_len)
+int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
+			unsigned int *resp_len)
 {
 	unsigned int timeout, total_resp_len = 0U;
 	uint32_t resp_data;
@@ -266,17 +260,15 @@
 	while (mbox_resp_len > 0U) {
 		timeout = 100U;
 		mbox_resp_len--;
-		resp_data = mmio_read_32(MBOX_OFFSET +
-					MBOX_RESP_BUFFER +
-					(rout)*4U);
+		resp_data = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++));
 
-		if ((resp_buf != NULL) && (resp_len != 0U)) {
+		if ((resp_buf != NULL) && (resp_len != NULL)
+			&& (*resp_len != 0U)) {
 			*(resp_buf + total_resp_len)
 					= resp_data;
-			resp_len--;
+			*resp_len = *resp_len - 1;
 			total_resp_len++;
 		}
-		rout++;
 		rout %= MBOX_RESP_BUFFER_SIZE;
 		mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
 
@@ -295,7 +287,11 @@
 			return MBOX_TIMEOUT;
 		}
 	}
-	return total_resp_len;
+
+	if (resp_len)
+		*resp_len = total_resp_len;
+
+	return MBOX_RET_OK;
 }
 
 int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args,
@@ -320,7 +316,7 @@
 
 int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args,
 			unsigned int len, uint32_t urgent, uint32_t *response,
-			unsigned int resp_len)
+			unsigned int *resp_len)
 {
 	int status = 0;
 
@@ -366,20 +362,20 @@
 {
 	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
 	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, NULL, 0U,
-				CMD_CASUAL, NULL, 0U);
+				CMD_CASUAL, NULL, NULL);
 }
 
 void mailbox_set_qspi_direct(void)
 {
 	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, NULL, 0U,
-				CMD_CASUAL, NULL, 0U);
+				CMD_CASUAL, NULL, NULL);
 }
 
 void mailbox_set_qspi_close(void)
 {
 	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
 	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, NULL, 0U,
-				CMD_CASUAL, NULL, 0U);
+				CMD_CASUAL, NULL, NULL);
 }
 
 void mailbox_qspi_set_cs(uint32_t device_select)
@@ -390,21 +386,27 @@
 	cs_setting = (device_select << 28);
 	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
 	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting,
-				1U, CMD_CASUAL, NULL, 0U);
+				1U, CMD_CASUAL, NULL, NULL);
 }
 
+void mailbox_hps_qspi_enable(void)
+{
+	mailbox_set_qspi_open();
+	mailbox_set_qspi_direct();
+}
+
 void mailbox_reset_cold(void)
 {
 	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
 	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, NULL, 0U,
-				CMD_CASUAL, NULL, 0U);
+				CMD_CASUAL, NULL, NULL);
 }
 
 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, unsigned int resp_buf_len)
 {
 	return mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_SUBPARTITION_TABLE,
 				NULL, 0U, CMD_CASUAL, resp_buf,
-				resp_buf_len);
+				&resp_buf_len);
 }
 
 struct rsu_status_info {
@@ -426,7 +428,7 @@
 
 	ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0U,
 				CMD_CASUAL, resp_buf,
-				resp_buf_len);
+				&resp_buf_len);
 
 	if (ret < 0) {
 		return ret;
@@ -445,14 +447,14 @@
 {
 	return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE,
 				flash_offset, 2U,
-				CMD_CASUAL, NULL, 0U);
+				CMD_CASUAL, NULL, NULL);
 }
 
 int mailbox_hps_stage_notify(uint32_t execution_stage)
 {
 	return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY,
 				&execution_stage, 1U, CMD_CASUAL,
-				NULL, 0U);
+				NULL, NULL);
 }
 
 int mailbox_init(void)
@@ -465,7 +467,7 @@
 	mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
 
 	status = mailbox_send_cmd(0U, MBOX_CMD_RESTART, NULL, 0U,
-					CMD_URGENT, NULL, 0U);
+					CMD_URGENT, NULL, NULL);
 
 	if (status != 0) {
 		return status;
@@ -477,13 +479,14 @@
 	return MBOX_RET_OK;
 }
 
-int intel_mailbox_get_config_status(uint32_t cmd)
+int intel_mailbox_get_config_status(uint32_t cmd, bool init_done)
 {
 	int status;
 	uint32_t res, response[6];
+	unsigned int resp_len = ARRAY_SIZE(response);
 
 	status = mailbox_send_cmd(MBOX_JOB_ID, cmd, NULL, 0U, CMD_CASUAL,
-				response, ARRAY_SIZE(response));
+				response, &resp_len);
 
 	if (status < 0) {
 		return status;
@@ -504,20 +507,22 @@
 		return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
 	}
 
-	if ((res & SOFTFUNC_STATUS_CONF_DONE) != 0U &&
-		(res & SOFTFUNC_STATUS_INIT_DONE) != 0U) {
-		return MBOX_RET_OK;
-	}
+	if ((res & SOFTFUNC_STATUS_CONF_DONE) == 0U)
+		return MBOX_CFGSTAT_STATE_CONFIG;
 
-	return MBOX_CFGSTAT_STATE_CONFIG;
+	if (init_done && (res & SOFTFUNC_STATUS_INIT_DONE) == 0U)
+		return MBOX_CFGSTAT_STATE_CONFIG;
+
+	return MBOX_RET_OK;
 }
 
 int intel_mailbox_is_fpga_not_ready(void)
 {
-	int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
+	int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true);
 
 	if ((ret != MBOX_RET_OK) && (ret != MBOX_CFGSTAT_STATE_CONFIG)) {
-		ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
+		ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
+							false);
 	}
 
 	return ret;
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 86a4455..d53e8de 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -83,9 +83,9 @@
 	uint32_t ret;
 
 	if (query_type == 1)
-		ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
+		ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false);
 	else
-		ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
+		ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true);
 
 	if (ret) {
 		if (ret == MBOX_CFGSTAT_STATE_CONFIG)
@@ -128,16 +128,16 @@
 static int intel_fpga_config_completed_write(uint32_t *completed_addr,
 					uint32_t *count, uint32_t *job_id)
 {
-	uint32_t status = INTEL_SIP_SMC_STATUS_OK;
-	*count = 0;
-	int resp_len = 0;
 	uint32_t resp[5];
+	unsigned int resp_len = ARRAY_SIZE(resp);
+	int status = INTEL_SIP_SMC_STATUS_OK;
 	int all_completed = 1;
+	*count = 0;
 
 	while (*count < 3) {
 
-		resp_len = mailbox_read_response(job_id,
-				resp, ARRAY_SIZE(resp));
+		status = mailbox_read_response(job_id,
+				resp, &resp_len);
 
 		if (resp_len < 0)
 			break;
@@ -183,17 +183,21 @@
 
 static int intel_fpga_config_start(uint32_t config_type)
 {
+	uint32_t argument = 0x1;
 	uint32_t response[3];
 	int status = 0;
+	unsigned int size = 0;
+	unsigned int resp_len = ARRAY_SIZE(response);
 
 	is_partial_reconfig = config_type;
 
 	mailbox_clear_response();
 
-	mailbox_send_cmd(1U, MBOX_CMD_CANCEL, NULL, 0U, CMD_CASUAL, NULL, 0U);
+	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
+			CMD_CASUAL, NULL, NULL);
 
-	status = mailbox_send_cmd(1U, MBOX_RECONFIG, NULL, 0U, CMD_CASUAL,
-			response, ARRAY_SIZE(response));
+	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
+			CMD_CASUAL, response, &resp_len);
 
 	if (status < 0)
 		return status;
@@ -234,6 +238,9 @@
 
 bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
 {
+	if (!addr && !size) {
+		return true;
+	}
 	if (size > (UINT64_MAX - addr))
 		return false;
 	if (addr < BL31_LIMIT)
@@ -341,7 +348,7 @@
 {
 	if (!intel_secure_reg_read(reg_addr, retval)) {
 		*retval &= ~mask;
-		*retval |= val;
+		*retval |= val & mask;
 		return intel_secure_reg_write(reg_addr, *retval, retval);
 	}
 
@@ -384,10 +391,11 @@
 }
 
 /* Mailbox services */
-static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, uint32_t len,
-				    uint32_t urgent, uint32_t *response,
-				    uint32_t resp_len, int *mbox_status,
-				    int *len_in_resp)
+static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
+				unsigned int len,
+				uint32_t urgent, uint32_t *response,
+				unsigned int resp_len, int *mbox_status,
+				unsigned int *len_in_resp)
 {
 	*len_in_resp = 0;
 	*mbox_status = 0;
@@ -396,7 +404,7 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 
 	int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
-				      response, resp_len);
+				      response, &resp_len);
 
 	if (status < 0) {
 		*mbox_status = -status;
@@ -404,7 +412,7 @@
 	}
 
 	*mbox_status = 0;
-	*len_in_resp = status;
+	*len_in_resp = resp_len;
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
@@ -425,9 +433,9 @@
 	uint32_t status = INTEL_SIP_SMC_STATUS_OK;
 	uint32_t completed_addr[3];
 	uint64_t rsu_respbuf[9];
+	int mbox_status;
+	unsigned int len_in_resp;
 	u_register_t x5, x6;
-	int mbox_status, len_in_resp;
-
 
 	switch (smc_fid) {
 	case SIP_SVC_UID:
@@ -525,7 +533,7 @@
 		status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4,
 					     (uint32_t *)x5, x6, &mbox_status,
 					     &len_in_resp);
-		SMC_RET4(handle, status, mbox_status, x5, len_in_resp);
+		SMC_RET3(handle, status, mbox_status, len_in_resp);
 
 	default:
 		return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 6f7dabd..a8026ea 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -110,6 +110,9 @@
 	mmc_info.mmc_dev_type = MMC_IS_SD;
 	mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
 
+	/* Request ownership and direct access to QSPI */
+	mailbox_hps_qspi_enable();
+
 	switch (boot_source) {
 	case BOOT_SOURCE_SDMMC:
 		dw_mmc_init(&params, &mmc_info);
@@ -117,8 +120,6 @@
 		break;
 
 	case BOOT_SOURCE_QSPI:
-		mailbox_set_qspi_open();
-		mailbox_set_qspi_direct();
 		cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
 			QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
 			QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
diff --git a/plat/marvell/armada/a3k/common/dram_win.c b/plat/marvell/armada/a3k/common/dram_win.c
index e89f295..9d7b3a9 100644
--- a/plat/marvell/armada/a3k/common/dram_win.c
+++ b/plat/marvell/armada/a3k/common/dram_win.c
@@ -106,7 +106,9 @@
 	 *    to configure it again here;
 	 *
 	 *	0xFFFFFFFF ---> +-----------------------+
-	 *			|	 Boot ROM	| 64 KB
+	 *			|	 Boot ROM	| 1 MB
+	 *			| AP Boot ROM - 16 KB:  |
+	 *			| 0xFFFF0000-0xFFFF4000 |
 	 *	0xFFF00000 ---> +-----------------------+
 	 *			:			:
 	 *	0xFE010000 ---> +-----------------------+
diff --git a/plat/nxp/soc-ls1046a/aarch64/ls1046a.S b/plat/nxp/soc-ls1046a/aarch64/ls1046a.S
new file mode 100644
index 0000000..daa0542
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/aarch64/ls1046a.S
@@ -0,0 +1,937 @@
+/*
+ * Copyright 2020-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <asm_macros.S>
+#include <dcfg_lsch2.h>
+#include <nxp_timer.h>
+#include <plat_gic.h>
+#include <scfg.h>
+
+#include <bl31_data.h>
+#include <plat_psci.h>
+#include <platform_def.h>
+
+#define DAIF_DATA		AUX_01_DATA
+#define TIMER_CNTRL_DATA	AUX_02_DATA
+
+.global soc_init_lowlevel
+.global soc_init_percpu
+.global _soc_core_release
+.global _soc_core_restart
+.global _soc_ck_disabled
+.global _soc_sys_reset
+.global _soc_sys_off
+.global _soc_set_start_addr
+.global _getGICC_BaseAddr
+.global _getGICD_BaseAddr
+.global _soc_core_prep_off
+.global _soc_core_entr_off
+.global _soc_core_exit_off
+.global _soc_core_prep_stdby
+.global _soc_core_entr_stdby
+.global _soc_core_exit_stdby
+.global _soc_core_prep_pwrdn
+.global _soc_core_entr_pwrdn
+.global _soc_core_exit_pwrdn
+.global _soc_clstr_prep_stdby
+.global _soc_clstr_exit_stdby
+.global _soc_clstr_prep_pwrdn
+.global _soc_clstr_exit_pwrdn
+.global _soc_sys_prep_stdby
+.global _soc_sys_exit_stdby
+.global _soc_sys_prep_pwrdn
+.global _soc_sys_pwrdn_wfi
+.global _soc_sys_exit_pwrdn
+
+
+/* This function initialize the soc
+ * in: void
+ * out: void
+ */
+func soc_init_lowlevel
+    ret
+endfunc soc_init_lowlevel
+
+
+/* void soc_init_percpu(void)
+ * this function performs any soc-specific initialization that is needed on
+ * a per-core basis
+ * in:  none
+ * out: none
+ * uses x0, x1, x2, x3
+ */
+func soc_init_percpu
+	mov	x3, x30
+
+	bl	plat_my_core_mask
+	mov	x2, x0
+
+	/* see if this core is marked for prefetch disable */
+	mov	x0, #PREFETCH_DIS_OFFSET
+	bl	_get_global_data  /* 0-1 */
+	tst	x0, x2
+	b.eq	1f
+	bl	_disable_ldstr_pfetch_A72  /* 0 */
+1:
+	mov	x30, x3
+	ret
+endfunc soc_init_percpu
+
+/* part of CPU_ON
+ * this function releases a secondary core from reset
+ * in:   x0 = core_mask_lsb
+ * out:  none
+ * uses: x0, x1, x2, x3
+ */
+func _soc_core_release
+
+#if (TEST_BL31)
+	rbit	w2, w0
+	/* x2 = core mask msb */
+#else
+	mov	x2, x0
+#endif
+	/* write COREBCR */
+	mov	x1, #NXP_SCFG_ADDR
+	rev	w3, w2
+	str	w3, [x1, #SCFG_COREBCR_OFFSET]
+	isb
+
+	/* read-modify-write BRR */
+	mov	x1, #NXP_DCFG_ADDR
+	ldr	w2, [x1, #DCFG_BRR_OFFSET]
+	rev	w3, w2
+	orr	w3, w3, w0
+	rev	w2, w3
+	str	w2, [x1, #DCFG_BRR_OFFSET]
+	isb
+
+	/* send event */
+	sev
+	isb
+	ret
+endfunc _soc_core_release
+
+
+/* part of CPU_ON
+ * this function restarts a core shutdown via _soc_core_entr_off
+ * in:  x0 = core mask lsb (of the target cpu)
+ * out: x0 == 0, on success
+ *      x0 != 0, on failure
+ * uses x0, x1, x2, x3, x4, x5
+ */
+func _soc_core_restart
+	mov	x5, x30
+	mov	x3, x0
+
+	/*
+	 * unset ph20 request in RCPM_PCPH20CLEARR
+	 * this is an lsb-0 register
+	 */
+	ldr	x1, =NXP_RCPM_ADDR
+	rev	w2, w3
+	str	w2, [x1, #RCPM_PCPH20CLRR_OFFSET]
+	dsb	sy
+	isb
+
+	bl	_getGICD_BaseAddr
+	mov	x4, x0
+
+	/* enable forwarding of group 0 interrupts by setting GICD_CTLR[0] = 1 */
+	ldr	w1, [x4, #GICD_CTLR_OFFSET]
+	orr	w1, w1, #GICD_CTLR_EN_GRP0
+	str	w1, [x4, #GICD_CTLR_OFFSET]
+	dsb	sy
+	isb
+
+
+	/*
+	 * fire SGI by writing to GICD_SGIR the following values:
+	 * [25:24] = 0x0 (forward interrupt to the CPU interfaces
+	 *           specified in CPUTargetList field)
+	 * [23:16] = core mask lsb[7:0] (forward interrupt to target cpu)
+	 * [15]    = 0 (forward SGI only if it is configured as group 0 interrupt)
+	 * [3:0]   = 0xF (interrupt ID = 15)
+	 */
+	lsl	w1, w3, #16
+	orr	w1, w1, #0xF
+	str	w1, [x4, #GICD_SGIR_OFFSET]
+	dsb	sy
+	isb
+
+	/* load '0' on success */
+	mov	x0, xzr
+
+	mov	x30, x5
+	ret
+endfunc _soc_core_restart
+
+/*
+ * This function determines if a core is disabled via COREDISR
+ * in:  w0  = core_mask_lsb
+ * out: w0  = 0, core not disabled
+ *      w0 != 0, core disabled
+ * uses x0, x1, x2
+ */
+func _soc_ck_disabled
+	/* get base addr of dcfg block */
+	mov	x1, #NXP_DCFG_ADDR
+
+	/* read COREDISR */
+	ldr	w1, [x1, #DCFG_COREDISR_OFFSET]
+	rev	w2, w1
+
+	/* test core bit */
+	and	w0, w2, w0
+	ret
+endfunc _soc_ck_disabled
+
+/*
+ *This function resets the system via SoC-specific methods
+ * in:  none
+ * out: none
+ * uses x0, x1, x2, x3
+ */
+func _soc_sys_reset
+	ldr	x2, =NXP_DCFG_ADDR
+
+	/* make sure the mask is cleared in the reset request mask register */
+	mov	w1, wzr
+	str	w1, [x2, #DCFG_RSTRQMR1_OFFSET]
+
+	/* set the reset request */
+	ldr	w1, =RSTCR_RESET_REQ
+	ldr	x3, =DCFG_RSTCR_OFFSET
+	rev	w0, w1
+	str	w0, [x2, x3]
+
+	/*
+	 * just in case this address range is mapped as cacheable,
+	 * flush the write out of the dcaches
+	 */
+	add	x3, x2, x3
+	dc	cvac, x3
+	dsb	st
+	isb
+
+	/* Note: this function does not return */
+1:
+	wfi
+	b	1b
+endfunc _soc_sys_reset
+
+/*
+ * Part of SYSTEM_OFF
+ * this function turns off the SoC clocks
+ * Note: this function is not intended to return, and the only allowable
+ *       recovery is POR
+ * in:  none
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5, x6, x7, x8, x9
+ */
+func _soc_sys_off
+
+	/* mask interrupts at the core */
+	mrs	x1, DAIF
+	mov	x0, #DAIF_SET_MASK
+	orr	x0, x1, x0
+	msr	DAIF, x0
+
+	/* disable icache, dcache, mmu @ EL1 */
+	mov	x1, #SCTLR_I_C_M_MASK
+	mrs	x0, sctlr_el1
+	bic	x0, x0, x1
+	msr	sctlr_el1, x0
+
+	/* disable dcache for EL3 */
+	mrs	x1, SCTLR_EL3
+	bic	x1, x1, #SCTLR_C_MASK
+	/* make sure icache is enabled */
+	orr	x1, x1, #SCTLR_I_MASK
+	msr	SCTLR_EL3, x1
+	isb
+
+	/* Enable dynamic retention ctrl (CPUECTLR[2:0]) and SMP (CPUECTLR[6]) */
+	mrs	x0, CORTEX_A72_ECTLR_EL1
+	orr	x0, x0, #CPUECTLR_TIMER_8TICKS
+	orr	x0, x0, #CPUECTLR_SMPEN_EN
+	msr	CORTEX_A72_ECTLR_EL1, x0
+
+	/* set WFIL2EN in SCFG_CLUSTERPMCR */
+	ldr	x0, =SCFG_COREPMCR_OFFSET
+	ldr	x1, =COREPMCR_WFIL2
+	bl	write_reg_scfg
+
+	/* request LPM20 */
+	mov	x0, #RCPM_POWMGTCSR_OFFSET
+	bl	read_reg_rcpm
+	orr	x1, x0, #RCPM_POWMGTCSR_LPM20_REQ
+	mov	x0, #RCPM_POWMGTCSR_OFFSET
+	bl	write_reg_rcpm
+
+	dsb  sy
+	isb
+1:
+	wfi
+	b	1b
+endfunc _soc_sys_off
+
+/*
+ * Write a register in the RCPM block
+ * in:  x0 = offset
+ * in:  w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+func write_reg_rcpm
+	ldr	x2, =NXP_RCPM_ADDR
+	/* swap for BE */
+	rev	w3, w1
+	str	w3, [x2, x0]
+	ret
+endfunc write_reg_rcpm
+
+/*
+ * Read a register in the RCPM block
+ * in:  x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+func read_reg_rcpm
+	ldr	x2, =NXP_RCPM_ADDR
+	ldr	w1, [x2, x0]
+	/* swap for BE */
+	rev	w0, w1
+	ret
+endfunc read_reg_rcpm
+
+/*
+ * Write a register in the SCFG block
+ * in:  x0 = offset
+ * in:  w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+func write_reg_scfg
+	mov	x2, #NXP_SCFG_ADDR
+	/* swap for BE */
+	rev	w3, w1
+	str	w3, [x2, x0]
+	ret
+endfunc write_reg_scfg
+
+/*
+ * Read a register in the SCFG block
+ * in:  x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+func read_reg_scfg
+	mov	x2, #NXP_SCFG_ADDR
+	ldr	w1, [x2, x0]
+	/* swap for BE */
+	rev	w0, w1
+	ret
+endfunc read_reg_scfg
+
+/*
+ * Part of CPU_OFF
+ * this function programs SoC & GIC registers in preparation for shutting down
+ * the core
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5, x6, x7
+ */
+func _soc_core_prep_off
+	mov	x7, x30
+	mov	x6, x0
+
+	/* Set retention control in CPUECTLR make sure smpen bit is set */
+	mrs	x4, CORTEX_A72_ECTLR_EL1
+	bic	x4, x4, #CPUECTLR_RET_MASK
+	orr	x4, x4, #CPUECTLR_TIMER_8TICKS
+	orr	x4, x4, #CPUECTLR_SMPEN_EN
+	msr	CORTEX_A72_ECTLR_EL1, x4
+
+	/* save timer control current value */
+	mov	x5, #NXP_TIMER_ADDR
+	ldr	w4, [x5, #SYS_COUNTER_CNTCR_OFFSET]
+	mov	w2, w4
+	mov	x0, x6
+	mov	x1, #TIMER_CNTRL_DATA
+	bl	_setCoreData
+
+	/* enable the timer */
+	orr	w4, w4, #CNTCR_EN_MASK
+	str	w4, [x5, #SYS_COUNTER_CNTCR_OFFSET]
+
+	bl	_getGICC_BaseAddr
+	mov	x5, x0
+
+	/* disable signaling of ints */
+	ldr	w3, [x5, #GICC_CTLR_OFFSET]
+	bic	w3, w3, #GICC_CTLR_EN_GRP0
+	bic	w3, w3, #GICC_CTLR_EN_GRP1
+	str	w3, [x5, #GICC_CTLR_OFFSET]
+	dsb	sy
+	isb
+
+
+	/*
+	 * set retention control in SCFG_RETREQCR
+	 * Note: this register is msb 0
+	 */
+	ldr	x4, =SCFG_RETREQCR_OFFSET
+	mov	x0, x4
+	bl	read_reg_scfg
+	rbit	w1, w6
+	orr	w1, w0, w1
+	mov	x0, x4
+	bl	write_reg_scfg
+
+	/* set the priority filter */
+	ldr	w2, [x5, #GICC_PMR_OFFSET]
+	orr	w2, w2, #GICC_PMR_FILTER
+	str	w2, [x5, #GICC_PMR_OFFSET]
+
+	/* setup GICC_CTLR */
+	bic	w3, w3, #GICC_CTLR_ACKCTL_MASK
+	orr	w3, w3, #GICC_CTLR_FIQ_EN_MASK
+	orr	w3, w3, #GICC_CTLR_EOImodeS_MASK
+	orr	w3, w3, #GICC_CTLR_CBPR_MASK
+	str	w3, [x5, #GICC_CTLR_OFFSET]
+
+	/* setup the banked-per-core GICD registers */
+	bl	_getGICD_BaseAddr
+	mov	x5, x0
+
+	/* define SGI15 as Grp0 */
+	ldr	w2, [x5, #GICD_IGROUPR0_OFFSET]
+	bic	w2, w2, #GICD_IGROUP0_SGI15
+	str	w2, [x5, #GICD_IGROUPR0_OFFSET]
+
+	/* set priority of SGI 15 to highest... */
+	ldr	w2, [x5, #GICD_IPRIORITYR3_OFFSET]
+	bic	w2, w2, #GICD_IPRIORITY_SGI15_MASK
+	str	w2, [x5, #GICD_IPRIORITYR3_OFFSET]
+
+	/* enable SGI 15 */
+	ldr	w2, [x5, #GICD_ISENABLER0_OFFSET]
+	orr	w2, w2, #GICD_ISENABLE0_SGI15
+	str	w2, [x5, #GICD_ISENABLER0_OFFSET]
+
+	/* enable the cpu interface */
+	bl	_getGICC_BaseAddr
+	mov	x2, x0
+	orr	w3, w3, #GICC_CTLR_EN_GRP0
+	str	w3, [x2, #GICC_CTLR_OFFSET]
+
+
+	/* clear any pending SGIs */
+	ldr	x2, =GICD_CPENDSGIR_CLR_MASK
+	add	x0, x5, #GICD_CPENDSGIR3_OFFSET
+	str	w2, [x0]
+
+	/*
+	 * Set the PC_PH20_REQ bit in RCPM_PCPH20SETR
+	 * this is an lsb-0 register
+	 */
+	mov	x1, x6
+	mov	x0, #RCPM_PCPH20SETR_OFFSET
+	bl	write_reg_rcpm
+
+	dsb	sy
+	isb
+	mov	x30, x7
+	ret
+endfunc _soc_core_prep_off
+
+/*
+ * Part of CPU_OFF
+ * this function performs the final steps to shutdown the core
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5
+ */
+func _soc_core_entr_off
+	mov	x5, x30
+	mov	x4, x0
+
+	bl	_getGICD_BaseAddr
+	mov	x3, x0
+
+3:
+	/* enter low-power state by executing wfi */
+	wfi
+
+	/* see if we got hit by SGI 15 */
+	add	x0, x3, #GICD_SPENDSGIR3_OFFSET
+	ldr	w2, [x0]
+	and	w2, w2, #GICD_SPENDSGIR3_SGI15_MASK
+	cbz	w2, 4f
+
+	/* clear the pending SGI */
+	ldr	x2, =GICD_CPENDSGIR_CLR_MASK
+	add	x0, x3, #GICD_CPENDSGIR3_OFFSET
+	str	w2, [x0]
+4:
+	/* check if core has been turned on */
+	mov	x0, x4
+	bl	_getCoreState
+
+	cmp	x0, #CORE_WAKEUP
+	b.ne	3b
+
+	/* if we get here, then we have exited the wfi */
+	dsb	sy
+	isb
+	mov	x30, x5
+	ret
+endfunc _soc_core_entr_off
+
+/*
+ * Part of CPU_OFF
+ * this function starts the process of starting a core back up
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5, x6
+ */
+func _soc_core_exit_off
+	mov	x6, x30
+	mov	x5, x0
+
+	/*
+	 * Clear ph20 request in RCPM_PCPH20CLRR - no need
+	 * to do that here, it has been done in _soc_core_restart
+	 */
+	bl	_getGICC_BaseAddr
+	mov	x1, x0
+
+	/* read GICC_IAR */
+	ldr	w0, [x1, #GICC_IAR_OFFSET]
+
+	/* write GICC_EIOR - signal end-of-interrupt */
+	str	w0, [x1, #GICC_EOIR_OFFSET]
+
+	/* write GICC_DIR - disable interrupt */
+	str	w0, [x1, #GICC_DIR_OFFSET]
+
+	/* disable signaling of grp0 ints */
+	ldr	w3, [x1, #GICC_CTLR_OFFSET]
+	bic	w3, w3, #GICC_CTLR_EN_GRP0
+	str	w3, [x1, #GICC_CTLR_OFFSET]
+
+	/*
+	 * Unset retention request in SCFG_RETREQCR
+	 * Note: this register is msb-0
+	 */
+	ldr	x4, =SCFG_RETREQCR_OFFSET
+	mov	x0, x4
+	bl	read_reg_scfg
+	rbit	w1, w5
+	bic	w1, w0, w1
+	mov	x0, x4
+	bl	write_reg_scfg
+
+	/* restore timer ctrl */
+	mov	x0, x5
+	mov	x1, #TIMER_CNTRL_DATA
+	bl	_getCoreData
+	/* w0 = timer ctrl saved value */
+	mov	x2, #NXP_TIMER_ADDR
+	str	w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
+
+	dsb	sy
+	isb
+	mov	x30, x6
+	ret
+endfunc _soc_core_exit_off
+
+/*
+ * Function loads a 64-bit execution address of the core in the soc registers
+ * BOOTLOCPTRL/H
+ * in:  x0, 64-bit address to write to BOOTLOCPTRL/H
+ * uses x0, x1, x2, x3
+ */
+func _soc_set_start_addr
+	/* get the 64-bit base address of the scfg block */
+	ldr	x2, =NXP_SCFG_ADDR
+
+	/* write the 32-bit BOOTLOCPTRL register */
+	mov	x1, x0
+	rev	w3, w1
+	str	w3, [x2, #SCFG_BOOTLOCPTRL_OFFSET]
+
+	/* write the 32-bit BOOTLOCPTRH register */
+	lsr	x1, x0, #32
+	rev	w3, w1
+	str	w3, [x2, #SCFG_BOOTLOCPTRH_OFFSET]
+	ret
+endfunc _soc_set_start_addr
+
+/*
+ * This function returns the base address of the gic distributor
+ * in:  none
+ * out: x0 = base address of gic distributor
+ * uses x0
+ */
+func _getGICD_BaseAddr
+#if (TEST_BL31)
+	/* defect in simulator - gic base addresses are on 4Kb boundary */
+	ldr	x0, =NXP_GICD_4K_ADDR
+#else
+	ldr	x0, =NXP_GICD_64K_ADDR
+#endif
+	ret
+endfunc _getGICD_BaseAddr
+
+/*
+ * This function returns the base address of the gic controller
+ * in:  none
+ * out: x0 = base address of gic controller
+ * uses x0
+ */
+func _getGICC_BaseAddr
+#if (TEST_BL31)
+	/* defect in simulator - gic base addresses are on 4Kb boundary */
+	ldr	x0, =NXP_GICC_4K_ADDR
+#else
+	ldr	x0, =NXP_GICC_64K_ADDR
+#endif
+	ret
+endfunc _getGICC_BaseAddr
+
+/*
+ * Part of CPU_SUSPEND
+ * this function puts the calling core into standby state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0
+ */
+func _soc_core_entr_stdby
+	dsb	sy
+	isb
+	wfi
+
+	ret
+endfunc _soc_core_entr_stdby
+
+
+/*
+ * Part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to standby
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+func _soc_core_prep_stdby
+	/* clear CORTEX_A72_ECTLR_EL1[2:0] */
+	mrs	x1, CORTEX_A72_ECTLR_EL1
+	bic	x1, x1, #CPUECTLR_TIMER_MASK
+	msr	CORTEX_A72_ECTLR_EL1, x1
+
+	ret
+endfunc _soc_core_prep_stdby
+
+/*
+ * Part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after standby state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_core_exit_stdby
+	ret
+endfunc _soc_core_exit_stdby
+
+/*
+ * Part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5
+ */
+func _soc_core_prep_pwrdn
+	mov	x5, x30
+	mov	x4, x0
+
+	/* enable CPU retention + set smp */
+	mrs	x1, CORTEX_A72_ECTLR_EL1
+	orr	x1, x1, #0x1
+	orr	x1, x1, #CPUECTLR_SMPEN_MASK
+	msr	CORTEX_A72_ECTLR_EL1, x1
+
+	/*
+	 * set the retention request in SCFG_RETREQCR
+	 * this is an msb-0 register
+	 */
+	ldr	x3, =SCFG_RETREQCR_OFFSET
+	mov	x0, x3
+	bl	read_reg_scfg
+	rbit	w1, w4
+	orr	w1, w0, w1
+	mov	x0, x3
+	bl	write_reg_scfg
+
+	/*
+	 * Set the PC_PH20_REQ bit in RCPM_PCPH20SETR
+	 * this is an lsb-0 register
+	 */
+	mov	x1, x4
+	mov	x0, #RCPM_PCPH20SETR_OFFSET
+	bl	write_reg_rcpm
+
+	mov	x30, x5
+	ret
+endfunc _soc_core_prep_pwrdn
+
+/*
+ * Part of CPU_SUSPEND
+ * this function puts the calling core into a power-down state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0
+ */
+func _soc_core_entr_pwrdn
+	dsb	sy
+	isb
+	wfi
+
+	ret
+endfunc _soc_core_entr_pwrdn
+
+/*
+ * Part of CPU_SUSPEND
+ * this function cleans up after a core exits power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5
+ */
+func _soc_core_exit_pwrdn
+	mov	x5, x30
+	mov	x4, x0
+
+	/*
+	 * Set the PC_PH20_REQ bit in RCPM_PCPH20CLRR
+	 * this is an lsb-0 register
+	 */
+	mov	x1, x4
+	mov	x0, #RCPM_PCPH20CLRR_OFFSET
+	bl	write_reg_rcpm
+
+	/*
+	 * Unset the retention request in SCFG_RETREQCR
+	 * this is an msb-0 register
+	 */
+	ldr	x3, =SCFG_RETREQCR_OFFSET
+	mov	x0, x3
+	bl	read_reg_scfg
+	rbit	w1, w4
+	bic	w1, w0, w1
+	mov	x0, x3
+	bl	write_reg_scfg
+
+	mov	x30, x5
+	ret
+endfunc _soc_core_exit_pwrdn
+
+/*
+ * Part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to standby
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_clstr_prep_stdby
+	/* clear CORTEX_A72_ECTLR_EL1[2:0] */
+	mrs	x1, CORTEX_A72_ECTLR_EL1
+	bic	x1, x1, #CPUECTLR_TIMER_MASK
+	msr	CORTEX_A72_ECTLR_EL1, x1
+
+	ret
+endfunc _soc_clstr_prep_stdby
+
+/*
+ * Part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after standby state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_clstr_exit_stdby
+	ret
+endfunc _soc_clstr_exit_stdby
+
+/*
+ * Part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5
+ */
+func _soc_clstr_prep_pwrdn
+	mov	x5, x30
+	mov	x4, x0
+
+	/* enable CPU retention + set smp */
+	mrs	x1, CORTEX_A72_ECTLR_EL1
+	orr	x1, x1, #0x1
+	orr	x1, x1, #CPUECTLR_SMPEN_MASK
+	msr	CORTEX_A72_ECTLR_EL1, x1
+
+	/*
+	 * Set the retention request in SCFG_RETREQCR
+	 * this is an msb-0 register.
+	 */
+	ldr	x3, =SCFG_RETREQCR_OFFSET
+	mov	x0, x3
+	bl	read_reg_scfg
+	rbit	w1, w4
+	orr	w1, w0, w1
+	mov	x0, x3
+	bl	write_reg_scfg
+
+	/*
+	 * Set the PC_PH20_REQ bit in RCPM_PCPH20SETR
+	 * this is an lsb-0 register.
+	 */
+	mov	x1, x4
+	mov	x0, #RCPM_PCPH20SETR_OFFSET
+	bl	write_reg_rcpm
+
+	mov	x30, x5
+	ret
+endfunc _soc_clstr_prep_pwrdn
+
+/*
+ * Part of CPU_SUSPEND
+ * this function cleans up after a core exits power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5
+ */
+func _soc_clstr_exit_pwrdn
+	mov	x5, x30
+	mov	x4, x0
+
+	/*
+	 * Set the PC_PH20_REQ bit in RCPM_PCPH20CLRR
+	 * this is an lsb-0 register.
+	 */
+	mov	x1, x4
+	mov	x0, #RCPM_PCPH20CLRR_OFFSET
+	bl	write_reg_rcpm
+
+	/*
+	 * Unset the retention request in SCFG_RETREQCR
+	 * this is an msb-0 register.
+	 */
+	ldr	x3, =SCFG_RETREQCR_OFFSET
+	mov	x0, x3
+	bl	read_reg_scfg
+	rbit	w1, w4
+	bic	w1, w0, w1
+	mov	x0, x3
+	bl	write_reg_scfg
+
+	mov	x30, x5
+	ret
+endfunc _soc_clstr_exit_pwrdn
+
+/*
+ * Part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to standby
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_sys_prep_stdby
+	/* clear CORTEX_A72_ECTLR_EL1[2:0] */
+	mrs	x1, CORTEX_A72_ECTLR_EL1
+	bic	x1, x1, #CPUECTLR_TIMER_MASK
+	msr	CORTEX_A72_ECTLR_EL1, x1
+
+	ret
+endfunc _soc_sys_prep_stdby
+
+/* Part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after standby state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_sys_exit_stdby
+	ret
+endfunc _soc_sys_exit_stdby
+
+/*
+ * Part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to
+ * suspend-to-power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4
+ */
+func _soc_sys_prep_pwrdn
+	mov	x4, x30
+
+	/* Enable dynamic retention contrl (CPUECTLR[2:0]) and SMP (CPUECTLR[6]) */
+	mrs	x0, CORTEX_A72_ECTLR_EL1
+	bic	x0, x0, #CPUECTLR_TIMER_MASK
+	orr	x0, x0, #CPUECTLR_TIMER_8TICKS
+	orr	x0, x0, #CPUECTLR_SMPEN_EN
+	msr	CORTEX_A72_ECTLR_EL1, x0
+
+	/* Set WFIL2EN in SCFG_CLUSTERPMCR */
+	ldr	x0, =SCFG_COREPMCR_OFFSET
+	ldr	x1, =COREPMCR_WFIL2
+	bl	write_reg_scfg
+
+	isb
+	mov	x30, x4
+	ret
+endfunc _soc_sys_prep_pwrdn
+
+/*
+ * Part of CPU_SUSPEND
+ * this function puts the calling core, and potentially the soc, into a
+ * low-power state
+ * in:  x0 = core mask lsb
+ * out: x0 = 0, success
+ *      x0 < 0, failure
+ * uses x0, x1, x2, x3, x4
+ */
+func _soc_sys_pwrdn_wfi
+	mov	x4, x30
+
+	/* request LPM20 */
+	mov	x0, #RCPM_POWMGTCSR_OFFSET
+	bl	read_reg_rcpm
+	orr	x1, x0, #RCPM_POWMGTCSR_LPM20_REQ
+	mov	x0, #RCPM_POWMGTCSR_OFFSET
+	bl	write_reg_rcpm
+
+	dsb	sy
+	isb
+	wfi
+
+	mov	x30, x4
+	ret
+endfunc _soc_sys_pwrdn_wfi
+
+/*
+ * Part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+func _soc_sys_exit_pwrdn
+	/* clear WFIL2_EN in SCFG_COREPMCR */
+	mov	x1, #NXP_SCFG_ADDR
+	str	wzr, [x1, #SCFG_COREPMCR_OFFSET]
+
+	ret
+endfunc _soc_sys_exit_pwrdn
diff --git a/plat/nxp/soc-ls1046a/aarch64/ls1046a_helpers.S b/plat/nxp/soc-ls1046a/aarch64/ls1046a_helpers.S
new file mode 100644
index 0000000..d2a48ea
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/aarch64/ls1046a_helpers.S
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+#include <platform_def.h>
+
+	.globl	plat_secondary_cold_boot_setup
+	.globl	plat_is_my_cpu_primary
+	.globl	plat_reset_handler
+	.globl  platform_mem_init
+
+func platform_mem1_init
+	ret
+endfunc platform_mem1_init
+
+func platform_mem_init
+	ret
+endfunc	platform_mem_init
+
+func l2_mem_init
+	/* Initialize the L2 RAM latency */
+	mrs	x1, S3_1_c11_c0_2
+	mov	x0, #0x1C7
+	/* Clear L2 Tag RAM latency and L2 Data RAM latency */
+	bic	x1, x1, x0
+	/* Set L2 data ram latency bits [2:0] */
+	orr	x1, x1, #0x2
+	/* set L2 tag ram latency bits [8:6] */
+	orr	x1,  x1, #0x80
+	msr	S3_1_c11_c0_2, x1
+	isb
+	ret
+endfunc	l2_mem_init
+
+func apply_platform_errata
+	ret
+endfunc apply_platform_errata
+
+func plat_reset_handler
+	mov	x29, x30
+#if (defined(IMAGE_BL2) && BL2_AT_EL3)
+	bl	l2_mem_init
+#endif
+	bl	apply_platform_errata
+
+#if defined(IMAGE_BL31)
+	ldr	x0, =POLICY_SMMU_PAGESZ_64K
+	cbz	x0, 1f
+	/* Set the SMMU page size in the SACR register */
+	bl	_set_smmu_pagesz_64
+#endif
+1:
+	/*
+	 * May be cntfrq_el0 needs to be assigned
+	 * the value COUNTER_FREQUENCY
+	 */
+	mov	x30, x29
+	ret
+endfunc plat_reset_handler
+
+/*
+ * void plat_secondary_cold_boot_setup (void);
+ *
+ * This function performs any platform specific actions
+ * needed for a secondary cpu after a cold reset e.g
+ * mark the cpu's presence, mechanism to place it in a
+ * holding pen etc.
+ */
+func plat_secondary_cold_boot_setup
+	/* ls1046a does not do cold boot for secondary CPU */
+cb_panic:
+	b	cb_panic
+endfunc plat_secondary_cold_boot_setup
+
+/*
+ * unsigned int plat_is_my_cpu_primary (void);
+ *
+ * Find out whether the current cpu is the primary cpu.
+ */
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
+	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+	cmp	x0, 0x0
+	cset	w0, eq
+	ret
+endfunc plat_is_my_cpu_primary
diff --git a/plat/nxp/soc-ls1046a/include/ns_access.h b/plat/nxp/soc-ls1046a/include/ns_access.h
new file mode 100644
index 0000000..25c1964
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/include/ns_access.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2017-2018, 2020-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NS_ACCESS_H
+#define NS_ACCESS_H
+
+#include <csu.h>
+
+enum csu_cslx_ind {
+	CSU_CSLX_PCIE2_IO = 0,
+	CSU_CSLX_PCIE1_IO,
+	CSU_CSLX_MG2TPR_IP,
+	CSU_CSLX_IFC_MEM,
+	CSU_CSLX_OCRAM,
+	CSU_CSLX_GIC,
+	CSU_CSLX_PCIE1,
+	CSU_CSLX_OCRAM2,
+	CSU_CSLX_QSPI_MEM,
+	CSU_CSLX_PCIE2,
+	CSU_CSLX_SATA,
+	CSU_CSLX_USB1,
+	CSU_CSLX_QM_BM_SWPORTAL,
+	CSU_CSLX_PCIE3 = 16,
+	CSU_CSLX_PCIE3_IO,
+	CSU_CSLX_USB3 = 20,
+	CSU_CSLX_USB2,
+	CSU_CSLX_PFE = 23,
+	CSU_CSLX_SERDES = 32,
+	CSU_CSLX_QDMA,
+	CSU_CSLX_LPUART2,
+	CSU_CSLX_LPUART1,
+	CSU_CSLX_LPUART4,
+	CSU_CSLX_LPUART3,
+	CSU_CSLX_LPUART6,
+	CSU_CSLX_LPUART5,
+	CSU_CSLX_DSPI1 = 41,
+	CSU_CSLX_QSPI,
+	CSU_CSLX_ESDHC,
+	CSU_CSLX_IFC = 45,
+	CSU_CSLX_I2C1,
+	CSU_CSLX_USB_2,
+	CSU_CSLX_I2C3 = 48,
+	CSU_CSLX_I2C2,
+	CSU_CSLX_DUART2 = 50,
+	CSU_CSLX_DUART1,
+	CSU_CSLX_WDT2,
+	CSU_CSLX_WDT1,
+	CSU_CSLX_EDMA,
+	CSU_CSLX_SYS_CNT,
+	CSU_CSLX_DMA_MUX2,
+	CSU_CSLX_DMA_MUX1,
+	CSU_CSLX_DDR,
+	CSU_CSLX_QUICC,
+	CSU_CSLX_DCFG_CCU_RCPM = 60,
+	CSU_CSLX_SECURE_BOOTROM,
+	CSU_CSLX_SFP,
+	CSU_CSLX_TMU,
+	CSU_CSLX_SECURE_MONITOR,
+	CSU_CSLX_SCFG,
+	CSU_CSLX_FM = 66,
+	CSU_CSLX_SEC5_5,
+	CSU_CSLX_BM,
+	CSU_CSLX_QM,
+	CSU_CSLX_GPIO2 = 70,
+	CSU_CSLX_GPIO1,
+	CSU_CSLX_GPIO4,
+	CSU_CSLX_GPIO3,
+	CSU_CSLX_PLATFORM_CONT,
+	CSU_CSLX_CSU,
+	CSU_CSLX_IIC4 = 77,
+	CSU_CSLX_WDT4,
+	CSU_CSLX_WDT3,
+	CSU_CSLX_ESDHC2 = 80,
+	CSU_CSLX_WDT5 = 81,
+	CSU_CSLX_SAI2,
+	CSU_CSLX_SAI1,
+	CSU_CSLX_SAI4,
+	CSU_CSLX_SAI3,
+	CSU_CSLX_FTM2 = 86,
+	CSU_CSLX_FTM1,
+	CSU_CSLX_FTM4,
+	CSU_CSLX_FTM3,
+	CSU_CSLX_FTM6 = 90,
+	CSU_CSLX_FTM5,
+	CSU_CSLX_FTM8,
+	CSU_CSLX_FTM7,
+	CSU_CSLX_DSCR = 121,
+};
+
+struct csu_ns_dev_st ns_dev[] = {
+	 {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
+	 {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
+	 {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM, CSU_S_SUP_RW},
+	 {CSU_CSLX_GIC, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE1, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM2, CSU_S_SUP_RW},
+	 {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE2, CSU_ALL_RW},
+	 {CSU_CSLX_SATA, CSU_ALL_RW},
+	 {CSU_CSLX_USB1, CSU_ALL_RW},
+	 {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE3, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+	 {CSU_CSLX_USB3, CSU_ALL_RW},
+	 {CSU_CSLX_USB2, CSU_ALL_RW},
+	 {CSU_CSLX_PFE, CSU_ALL_RW},
+	 {CSU_CSLX_SERDES, CSU_ALL_RW},
+	 {CSU_CSLX_QDMA, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART2, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART1, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART4, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART3, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART6, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART5, CSU_ALL_RW},
+	 {CSU_CSLX_DSPI1, CSU_ALL_RW},
+	 {CSU_CSLX_QSPI, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC, CSU_ALL_RW},
+	 {CSU_CSLX_IFC, CSU_ALL_RW},
+	 {CSU_CSLX_I2C1, CSU_ALL_RW},
+	 {CSU_CSLX_USB_2, CSU_ALL_RW},
+	 {CSU_CSLX_I2C3, CSU_ALL_RW},
+	 {CSU_CSLX_I2C2, CSU_ALL_RW},
+	 {CSU_CSLX_DUART2, CSU_ALL_RW},
+	 {CSU_CSLX_DUART1, CSU_ALL_RW},
+	 {CSU_CSLX_WDT2, CSU_ALL_RW},
+	 {CSU_CSLX_WDT1, CSU_ALL_RW},
+	 {CSU_CSLX_EDMA, CSU_ALL_RW},
+	 {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
+	 {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
+	 {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
+	 {CSU_CSLX_DDR, CSU_ALL_RW},
+	 {CSU_CSLX_QUICC, CSU_ALL_RW},
+	 {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
+	 {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
+	 {CSU_CSLX_SFP, CSU_ALL_RW},
+	 {CSU_CSLX_TMU, CSU_ALL_RW},
+	 {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
+	 {CSU_CSLX_SCFG, CSU_ALL_RW},
+	 {CSU_CSLX_FM, CSU_ALL_RW},
+	 {CSU_CSLX_SEC5_5, CSU_ALL_RW},
+	 {CSU_CSLX_BM, CSU_ALL_RW},
+	 {CSU_CSLX_QM, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO2, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO1, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO4, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO3, CSU_ALL_RW},
+	 {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
+	 {CSU_CSLX_CSU, CSU_ALL_RW},
+	 {CSU_CSLX_IIC4, CSU_ALL_RW},
+	 {CSU_CSLX_WDT4, CSU_ALL_RW},
+	 {CSU_CSLX_WDT3, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC2, CSU_ALL_RW},
+	 {CSU_CSLX_WDT5, CSU_ALL_RW},
+	 {CSU_CSLX_SAI2, CSU_ALL_RW},
+	 {CSU_CSLX_SAI1, CSU_ALL_RW},
+	 {CSU_CSLX_SAI4, CSU_ALL_RW},
+	 {CSU_CSLX_SAI3, CSU_ALL_RW},
+	 {CSU_CSLX_FTM2, CSU_ALL_RW},
+	 {CSU_CSLX_FTM1, CSU_ALL_RW},
+	 {CSU_CSLX_FTM4, CSU_ALL_RW},
+	 {CSU_CSLX_FTM3, CSU_ALL_RW},
+	 {CSU_CSLX_FTM6, CSU_ALL_RW},
+	 {CSU_CSLX_FTM5, CSU_ALL_RW},
+	 {CSU_CSLX_FTM8, CSU_ALL_RW},
+	 {CSU_CSLX_FTM7, CSU_ALL_RW},
+	 {CSU_CSLX_DSCR, CSU_ALL_RW},
+};
+
+#endif /* NS_ACCESS_H */
diff --git a/plat/nxp/soc-ls1046a/include/soc.h b/plat/nxp/soc-ls1046a/include/soc.h
new file mode 100644
index 0000000..67810c3
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/include/soc.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SOC_H
+#define	SOC_H
+
+/* Chassis specific defines - common across SoC's of a particular platform */
+#include <dcfg_lsch2.h>
+
+#include <soc_default_base_addr.h>
+#include <soc_default_helper_macros.h>
+
+/* DDR Regions Info */
+#define NUM_DRAM_REGIONS		U(3)
+#define	NXP_DRAM0_ADDR			ULL(0x80000000)
+#define NXP_DRAM0_MAX_SIZE		ULL(0x80000000)	/*  2 GB  */
+
+#define	NXP_DRAM1_ADDR			ULL(0x880000000)
+#define NXP_DRAM1_MAX_SIZE		ULL(0x780000000)	/* 30 GB  */
+
+#define	NXP_DRAM2_ADDR			ULL(0x8800000000)
+#define NXP_DRAM2_MAX_SIZE		ULL(0x7800000000)	/* 480 GB */
+
+/*DRAM0 Size defined in platform_def.h */
+#define	NXP_DRAM0_SIZE			PLAT_DEF_DRAM0_SIZE
+
+/*
+ * SVR Definition (not include major and minor rev)
+ * A: without security
+ * AE: with security
+ */
+#define SVR_LS1026A			0x870709
+#define SVR_LS1026AE			0x870708
+#define SVR_LS1046A			0x870701
+#define SVR_LS1046AE			0x870700
+
+/* Number of cores in platform */
+/* Used by common code for array initialization */
+#define NUMBER_OF_CLUSTERS		U(1)
+#define CORES_PER_CLUSTER		U(4)
+#define PLATFORM_CORE_COUNT		(NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER)
+
+/*
+ * Required LS standard platform porting definitions
+ * for CCI-400
+ */
+#define NXP_CCI_CLUSTER0_SL_IFACE_IX	4
+
+
+/* Defines required for using XLAT tables from ARM common code */
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 40)
+
+/* Clock Divisors */
+#define NXP_PLATFORM_CLK_DIVIDER	U(1)
+#define NXP_UART_CLK_DIVIDER		U(2)
+
+/* set to 0 if the clusters are not symmetrical */
+#define SYMMETRICAL_CLUSTERS		U(1)
+
+ /*
+  * set this switch to 1 if you need to keep the debug block
+  * clocked during system power-down
+  */
+#define DEBUG_ACTIVE			0
+
+ /*
+  * pwr mgmt features supported in the soc-specific code:
+  *   value == 0x0  the soc code does not support this feature
+  *   value != 0x0  the soc code supports this feature
+  */
+#define SOC_CORE_RELEASE		0x1
+#define SOC_CORE_RESTART		0x1
+#define SOC_CORE_OFF			0x1
+#define SOC_CORE_STANDBY		0x1
+#define SOC_CORE_PWR_DWN		0x1
+#define SOC_CLUSTER_STANDBY		0x1
+#define SOC_CLUSTER_PWR_DWN		0x1
+#define SOC_SYSTEM_STANDBY		0x1
+#define SOC_SYSTEM_PWR_DWN		0x1
+#define SOC_SYSTEM_OFF			0x1
+#define SOC_SYSTEM_RESET		0x1
+
+/* Start: Macros used by lib/psci files */
+#define SYSTEM_PWR_DOMAINS		1
+#define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CORE_COUNT + \
+					NUMBER_OF_CLUSTERS  + \
+					SYSTEM_PWR_DOMAINS)
+
+/* Power state coordination occurs at the system level */
+#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL2
+
+/* define retention state */
+#define PLAT_MAX_RET_STATE		(PSCI_LOCAL_STATE_RUN + 1)
+
+/* define power-down state */
+#define PLAT_MAX_OFF_STATE		(PLAT_MAX_RET_STATE + 1)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ *
+ * CACHE_WRITEBACK_GRANULE is defined in soc.def
+ */
+
+ /* One cache line needed for bakery locks on ARM platforms */
+#define PLAT_PERCPU_BAKERY_LOCK_SIZE	(1 * CACHE_WRITEBACK_GRANULE)
+
+#ifndef __ASSEMBLER__
+/* CCI slave interfaces */
+static const int cci_map[] = {
+	NXP_CCI_CLUSTER0_SL_IFACE_IX,
+};
+
+void soc_init_lowlevel(void);
+void soc_init_percpu(void);
+void _soc_set_start_addr(unsigned long addr);
+#endif
+
+#endif /* SOC_H */
diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c b/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c
new file mode 100644
index 0000000..3d561c7
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+
+#include <errata.h>
+#include <platform_def.h>
+
+#ifdef CONFIG_STATIC_DDR
+const struct ddr_cfg_regs static_1600 = {
+	.cs[0].config = U(0x80010412),
+	.cs[0].bnds = U(0x7F),
+	.sdram_cfg[0] = U(0xE50C0008),
+	.sdram_cfg[1] = U(0x00401010),
+	.sdram_cfg[2] = U(0x1),
+	.timing_cfg[0] = U(0xFA550018),
+	.timing_cfg[1] = U(0xBAB40C52),
+	.timing_cfg[2] = U(0x0048C11C),
+	.timing_cfg[3] = U(0x01111000),
+	.timing_cfg[4] = U(0x00000002),
+	.timing_cfg[5] = U(0x03401400),
+	.timing_cfg[6] = U(0x0),
+	.timing_cfg[7] = U(0x23300000),
+	.timing_cfg[8] = U(0x02116600),
+	.timing_cfg[9] = U(0x0),
+	.dq_map[0] = U(0x0),
+	.dq_map[1] = U(0x0),
+	.dq_map[2] = U(0x0),
+	.dq_map[3] = U(0x0),
+	.sdram_mode[0] = U(0x01010210),
+	.sdram_mode[1] = U(0x0),
+	.sdram_mode[8] = U(0x00000500),
+	.sdram_mode[9] = U(0x04000000),
+	.interval = U(0x18600618),
+	.zq_cntl = U(0x8A090705),
+	.ddr_sr_cntr = U(0x0),
+	.clk_cntl = U(0x2000000),
+	.cdr[0] = U(0x80040000),
+	.cdr[1] = U(0xC1),
+	.wrlvl_cntl[0] = U(0x86550607),
+	.wrlvl_cntl[1] = U(0x07070708),
+	.wrlvl_cntl[2] = U(0x0808088),
+};
+
+long long board_static_ddr(struct ddr_info *priv)
+{
+	memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
+
+	return 0x80000000ULL;
+}
+#else /* ifndef CONFIG_STATIC_DDR */
+static const struct rc_timing rcz[] = {
+	{U(1600), U(8), U(7)},
+	{U(2100), U(8), U(7)},
+	{}
+};
+
+static const struct board_timing ram[] = {
+	{U(0x1f), rcz, U(0x01010101), U(0x01010101)},
+};
+
+int ddr_board_options(struct ddr_info *priv)
+{
+	int ret;
+	struct memctl_opt *popts = &priv->opt;
+
+	ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
+	if (ret != 0) {
+		return ret;
+	}
+
+	popts->bstopre = 0;
+	popts->half_strength_drive_en = 1;
+	popts->cpo_sample = U(0x46);
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_50ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_50ohm) |
+				DDR_CDR2_VREF_TRAIN_EN;
+	popts->output_driver_impedance = 1;
+
+	return 0;
+}
+
+/* DDR model number:  MT40A512M16JY-083E:B */
+struct dimm_params ddr_raw_timing = {
+		.n_ranks = U(1),
+		.rank_density = ULL(4294967296),
+		.capacity = ULL(4294967296),
+		.primary_sdram_width = U(64),
+		.ec_sdram_width = U(8),
+		.rdimm = U(0),
+		.mirrored_dimm = U(0),
+		.n_row_addr = U(16),
+		.n_col_addr = U(10),
+		.bank_group_bits = U(1),
+		.edc_config = U(2),
+		.burst_lengths_bitmask = U(0x0c),
+		.tckmin_x_ps = 750,
+		.tckmax_ps = 1900,
+		.caslat_x = U(0x0001FFE00),
+		.taa_ps = 13500,
+		.trcd_ps = 13500,
+		.trp_ps = 13500,
+		.tras_ps = 33000,
+		.trc_ps = 46500,
+		.twr_ps = 15000,
+		.trfc1_ps = 350000,
+		.trfc2_ps = 260000,
+		.trfc4_ps = 160000,
+		.tfaw_ps = 30000,
+		.trrds_ps = 5300,
+		.trrdl_ps = 6400,
+		.tccdl_ps = 5355,
+		.refresh_rate_ps = U(7800000),
+		.dq_mapping[0] = U(0x0),
+		.dq_mapping[1] = U(0x0),
+		.dq_mapping[2] = U(0x0),
+		.dq_mapping[3] = U(0x0),
+		.dq_mapping[4] = U(0x0),
+		.dq_mapping_ors = U(0),
+		.rc = U(0x1f),
+};
+
+int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf)
+{
+	static const char dimm_model[] = "Fixed DDR on board";
+
+	conf->dimm_in_use[0] = 1;
+	memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
+	memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+
+	return 1;
+}
+#endif /* ifdef CONFIG_STATIC_DDR */
+
+long long init_ddr(void)
+{
+	int spd_addr[] = {NXP_SPD_EEPROM0};
+	struct ddr_info info;
+	struct sysinfo sys;
+	long long dram_size;
+
+	zeromem(&sys, sizeof(sys));
+	if (get_clocks(&sys)) {
+		ERROR("System clocks are not set\n");
+		assert(0);
+	}
+	debug("platform clock %lu\n", sys.freq_platform);
+	debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+	debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+	zeromem(&info, sizeof(struct ddr_info));
+	info.num_ctlrs = 1;
+	info.dimm_on_ctlr = 1;
+	info.clk = get_ddr_freq(&sys, 0);
+	info.spd_addr = spd_addr;
+	info.ddr[0] = (void *)NXP_DDR_ADDR;
+
+	dram_size = dram_init(&info);
+	if (dram_size < 0) {
+		ERROR("DDR init failed.\n");
+	}
+
+#ifdef ERRATA_SOC_A008850
+	erratum_a008850_post();
+#endif
+
+	return dram_size;
+}
diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/plat_def.h b/plat/nxp/soc-ls1046a/ls1046afrwy/plat_def.h
new file mode 100644
index 0000000..5134a00
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/plat_def.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+/*
+ * Required without TBBR.
+ * To include the defines for DDR PHY Images.
+ */
+#include <tbbr_img_def.h>
+
+#include "policy.h"
+#include <soc.h>
+
+#define NXP_SPD_EEPROM0		0x51
+
+#define NXP_SYSCLK_FREQ		100000000
+#define NXP_DDRCLK_FREQ		100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR	NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE	115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE	0x2000
+#else
+#define PLATFORM_STACK_SIZE	0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE	0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE	(0x8000)
+#define NXP_SD_BLOCK_BUF_ADDR	ULL(0x80000000)
+
+#define BL2_LIMIT		(NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES		U(3)
+#define MAX_IO_BLOCK_DEVICES	U(1)
+#define MAX_IO_HANDLES		U(4)
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES		U(2)
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES		U(1)
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER	29
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_LEVEL)
+
+#define PLAT_LS_G0_IRQ_PROPS(grp)
+
+#endif /* PLAT_DEF_H */
diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/platform.c b/plat/nxp/soc-ls1046a/ls1046afrwy/platform.c
new file mode 100644
index 0000000..cef920f
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/platform.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+	return true;
+#else
+	return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+	return true;
+#else
+	return false;
+#endif
+}
diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/platform.mk b/plat/nxp/soc-ls1046a/ls1046afrwy/platform.mk
new file mode 100644
index 0000000..1f7fad6
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/platform.mk
@@ -0,0 +1,39 @@
+#
+# Copyright 2018-2022 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+
+BOOT_MODE	?=	qspi
+BOARD		:=	ls1046afrwy
+POVDD_ENABLE	:=	no
+
+# DDR Compilation Configs
+CONFIG_STATIC_DDR := 0
+CONFIG_DDR_NODIMM := 1
+DDRC_NUM_DIMM	:=	0
+NUM_OF_DDRC	:=	1
+DDRC_NUM_CS	:=	1
+DDR_ECC_EN	:=	yes
+
+# On-Board Flash Details
+QSPI_FLASH_SZ	:=	0x20000000
+NOR_FLASH_SZ	:=	0x20000000
+
+# Platform specific features.
+WARM_BOOT	:=	no
+
+# Adding Platform files build files
+BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
+			${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE	:=	qspi	\
+				sd
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
+include plat/nxp/soc-ls1046a/soc.mk
diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/platform_def.h b/plat/nxp/soc-ls1046a/ls1046afrwy/platform_def.h
new file mode 100644
index 0000000..7f98bb1
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/platform_def.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat_def.h>
+#include <plat_default_def.h>
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/policy.h b/plat/nxp/soc-ls1046a/ls1046afrwy/policy.h
new file mode 100644
index 0000000..c6c325f
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/policy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef POLICY_H
+#define	POLICY_H
+
+/* Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+#endif /* POLICY_H */
diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c
new file mode 100644
index 0000000..6d1707c
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+
+#include <errata.h>
+
+static const struct rc_timing rce[] = {
+	{U(1600), U(8), U(7)},
+	{U(1867), U(8), U(7)},
+	{U(2134), U(8), U(9)},
+	{}
+};
+
+static const struct board_timing udimm[] = {
+	{U(0x04), rce, U(0x01020304), U(0x06070805)},
+};
+
+int ddr_board_options(struct ddr_info *priv)
+{
+	int ret;
+	struct memctl_opt *popts = &priv->opt;
+
+	if (popts->rdimm) {
+		debug("RDIMM parameters not set.\n");
+		return -EINVAL;
+	}
+
+	ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm));
+	if (ret != 0) {
+		return ret;
+	}
+
+	popts->wrlvl_override = U(1);
+	popts->wrlvl_sample = U(0x0);	/* 32 clocks */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN	|
+			  DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm)	|
+			  DDR_CDR2_VREF_TRAIN_EN		|
+			  DDR_CDR2_VREF_RANGE_2;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = U(0x70);
+
+	return 0;
+}
+
+long long init_ddr(void)
+{
+	int spd_addr[] = { NXP_SPD_EEPROM0 };
+	struct ddr_info info;
+	struct sysinfo sys;
+	long long dram_size;
+
+	zeromem(&sys, sizeof(sys));
+	if (get_clocks(&sys)) {
+		ERROR("System clocks are not set\n");
+		assert(0);
+	}
+	debug("platform clock %lu\n", sys.freq_platform);
+	debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+	debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+	zeromem(&info, sizeof(struct ddr_info));
+	info.num_ctlrs = 1;
+	info.dimm_on_ctlr = 1;
+	info.clk = get_ddr_freq(&sys, 0);
+	info.spd_addr = spd_addr;
+	info.ddr[0] = (void *)NXP_DDR_ADDR;
+
+	dram_size = dram_init(&info);
+
+	if (dram_size < 0) {
+		ERROR("DDR init failed.\n");
+	}
+
+#ifdef ERRATA_SOC_A008850
+	erratum_a008850_post();
+#endif
+
+	return dram_size;
+}
diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/plat_def.h b/plat/nxp/soc-ls1046a/ls1046aqds/plat_def.h
new file mode 100644
index 0000000..aa69a66
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046aqds/plat_def.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+/* Required without TBBR.
+ * To include the defines for DDR PHY
+ * Images.
+ */
+#include <tbbr_img_def.h>
+
+#include <policy.h>
+#include <soc.h>
+
+#define NXP_SPD_EEPROM0		0x51
+
+#define NXP_SYSCLK_FREQ		100000000
+#define NXP_DDRCLK_FREQ		100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR	NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE	115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE	0x2000
+#else
+#define PLATFORM_STACK_SIZE	0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE	0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE	(0x00100000)
+#define NXP_SD_BLOCK_BUF_ADDR	ULL(0x80000000)
+
+#define BL2_LIMIT		(NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES		U(3)
+#define MAX_IO_BLOCK_DEVICES	U(1)
+#define MAX_IO_HANDLES		U(4)
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES		U(2)
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES		U(1)
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER	29
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_LEVEL)
+
+#define PLAT_LS_G0_IRQ_PROPS(grp)
+
+#endif
diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/platform.c b/plat/nxp/soc-ls1046a/ls1046aqds/platform.c
new file mode 100644
index 0000000..cef920f
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046aqds/platform.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+	return true;
+#else
+	return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+	return true;
+#else
+	return false;
+#endif
+}
diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/platform.mk b/plat/nxp/soc-ls1046a/ls1046aqds/platform.mk
new file mode 100644
index 0000000..9600b93
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046aqds/platform.mk
@@ -0,0 +1,39 @@
+#
+# Copyright 2018-2022 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+BOOT_MODE	?=	qspi
+BOARD		:=	ls1046aqds
+POVDD_ENABLE	:=	no
+
+ # DDR Compilation Configs
+NUM_OF_DDRC	:=	1
+DDRC_NUM_DIMM	:=	1
+DDRC_NUM_CS	:=	4
+DDR_ECC_EN	:=	yes
+CONFIG_STATIC_DDR := 0
+
+# On-Board Flash Details
+QSPI_FLASH_SZ	:=	0x20000000
+NOR_FLASH_SZ	:=	0x20000000
+
+# Platform specific features.
+WARM_BOOT	:=	no
+
+# Adding Platform files build files
+BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
+			${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE	:=	qspi	\
+				sd	\
+				nor	\
+				nand
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
+include plat/nxp/soc-ls1046a/soc.mk
diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/platform_def.h b/plat/nxp/soc-ls1046a/ls1046aqds/platform_def.h
new file mode 100644
index 0000000..7f98bb1
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046aqds/platform_def.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat_def.h>
+#include <plat_default_def.h>
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/policy.h b/plat/nxp/soc-ls1046a/ls1046aqds/policy.h
new file mode 100644
index 0000000..c6c325f
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046aqds/policy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef POLICY_H
+#define	POLICY_H
+
+/* Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+#endif /* POLICY_H */
diff --git a/plat/nxp/soc-ls1046a/ls1046ardb/ddr_init.c b/plat/nxp/soc-ls1046a/ls1046ardb/ddr_init.c
new file mode 100644
index 0000000..b9940cf
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046ardb/ddr_init.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+
+#include <errata.h>
+#include <platform_def.h>
+
+#ifdef CONFIG_STATIC_DDR
+const struct ddr_cfg_regs static_2100 = {
+	.cs[0].config = U(0x80040322),
+	.cs[0].bnds = U(0x1FF),
+	.cs[1].config = U(0x80000322),
+	.cs[1].bnds = U(0x1FF),
+	.sdram_cfg[0] = U(0xE5004000),
+	.sdram_cfg[1] = U(0x401151),
+	.timing_cfg[0] = U(0xD1770018),
+	.timing_cfg[1] = U(0xF2FC9245),
+	.timing_cfg[2] = U(0x594197),
+	.timing_cfg[3] = U(0x2101100),
+	.timing_cfg[4] = U(0x220002),
+	.timing_cfg[5] = U(0x5401400),
+	.timing_cfg[7] = U(0x26600000),
+	.timing_cfg[8] = U(0x5446A00),
+	.dq_map[0] = U(0x32C57554),
+	.dq_map[1] = U(0xD4BB0BD4),
+	.dq_map[2] = U(0x2EC2F554),
+	.dq_map[3] = U(0xD95D4001),
+	.sdram_mode[0] = U(0x3010631),
+	.sdram_mode[1] = U(0x100200),
+	.sdram_mode[9] = U(0x8400000),
+	.sdram_mode[8] = U(0x500),
+	.sdram_mode[2] = U(0x10631),
+	.sdram_mode[3] = U(0x100200),
+	.sdram_mode[10] = U(0x400),
+	.sdram_mode[11] = U(0x8400000),
+	.sdram_mode[4] = U(0x10631),
+	.sdram_mode[5] = U(0x100200),
+	.sdram_mode[12] = U(0x400),
+	.sdram_mode[13] = U(0x8400000),
+	.sdram_mode[6] = U(0x10631),
+	.sdram_mode[7] = U(0x100200),
+	.sdram_mode[14] = U(0x400),
+	.sdram_mode[15] = U(0x8400000),
+	.interval = U(0x1FFE07FF),
+	.zq_cntl = U(0x8A090705),
+	.clk_cntl = U(0x2000000),
+	.cdr[0] = U(0x80040000),
+	.cdr[1] = U(0xC1),
+	.wrlvl_cntl[0] = U(0x86750609),
+	.wrlvl_cntl[1] = U(0xA0B0C0D),
+	.wrlvl_cntl[2] = U(0xF10110E),
+};
+
+const struct ddr_cfg_regs static_1800 = {
+	.cs[0].config = U(0x80040322),
+	.cs[0].bnds = U(0x1FF),
+	.cs[1].config = U(0x80000322),
+	.cs[1].bnds = U(0x1FF),
+	.sdram_cfg[0] = U(0xE5004000),
+	.sdram_cfg[1] = U(0x401151),
+	.timing_cfg[0] = U(0x91660018),
+	.timing_cfg[1] = U(0xDDD82045),
+	.timing_cfg[2] = U(0x512153),
+	.timing_cfg[3] = U(0x10E1100),
+	.timing_cfg[4] = U(0x220002),
+	.timing_cfg[5] = U(0x4401400),
+	.timing_cfg[7] = U(0x14400000),
+	.timing_cfg[8] = U(0x3335900),
+	.dq_map[0] = U(0x32C57554),
+	.dq_map[1] = U(0xD4BB0BD4),
+	.dq_map[2] = U(0x2EC2F554),
+	.dq_map[3] = U(0xD95D4001),
+	.sdram_mode[0] = U(0x3010421),
+	.sdram_mode[1] = U(0x80200),
+	.sdram_mode[9] = U(0x4400000),
+	.sdram_mode[8] = U(0x500),
+	.sdram_mode[2] = U(0x10421),
+	.sdram_mode[3] = U(0x80200),
+	.sdram_mode[10] = U(0x400),
+	.sdram_mode[11] = U(0x4400000),
+	.sdram_mode[4] = U(0x10421),
+	.sdram_mode[5] = U(0x80200),
+	.sdram_mode[12] = U(0x400),
+	.sdram_mode[13] = U(0x4400000),
+	.sdram_mode[6] = U(0x10421),
+	.sdram_mode[7] = U(0x80200),
+	.sdram_mode[14] = U(0x400),
+	.sdram_mode[15] = U(0x4400000),
+	.interval = U(0x1B6C06DB),
+	.zq_cntl = U(0x8A090705),
+	.clk_cntl = U(0x2000000),
+	.cdr[0] = U(0x80040000),
+	.cdr[1] = U(0xC1),
+	.wrlvl_cntl[0] = U(0x86750607),
+	.wrlvl_cntl[1] = U(0x8090A0B),
+	.wrlvl_cntl[2] = U(0xD0E0F0C),
+};
+
+const struct ddr_cfg_regs static_1600 = {
+	.cs[0].config = U(0x80040322),
+	.cs[0].bnds = U(0x1FF),
+	.cs[1].config = U(0x80000322),
+	.cs[1].bnds = U(0x1FF),
+	.sdram_cfg[0] = U(0xE5004000),
+	.sdram_cfg[1] = U(0x401151),
+	.sdram_cfg[2] = U(0x0),
+	.timing_cfg[0] = U(0x91550018),
+	.timing_cfg[1] = U(0xBAB48E44),
+	.timing_cfg[2] = U(0x490111),
+	.timing_cfg[3] = U(0x10C1000),
+	.timing_cfg[4] = U(0x220002),
+	.timing_cfg[5] = U(0x3401400),
+	.timing_cfg[6] = U(0x0),
+	.timing_cfg[7] = U(0x13300000),
+	.timing_cfg[8] = U(0x1224800),
+	.timing_cfg[9] = U(0x0),
+	.dq_map[0] = U(0x32C57554),
+	.dq_map[1] = U(0xD4BB0BD4),
+	.dq_map[2] = U(0x2EC2F554),
+	.dq_map[3] = U(0xD95D4001),
+	.sdram_mode[0] = U(0x3010211),
+	.sdram_mode[1] = U(0x0),
+	.sdram_mode[9] = U(0x400000),
+	.sdram_mode[8] = U(0x500),
+	.sdram_mode[2] = U(0x10211),
+	.sdram_mode[3] = U(0x0),
+	.sdram_mode[10] = U(0x400),
+	.sdram_mode[11] = U(0x400000),
+	.sdram_mode[4] = U(0x10211),
+	.sdram_mode[5] = U(0x0),
+	.sdram_mode[12] = U(0x400),
+	.sdram_mode[13] = U(0x400000),
+	.sdram_mode[6] = U(0x10211),
+	.sdram_mode[7] = U(0x0),
+	.sdram_mode[14] = U(0x400),
+	.sdram_mode[15] = U(0x400000),
+	.interval = U(0x18600618),
+	.zq_cntl = U(0x8A090705),
+	.ddr_sr_cntr = U(0x0),
+	.clk_cntl = U(0x2000000),
+	.cdr[0] = U(0x80040000),
+	.cdr[1] = U(0xC1),
+	.wrlvl_cntl[0] = U(0x86750607),
+	.wrlvl_cntl[1] = U(0x8090A0B),
+	.wrlvl_cntl[2] = U(0xD0E0F0C),
+};
+
+struct static_table {
+	unsigned long rate;
+	const struct ddr_cfg_regs *regs;
+};
+
+const struct static_table table[] = {
+	{1600, &static_1600},
+	{1800, &static_1800},
+	{2100, &static_2100},
+};
+
+long long board_static_ddr(struct ddr_info *priv)
+{
+	const unsigned long clk = priv->clk / 1000000;
+	long long size = 0;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(table); i++) {
+		if (table[i].rate >= clk) {
+			break;
+		}
+	}
+	if (i < ARRAY_SIZE(table)) {
+		VERBOSE("Found static setting for rate %ld\n", table[i].rate);
+		memcpy(&priv->ddr_reg, table[i].regs,
+		       sizeof(struct ddr_cfg_regs));
+		size = 0x200000000UL;
+	} else {
+		ERROR("Not static settings for rate %ld\n", clk);
+	}
+
+	return size;
+}
+#else /* ifndef CONFIG_STATIC_DDR */
+static const struct rc_timing rce[] = {
+	{U(1600), U(8), U(7)},
+	{U(1867), U(8), U(7)},
+	{U(2134), U(8), U(9)},
+	{}
+};
+
+static const struct board_timing udimm[] = {
+	{U(0x04), rce, U(0x01020304), U(0x06070805)},
+	{U(0x1f), rce, U(0x01020304), U(0x06070805)},
+};
+
+int ddr_board_options(struct ddr_info *priv)
+{
+	int ret;
+	struct memctl_opt *popts = &priv->opt;
+
+	if (popts->rdimm) {
+		debug("RDIMM parameters not set.\n");
+		return -EINVAL;
+	}
+
+	ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm));
+	if (ret != 0) {
+		return ret;
+	}
+
+	popts->wrlvl_override = U(1);
+	popts->wrlvl_sample = U(0x0);	/* 32 clocks */
+	popts->cpo_sample = U(0x61);
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN	|
+			  DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm)	|
+			  DDR_CDR2_VREF_TRAIN_EN		|
+			  DDR_CDR2_VREF_RANGE_2;
+	popts->bstopre = U(0);
+
+	return 0;
+}
+#endif /* ifdef CONFIG_STATIC_DDR */
+
+long long init_ddr(void)
+{
+	int spd_addr[] = {NXP_SPD_EEPROM0};
+	struct ddr_info info;
+	struct sysinfo sys;
+	long long dram_size;
+
+	zeromem(&sys, sizeof(sys));
+	if (get_clocks(&sys)) {
+		ERROR("System clocks are not set\n");
+		assert(0);
+	}
+	debug("platform clock %lu\n", sys.freq_platform);
+	debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+	debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+	zeromem(&info, sizeof(struct ddr_info));
+	info.num_ctlrs = U(1);
+	info.dimm_on_ctlr = U(1);
+	info.clk = get_ddr_freq(&sys, 0);
+	info.spd_addr = spd_addr;
+	info.ddr[0] = (void *)NXP_DDR_ADDR;
+
+	dram_size = dram_init(&info);
+
+	if (dram_size < 0) {
+		ERROR("DDR init failed.\n");
+	}
+
+#ifdef ERRATA_SOC_A008850
+	erratum_a008850_post();
+#endif
+
+	return dram_size;
+}
diff --git a/plat/nxp/soc-ls1046a/ls1046ardb/plat_def.h b/plat/nxp/soc-ls1046a/ls1046ardb/plat_def.h
new file mode 100644
index 0000000..b5e66ae
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046ardb/plat_def.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+/*
+ * Required without TBBR.
+ * To include the defines for DDR PHY Images.
+ */
+#include <tbbr_img_def.h>
+
+#include "policy.h"
+#include <soc.h>
+
+#define NXP_SPD_EEPROM0		0x51
+
+#define NXP_SYSCLK_FREQ		100000000
+#define NXP_DDRCLK_FREQ		100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR	NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE	115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE	0x2000
+#else
+#define PLATFORM_STACK_SIZE	0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE	0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE	(0x00100000)
+#define NXP_SD_BLOCK_BUF_ADDR	ULL(0x80000000)
+
+#define BL2_LIMIT		(NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES		U(3)
+#define MAX_IO_BLOCK_DEVICES	U(1)
+#define MAX_IO_HANDLES		U(4)
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES		U(2)
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES		U(1)
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER	29
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_LEVEL)
+
+#define PLAT_LS_G0_IRQ_PROPS(grp)
+
+#endif /* PLAT_DEF_H */
diff --git a/plat/nxp/soc-ls1046a/ls1046ardb/platform.c b/plat/nxp/soc-ls1046a/ls1046ardb/platform.c
new file mode 100644
index 0000000..cef920f
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046ardb/platform.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+	return true;
+#else
+	return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+	return true;
+#else
+	return false;
+#endif
+}
diff --git a/plat/nxp/soc-ls1046a/ls1046ardb/platform.mk b/plat/nxp/soc-ls1046a/ls1046ardb/platform.mk
new file mode 100644
index 0000000..32e6db5
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046ardb/platform.mk
@@ -0,0 +1,38 @@
+#
+# Copyright 2018-2022 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+BOOT_MODE	?=	qspi
+BOARD		:=	ls1046ardb
+POVDD_ENABLE	:=	no
+
+# DDR Compilation Configs
+NUM_OF_DDRC	:=	1
+DDRC_NUM_DIMM	:=	1
+DDRC_NUM_CS	:=	4
+DDR_ECC_EN	:=	yes
+CONFIG_STATIC_DDR := 0
+
+# On-Board Flash Details
+QSPI_FLASH_SZ	:=	0x20000000
+NOR_FLASH_SZ	:=	0x20000000
+
+# Platform specific features.
+WARM_BOOT	:=	no
+
+# Adding Platform files build files
+BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
+			${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE	:=	qspi	\
+				sd	\
+				emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
+include plat/nxp/soc-ls1046a/soc.mk
diff --git a/plat/nxp/soc-ls1046a/ls1046ardb/platform_def.h b/plat/nxp/soc-ls1046a/ls1046ardb/platform_def.h
new file mode 100644
index 0000000..7f98bb1
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046ardb/platform_def.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat_def.h>
+#include <plat_default_def.h>
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/nxp/soc-ls1046a/ls1046ardb/policy.h b/plat/nxp/soc-ls1046a/ls1046ardb/policy.h
new file mode 100644
index 0000000..c6c325f
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046ardb/policy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef POLICY_H
+#define	POLICY_H
+
+/* Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+#endif /* POLICY_H */
diff --git a/plat/nxp/soc-ls1046a/soc.c b/plat/nxp/soc-ls1046a/soc.c
new file mode 100644
index 0000000..d17e672
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/soc.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <caam.h>
+#include <cassert.h>
+#include <cci.h>
+#include <common/debug.h>
+#include <dcfg.h>
+#ifdef I2C_INIT
+#include <i2c.h>
+#endif
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <ls_interconnect.h>
+#ifdef POLICY_FUSE_PROVISION
+#include <nxp_gpio.h>
+#endif
+#if TRUSTED_BOARD_BOOT
+#include <nxp_smmu.h>
+#endif
+#include <nxp_timer.h>
+#include <plat_console.h>
+#include <plat_gic.h>
+#include <plat_tzc400.h>
+#include <scfg.h>
+#if defined(NXP_SFP_ENABLED)
+#include <sfp.h>
+#endif
+
+#include <errata.h>
+#include <ns_access.h>
+#ifdef CONFIG_OCRAM_ECC_EN
+#include <ocram.h>
+#endif
+#include <plat_common.h>
+#include <platform_def.h>
+#include <soc.h>
+
+static dcfg_init_info_t dcfg_init_data = {
+	.g_nxp_dcfg_addr = NXP_DCFG_ADDR,
+	.nxp_sysclk_freq = NXP_SYSCLK_FREQ,
+	.nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
+	.nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
+};
+
+/* Function to return the SoC SYS CLK  */
+static unsigned int get_sys_clk(void)
+{
+	return NXP_SYSCLK_FREQ;
+}
+
+/*
+ * Function returns the base counter frequency
+ * after reading the first entry at CNTFID0 (0x20 offset).
+ *
+ * Function is used by:
+ *   1. ARM common code for PSCI management.
+ *   2. ARM Generic Timer init.
+ *
+ */
+unsigned int plat_get_syscnt_freq2(void)
+{
+	unsigned int counter_base_frequency;
+
+	counter_base_frequency = get_sys_clk() / 4;
+
+	return counter_base_frequency;
+}
+
+#ifdef IMAGE_BL2
+/* Functions for BL2 */
+
+static struct soc_type soc_list[] =  {
+	SOC_ENTRY(LS1046A, LS1046A, 1, 4),
+	SOC_ENTRY(LS1046AE, LS1046AE, 1, 4),
+	SOC_ENTRY(LS1026A, LS1026A, 1, 2),
+	SOC_ENTRY(LS1026AE, LS1026AE, 1, 2),
+};
+
+#ifdef POLICY_FUSE_PROVISION
+static gpio_init_info_t gpio_init_data = {
+	.gpio1_base_addr = NXP_GPIO1_ADDR,
+	.gpio2_base_addr = NXP_GPIO2_ADDR,
+	.gpio3_base_addr = NXP_GPIO3_ADDR,
+	.gpio4_base_addr = NXP_GPIO4_ADDR,
+};
+#endif
+
+/*
+ * Function to set the base counter frequency at
+ * the first entry of the Frequency Mode Table,
+ * at CNTFID0 (0x20 offset).
+ *
+ * Set the value of the pirmary core register cntfrq_el0.
+ */
+static void set_base_freq_CNTFID0(void)
+{
+	/*
+	 * Below register specifies the base frequency of the system counter.
+	 * As per NXP Board Manuals:
+	 * The system counter always works with SYS_REF_CLK/4 frequency clock.
+	 */
+	unsigned int counter_base_frequency = get_sys_clk() / 4;
+
+	/* Setting the frequency in the Frequency modes table.
+	 *
+	 * Note: The value for ls1046ardb board at this offset
+	 *       is not RW as stated. This offset have the
+	 *       fixed value of 100000400 Hz.
+	 *
+	 * The below code line has no effect.
+	 * Keeping it for other platforms where it has effect.
+	 */
+	mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency);
+
+	write_cntfrq_el0(counter_base_frequency);
+}
+
+void soc_preload_setup(void)
+{
+
+}
+
+/*
+ * This function implements soc specific erratas
+ * This is called before DDR is initialized or MMU is enabled
+ */
+void soc_early_init(void)
+{
+	uint8_t num_clusters, cores_per_cluster;
+	dram_regions_info_t *dram_regions_info = get_dram_regions_info();
+
+#ifdef CONFIG_OCRAM_ECC_EN
+	ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
+#endif
+	dcfg_init(&dcfg_init_data);
+#ifdef POLICY_FUSE_PROVISION
+	gpio_init(&gpio_init_data);
+	sec_init(NXP_CAAM_ADDR);
+#endif
+#if LOG_LEVEL > 0
+	/* Initialize the console to provide early debug support */
+
+	plat_console_init(NXP_CONSOLE_ADDR,
+				NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
+#endif
+	set_base_freq_CNTFID0();
+
+	/* Enable snooping on SEC read and write transactions */
+	scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET),
+			SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP);
+
+	/*
+	 * Initialize Interconnect for this cluster during cold boot.
+	 * No need for locks as no other CPU is active.
+	 */
+	cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
+
+	/*
+	 * Enable Interconnect coherency for the primary CPU's cluster.
+	 */
+	get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
+	plat_ls_interconnect_enter_coherency(num_clusters);
+
+#if TRUSTED_BOARD_BOOT
+	uint32_t mode;
+
+	sfp_init(NXP_SFP_ADDR);
+	/*
+	 * For secure boot disable SMMU.
+	 * Later when platform security policy comes in picture,
+	 * this might get modified based on the policy
+	 */
+	if (check_boot_mode_secure(&mode) == true) {
+		bypass_smmu(NXP_SMMU_ADDR);
+	}
+
+	/*
+	 * For Mbedtls currently crypto is not supported via CAAM
+	 * enable it when that support is there. In tbbr.mk
+	 * the CAAM_INTEG is set as 0.
+	 */
+#ifndef MBEDTLS_X509
+	/* Initialize the crypto accelerator if enabled */
+	if (is_sec_enabled() == false) {
+		INFO("SEC is disabled.\n");
+	} else {
+		sec_init(NXP_CAAM_ADDR);
+	}
+#endif
+#elif defined(POLICY_FUSE_PROVISION)
+	gpio_init(&gpio_init_data);
+	sfp_init(NXP_SFP_ADDR);
+	sec_init(NXP_CAAM_ADDR);
+#endif
+
+	soc_errata();
+
+	/* Initialize system level generic timer for Layerscape Socs. */
+	delay_timer_init(NXP_TIMER_ADDR);
+
+#ifdef DDR_INIT
+	i2c_init(NXP_I2C_ADDR);
+	dram_regions_info->total_dram_size = init_ddr();
+#endif
+}
+
+void soc_bl2_prepare_exit(void)
+{
+#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
+	set_sfp_wr_disable();
+#endif
+}
+
+/* This function returns the boot device based on RCW_SRC */
+enum boot_device get_boot_dev(void)
+{
+	enum boot_device src = BOOT_DEVICE_NONE;
+	uint32_t porsr1;
+	uint32_t rcw_src, val;
+
+	porsr1 = read_reg_porsr1();
+
+	rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
+
+	val = rcw_src & RCW_SRC_NAND_MASK;
+
+	if (val == RCW_SRC_NAND_VAL) {
+		val = rcw_src & NAND_RESERVED_MASK;
+		if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
+			src = BOOT_DEVICE_IFC_NAND;
+			INFO("RCW BOOT SRC is IFC NAND\n");
+		}
+	} else {
+		/* RCW SRC NOR */
+		val = rcw_src & RCW_SRC_NOR_MASK;
+		if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
+			src = BOOT_DEVICE_IFC_NOR;
+			INFO("RCW BOOT SRC is IFC NOR\n");
+		} else {
+			switch (rcw_src) {
+			case QSPI_VAL1:
+			case QSPI_VAL2:
+				src = BOOT_DEVICE_QSPI;
+				INFO("RCW BOOT SRC is QSPI\n");
+				break;
+			case SD_VAL:
+				src = BOOT_DEVICE_EMMC;
+				INFO("RCW BOOT SRC is SD/EMMC\n");
+				break;
+			default:
+				src = BOOT_DEVICE_NONE;
+			}
+		}
+	}
+
+	return src;
+}
+
+/* This function sets up access permissions on memory regions */
+void soc_mem_access(void)
+{
+	dram_regions_info_t *info_dram_regions = get_dram_regions_info();
+	struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
+	unsigned int dram_idx, index = 0U;
+
+	for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions;
+			dram_idx++) {
+		if (info_dram_regions->region[dram_idx].size == 0) {
+			ERROR("DDR init failure, or");
+			ERROR("DRAM regions not populated correctly.\n");
+			break;
+		}
+
+		index = populate_tzc400_reg_list(tzc400_reg_list,
+				dram_idx, index,
+				info_dram_regions->region[dram_idx].addr,
+				info_dram_regions->region[dram_idx].size,
+				NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
+	}
+
+	mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list);
+}
+
+#else /* IMAGE_BL2 */
+/* Functions for BL31 */
+
+const unsigned char _power_domain_tree_desc[] = {1, 1, 4};
+
+CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
+		assert_invalid_ls1046_cluster_count);
+
+/* This function returns the SoC topology */
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return _power_domain_tree_desc;
+}
+
+/*
+ * This function returns the core count within the cluster corresponding to
+ * `mpidr`.
+ */
+unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
+{
+	return CORES_PER_CLUSTER;
+}
+
+void soc_early_platform_setup2(void)
+{
+	dcfg_init(&dcfg_init_data);
+	/* Initialize system level generic timer for SoCs */
+	delay_timer_init(NXP_TIMER_ADDR);
+
+#if LOG_LEVEL > 0
+	/* Initialize the console to provide early debug support */
+	plat_console_init(NXP_CONSOLE_ADDR,
+				NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
+#endif
+}
+
+void soc_platform_setup(void)
+{
+	static uint32_t target_mask_array[PLATFORM_CORE_COUNT];
+	/*
+	 * On a GICv2 system, the Group 1 secure interrupts are treated
+	 * as Group 0 interrupts.
+	 */
+	static interrupt_prop_t ls_interrupt_props[] = {
+		PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
+		PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
+	};
+
+	plat_ls_gic_driver_init(
+#if (TEST_BL31)
+	/* Defect in simulator - GIC base addresses (4Kb aligned) */
+			NXP_GICD_4K_ADDR,
+			NXP_GICC_4K_ADDR,
+#else
+			NXP_GICD_64K_ADDR,
+			NXP_GICC_64K_ADDR,
+#endif
+			PLATFORM_CORE_COUNT,
+			ls_interrupt_props,
+			ARRAY_SIZE(ls_interrupt_props),
+			target_mask_array);
+
+	plat_ls_gic_init();
+	enable_init_timer();
+}
+
+/* This function initializes the soc from the BL31 module */
+void soc_init(void)
+{
+	 /* low-level init of the soc */
+	soc_init_lowlevel();
+	_init_global_data();
+	soc_init_percpu();
+	_initialize_psci();
+
+	/*
+	 * Initialize the interconnect during cold boot.
+	 * No need for locks as no other CPU is active.
+	 */
+	cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
+
+	/*
+	 * Enable coherency in interconnect for the primary CPU's cluster.
+	 * Earlier bootloader stages might already do this but we can't
+	 * assume so. No harm in executing this code twice.
+	 */
+	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+
+	/* Init CSU to enable non-secure access to peripherals */
+	enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR);
+
+	/* Initialize the crypto accelerator if enabled */
+	if (is_sec_enabled() == false) {
+		INFO("SEC is disabled.\n");
+	} else {
+		sec_init(NXP_CAAM_ADDR);
+	}
+}
+
+void soc_runtime_setup(void)
+{
+
+}
+
+#endif /* IMAGE_BL2 */
diff --git a/plat/nxp/soc-ls1046a/soc.def b/plat/nxp/soc-ls1046a/soc.def
new file mode 100644
index 0000000..e6b37c0
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/soc.def
@@ -0,0 +1,107 @@
+#
+# Copyright 2022 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# This file contains the basic architecture definitions that drive the build
+#
+# -----------------------------------------------------------------------------
+
+CORE_TYPE	:=	a72
+
+CACHE_LINE	:=	6
+
+# set to GIC400 or GIC500
+GIC		:=	GIC400
+
+# set to CCI400 or CCN504 or CCN508
+INTERCONNECT	:=	CCI400
+
+# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
+CHASSIS		:=	2
+
+# TZC IP Details TZC used is TZC380 or TZC400
+TZC_ID		:=	TZC400
+
+# CONSOLE Details available is NS16550 or PL011
+CONSOLE		:=	NS16550
+
+ # Select the DDR PHY generation to be used
+PLAT_DDR_PHY	:=      PHY_GEN1
+
+PHYS_SYS	:=	64
+
+# ddr controller - set to MMDC or NXP
+DDRCNTLR	:=	NXP
+
+# ddr phy - set to NXP or SNPS
+DDRPHY		:=	NXP
+
+# Area of OCRAM reserved by ROM code
+NXP_ROM_RSVD	:= 0x5900
+
+# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
+# Input to CST create_hdr_esbc tool
+CSF_HDR_SZ	:= 0x3000
+
+# In IMAGE_BL2, compile time flag for handling Cache coherency
+# with CAAM for BL2 running from OCRAM
+SEC_MEM_NON_COHERENT	:= yes
+
+# OCRAM MAP
+OCRAM_START_ADDR	:=	0x10000000
+OCRAM_SIZE		:=	0x20000
+
+# BL2 binary is placed at  start of OCRAM.
+# Also used by create_pbl.mk.
+BL2_BASE		:=	0x10000000
+
+# After BL2 bin, OCRAM is used by ROM Code:
+# (OCRAM_START_ADDR + BL2_BIN_SIZE) ->  (NXP_ROM_RSVD - 1)
+
+# After ROM Code, OCRAM is used by CSF header.
+# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1)
+
+# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ)
+# This value should be greater than BL2_TEXT_LIMIT
+# Input to CST create_hdr_isbc tool
+BL2_HDR_LOC_HDR		?=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ))))
+# Covert to HEX to be used by create_pbl.mk
+BL2_HDR_LOC		:=	$$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
+
+# Core Errata
+ERRATA_A72_859971	:=	1
+
+# SoC ERRATAS
+ERRATA_SOC_A008850	:=      1
+ERRATA_SOC_A010539	:= 	1
+
+# DDR Errata
+ERRATA_DDR_A008511	:=	1
+ERRATA_DDR_A009803	:=	1
+ERRATA_DDR_A009942	:=	1
+ERRATA_DDR_A010165	:=	1
+
+# enable dynamic memory mapping
+PLAT_XLAT_TABLES_DYNAMIC :=	1
+
+# Define Endianness of each module
+NXP_GUR_ENDIANNESS	:=	BE
+NXP_DDR_ENDIANNESS	:=	BE
+NXP_SEC_ENDIANNESS	:=	BE
+NXP_SFP_ENDIANNESS	:=	BE
+NXP_SNVS_ENDIANNESS	:=	BE
+NXP_ESDHC_ENDIANNESS	:=	BE
+NXP_QSPI_ENDIANNESS	:=	BE
+NXP_FSPI_ENDIANNESS	:=	BE
+NXP_SCFG_ENDIANNESS	:=	BE
+NXP_GPIO_ENDIANNESS	:=	BE
+NXP_IFC_ENDIANNESS	:=	BE
+
+NXP_SFP_VER		:= 3_2
+
+# OCRAM ECC Enabled
+OCRAM_ECC_EN		:=	yes
diff --git a/plat/nxp/soc-ls1046a/soc.mk b/plat/nxp/soc-ls1046a/soc.mk
new file mode 100644
index 0000000..8207dcd
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/soc.mk
@@ -0,0 +1,114 @@
+#
+# Copyright 2018-2022 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# SoC-specific build parameters
+SOC		:=	ls1046a
+PLAT_PATH	:=	plat/nxp
+PLAT_COMMON_PATH:=	plat/nxp/common
+PLAT_DRIVERS_PATH:=	drivers/nxp
+PLAT_SOC_PATH	:=	${PLAT_PATH}/soc-${SOC}
+BOARD_PATH	:=	${PLAT_SOC_PATH}/${BOARD}
+
+# Get SoC-specific defnitions
+include ${PLAT_SOC_PATH}/soc.def
+include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
+include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
+
+# For Security Features
+DISABLE_FUSE_WRITE	:= 1
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
+SECURE_BOOT	:= yes
+endif
+$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
+
+# Selecting Drivers for SoC
+$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,CSU_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
+$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
+
+# Selecting PSCI & SIP_SVC support
+$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
+$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
+
+# Source File Addition
+PLAT_INCLUDES		+=	-I${PLAT_COMMON_PATH}/include/default\
+				-I${BOARD_PATH}\
+				-I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
+				-I${PLAT_SOC_PATH}/include\
+				-I${PLAT_COMMON_PATH}/soc_errata
+
+ifeq (${SECURE_BOOT},yes)
+include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
+endif
+
+ifeq ($(WARM_BOOT),yes)
+include ${PLAT_COMMON_PATH}/warm_reset/warm_reset.mk
+endif
+
+ifeq (${NXP_NV_SW_MAINT_LAST_EXEC_DATA}, yes)
+include ${PLAT_COMMON_PATH}/nv_storage/nv_storage.mk
+endif
+
+ifeq (${PSCI_NEEDED}, yes)
+include ${PLAT_COMMON_PATH}/psci/psci.mk
+endif
+
+ifeq (${SIPSVC_NEEDED}, yes)
+include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
+endif
+
+# For fuse-fip & fuse-programming
+ifeq (${FUSE_PROG}, 1)
+include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
+endif
+
+ifeq (${IMG_LOADR_NEEDED},yes)
+include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
+endif
+
+# Adding source files for the above selected drivers.
+include ${PLAT_DRIVERS_PATH}/drivers.mk
+
+# Adding SoC specific files
+include ${PLAT_COMMON_PATH}/soc_errata/errata.mk
+
+PLAT_INCLUDES		+=	${NV_STORAGE_INCLUDES}\
+				${WARM_RST_INCLUDES}
+
+BL31_SOURCES		+=	${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
+				${WARM_RST_BL31_SOURCES}\
+				${PSCI_SOURCES}\
+				${SIPSVC_SOURCES}\
+				${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
+
+PLAT_BL_COMMON_SOURCES	+=	${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
+				${PLAT_SOC_PATH}/aarch64/${SOC}_helpers.S\
+				${NV_STORAGE_SOURCES}\
+				${WARM_RST_BL_COMM_SOURCES}\
+				${PLAT_SOC_PATH}/soc.c
+
+ifeq (${TEST_BL31}, 1)
+BL31_SOURCES		+=	${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S\
+				${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
+endif
+
+BL2_SOURCES		+=	${DDR_CNTLR_SOURCES}\
+				${TBBR_SOURCES}\
+				${FUSE_SOURCES}
+
+# Adding TFA setup files
+include ${PLAT_PATH}/common/setup/common.mk
diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
index 4679fc2..cc679f2 100644
--- a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
+++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
@@ -563,14 +563,6 @@
  */
 func _soc_sys_off
 
-	/* A-009810: LPM20 entry sequence might cause
-	 * spurious timeout reset request
-	 * workaround: MASK RESET REQ RPTOE
-	 */
-	ldr  x0, =NXP_RESET_ADDR
-	ldr  w1, =RSTRQMR_RPTOE_MASK
-	str  w1, [x0, #RST_RSTRQMR1_OFFSET]
-
 	/* disable sec, QBman, spi and qspi */
 	ldr  x2, =NXP_DCFG_ADDR
 	ldr  x0, =DCFG_DEVDISR1_OFFSET
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 8d4320a..ca2bad8 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -16,11 +16,6 @@
 # If it is set to 0, then FIP is used
 STM32MP_USE_STM32IMAGE	?=	0
 
-ifneq ($(STM32MP_USE_STM32IMAGE),1)
-ENABLE_PIE		:=	1
-BL2_IN_XIP_MEM		:=	1
-endif
-
 # Please don't increment this value without good understanding of
 # the monotonic counter
 STM32_TF_VERSION	?=	0
@@ -38,6 +33,7 @@
 endif
 
 TF_CFLAGS		+=	-Wsign-compare
+TF_CFLAGS		+=	-Wformat-signedness
 
 # Not needed for Cortex-A7
 WORKAROUND_CVE_2017_5715:=	0
diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
index 239b60a..b506e95 100644
--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
+++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
@@ -1,11 +1,17 @@
 #
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 SP_MIN_WITH_SECURE_FIQ	:=	1
 
+ifneq ($(STM32MP_USE_STM32IMAGE),1)
+override ENABLE_PIE	:=	1
+BL32_CFLAGS		+=	-fpie -DENABLE_PIE
+BL32_LDFLAGS		+=	$(PIE_LDFLAGS)
+endif
+
 BL32_CFLAGS		+=	-DSTM32MP_SHARED_RESOURCES
 
 BL32_SOURCES		+=	drivers/st/etzpc/etzpc.c			\
diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c
index 27dbf4e..b05de1c 100644
--- a/plat/st/stm32mp1/stm32mp1_boot_device.c
+++ b/plat/st/stm32mp1/stm32mp1_boot_device.c
@@ -115,8 +115,8 @@
 		}
 	}
 
-	VERBOSE("OTP: Block %i Page %i Size %lli\n", nand_dev->block_size,
-	     nand_dev->page_size, nand_dev->size);
+	VERBOSE("OTP: Block %u Page %u Size %llu\n", nand_dev->block_size,
+		nand_dev->page_size, nand_dev->size);
 
 	return 0;
 }
diff --git a/plat/st/stm32mp1/stm32mp1_shared_resources.c b/plat/st/stm32mp1/stm32mp1_shared_resources.c
index 6b1bcaa..a0ca697 100644
--- a/plat/st/stm32mp1/stm32mp1_shared_resources.c
+++ b/plat/st/stm32mp1/stm32mp1_shared_resources.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,12 +7,11 @@
 #include <assert.h>
 #include <stdint.h>
 
-#include <platform_def.h>
-
 #include <common/debug.h>
 #include <drivers/st/etzpc.h>
 #include <drivers/st/stm32_gpio.h>
 
+#include <platform_def.h>
 #include <stm32mp_shared_resources.h>
 
 /*
@@ -164,8 +163,8 @@
 	if ((id >= STM32MP1_SHRES_GPIOZ(0)) &&
 	    (id <= STM32MP1_SHRES_GPIOZ(7)) &&
 	    ((unsigned int)(id - STM32MP1_SHRES_GPIOZ(0)) >= get_gpioz_nbpin())) {
-		ERROR("Invalid GPIO pin %u, %u pin(s) available\n",
-		      id - STM32MP1_SHRES_GPIOZ(0), get_gpioz_nbpin());
+		ERROR("Invalid GPIO pin %d, %u pin(s) available\n",
+		      (int)(id - STM32MP1_SHRES_GPIOZ(0)), get_gpioz_nbpin());
 		panic();
 	}
 
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index f5de549..bfee2dd 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -688,16 +688,13 @@
 	case FFA_NOTIFICATION_GET:
 	case FFA_NOTIFICATION_INFO_GET:
 	case FFA_NOTIFICATION_INFO_GET_SMC64:
+	case FFA_MSG_SEND2:
 #endif
+	case FFA_MSG_RUN:
 		/*
-		 * Above calls should not be forwarded from Secure world to
-		 * Normal world.
-		 *
-		 * Fall through to forward the call to the other world
+		 * Above calls should be invoked only by the Normal world and
+		 * must not be forwarded from Secure world to Normal world.
 		 */
-	case FFA_MSG_RUN:
-		/* This interface must be invoked only by the Normal world */
-
 		if (secure_origin) {
 			return spmd_ffa_error_return(handle,
 						     FFA_ERROR_NOT_SUPPORTED);
diff --git a/tools/nxp/create_pbl/create_pbl.mk b/tools/nxp/create_pbl/create_pbl.mk
index b68882e..305c049 100644
--- a/tools/nxp/create_pbl/create_pbl.mk
+++ b/tools/nxp/create_pbl/create_pbl.mk
@@ -6,7 +6,7 @@
 #
 
 CREATE_PBL	?=	${CREATE_PBL_TOOL_PATH}/create_pbl${BIN_EXT}
-BYTE_SWAP	?=	${CREATE_PBL_PLAT_TOOL_PATH}/byte_swap${BIN_EXT}
+BYTE_SWAP	?=	${CREATE_PBL_TOOL_PATH}/byte_swap${BIN_EXT}
 
 HOST_GCC	:= gcc