Merge "refactor(ast2700): adopt RESET_TO_BL31 boot flow" into integration
diff --git a/bl31/ehf.c b/bl31/ehf.c
index b328380..6f3d941 100644
--- a/bl31/ehf.c
+++ b/bl31/ehf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -458,7 +458,7 @@
int ret __unused;
/* Ensure EL3 interrupts are supported */
- assert(plat_ic_has_interrupt_type(INTR_TYPE_EL3) != 0);
+ assert(plat_ic_has_interrupt_type(INTR_TYPE_EL3));
/*
* Make sure that priority water mark has enough bits to represent the
diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c
index b8cc3de..68c7f10 100644
--- a/bl31/interrupt_mgmt.c
+++ b/bl31/interrupt_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,9 +47,9 @@
******************************************************************************/
static int32_t validate_interrupt_type(uint32_t type)
{
- if ((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_NS) ||
- (type == INTR_TYPE_EL3))
+ if (plat_ic_has_interrupt_type(type)) {
return 0;
+ }
return -EINVAL;
}
diff --git a/changelog.yaml b/changelog.yaml
index 7e75832..cd514f7 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -902,6 +902,9 @@
- title: GIC-600AE
scope: gic600ae
+ - title: GICv2
+ scope: gicv2
+
- title: SMMU
scope: smmu
diff --git a/docs/components/platform-interrupt-controller-API.rst b/docs/components/platform-interrupt-controller-API.rst
index 069c87b..4de39d1 100644
--- a/docs/components/platform-interrupt-controller-API.rst
+++ b/docs/components/platform-interrupt-controller-API.rst
@@ -120,39 +120,39 @@
In case of Arm standard platforms using GIC, the implementation of the API
writes to GIC *Priority Register* set interrupt priority.
-Function: int plat_ic_has_interrupt_type(unsigned int type); [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function: bool plat_ic_has_interrupt_type(unsigned int type); [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
Argument : unsigned int
- Return : int
+ Return : bool
This API should return whether the platform supports a given interrupt type. The
parameter ``type`` shall be one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, or
``INTR_TYPE_NS``.
In case of Arm standard platforms using GICv3, the implementation of the API
-returns ``1`` for all interrupt types.
+returns *true* for all interrupt types.
-In case of Arm standard platforms using GICv2, the API always return ``1`` for
+In case of Arm standard platforms using GICv2, the API always return *true* for
``INTR_TYPE_NS``. Return value for other types depends on the value of build
option ``GICV2_G0_FOR_EL3``:
- For interrupt type ``INTR_TYPE_EL3``:
- - When ``GICV2_G0_FOR_EL3`` is ``0``, it returns ``0``, indicating no support
+ - When ``GICV2_G0_FOR_EL3`` is ``0``, it returns *false*, indicating no support
for EL3 interrupts.
- - When ``GICV2_G0_FOR_EL3`` is ``1``, it returns ``1``, indicating support for
+ - When ``GICV2_G0_FOR_EL3`` is ``1``, it returns *true*, indicating support for
EL3 interrupts.
- For interrupt type ``INTR_TYPE_S_EL1``:
- - When ``GICV2_G0_FOR_EL3`` is ``0``, it returns ``1``, indicating support for
+ - When ``GICV2_G0_FOR_EL3`` is ``0``, it returns *true*, indicating support for
Secure EL1 interrupts.
- - When ``GICV2_G0_FOR_EL3`` is ``1``, it returns ``0``, indicating no support
+ - When ``GICV2_G0_FOR_EL3`` is ``1``, it returns *false*, indicating no support
for Secure EL1 interrupts.
Function: void plat_ic_set_interrupt_type(unsigned int id, unsigned int type); [optional]
@@ -306,4 +306,4 @@
--------------
-*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.*
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index ca2a038..696bede 100644
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -390,7 +390,7 @@
* This function assigns group for the interrupt identified by id. The group can
* be any of GICV2_INTR_GROUP*
******************************************************************************/
-void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
+void gicv2_set_interrupt_group(unsigned int id, unsigned int group)
{
assert(driver_data != NULL);
assert(driver_data->gicd_base != 0U);
@@ -398,7 +398,7 @@
/* Serialize read-modify-write to Distributor registers */
spin_lock(&gic_lock);
- switch (type) {
+ switch (group) {
case GICV2_INTR_GROUP1:
gicd_set_igroupr(driver_data->gicd_base, id);
break;
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 2c74800..3c99517 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -421,16 +421,15 @@
}
/*******************************************************************************
- * This function returns the type of the interrupt id depending upon the group
- * this interrupt has been configured under by the interrupt controller i.e.
- * group0 or group1 Secure / Non Secure. The return value can be one of the
- * following :
+ * This function returns the group that has been configured under by the
+ * interrupt controller for the given interrupt id i.e. either group0 or group1
+ * Secure / Non Secure. The return value can be one of the following :
* INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
* INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
* INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
* interrupt.
******************************************************************************/
-unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num)
+unsigned int gicv3_get_interrupt_group(unsigned int id, unsigned int proc_num)
{
unsigned int igroup, grpmodr;
uintptr_t gicr_base;
@@ -1059,8 +1058,8 @@
* is used if the interrupt is SGI or (E)PPI, and programs the corresponding
* Redistributor interface. The group can be any of GICV3_INTR_GROUP*
******************************************************************************/
-void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
- unsigned int type)
+void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num,
+ unsigned int group)
{
bool igroup = false, grpmod = false;
uintptr_t gicr_base;
@@ -1071,7 +1070,7 @@
assert(proc_num < gicv3_driver_data->rdistif_num);
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
- switch (type) {
+ switch (group) {
case INTR_GROUP1S:
igroup = false;
grpmod = true;
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index cfc168d..bebd9ce 100644
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -188,7 +188,7 @@
void gicv2_enable_interrupt(unsigned int id);
void gicv2_disable_interrupt(unsigned int id);
void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority);
-void gicv2_set_interrupt_type(unsigned int id, unsigned int type);
+void gicv2_set_interrupt_group(unsigned int id, unsigned int group);
void gicv2_raise_sgi(int sgi_num, bool ns, int proc_num);
void gicv2_set_spi_routing(unsigned int id, int proc_num);
void gicv2_set_interrupt_pending(unsigned int id);
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index 5bb22fd..cf6a746 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -556,7 +556,7 @@
void gicv3_cpuif_disable(unsigned int proc_num);
unsigned int gicv3_get_pending_interrupt_type(void);
unsigned int gicv3_get_pending_interrupt_id(void);
-unsigned int gicv3_get_interrupt_type(unsigned int id,
+unsigned int gicv3_get_interrupt_group(unsigned int id,
unsigned int proc_num);
void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx);
void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx);
@@ -579,8 +579,8 @@
void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num);
void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
unsigned int priority);
-void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
- unsigned int type);
+void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num,
+ unsigned int group);
void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group,
u_register_t target);
void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index e024d91..c92121f 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -111,7 +111,7 @@
unsigned int plat_ic_get_interrupt_active(unsigned int id);
void plat_ic_disable_interrupt(unsigned int id);
void plat_ic_enable_interrupt(unsigned int id);
-int plat_ic_has_interrupt_type(unsigned int type);
+bool plat_ic_has_interrupt_type(unsigned int type);
void plat_ic_set_interrupt_type(unsigned int id, unsigned int type);
void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority);
void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target);
diff --git a/include/services/el3_spmd_logical_sp.h b/include/services/el3_spmd_logical_sp.h
index 1f9ef0d..15bea9f 100644
--- a/include/services/el3_spmd_logical_sp.h
+++ b/include/services/el3_spmd_logical_sp.h
@@ -105,33 +105,33 @@
}
static inline uint16_t ffa_partition_info_regs_get_last_idx(
- struct ffa_value args)
+ struct ffa_value *args)
{
- return (uint16_t)(args.arg2 & 0xFFFFU);
+ return (uint16_t)(args->arg2 & 0xFFFFU);
}
static inline uint16_t ffa_partition_info_regs_get_curr_idx(
- struct ffa_value args)
+ struct ffa_value *args)
{
- return (uint16_t)((args.arg2 >> 16) & 0xFFFFU);
+ return (uint16_t)((args->arg2 >> 16) & 0xFFFFU);
}
-static inline uint16_t ffa_partition_info_regs_get_tag(struct ffa_value args)
+static inline uint16_t ffa_partition_info_regs_get_tag(struct ffa_value *args)
{
- return (uint16_t)((args.arg2 >> 32) & 0xFFFFU);
+ return (uint16_t)((args->arg2 >> 32) & 0xFFFFU);
}
static inline uint16_t ffa_partition_info_regs_get_desc_size(
- struct ffa_value args)
+ struct ffa_value *args)
{
- return (uint16_t)(args.arg2 >> 48);
+ return (uint16_t)(args->arg2 >> 48);
}
uint64_t spmd_el3_populate_logical_partition_info(void *handle, uint64_t x1,
uint64_t x2, uint64_t x3);
bool ffa_partition_info_regs_get_part_info(
- struct ffa_value args, uint8_t idx,
+ struct ffa_value *args, uint8_t idx,
struct ffa_partition_info_v1_1 *partition_info);
bool spmd_el3_invoke_partition_info_get(
diff --git a/plat/arm/board/fvp/fvp_spmd_logical_sp.c b/plat/arm/board/fvp/fvp_spmd_logical_sp.c
index 37b4466..8841fc1 100644
--- a/plat/arm/board/fvp/fvp_spmd_logical_sp.c
+++ b/plat/arm/board/fvp/fvp_spmd_logical_sp.c
@@ -32,7 +32,7 @@
panic();
}
- num_partitions = ffa_partition_info_regs_get_last_idx(ret) + 1;
+ num_partitions = ffa_partition_info_regs_get_last_idx(&ret) + 1;
if (num_partitions > SPMD_LP_MAX_SUPPORTED_SP) {
panic();
}
@@ -41,7 +41,7 @@
for (uint16_t i = 0; i < num_partitions; i++) {
INFO("***Start Partition***\n");
- if (!ffa_partition_info_regs_get_part_info(ret, i, &part_info[i]))
+ if (!ffa_partition_info_regs_get_part_info(&ret, i, &part_info[i]))
panic();
INFO("\tPartition ID: 0x%x\n", part_info[i].ep_id);
INFO("\tvCPU count:0x%x\n", part_info[i].execution_ctx_count);
diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c
index 0f988dc..f78d2df 100644
--- a/plat/common/plat_gicv2.c
+++ b/plat/common/plat_gicv2.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -193,9 +193,9 @@
gicv2_set_interrupt_priority(id, priority);
}
-int plat_ic_has_interrupt_type(unsigned int type)
+bool plat_ic_has_interrupt_type(unsigned int type)
{
- int has_interrupt_type = 0;
+ bool has_interrupt_type = false;
switch (type) {
#if GICV2_G0_FOR_EL3
@@ -204,7 +204,7 @@
case INTR_TYPE_S_EL1:
#endif
case INTR_TYPE_NS:
- has_interrupt_type = 1;
+ has_interrupt_type = true;
break;
default:
/* Do nothing in default case */
@@ -216,7 +216,7 @@
void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
{
- unsigned int gicv2_type = 0U;
+ unsigned int gicv2_group = 0U;
/* Map canonical interrupt type to GICv2 type */
switch (type) {
@@ -225,17 +225,17 @@
#else
case INTR_TYPE_S_EL1:
#endif
- gicv2_type = GICV2_INTR_GROUP0;
+ gicv2_group = GICV2_INTR_GROUP0;
break;
case INTR_TYPE_NS:
- gicv2_type = GICV2_INTR_GROUP1;
+ gicv2_group = GICV2_INTR_GROUP1;
break;
default:
- assert(0); /* Unreachable */
+ assert(false); /* Unreachable */
break;
}
- gicv2_set_interrupt_type(id, gicv2_type);
+ gicv2_set_interrupt_group(id, gicv2_group);
}
void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c
index e1420bb..baa70e0 100644
--- a/plat/common/plat_gicv3.c
+++ b/plat/common/plat_gicv3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -47,10 +47,6 @@
#pragma weak plat_ic_set_interrupt_pending
#pragma weak plat_ic_clear_interrupt_pending
-CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) &&
- (INTR_TYPE_NS == INTR_GROUP1NS) &&
- (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch);
-
/*
* This function returns the highest priority pending interrupt at
* the Interrupt controller
@@ -116,12 +112,26 @@
/*
* This function returns the type of the interrupt `id`, depending on how
- * the interrupt has been configured in the interrupt controller
+ * the interrupt has been configured in the interrupt controller.
*/
uint32_t plat_ic_get_interrupt_type(uint32_t id)
{
+ unsigned int group;
+
assert(IS_IN_EL3());
- return gicv3_get_interrupt_type(id, plat_my_core_pos());
+ group = gicv3_get_interrupt_group(id, plat_my_core_pos());
+
+ switch (group) {
+ case INTR_GROUP0:
+ return INTR_TYPE_EL3;
+ case INTR_GROUP1S:
+ return INTR_TYPE_S_EL1;
+ case INTR_GROUP1NS:
+ return INTR_TYPE_NS;
+ default:
+ assert(false); /* Unreachable */
+ return INTR_TYPE_EL3;
+ }
}
/*
@@ -225,16 +235,37 @@
gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority);
}
-int plat_ic_has_interrupt_type(unsigned int type)
+bool plat_ic_has_interrupt_type(unsigned int type)
{
- assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) ||
- (type == INTR_TYPE_NS));
- return 1;
+ if ((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) ||
+ (type == INTR_TYPE_NS)) {
+ return true;
+ }
+
+ return false;
}
void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
{
- gicv3_set_interrupt_type(id, plat_my_core_pos(), type);
+ unsigned int group;
+
+ switch (type) {
+ case INTR_TYPE_EL3:
+ group = INTR_GROUP0;
+ break;
+ case INTR_TYPE_S_EL1:
+ group = INTR_GROUP1S;
+ break;
+ case INTR_TYPE_NS:
+ group = INTR_GROUP1NS;
+ break;
+ default:
+ assert(false); /* Unreachable */
+ group = INTR_GROUP0;
+ break;
+ }
+
+ gicv3_set_interrupt_group(id, plat_my_core_pos(), group);
}
void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
index 7eeadec..8810be3 100644
--- a/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
+++ b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
@@ -118,12 +118,7 @@
u_register_t x3, u_register_t x4,
void *handle, struct smccc_res *smccc_ret)
{
- int ret;
-
- ret = emi_mpu_optee_handler(x1, x2, x3);
- SMC_RET2(handle, ret, 0U);
-
- return 0;
+ return (u_register_t) emi_mpu_optee_handler(x1, x2, x3);
}
DECLARE_SMC_HANDLER(MTK_SIP_TEE_MPU_PERM_SET, mtk_emi_mpu_sip_handler);
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index 53c97e2..06393e4 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -44,6 +44,7 @@
plat/rpi/common/rpi3_io_storage.c
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
+ plat/common/plat_gicv2.c \
plat/common/plat_psci_common.c \
plat/rpi/rpi3/rpi3_bl31_setup.c \
plat/rpi/common/rpi3_pm.c \
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index c50f06f..99797b5 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -86,7 +86,7 @@
}
console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT |
- CONSOLE_FLAG_RUNTIME));
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
} else if (VERSAL_CONSOLE_IS(dcc)) {
/* Initialize the dcc console for debug */
int32_t rc = console_dcc_register();
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
index ccebff2..dab8717 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
+++ b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,9 +16,6 @@
.globl plat_is_my_cpu_primary
.globl platform_mem_init
.globl plat_my_core_pos
- .globl plat_crash_console_init
- .globl plat_crash_console_putc
- .globl plat_crash_console_flush
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
@@ -69,43 +66,3 @@
func platform_mem_init
ret
endfunc platform_mem_init
-
-
- /* ---------------------------------------------
- * int plat_crash_console_init(void)
- * Function to initialize the crash console
- * without a C Runtime to print crash report.
- * Clobber list : x0, x1, x2
- * ---------------------------------------------
- */
-func plat_crash_console_init
-/* mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE
- mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ
- mov_imm x2, VERSAL_NET_CONSOLE_BAUDRATE
- b console_pl011_core_init */
-endfunc plat_crash_console_init
-
- /* ---------------------------------------------
- * int plat_crash_console_putc(int c)
- * Function to print a character on the crash
- * console without a C Runtime.
- * Clobber list : x1, x2
- * ---------------------------------------------
- */
-func plat_crash_console_putc
- mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_BASE
- b console_pl011_core_putc
-endfunc plat_crash_console_putc
-
- /* ---------------------------------------------
- * void plat_crash_console_flush()
- * Function to force a write of all buffered
- * data that hasn't been output.
- * Out : void.
- * Clobber list : x0, x1
- * ---------------------------------------------
- */
-func plat_crash_console_flush
- mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE
- b console_pl011_core_flush
-endfunc plat_crash_console_flush
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index d2b6c7b..91f9a46 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -113,7 +113,7 @@
}
console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT |
- CONSOLE_FLAG_RUNTIME);
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
} else if (VERSAL_NET_CONSOLE_IS(dcc)) {
/* Initialize the dcc console for debug.
* dcc is over jtag and does not configures uart0 or uart1.
diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index 758882c..53eb2cd 100644
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -144,8 +144,6 @@
#define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE
#endif
-#define PLAT_VERSAL_NET_CRASH_UART_BASE VERSAL_NET_UART_BASE
-#define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK
#define VERSAL_NET_CONSOLE_BAUDRATE VERSAL_NET_UART_BAUDRATE
/* Processor core device IDs */
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index 9c4cfa0..9fa16fd 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -86,6 +86,7 @@
drivers/delay_timer/generic_delay_timer.c \
${GICV3_SOURCES} \
drivers/arm/pl011/aarch64/pl011_console.S \
+ plat/common/aarch64/crash_console_helpers.S \
plat/arm/common/arm_common.c \
plat/common/plat_gicv3.c \
${PLAT_PATH}/aarch64/versal_net_helpers.S \
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 56d402f..f408992 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -81,7 +81,8 @@
ZYNQMP_UART_BAUDRATE,
&bl31_boot_console);
console_set_scope(&bl31_boot_console,
- CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_CRASH);
} else if (ZYNQMP_CONSOLE_IS(dcc)) {
/* Initialize the dcc console for debug */
int32_t rc = console_dcc_register();
diff --git a/services/std_svc/spmd/spmd_logical_sp.c b/services/std_svc/spmd/spmd_logical_sp.c
index 964b36b..d992187 100644
--- a/services/std_svc/spmd/spmd_logical_sp.c
+++ b/services/std_svc/spmd/spmd_logical_sp.c
@@ -356,7 +356,7 @@
* other code to consume.
*/
bool ffa_partition_info_regs_get_part_info(
- struct ffa_value args, uint8_t idx,
+ struct ffa_value *args, uint8_t idx,
struct ffa_partition_info_v1_1 *partition_info)
{
uint64_t *arg_ptrs;
@@ -375,7 +375,7 @@
* function, arg1 is reserved, arg2 encodes indices. arg3 and greater
* values reflect partition properties.
*/
- arg_ptrs = (uint64_t *)&args + ((idx * 3) + 3);
+ arg_ptrs = (uint64_t *)args + ((idx * 3) + 3);
info = *arg_ptrs;
arg_ptrs++;