| commit | a09363cca2a750d2797fd52dd7954e57c9248df7 | [log] [tgz] |
|---|---|---|
| author | Sieu Mun Tang <sieu.mun.tang@intel.com> | Thu Oct 24 23:41:02 2024 +0800 |
| committer | Sieu Mun Tang <sieu.mun.tang@intel.com> | Fri Oct 25 00:08:21 2024 +0800 |
| tree | fe61c3e7023cc3cd7806a038ab21fe47e8eff401 | |
| parent | a3abd3280c1fcf36596f742bce81c83881fad669 [diff] |
fix(intel): update Agilex5 warm reset subroutines Update the 'plat_get_my_entrypoint' assembly routine to differentiate between cold reset, warm reset and SMP secondary boot cores request. Add secondary core boot request markup in BL31. Perform CACHE flush/clean ops in case of warm reset request also. Change-Id: I7d33e362a3a513c60c8333e062ce832aa7facf38 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>