commit c11116fe761f55b7d3333193f5095968517447d9
author Sandrine Bailleux <sandrine.bailleux@arm.com> Thu Apr 14 14:04:48 2016 +0100
committer Sandrine Bailleux <sandrine.bailleux@arm.com> Thu Apr 21 12:59:59 2016 +0100
tree 5d36f48e5d726fe162021a28021befe44c76f8fc
parent a7e0c53efcdca27712dccb7332f6a72550a04b8d

Add support for Cortex-A57 erratum 828024 workaround

Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d

include/lib/cpus/aarch64/cortex_a57.h

diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 7711e69..68d0821 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -65,6 +65,8 @@
 #define CPUACTLR_DIS_OVERREAD		(1 << 52)
 #define CPUACTLR_NO_ALLOC_WBWA		(1 << 49)
 #define CPUACTLR_DCC_AS_DCCI		(1 << 44)
+#define CPUACTLR_DIS_STREAMING		(3 << 27)
+#define CPUACTLR_DIS_L1_STREAMING	(3 << 25)
 
 /*******************************************************************************
  * L2 Control register specific definitions.