tree a8f5b83bceb09a490da45e878354feb114a79321
parent 1670a2b56ac3c805257fe4ea3503c6f6e0d4eb51
author Jagdish Gediya <jagdish.gediya@arm.com> 1721745694 +0100
committer Leo Yan <leo.yan@arm.com> 1721828110 +0100

feat(tc): enable Last-level cache (LLC)

The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.

This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.

Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>