Merge pull request #1555 from theopolis/tbb-hikey960
hikey960: Add development TBB support
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 650181d..5479a49 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -109,7 +109,8 @@
int32_t rc = (*bl32_init)();
if (rc != 0) {
- ERROR("BL31: BL32 initialization failed (rc = %d)", rc);
+ WARN("BL31: BL32 initialization failed (rc = %d)\n",
+ rc);
}
}
/*
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index 151c99e..077d470 100644
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -187,7 +187,8 @@
*Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.*
-.. _CVE-2017-5715: http://www.cve.mitre.org/cgi-bin/cvename.cgi?name=2017-5715
+.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
+.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf
.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf
.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
diff --git a/docs/marvell/build.txt b/docs/marvell/build.txt
index 63a40a8..b354ab6 100644
--- a/docs/marvell/build.txt
+++ b/docs/marvell/build.txt
@@ -22,14 +22,14 @@
u-boot.bin should be used and not u-boot-spl.bin
- Set MSS/SCP image path (mandatory only for Armada80x0 and Aramada8xxy)::
+ Set MSS/SCP image path (mandatory only for Armada80x0)::
> export SCP_BL2=path/to/mrvl_scp_bl2*.img
(3) Armada-37x0 build requires WTP tools installation.
- See below in the section "Tools Installation for Armada37x0 Builds".
- Install ARM 32-bit cross compiler, which is required by building WTMI image for CM3::
+ See below in the section "Tools and external components installation".
+ Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3::
> sudo apt-get install gcc-arm-linux-gnueabi
@@ -42,6 +42,8 @@
There are several build options:
- DEBUG: default is without debug information (=0). in order to enable it use DEBUG=1
+ Must be disabled when building UART recovery images due to current console driver
+ implementation that is not compatible with Xmodem protocol used for boot image download.
- LOG_LEVEL: defines the level of logging which will be purged to the default output port.
@@ -55,13 +57,14 @@
- USE_COHERENT_MEM: This flag determines whether to include the coherent memory region in the
BL memory map or not.
- -LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1).
+ - LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1).
- MARVELL_SECURE_BOOT: build trusted(=1)/non trusted(=0) image, default is non trusted.
- BLE_PATH:
- Points to BLE (Binary ROM extension) sources folder. Only required for A8K and A8K+ builds.
+ Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds.
The parameter is optional, its default value is "ble".
+ For the BLE source location, check the section "Tools and external components installation"
- MV_DDR_PATH:
For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
@@ -70,6 +73,7 @@
The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr
sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter
is necessary for A37x0.
+ For the mv_ddr source location, check the section "Tools and external components installation"
- DDR_TOPOLOGY: For Armada37x0 only, the DDR topology map index/name, default is 0.
Supported Options:
@@ -88,14 +92,14 @@
- CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
- BOOTDEV: For Armada37x0 only, the flash boot device, default is SPINOR,
- Currently, Armada37x0 only supports SPINOR, SPINAND, EMMCNORM and SATA:
+ Currently, Armada37x0 only supports SPINOR, SPINAND, EMMCNORM and SATA:
- - SPINOR - SPI NOR flash boot
- - SPINAND - SPI NAND flash boot
- - EMMCNORM - eMMC Download Mode
- Download boot loader or program code from eMMC flash into CM3 or CA53
- Requires full initialization and command sequence
- - SATA - SATA device boot
+ - SPINOR - SPI NOR flash boot
+ - SPINAND - SPI NAND flash boot
+ - EMMCNORM - eMMC Download Mode
+ Download boot loader or program code from eMMC flash into CM3 or CA53
+ Requires full initialization and command sequence
+ - SATA - SATA device boot
- PARTNUM: For Armada37x0 only, the boot partition number, default is 0. To boot from eMMC, the value
should be aligned with the parameter in U-Boot with name of CONFIG_SYS_MMC_ENV_PART, whose
@@ -106,45 +110,35 @@
nothing, an image which supports EFUSE or a customized CM3 firmware binary. The default image
is wtmi.bin that built from sources in WTP folder, which is the next option. If the default
image is OK, then this option should be skipped.
+
- WTP: For Armada37x0 only, use this parameter to point to wtptools source code directory, which
can be found as a3700_utils.zip in the release.
Usage example: WTP=/path/to/a3700_utils
- - CP_NUM: Total amount of CPs (South Bridge) chips wired to the interconnected APs.
- When the parameter is omitted, the build is uses the default number of CPs equal to 2.
- The parameter is valid for Armada 8K-plus SoC family (PLAT=a8xxy) and results in a build of images
- suitable for a8xxY SoC, where "Y" is a number of connected CPs and "xx" is a number of CPU cores.
- Valid values with CP_NUM is in a range of 0 to 8.
- The CPs defined by this parameter are evenly distributed across interconnected APs that in turn
- are dynamically detected. For instance, if the CP_NUM=6 and the TF-A detects 2 interconnected
- APs, each AP assumed to have 3 attached CPs. With the same amount of APs and CP_NUM=3, the AP0
- will have 2 CPs connected and AP1 - a just single CP.
-
For example, in order to build the image in debug mode with log level up to 'notice' level run::
> make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> all fip
And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level,
- the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR3 2CS,
+ the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command
line is as following::
> make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 SECURE=0 CLOCKSPRESET=CPU_1000_DDR_800 \
- DDR_TOPOLOGY=2 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip
+ DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip
Supported MARVELL_PLATFORM are:
- - a3700
+ - a3700 (for both A3720 DB and EspressoBin)
- a70x0
- a70x0_amc (for AMC board)
- - a70x0_cust (for customers)
- a80x0
- a80x0_mcbin (for MacciatoBin)
Special Build Flags
--------------------
- PLAT_RECOVERY_IMAGE_ENABLE: When set this option to enable secondary recovery function when build
- atf. In order to build uart recovery image this operation should be disabled for a70x0 and a80x0
- because of hardware limitation(boot from secondary image can interrupt uart recovery process).
+ atf. In order to build UART recovery image this operation should be disabled for a70x0 and a80x0
+ because of hardware limitation (boot from secondary image can interrupt UART recovery process).
This MACRO definition is set in plat/marvell/a8k/common/include/platform_def.h file
(for more information about build options, please refer to section 'Summary of build options' in TF-A user-guide:
@@ -160,22 +154,44 @@
- bl31.bin - BL31 image
- fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images)
- boot-image.bin - TF-A image (contains BL1 and FIP images)
- - flash-image.bin - Image which contains boot-image.bin and SPL image; should be placed on the boot flash/device.
+ - flash-image.bin - Image which contains boot-image.bin and SPL image;
+ should be placed on the boot flash/device.
-Tools Installation for Armada37x0 Builds
------------------------------------------
-Install a cross GNU ARM tool chain for building the WTMI binary.
-Any cross GNU ARM tool chain that is able to build ARM Cortex M3 binaries
-is suitable.
+Tools and external components installation
+==========================================
-On Debian/Uboot hosts the default GNU ARM tool chain can be installed
-using the following command::
+Armada37x0 Builds require installation of 3 components
+-------------------------------------------------------
+
+(1) ARM cross compiler capable of building images for the service CPU (CM3).
+ This component is usually included in the Linux host packages.
+ On Debian/Uboot hosts the default GNU ARM tool chain can be installed
+ using the following command::
> sudo apt-get install gcc-arm-linux-gnueabi
-If required, the default tool chain prefix "arm-linux-gnueabi-" can be
-overwritten using the environment variable CROSS_CM3.
-Example for BASH shell::
+ Only if required, the default tool chain prefix "arm-linux-gnueabi-" can be
+ overwritten using the environment variable CROSS_CM3.
+ Example for BASH shell::
> export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi
+
+(2) DDR initialization library sources (mv_ddr) available at the following repository
+ (use the "mv_ddr-armada-atf-mainline" branch)::
+ https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
+
+(3) Armada3700 tools available at the following repository (use the latest release branch)::
+ https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
+
+Armada70x0 and Armada80x0 Builds require installation of 2 components
+---------------------------------------------------------------------
+
+(1) DDR initialization library sources (mv_ddr) available at the following repository
+ (use the "mv_ddr-armada-atf-mainline" branch)::
+ https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
+
+(2) BLE sources available at the following repository (use the "atf-mainline" branch)::
+ https://github.com/MarvellEmbeddedProcessors/ble-marvell.git
+
+
diff --git a/docs/plat/warp7.rst b/docs/plat/warp7.rst
new file mode 100644
index 0000000..51c2609
--- /dev/null
+++ b/docs/plat/warp7.rst
@@ -0,0 +1,156 @@
+Trusted Firmware-A for i.MX7 WaRP7
+==================================
+
+The Trusted Firmware-A port for the i.MX7Solo WaRP7 implements BL2 at EL3.
+The i.MX7S contains a BootROM with a High Assurance Boot (HAB) functionality.
+This functionality provides a mechanism for establishing a root-of-trust from
+the reset vector to the command-line in user-space.
+
+Boot Flow
+=========
+
+BootROM --> TF-A BL2 --> BL32(OP-TEE) --> BL33(U-Boot) --> Linux
+
+In the WaRP7 port we encapsulate OP-TEE, DTB and U-Boot into a FIP. This FIP is
+expected and required
+
+# Build Instructions
+
+We need to use a file generated by u-boot in order to generate a .imx image the
+BootROM will boot. It is therefore _required_ to build u-boot before TF-A and
+furthermore it is _recommended_ to use the mkimage in the u-boot/tools directory
+to generate the TF-A .imx image.
+
+## U-Boot:
+
+https://git.linaro.org/landing-teams/working/mbl/u-boot.git
+
+.. code:: shell
+
+ git checkout -b rms-atf-optee-uboot linaro-mbl/rms-atf-optee-uboot
+ make warp7_bl33_defconfig;
+ make u-boot.imx arch=ARM CROSS_COMPILE=arm-linux-gnueabihf-
+
+## TF-A:
+
+https://github.com/ARM-software/arm-trusted-firmware.git
+
+.. code:: shell
+
+ make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=warp7 ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes AARCH32_SP=optee all
+ /path/to/u-boot/tools/mkimage -n /path/to/u-boot/u-boot.cfgout -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.bin.imx
+
+## OP-TEE:
+
+https://github.com/OP-TEE/optee_os.git
+
+.. code:: shell
+
+ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- PLATFORM=imx PLATFORM_FLAVOR=mx7swarp7 ARCH=arm CFG_PAGEABLE_ADDR=0 CFG_DT_ADDR=0x83000000 CFG_NS_ENTRY_ADDR=0x87800000
+
+
+## FIP:
+
+.. code:: shell
+
+ mkdir fiptool_images
+ cp /path/to/uboot/u-boot.bin fiptool_images
+ cp /path/to/optee/out/arm-plat-imx/core/tee-header_v2.bin fiptool_images
+ cp /path/to/optee/out/arm-plat-imx/core/tee-pager_v2.bin fiptool_images
+ cp /path/to/optee/out/arm-plat-imx/core/tee-pageable_v2.bin fiptool_images
+ cp /path/to/linux/arch/boot/dts/imx7s-warp.dtb fiptool_images
+ tools/fiptool/fiptool create --tos-fw fiptool_images/tee-header_v2.bin --tos-fw-extra1 fiptool_images/tee-pager_v2.bin --tos-fw-extra2 fiptool_images/tee-pageable_v2.bin --nt-fw fiptool_images/u-boot.bin --hw-config fiptool_images/imx7s-warp.dtb warp7.fip
+
+
+# Deploy Images
+
+
+First place the WaRP7 into UMS mode in u-boot this should produce an entry in
+/dev like /dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0\:0
+
+.. code:: shell
+
+ => ums 0 mmc 0
+
+Next flash bl2.imx and warp7.fip
+
+bl2.imx is flashed @ 1024 bytes
+warp7.fip is flash @ 1048576 bytes
+
+.. code:: shell
+
+ sudo dd if=bl2.bin.imx of=/dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0\:0 bs=512 seek=2 conv=notrunc
+ # Offset is 1MB 1048576 => 1048576 / 512 = 2048
+ sudo dd if=./warp7.fip of=/dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0\:0 bs=512 seek=2048 conv=notrunc
+
+Remember to umount the USB device pefore proceeding
+
+.. code:: shell
+
+ sudo umount /dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0\:0*
+
+
+# Signing BL2
+
+A further step is to sign BL2.
+
+The image_sign.sh and bl2_sign.csf files alluded to blow are available here.
+
+https://github.com/bryanodonoghue/atf-code-signing
+
+It is suggested you use this script plus the example CSF file in order to avoid
+hard-coding data into your CSF files.
+
+Download both "image_sign.sh" and "bl2_sign.csf" to your
+arm-trusted-firmware top-level directory.
+
+.. code:: shell
+
+ #!/bin/bash
+ SIGN=image_sign.sh
+ TEMP=`pwd`/temp
+ BL2_CSF=bl2_sign.csf
+ BL2_IMX=bl2.bin.imx
+ CST_PATH=/path/to/cst-2.3.2
+ CST_BIN=${CST_PATH}/linux64/cst
+
+ #Remove temp
+ rm -rf ${TEMP}
+ mkdir ${TEMP}
+
+ # Generate IMX header
+ /path/to/u-boot/tools/mkimage -n u-boot.cfgout.warp7 -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.bin.imx > ${TEMP}/${BL2_IMX}.log
+
+ # Copy required items to $TEMP
+ cp build/warp7/debug/bl2.bin.imx ${TEMP}
+ cp ${CST_PATH}/keys/* ${TEMP}
+ cp ${CST_PATH}/crts/* ${TEMP}
+ cp ${BL2_CSF} ${TEMP}
+
+ # Generate signed BL2 image
+ ./${SIGN} image_sign_mbl_binary ${TEMP} ${BL2_CSF} ${BL2_IMX} ${CST_BIN}
+
+ # Copy signed BL2 to top-level directory
+ cp ${TEMP}/${BL2_IMX}-signed .
+ cp ${BL2_RECOVER_CSF} ${TEMP}
+
+
+The resulting bl2.bin.imx-signed can replace bl2.bin.imx in the Deploy
+Images section above, once done.
+
+Suggested flow for verifying.
+
+1. Followed all previous steps above and verify a non-secure ATF boot
+2. Down the NXP Code Singing Tool
+3. Generate keys
+4. Program the fuses on your board
+5. Replace bl2.bin.imx with bl2.bin.imx-signed
+6. Verify inside u-boot that "hab_status" shows no events
+7. Subsequently close your board.
+
+If you have HAB events @ step 6 - do not lock your board.
+
+To get a good over-view of generating keys and programming the fuses on the
+board read "High Assurance Boot for Dummies" by Boundary Devices.
+
+https://boundarydevices.com/high-assurance-boot-hab-dummies/
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index de7b5db..84f4c9d 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -1055,7 +1055,7 @@
to the next BL image, when LOAD\_IMAGE\_V2 is enabled.
Function : plat\_log\_get\_prefix()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1066,9 +1066,32 @@
prepended to all the log output from TF-A. The `log_level` (argument) will
correspond to one of the standard log levels defined in debug.h. The platform
can override the common implementation to define a different prefix string for
-the log output. The implementation should be robust to future changes that
+the log output. The implementation should be robust to future changes that
increase the number of log levels.
+Function : plat\_get\_mbedtls\_heap()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Arguments : void **heap_addr, size_t *heap_size
+ Return : int
+
+This function is invoked during Mbed TLS library initialisation to get
+a heap, by means of a starting address and a size. This heap will then be used
+internally by the Mbed TLS library. The heap is requested from the current BL
+stage, i.e. the current BL image inside which Mbed TLS is used.
+
+In the default implementation a heap is statically allocated inside every image
+(i.e. every BL stage) that utilises Mbed TLS. So, in this case, the function
+simply returns the address and size of this "pre-allocated" heap. However, by
+overriding the default implementation, platforms have the potential to optimise
+memory usage. For example, on some Arm platforms, the Mbed TLS heap is shared
+between BL1 and BL2 stages and, thus, the necessary space is not reserved
+twice.
+
+On success the function should return 0 and a negative error code otherwise.
+
Modifications specific to a Boot Loader stage
---------------------------------------------
diff --git a/drivers/allwinner/sunxi_i2c.c b/drivers/allwinner/sunxi_i2c.c
new file mode 100644
index 0000000..cc91ca5
--- /dev/null
+++ b/drivers/allwinner/sunxi_i2c.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* This driver provides I2C support for Allwinner sunXi SoCs */
+
+#include <mmio.h>
+
+#define CONFIG_SYS_TCLK 24000000
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+#define I2C_INTERRUPT_CLEAR_INVERTED
+
+struct mentor_i2c_regs {
+ uint32_t slave_address;
+ uint32_t xtnd_slave_addr;
+ uint32_t data;
+ uint32_t control;
+ uint32_t status;
+ uint32_t baudrate;
+ uint32_t soft_reset;
+};
+
+#include "../mentor/i2c/mi2cv.c"
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index 311e77e..55897bf 100644
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -597,3 +597,12 @@
return old_mask;
}
+
+/*******************************************************************************
+ * This function updates single interrupt configuration to be level/edge
+ * triggered
+ ******************************************************************************/
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg)
+{
+ gicd_set_icfgr(driver_data->gicd_base, id, cfg);
+}
diff --git a/drivers/auth/mbedtls/mbedtls_common.c b/drivers/auth/mbedtls/mbedtls_common.c
index 7095fde..dbf45ba 100644
--- a/drivers/auth/mbedtls/mbedtls_common.c
+++ b/drivers/auth/mbedtls/mbedtls_common.c
@@ -4,26 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <assert.h>
#include <debug.h>
-#include <stdlib.h>
-#include <stdio.h>
-
/* mbed TLS headers */
#include <mbedtls/memory_buffer_alloc.h>
#include <mbedtls/platform.h>
-#include <mbedtls_config.h>
#include <mbedtls_common.h>
-
-/*
- * mbed TLS heap
- */
-#if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA) \
- || (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)
-#define MBEDTLS_HEAP_SIZE (13*1024)
-#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA)
-#define MBEDTLS_HEAP_SIZE (7*1024)
-#endif
-static unsigned char heap[MBEDTLS_HEAP_SIZE];
+#include <mbedtls_config.h>
+#include <platform.h>
+#include <stddef.h>
static void cleanup(void)
{
@@ -37,13 +26,25 @@
void mbedtls_init(void)
{
static int ready;
+ void *heap_addr;
+ size_t heap_size = 0;
+ int err;
if (!ready) {
if (atexit(cleanup))
panic();
+
+ err = plat_get_mbedtls_heap(&heap_addr, &heap_size);
+
+ /* Ensure heap setup is proper */
+ if (err < 0) {
+ ERROR("Mbed TLS failed to get a heap\n");
+ panic();
+ }
+ assert(heap_size >= TF_MBEDTLS_HEAP_SIZE);
/* Initialize the mbed TLS heap */
- mbedtls_memory_buffer_alloc_init(heap, MBEDTLS_HEAP_SIZE);
+ mbedtls_memory_buffer_alloc_init(heap_addr, heap_size);
#ifdef MBEDTLS_PLATFORM_SNPRINTF_ALT
mbedtls_platform_set_snprintf(snprintf);
diff --git a/drivers/imx/timer/imx_gpt.c b/drivers/imx/timer/imx_gpt.c
new file mode 100644
index 0000000..bd364eb
--- /dev/null
+++ b/drivers/imx/timer/imx_gpt.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <delay_timer.h>
+#include <mmio.h>
+#include <imx_gpt.h>
+
+#define GPTCR_SWR BIT(15) /* Software reset */
+#define GPTCR_24MEN BIT(10) /* Enable 24MHz clock input */
+#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
+#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
+#define GPTCR_TEN 1 /* Timer enable */
+
+#define GPTPR_PRESCL_24M_SHIFT 12
+
+#define SYS_COUNTER_FREQ_IN_MHZ 3
+
+#define GPTPR_TIMER_CTRL (imx_base_addr + 0x000)
+#define GPTPR_TIMER_PRESCL (imx_base_addr + 0x004)
+#define GPTPR_TIMER_CNTR (imx_base_addr + 0x024)
+
+static uintptr_t imx_base_addr;
+
+uint32_t imx_get_timer_value(void)
+{
+ return ~mmio_read_32(GPTPR_TIMER_CNTR);
+}
+
+static const timer_ops_t imx_gpt_ops = {
+ .get_timer_value = imx_get_timer_value,
+ .clk_mult = 1,
+ .clk_div = SYS_COUNTER_FREQ_IN_MHZ,
+};
+
+void imx_gpt_ops_init(uintptr_t base_addr)
+{
+ int val;
+
+ assert(base_addr != 0);
+
+ imx_base_addr = base_addr;
+
+ /* setup GP Timer */
+ mmio_write_32(GPTPR_TIMER_CTRL, GPTCR_SWR);
+ mmio_write_32(GPTPR_TIMER_CTRL, 0);
+
+ /* get 3MHz from 24MHz */
+ mmio_write_32(GPTPR_TIMER_PRESCL, (7 << GPTPR_PRESCL_24M_SHIFT));
+
+ val = mmio_read_32(GPTPR_TIMER_CTRL);
+ val &= ~GPTCR_CLKSOURCE_MASK;
+ val |= GPTCR_24MEN | GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
+ mmio_write_32(GPTPR_TIMER_CTRL, val);
+
+ timer_init(&imx_gpt_ops);
+}
diff --git a/drivers/imx/timer/imx_gpt.h b/drivers/imx/timer/imx_gpt.h
new file mode 100644
index 0000000..6416c3c
--- /dev/null
+++ b/drivers/imx/timer/imx_gpt.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_GPT_H__
+#define __IMX_GPT_H__
+
+#include <stdint.h>
+
+void imx_gpt_ops_init(uintptr_t reg_base);
+
+#endif /* __IMX_GPT_H__ */
diff --git a/drivers/imx/uart/imx_crash_uart.S b/drivers/imx/uart/imx_crash_uart.S
new file mode 100644
index 0000000..aa987b3
--- /dev/null
+++ b/drivers/imx/uart/imx_crash_uart.S
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+#include <imx_uart.h>
+#include <platform_def.h>
+
+ .globl imx_crash_uart_init
+ .globl imx_crash_uart_putc
+
+ /* -----------------------------------------------
+ * int imx_crash_uart_init(uintptr_t base_addr,
+ * unsigned int uart_clk, unsigned int baud_rate)
+ * Function to initialize the console without a
+ * C Runtime to print debug information. This
+ * function will be accessed by console_init and
+ * crash reporting.
+ * In: r0 - console base address
+ * r1 - Uart clock in Hz
+ * r2 - Baud rate
+ * Out: return 1 on success else 0 on error
+ * Clobber list : r1, r2, r3, r4
+ * -----------------------------------------------
+ */
+func imx_crash_uart_init
+ /* Free up r1 as a scratch reg */
+ mov r4, r0
+ mov r0, r1
+
+ /* Reset UART via CR2 */
+ add r1, r4, #IMX_UART_CR2_OFFSET
+ movs r3, #0
+ str r3, [r4, #IMX_UART_CR2_OFFSET]
+
+ /* Wait for reset complete */
+__wait_cr2_reset:
+ ldr r3, [r1, #0]
+ ands r3, #IMX_UART_CR2_SRST
+ beq __wait_cr2_reset
+
+ /* Enable UART */
+ movs r3, #IMX_UART_CR1_UARTEN
+ mov r1, r2
+ str r3, [r4, #IMX_UART_CR1_OFFSET]
+
+ /*
+ * Ignore RTC/CTS - disable reset
+ * Magic value #16423 =>
+ * IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN | IMX_UART_CR2_RXEN | IMX_UART_CR2_SRST
+ */
+ movw r3, #16423
+ str r3, [r4, #IMX_UART_CR2_OFFSET]
+
+ /*
+ * No parity, autobaud detect-old, rxdmuxsel=1 (fixed i.mx7)
+ * Magic value => #132
+ * IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL
+ */
+ movs r3, #132
+ str r3, [r4, #IMX_UART_CR3_OFFSET]
+
+ /*
+ * Set CTS FIFO trigger to 32 bytes bits 15:10
+ * Magic value => #32768
+ * FIFO trigger bitmask 100000
+ * */
+ mov r3, #32768
+ str r3, [r4, #IMX_UART_CR4_OFFSET]
+
+ /*
+ * TX/RX-thresh = 2 bytes, DCE (bit6 = 0), refclk @24MHz / 4
+ * Magic value #2562
+ * IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) | IMX_UART_FCR_RFDIV2
+ */
+ #ifdef IMX_UART_DTE
+ movw r3, #2626
+ #else
+ movw r3, #2562
+ #endif
+ str r3, [r4, #IMX_UART_FCR_OFFSET]
+
+ /* This BIR should be set to 0x0F prior to writing the BMR */
+ movs r3, #15
+ str r3, [r4, #IMX_UART_BIR_OFFSET]
+
+ /* Hard-code to 115200 @ 24 MHz */
+ movs r0, #104
+ str r0, [r4, #IMX_UART_BMR_OFFSET]
+
+ /* Indicate success */
+ movs r0, #1
+ bx lr
+endfunc imx_crash_uart_init
+
+ /* --------------------------------------------------------
+ * int imx_crash_uart_putc(int c, uintptr_t base_addr)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : r0 - character to be printed
+ * r1 - console base address
+ * Out : return -1 on error else return character.
+ * Clobber list : r2
+ * --------------------------------------------------------
+ */
+func imx_crash_uart_putc
+ /* Output specified character to UART shift-register */
+ str r0, [r1, #IMX_UART_TXD_OFFSET]
+
+ /* Wait for transmit IMX_UART_STAT2_OFFSET.IMX_UART_STAT2_TXDC == 1 */
+__putc_spin_ready:
+ ldr r2, [r1, #IMX_UART_STAT2_OFFSET]
+ ands r2, #IMX_UART_STAT2_TXDC
+ beq __putc_spin_ready
+
+ /* Transmit complete do we need to fixup \n to \n\r */
+ cmp r0, #10
+ beq __putc_fixup_lf
+
+ /* No fixup necessary - exit here */
+ movs r0, #0
+ bx lr
+
+ /* Fixup \n to \n\r */
+__putc_fixup_lf:
+ movs r0, #13
+ b imx_crash_uart_putc
+endfunc imx_crash_uart_putc
diff --git a/drivers/imx/uart/imx_uart.c b/drivers/imx/uart/imx_uart.c
new file mode 100644
index 0000000..0250a41
--- /dev/null
+++ b/drivers/imx/uart/imx_uart.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <stdint.h>
+#include <mmio.h>
+#include <platform_def.h>
+#include <imx_uart.h>
+
+/* TX/RX FIFO threshold */
+#define TX_RX_THRESH 2
+
+struct clk_div_factors {
+ uint32_t fcr_div;
+ uint32_t bmr_div;
+};
+
+static struct clk_div_factors clk_div[] = {
+ {
+ .fcr_div = IMX_UART_FCR_RFDIV1,
+ .bmr_div = 1,
+ },
+ {
+ .fcr_div = IMX_UART_FCR_RFDIV2,
+ .bmr_div = 2,
+ },
+ {
+ .fcr_div = IMX_UART_FCR_RFDIV3,
+ .bmr_div = 3,
+ },
+ {
+ .fcr_div = IMX_UART_FCR_RFDIV4,
+ .bmr_div = 4,
+ },
+ {
+ .fcr_div = IMX_UART_FCR_RFDIV5,
+ .bmr_div = 5,
+ },
+ {
+ .fcr_div = IMX_UART_FCR_RFDIV6,
+ .bmr_div = 6,
+ },
+ {
+ .fcr_div = IMX_UART_FCR_RFDIV7,
+ .bmr_div = 7,
+ },
+};
+
+static void write_reg(uintptr_t base, uint32_t offset, uint32_t val)
+{
+ mmio_write_32(base + offset, val);
+}
+
+static uint32_t read_reg(uintptr_t base, uint32_t offset)
+{
+ return mmio_read_32(base + offset);
+}
+
+int console_core_init(uintptr_t base_addr, unsigned int uart_clk,
+ unsigned int baud_rate)
+{
+ uint32_t val;
+ uint8_t clk_idx = 1;
+
+ /* Reset UART */
+ write_reg(base_addr, IMX_UART_CR2_OFFSET, 0);
+ do {
+ val = read_reg(base_addr, IMX_UART_CR2_OFFSET);
+ } while (!(val & IMX_UART_CR2_SRST));
+
+ /* Enable UART */
+ write_reg(base_addr, IMX_UART_CR1_OFFSET, IMX_UART_CR1_UARTEN);
+
+ /* Ignore RTS, 8N1, enable tx/rx, disable reset */
+ val = (IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN |
+ IMX_UART_CR2_RXEN | IMX_UART_CR2_SRST);
+ write_reg(base_addr, IMX_UART_CR2_OFFSET, val);
+
+ /* No parity, autobaud detect-old, rxdmuxsel=1 (fixed i.mx7) */
+ val = IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL;
+ write_reg(base_addr, IMX_UART_CR3_OFFSET, val);
+
+ /* Set CTS FIFO trigger to 32 bytes bits 15:10 */
+ write_reg(base_addr, IMX_UART_CR4_OFFSET, 0x8000);
+
+ /* TX/RX-thresh = 2 bytes, DTE (bit6 = 0), refclk @24MHz / 4 */
+ val = IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) |
+ clk_div[clk_idx].fcr_div;
+ #ifdef IMX_UART_DTE
+ /* Set DTE (bit6 = 1) */
+ val |= IMX_UART_FCR_DCEDTE;
+ #endif
+ write_reg(base_addr, IMX_UART_FCR_OFFSET, val);
+
+ /*
+ * The equation for BAUD rate calculation is
+ * RefClk = Supplied clock / FCR_DIVx
+ *
+ * BAUD = Refclk
+ * ------------
+ * 16 x (UBMR + 1/ UBIR + 1)
+ *
+ * We write 0x0f into UBIR to remove the 16 mult
+ * BAUD = 6000000
+ * ------------
+ * 16 x (UBMR + 1/ 15 + 1)
+ */
+
+ write_reg(base_addr, IMX_UART_BIR_OFFSET, 0x0f);
+ val = ((uart_clk / clk_div[clk_idx].bmr_div) / baud_rate) - 1;
+ write_reg(base_addr, IMX_UART_BMR_OFFSET, val);
+
+ return 0;
+}
+
+/* --------------------------------------------------------
+ * int console_core_putc(int c, uintptr_t base_addr)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : r0 - character to be printed
+ * r1 - console base address
+ * Out : return -1 on error else return character.
+ * Clobber list : r2
+ * --------------------------------------------------------
+ */
+int console_core_putc(int c, uintptr_t base_addr)
+{
+ uint32_t val;
+
+ if (c == '\n')
+ console_core_putc('\r', base_addr);
+
+ /* Write data */
+ write_reg(base_addr, IMX_UART_TXD_OFFSET, c);
+
+ /* Wait for transmit */
+ do {
+ val = read_reg(base_addr, IMX_UART_STAT2_OFFSET);
+ } while (!(val & IMX_UART_STAT2_TXDC));
+
+ return 0;
+}
+
+/*
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 on error.
+ * In : r0 - console base address
+ * Clobber list : r0, r1
+ * ---------------------------------------------
+ */
+int console_core_getc(uintptr_t base_addr)
+{
+ uint32_t val;
+
+ val = read_reg(base_addr, IMX_UART_TS_OFFSET);
+ if (val & IMX_UART_TS_RXEMPTY)
+ return -1;
+
+ val = read_reg(base_addr, IMX_UART_RXD_OFFSET);
+ return (int)(val & 0x000000FF);
+}
+
+/*
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : r0 - console base address
+ * Out : return -1 on error else return 0.
+ * Clobber list : r0, r1
+ * ---------------------------------------------
+ */
+int console_core_flush(uintptr_t base_addr)
+{
+ return 0;
+}
+
diff --git a/drivers/imx/uart/imx_uart.h b/drivers/imx/uart/imx_uart.h
new file mode 100644
index 0000000..de42125
--- /dev/null
+++ b/drivers/imx/uart/imx_uart.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __IMX_CONSOLE_H__
+#define __IMX_CONSOLE_H__
+
+#define IMX_UART_RXD_OFFSET 0x00
+#define IMX_UART_RXD_CHARRDY BIT(15)
+#define IMX_UART_RXD_ERR BIT(14)
+#define IMX_UART_RXD_OVERRUN BIT(13)
+#define IMX_UART_RXD_FRMERR BIT(12)
+#define IMX_UART_RXD_BRK BIT(11)
+#define IMX_UART_RXD_PRERR BIT(10)
+
+#define IMX_UART_TXD_OFFSET 0x40
+
+#define IMX_UART_CR1_OFFSET 0x80
+#define IMX_UART_CR1_ADEN BIT(15)
+#define IMX_UART_CR1_ADBR BIT(14)
+#define IMX_UART_CR1_TRDYEN BIT(13)
+#define IMX_UART_CR1_IDEN BIT(12)
+#define IMX_UART_CR1_RRDYEN BIT(9)
+#define IMX_UART_CR1_RXDMAEN BIT(8)
+#define IMX_UART_CR1_IREN BIT(7)
+#define IMX_UART_CR1_TXMPTYEN BIT(6)
+#define IMX_UART_CR1_RTSDEN BIT(5)
+#define IMX_UART_CR1_SNDBRK BIT(4)
+#define IMX_UART_CR1_TXDMAEN BIT(3)
+#define IMX_UART_CR1_ATDMAEN BIT(2)
+#define IMX_UART_CR1_DOZE BIT(1)
+#define IMX_UART_CR1_UARTEN BIT(0)
+
+#define IMX_UART_CR2_OFFSET 0x84
+#define IMX_UART_CR2_ESCI BIT(15)
+#define IMX_UART_CR2_IRTS BIT(14)
+#define IMX_UART_CR2_CTSC BIT(13)
+#define IMX_UART_CR2_CTS BIT(12)
+#define IMX_UART_CR2_ESCEN BIT(11)
+#define IMX_UART_CR2_PREN BIT(8)
+#define IMX_UART_CR2_PROE BIT(7)
+#define IMX_UART_CR2_STPB BIT(6)
+#define IMX_UART_CR2_WS BIT(5)
+#define IMX_UART_CR2_RTSEN BIT(4)
+#define IMX_UART_CR2_ATEN BIT(3)
+#define IMX_UART_CR2_TXEN BIT(2)
+#define IMX_UART_CR2_RXEN BIT(1)
+#define IMX_UART_CR2_SRST BIT(0)
+
+#define IMX_UART_CR3_OFFSET 0x88
+#define IMX_UART_CR3_DTREN BIT(13)
+#define IMX_UART_CR3_PARERREN BIT(12)
+#define IMX_UART_CR3_FARERREN BIT(11)
+#define IMX_UART_CR3_DSD BIT(10)
+#define IMX_UART_CR3_DCD BIT(9)
+#define IMX_UART_CR3_RI BIT(8)
+#define IMX_UART_CR3_ADNIMP BIT(7)
+#define IMX_UART_CR3_RXDSEN BIT(6)
+#define IMX_UART_CR3_AIRINTEN BIT(5)
+#define IMX_UART_CR3_AWAKEN BIT(4)
+#define IMX_UART_CR3_DTRDEN BIT(3)
+#define IMX_UART_CR3_RXDMUXSEL BIT(2)
+#define IMX_UART_CR3_INVT BIT(1)
+#define IMX_UART_CR3_ACIEN BIT(0)
+
+#define IMX_UART_CR4_OFFSET 0x8c
+#define IMX_UART_CR4_INVR BIT(9)
+#define IMX_UART_CR4_ENIRI BIT(8)
+#define IMX_UART_CR4_WKEN BIT(7)
+#define IMX_UART_CR4_IDDMAEN BIT(6)
+#define IMX_UART_CR4_IRSC BIT(5)
+#define IMX_UART_CR4_LPBYP BIT(4)
+#define IMX_UART_CR4_TCEN BIT(3)
+#define IMX_UART_CR4_BKEN BIT(2)
+#define IMX_UART_CR4_OREN BIT(1)
+#define IMX_UART_CR4_DREN BIT(0)
+
+#define IMX_UART_FCR_OFFSET 0x90
+#define IMX_UART_FCR_TXTL_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12) |\
+ BIT(11) | BIT(10))
+#define IMX_UART_FCR_TXTL(x) ((x) << 10)
+#define IMX_UART_FCR_RFDIV_MASK (BIT(9) | BIT(8) | BIT(7))
+#define IMX_UART_FCR_RFDIV7 (BIT(9) | BIT(8))
+#define IMX_UART_FCR_RFDIV1 (BIT(9) | BIT(7))
+#define IMX_UART_FCR_RFDIV2 BIT(9)
+#define IMX_UART_FCR_RFDIV3 (BIT(8) | BIT(7))
+#define IMX_UART_FCR_RFDIV4 BIT(8)
+#define IMX_UART_FCR_RFDIV5 BIT(7)
+#define IMX_UART_FCR_RFDIV6 0
+#define IMX_UART_FCR_DCEDTE BIT(6)
+#define IMX_UART_FCR_RXTL_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2) |\
+ BIT(1) | BIT(0))
+#define IMX_UART_FCR_RXTL(x) x
+
+#define IMX_UART_STAT1_OFFSET 0x94
+#define IMX_UART_STAT1_PARITYERR BIT(15)
+#define IMX_UART_STAT1_RTSS BIT(14)
+#define IMX_UART_STAT1_TRDY BIT(13)
+#define IMX_UART_STAT1_RTSD BIT(12)
+#define IMX_UART_STAT1_ESCF BIT(11)
+#define IMX_UART_STAT1_FRAMEERR BIT(10)
+#define IMX_UART_STAT1_RRDY BIT(9)
+#define IMX_UART_STAT1_AGTIM BIT(8)
+#define IMX_UART_STAT1_DTRD BIT(7)
+#define IMX_UART_STAT1_RXDS BIT(6)
+#define IMX_UART_STAT1_AIRINT BIT(5)
+#define IMX_UART_STAT1_AWAKE BIT(4)
+#define IMX_UART_STAT1_SAD BIT(3)
+
+#define IMX_UART_STAT2_OFFSET 0x98
+#define IMX_UART_STAT2_ADET BIT(15)
+#define IMX_UART_STAT2_TXFE BIT(14)
+#define IMX_UART_STAT2_DTRF BIT(13)
+#define IMX_UART_STAT2_IDLE BIT(12)
+#define IMX_UART_STAT2_ACST BIT(11)
+#define IMX_UART_STAT2_RIDELT BIT(10)
+#define IMX_UART_STAT2_RIIN BIT(9)
+#define IMX_UART_STAT2_IRINT BIT(8)
+#define IMX_UART_STAT2_WAKE BIT(7)
+#define IMX_UART_STAT2_DCDDELT BIT(6)
+#define IMX_UART_STAT2_DCDIN BIT(5)
+#define IMX_UART_STAT2_RTSF BIT(4)
+#define IMX_UART_STAT2_TXDC BIT(3)
+#define IMX_UART_STAT2_BRCD BIT(2)
+#define IMX_UART_STAT2_ORE BIT(1)
+#define IMX_UART_STAT2_RCR BIT(0)
+
+#define IMX_UART_ESC_OFFSET 0x9c
+
+#define IMX_UART_TIM_OFFSET 0xa0
+
+#define IMX_UART_BIR_OFFSET 0xa4
+
+#define IMX_UART_BMR_OFFSET 0xa8
+
+#define IMX_UART_BRC_OFFSET 0xac
+
+#define IMX_UART_ONEMS_OFFSET 0xb0
+
+#define IMX_UART_TS_OFFSET 0xb4
+#define IMX_UART_TS_FRCPERR BIT(13)
+#define IMX_UART_TS_LOOP BIT(12)
+#define IMX_UART_TS_DBGEN BIT(11)
+#define IMX_UART_TS_LOOPIR BIT(10)
+#define IMX_UART_TS_RXDBG BIT(9)
+#define IMX_UART_TS_TXEMPTY BIT(6)
+#define IMX_UART_TS_RXEMPTY BIT(5)
+#define IMX_UART_TS_TXFULL BIT(4)
+#define IMX_UART_TS_RXFULL BIT(3)
+#define IMX_UART_TS_SOFTRST BIT(0)
+
+#endif /* __IMX_UART_H__ */
diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
new file mode 100644
index 0000000..ea96833
--- /dev/null
+++ b/drivers/imx/usdhc/imx_usdhc.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <debug.h>
+#include <delay_timer.h>
+#include <imx_usdhc.h>
+#include <mmc.h>
+#include <errno.h>
+#include <mmio.h>
+#include <string.h>
+
+static void imx_usdhc_initialize(void);
+static int imx_usdhc_send_cmd(struct mmc_cmd *cmd);
+static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
+static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size);
+static int imx_usdhc_read(int lba, uintptr_t buf, size_t size);
+static int imx_usdhc_write(int lba, uintptr_t buf, size_t size);
+
+static const struct mmc_ops imx_usdhc_ops = {
+ .init = imx_usdhc_initialize,
+ .send_cmd = imx_usdhc_send_cmd,
+ .set_ios = imx_usdhc_set_ios,
+ .prepare = imx_usdhc_prepare,
+ .read = imx_usdhc_read,
+ .write = imx_usdhc_write,
+};
+
+static imx_usdhc_params_t imx_usdhc_params;
+
+#define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000)
+static void imx_usdhc_set_clk(int clk)
+{
+ int div = 1;
+ int pre_div = 1;
+ unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE;
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+
+ assert(clk > 0);
+
+ while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256)
+ pre_div *= 2;
+
+ while (sdhc_clk / div > clk && div < 16)
+ div++;
+
+ pre_div >>= 1;
+ div -= 1;
+ clk = (pre_div << 8) | (div << 4);
+
+ mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
+ mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
+ udelay(10000);
+
+ mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN);
+}
+
+static void imx_usdhc_initialize(void)
+{
+ unsigned int timeout = 10000;
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+
+ assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0);
+
+ /* reset the controller */
+ mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA);
+
+ /* wait for reset done */
+ while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) {
+ if (!timeout)
+ ERROR("IMX MMC reset timeout.\n");
+ timeout--;
+ }
+
+ mmio_write_32(reg_base + MMCBOOT, 0);
+ mmio_write_32(reg_base + MIXCTRL, 0);
+ mmio_write_32(reg_base + CLKTUNECTRLSTS, 0);
+
+ mmio_write_32(reg_base + VENDSPEC, VENDSPEC_INIT);
+ mmio_write_32(reg_base + DLLCTRL, 0);
+ mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_IPG_CLKEN | VENDSPEC_PER_CLKEN);
+
+ /* Set the initial boot clock rate */
+ imx_usdhc_set_clk(MMC_BOOT_CLK_RATE);
+ udelay(100);
+
+ /* Clear read/write ready status */
+ mmio_clrbits32(reg_base + INTSTATEN, INTSTATEN_BRR | INTSTATEN_BWR);
+
+ /* configure as little endian */
+ mmio_write_32(reg_base + PROTCTRL, PROTCTRL_LE);
+
+ /* Set timeout to the maximum value */
+ mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_TIMEOUT_MASK,
+ SYSCTRL_TIMEOUT(15));
+
+ /* set wartermark level as 16 for safe for MMC */
+ mmio_clrsetbits32(reg_base + WATERMARKLEV, WMKLV_MASK, 16 | (16 << 16));
+}
+
+#define FSL_CMD_RETRIES 1000
+
+static int imx_usdhc_send_cmd(struct mmc_cmd *cmd)
+{
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+ unsigned int xfertype = 0, mixctl = 0, multiple = 0, data = 0, err = 0;
+ unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE;
+ unsigned int cmd_retries = 0;
+
+ assert(cmd);
+
+ /* clear all irq status */
+ mmio_write_32(reg_base + INTSTAT, 0xffffffff);
+
+ /* Wait for the bus to be idle */
+ do {
+ state = mmio_read_32(reg_base + PSTATE);
+ } while (state & (PSTATE_CDIHB | PSTATE_CIHB));
+
+ while (mmio_read_32(reg_base + PSTATE) & PSTATE_DLA)
+ ;
+
+ mmio_write_32(reg_base + INTSIGEN, 0);
+ udelay(1000);
+
+ switch (cmd->cmd_idx) {
+ case MMC_CMD(12):
+ xfertype |= XFERTYPE_CMDTYP_ABORT;
+ break;
+ case MMC_CMD(18):
+ multiple = 1;
+ /* fall thru for read op */
+ case MMC_CMD(17):
+ case MMC_CMD(8):
+ mixctl |= MIXCTRL_DTDSEL;
+ data = 1;
+ break;
+ case MMC_CMD(25):
+ multiple = 1;
+ /* fall thru for data op flag */
+ case MMC_CMD(24):
+ data = 1;
+ break;
+ default:
+ break;
+ }
+
+ if (multiple) {
+ mixctl |= MIXCTRL_MSBSEL;
+ mixctl |= MIXCTRL_BCEN;
+ }
+
+ if (data) {
+ xfertype |= XFERTYPE_DPSEL;
+ mixctl |= MIXCTRL_DMAEN;
+ }
+
+ if (cmd->resp_type & MMC_RSP_48)
+ xfertype |= XFERTYPE_RSPTYP_48;
+ else if (cmd->resp_type & MMC_RSP_136)
+ xfertype |= XFERTYPE_RSPTYP_136;
+ else if (cmd->resp_type & MMC_RSP_BUSY)
+ xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+
+ if (cmd->resp_type & MMC_RSP_CMD_IDX)
+ xfertype |= XFERTYPE_CICEN;
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ xfertype |= XFERTYPE_CCCEN;
+
+ xfertype |= XFERTYPE_CMD(cmd->cmd_idx);
+
+ /* Send the command */
+ mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);
+ mmio_clrsetbits32(reg_base + MIXCTRL, MIXCTRL_DATMASK, mixctl);
+ mmio_write_32(reg_base + XFERTYPE, xfertype);
+
+ /* Wait for the command done */
+ do {
+ state = mmio_read_32(reg_base + INTSTAT);
+ if (cmd_retries)
+ udelay(1);
+ } while ((!(state & flags)) && ++cmd_retries < FSL_CMD_RETRIES);
+
+ if ((state & (INTSTATEN_CTOE | CMD_ERR)) || cmd_retries == FSL_CMD_RETRIES) {
+ if (cmd_retries == FSL_CMD_RETRIES)
+ err = -ETIMEDOUT;
+ else
+ err = -EIO;
+ ERROR("imx_usdhc mmc cmd %d state 0x%x errno=%d\n",
+ cmd->cmd_idx, state, err);
+ goto out;
+ }
+
+ /* Copy the response to the response buffer */
+ if (cmd->resp_type & MMC_RSP_136) {
+ unsigned int cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
+
+ cmdrsp3 = mmio_read_32(reg_base + CMDRSP3);
+ cmdrsp2 = mmio_read_32(reg_base + CMDRSP2);
+ cmdrsp1 = mmio_read_32(reg_base + CMDRSP1);
+ cmdrsp0 = mmio_read_32(reg_base + CMDRSP0);
+ cmd->resp_data[3] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
+ cmd->resp_data[2] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
+ cmd->resp_data[1] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
+ cmd->resp_data[0] = (cmdrsp0 << 8);
+ } else {
+ cmd->resp_data[0] = mmio_read_32(reg_base + CMDRSP0);
+ }
+
+ /* Wait until all of the blocks are transferred */
+ if (data) {
+ flags = DATA_COMPLETE;
+ do {
+ state = mmio_read_32(reg_base + INTSTAT);
+
+ if (state & (INTSTATEN_DTOE | DATA_ERR)) {
+ err = -EIO;
+ ERROR("imx_usdhc mmc data state 0x%x\n", state);
+ goto out;
+ }
+ } while ((state & flags) != flags);
+ }
+
+out:
+ /* Reset CMD and DATA on error */
+ if (err) {
+ mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTC);
+ while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTC)
+ ;
+
+ if (data) {
+ mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTD);
+ while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTD)
+ ;
+ }
+ }
+
+ /* clear all irq status */
+ mmio_write_32(reg_base + INTSTAT, 0xffffffff);
+
+ return err;
+}
+
+static int imx_usdhc_set_ios(unsigned int clk, unsigned int width)
+{
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+
+ imx_usdhc_set_clk(clk);
+
+ if (width == MMC_BUS_WIDTH_4)
+ mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,
+ PROTCTRL_WIDTH_4);
+ else if (width == MMC_BUS_WIDTH_8)
+ mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,
+ PROTCTRL_WIDTH_8);
+
+ return 0;
+}
+
+static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size)
+{
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+
+ mmio_write_32(reg_base + DSADDR, buf);
+ mmio_write_32(reg_base + BLKATT,
+ (size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE);
+
+ return 0;
+}
+
+static int imx_usdhc_read(int lba, uintptr_t buf, size_t size)
+{
+ return 0;
+}
+
+static int imx_usdhc_write(int lba, uintptr_t buf, size_t size)
+{
+ return 0;
+}
+
+void imx_usdhc_init(imx_usdhc_params_t *params,
+ struct mmc_device_info *mmc_dev_info)
+{
+ assert((params != 0) &&
+ ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
+ (params->clk_rate > 0) &&
+ ((params->bus_width == MMC_BUS_WIDTH_1) ||
+ (params->bus_width == MMC_BUS_WIDTH_4) ||
+ (params->bus_width == MMC_BUS_WIDTH_8)));
+
+ memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t));
+ mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width,
+ params->flags, mmc_dev_info);
+}
diff --git a/drivers/imx/usdhc/imx_usdhc.h b/drivers/imx/usdhc/imx_usdhc.h
new file mode 100644
index 0000000..6214cc1
--- /dev/null
+++ b/drivers/imx/usdhc/imx_usdhc.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_USDHC_H__
+#define __IMX_USDHC_H__
+
+#include <mmc.h>
+
+typedef struct imx_usdhc_params {
+ uintptr_t reg_base;
+ int clk_rate;
+ int bus_width;
+ unsigned int flags;
+} imx_usdhc_params_t;
+
+void imx_usdhc_init(imx_usdhc_params_t *params,
+ struct mmc_device_info *mmc_dev_info);
+
+/* iMX MMC registers definition */
+#define DSADDR 0x000
+#define BLKATT 0x004
+#define CMDARG 0x008
+#define CMDRSP0 0x010
+#define CMDRSP1 0x014
+#define CMDRSP2 0x018
+#define CMDRSP3 0x01c
+
+#define XFERTYPE 0x00c
+#define XFERTYPE_CMD(x) (((x) & 0x3f) << 24)
+#define XFERTYPE_CMDTYP_ABORT (3 << 22)
+#define XFERTYPE_DPSEL BIT(21)
+#define XFERTYPE_CICEN BIT(20)
+#define XFERTYPE_CCCEN BIT(19)
+#define XFERTYPE_RSPTYP_136 BIT(16)
+#define XFERTYPE_RSPTYP_48 BIT(17)
+#define XFERTYPE_RSPTYP_48_BUSY (BIT(16) | BIT(17))
+
+#define PSTATE 0x024
+#define PSTATE_DAT0 BIT(24)
+#define PSTATE_DLA BIT(2)
+#define PSTATE_CDIHB BIT(1)
+#define PSTATE_CIHB BIT(0)
+
+#define PROTCTRL 0x028
+#define PROTCTRL_LE BIT(5)
+#define PROTCTRL_WIDTH_4 BIT(1)
+#define PROTCTRL_WIDTH_8 BIT(2)
+#define PROTCTRL_WIDTH_MASK 0x6
+
+#define SYSCTRL 0x02c
+#define SYSCTRL_RSTD BIT(26)
+#define SYSCTRL_RSTC BIT(25)
+#define SYSCTRL_RSTA BIT(24)
+#define SYSCTRL_CLOCK_MASK 0x0000fff0
+#define SYSCTRL_TIMEOUT_MASK 0x000f0000
+#define SYSCTRL_TIMEOUT(x) ((0xf & (x)) << 16)
+
+#define INTSTAT 0x030
+#define INTSTAT_DMAE BIT(28)
+#define INTSTAT_DEBE BIT(22)
+#define INTSTAT_DCE BIT(21)
+#define INTSTAT_DTOE BIT(20)
+#define INTSTAT_CIE BIT(19)
+#define INTSTAT_CEBE BIT(18)
+#define INTSTAT_CCE BIT(17)
+#define INTSTAT_DINT BIT(3)
+#define INTSTAT_BGE BIT(2)
+#define INTSTAT_TC BIT(1)
+#define INTSTAT_CC BIT(0)
+#define CMD_ERR (INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE)
+#define DATA_ERR (INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \
+ INTSTAT_DTOE)
+#define DATA_COMPLETE (INTSTAT_DINT | INTSTAT_TC)
+
+#define INTSTATEN 0x034
+#define INTSTATEN_DEBE BIT(22)
+#define INTSTATEN_DCE BIT(21)
+#define INTSTATEN_DTOE BIT(20)
+#define INTSTATEN_CIE BIT(19)
+#define INTSTATEN_CEBE BIT(18)
+#define INTSTATEN_CCE BIT(17)
+#define INTSTATEN_CTOE BIT(16)
+#define INTSTATEN_CINT BIT(8)
+#define INTSTATEN_BRR BIT(5)
+#define INTSTATEN_BWR BIT(4)
+#define INTSTATEN_DINT BIT(3)
+#define INTSTATEN_TC BIT(1)
+#define INTSTATEN_CC BIT(0)
+#define EMMC_INTSTATEN_BITS (INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \
+ INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \
+ INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \
+ INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \
+ INTSTATEN_DEBE)
+
+#define INTSIGEN 0x038
+
+#define WATERMARKLEV 0x044
+#define WMKLV_RD_MASK 0xff
+#define WMKLV_WR_MASK 0x00ff0000
+#define WMKLV_MASK (WMKLV_RD_MASK | WMKLV_WR_MASK)
+
+#define MIXCTRL 0x048
+#define MIXCTRL_MSBSEL BIT(5)
+#define MIXCTRL_DTDSEL BIT(4)
+#define MIXCTRL_DDREN BIT(3)
+#define MIXCTRL_AC12EN BIT(2)
+#define MIXCTRL_BCEN BIT(1)
+#define MIXCTRL_DMAEN BIT(0)
+#define MIXCTRL_DATMASK 0x7f
+
+#define DLLCTRL 0x060
+
+#define CLKTUNECTRLSTS 0x068
+
+#define VENDSPEC 0x0c0
+#define VENDSPEC_RSRV1 BIT(29)
+#define VENDSPEC_CARD_CLKEN BIT(14)
+#define VENDSPEC_PER_CLKEN BIT(13)
+#define VENDSPEC_AHB_CLKEN BIT(12)
+#define VENDSPEC_IPG_CLKEN BIT(11)
+#define VENDSPEC_AC12_CHKBUSY BIT(3)
+#define VENDSPEC_EXTDMA BIT(0)
+#define VENDSPEC_INIT (VENDSPEC_RSRV1 | VENDSPEC_CARD_CLKEN | \
+ VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \
+ VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \
+ VENDSPEC_EXTDMA)
+
+#define MMCBOOT 0x0c4
+
+#define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
+#define mmio_clrbits32(addr, clear) mmio_write_32(addr, mmio_read_32(addr) & ~(clear))
+#define mmio_setbits32(addr, set) mmio_write_32(addr, mmio_read_32(addr) | (set))
+
+#endif /* __IMX_USDHC_H__ */
diff --git a/drivers/marvell/amb_adec.c b/drivers/marvell/amb_adec.c
index 3fb2f38..16fe772 100644
--- a/drivers/marvell/amb_adec.c
+++ b/drivers/marvell/amb_adec.c
@@ -7,7 +7,7 @@
/* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */
-#include <a8k_common.h>
+#include <armada_common.h>
#include <debug.h>
#include <mmio.h>
#include <mvebu.h>
diff --git a/drivers/marvell/ccu.c b/drivers/marvell/ccu.c
index 1502c3f..acb1c00 100644
--- a/drivers/marvell/ccu.c
+++ b/drivers/marvell/ccu.c
@@ -7,7 +7,7 @@
/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */
-#include <a8k_common.h>
+#include <armada_common.h>
#include <ccu.h>
#include <debug.h>
#include <mmio.h>
diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h
index 925abb5..6afa2c2 100644
--- a/drivers/marvell/comphy/comphy-cp110.h
+++ b/drivers/marvell/comphy/comphy-cp110.h
@@ -217,9 +217,9 @@
#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET 3
+#define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK \
+ (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET)
#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
@@ -251,9 +251,9 @@
#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET 3
+#define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK \
+ (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET)
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index 8b78280..19bd182 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -481,8 +481,8 @@
/* G1 settings */
mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
@@ -506,8 +506,8 @@
/* G2 settings */
mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
+ data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
@@ -1000,13 +1000,13 @@
if (speed == COMPHY_SPEED_5_15625G) {
mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
} else {
mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
- data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+ data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
@@ -1504,8 +1504,8 @@
/* Genration 2 setting 1*/
mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
+ data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
@@ -1741,8 +1741,8 @@
/* 0xE-G1_Setting_1 */
mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
@@ -2201,7 +2201,7 @@
return 0;
}
-int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint64_t comphy_index,
+int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
uint64_t comphy_mode)
{
int mode = COMPHY_GET_MODE(comphy_mode);
@@ -2247,7 +2247,7 @@
err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index);
break;
default:
- ERROR("comphy%lld: unsupported comphy mode\n", comphy_index);
+ ERROR("comphy%d: unsupported comphy mode\n", comphy_index);
err = -EINVAL;
break;
}
@@ -2257,7 +2257,7 @@
return err;
}
-int mvebu_cp110_comphy_power_off(uint64_t comphy_base, uint64_t comphy_index)
+int mvebu_cp110_comphy_power_off(uint64_t comphy_base, uint8_t comphy_index)
{
uintptr_t sd_ip_addr, comphy_ip_addr;
uint32_t mask, data;
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.h b/drivers/marvell/comphy/phy-comphy-cp110.h
index ada6aec..2461e5c 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.h
+++ b/drivers/marvell/comphy/phy-comphy-cp110.h
@@ -8,11 +8,11 @@
/* Marvell CP110 SoC COMPHY unit driver */
int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
- uint64_t comphy_index);
+ uint8_t comphy_index);
int mvebu_cp110_comphy_power_off(uint64_t comphy_base,
- uint64_t comphy_index);
+ uint8_t comphy_index);
int mvebu_cp110_comphy_power_on(uint64_t comphy_base,
- uint64_t comphy_index, uint64_t comphy_mode);
+ uint8_t comphy_index, uint64_t comphy_mode);
int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
uint8_t comphy_index);
int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,
diff --git a/drivers/marvell/gwin.c b/drivers/marvell/gwin.c
index b5705f7..a4743eb 100644
--- a/drivers/marvell/gwin.c
+++ b/drivers/marvell/gwin.c
@@ -7,7 +7,7 @@
/* GWIN unit device driver for Marvell AP810 SoC */
-#include <a8k_common.h>
+#include <armada_common.h>
#include <debug.h>
#include <gwin.h>
#include <mmio.h>
diff --git a/drivers/marvell/i2c/a8k_i2c.c b/drivers/marvell/i2c/a8k_i2c.c
index 737dd0a..1c0f922 100644
--- a/drivers/marvell/i2c/a8k_i2c.c
+++ b/drivers/marvell/i2c/a8k_i2c.c
@@ -7,57 +7,22 @@
/* This driver provides I2C support for Marvell A8K and compatible SoCs */
-#include <a8k_i2c.h>
-#include <debug.h>
-#include <delay_timer.h>
-#include <errno.h>
#include <mmio.h>
-#include <mvebu_def.h>
-
-#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
-#define DEBUG_I2C
-#endif
#define CONFIG_SYS_TCLK 250000000
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0x0
-#define I2C_TIMEOUT_VALUE 0x500
-#define I2C_MAX_RETRY_CNT 1000
-#define I2C_CMD_WRITE 0x0
-#define I2C_CMD_READ 0x1
-
-#define I2C_DATA_ADDR_7BIT_OFFS 0x1
-#define I2C_DATA_ADDR_7BIT_MASK (0xFF << I2C_DATA_ADDR_7BIT_OFFS)
-
-#define I2C_CONTROL_ACK 0x00000004
-#define I2C_CONTROL_IFLG 0x00000008
-#define I2C_CONTROL_STOP 0x00000010
-#define I2C_CONTROL_START 0x00000020
-#define I2C_CONTROL_TWSIEN 0x00000040
-#define I2C_CONTROL_INTEN 0x00000080
-#define I2C_STATUS_START 0x08
-#define I2C_STATUS_REPEATED_START 0x10
-#define I2C_STATUS_ADDR_W_ACK 0x18
-#define I2C_STATUS_DATA_W_ACK 0x28
-#define I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER 0x38
-#define I2C_STATUS_ADDR_R_ACK 0x40
-#define I2C_STATUS_DATA_R_ACK 0x50
-#define I2C_STATUS_DATA_R_NAK 0x58
-#define I2C_STATUS_LOST_ARB_GENERAL_CALL 0x78
-#define I2C_STATUS_IDLE 0xF8
+#define I2C_CAN_UNSTUCK
-#define I2C_UNSTUCK_TRIGGER 0x1
-#define I2C_UNSTUCK_ONGOING 0x2
-#define I2C_UNSTUCK_ERROR 0x4
-struct marvell_i2c_regs {
+struct mentor_i2c_regs {
uint32_t slave_address;
uint32_t data;
uint32_t control;
union {
uint32_t status; /* when reading */
uint32_t baudrate; /* when writing */
- } u;
+ };
uint32_t xtnd_slave_addr;
uint32_t reserved[2];
uint32_t soft_reset;
@@ -65,549 +30,4 @@
uint32_t unstuck;
};
-static struct marvell_i2c_regs *base;
-
-static int marvell_i2c_lost_arbitration(uint32_t *status)
-{
- *status = mmio_read_32((uintptr_t)&base->u.status);
- if ((*status == I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER) ||
- (*status == I2C_STATUS_LOST_ARB_GENERAL_CALL))
- return -EAGAIN;
-
- return 0;
-}
-
-static void marvell_i2c_interrupt_clear(void)
-{
- uint32_t reg;
-
- reg = mmio_read_32((uintptr_t)&base->control);
- reg &= ~(I2C_CONTROL_IFLG);
- mmio_write_32((uintptr_t)&base->control, reg);
- /* Wait for 1 us for the clear to take effect */
- udelay(1);
-}
-
-static int marvell_i2c_interrupt_get(void)
-{
- uint32_t reg;
-
- /* get the interrupt flag bit */
- reg = mmio_read_32((uintptr_t)&base->control);
- reg &= I2C_CONTROL_IFLG;
- return reg && I2C_CONTROL_IFLG;
-}
-
-static int marvell_i2c_wait_interrupt(void)
-{
- uint32_t timeout = 0;
-
- while (!marvell_i2c_interrupt_get() && (timeout++ < I2C_TIMEOUT_VALUE))
- ;
- if (timeout >= I2C_TIMEOUT_VALUE)
- return -ETIMEDOUT;
-
- return 0;
-}
-
-static int marvell_i2c_start_bit_set(void)
-{
- int is_int_flag = 0;
- uint32_t status;
-
- if (marvell_i2c_interrupt_get())
- is_int_flag = 1;
-
- /* set start bit */
- mmio_write_32((uintptr_t)&base->control,
- mmio_read_32((uintptr_t)&base->control) |
- I2C_CONTROL_START);
-
- /* in case that the int flag was set before i.e. repeated start bit */
- if (is_int_flag) {
- VERBOSE("%s: repeated start Bit\n", __func__);
- marvell_i2c_interrupt_clear();
- }
-
- if (marvell_i2c_wait_interrupt()) {
- ERROR("Start clear bit timeout\n");
- return -ETIMEDOUT;
- }
-
- /* check that start bit went down */
- if ((mmio_read_32((uintptr_t)&base->control) &
- I2C_CONTROL_START) != 0) {
- ERROR("Start bit didn't went down\n");
- return -EPERM;
- }
-
- /* check the status */
- if (marvell_i2c_lost_arbitration(&status)) {
- ERROR("%s - %d: Lost arbitration, got status %x\n",
- __func__, __LINE__, status);
- return -EAGAIN;
- }
- if ((status != I2C_STATUS_START) &&
- (status != I2C_STATUS_REPEATED_START)) {
- ERROR("Got status %x after enable start bit.\n", status);
- return -EPERM;
- }
-
- return 0;
-}
-
-static int marvell_i2c_stop_bit_set(void)
-{
- int timeout;
- uint32_t status;
-
- /* Generate stop bit */
- mmio_write_32((uintptr_t)&base->control,
- mmio_read_32((uintptr_t)&base->control) |
- I2C_CONTROL_STOP);
- marvell_i2c_interrupt_clear();
-
- timeout = 0;
- /* Read control register, check the control stop bit */
- while ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_STOP) &&
- (timeout++ < I2C_TIMEOUT_VALUE))
- ;
- if (timeout >= I2C_TIMEOUT_VALUE) {
- ERROR("Stop bit didn't went down\n");
- return -ETIMEDOUT;
- }
-
- /* check that stop bit went down */
- if ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_STOP) != 0) {
- ERROR("Stop bit didn't went down\n");
- return -EPERM;
- }
-
- /* check the status */
- if (marvell_i2c_lost_arbitration(&status)) {
- ERROR("%s - %d: Lost arbitration, got status %x\n",
- __func__, __LINE__, status);
- return -EAGAIN;
- }
- if (status != I2C_STATUS_IDLE) {
- ERROR("Got status %x after enable stop bit.\n", status);
- return -EPERM;
- }
-
- return 0;
-}
-
-static int marvell_i2c_address_set(uint8_t chain, int command)
-{
- uint32_t reg, status;
-
- reg = (chain << I2C_DATA_ADDR_7BIT_OFFS) & I2C_DATA_ADDR_7BIT_MASK;
- reg |= command;
- mmio_write_32((uintptr_t)&base->data, reg);
- udelay(1);
-
- marvell_i2c_interrupt_clear();
-
- if (marvell_i2c_wait_interrupt()) {
- ERROR("Start clear bit timeout\n");
- return -ETIMEDOUT;
- }
-
- /* check the status */
- if (marvell_i2c_lost_arbitration(&status)) {
- ERROR("%s - %d: Lost arbitration, got status %x\n",
- __func__, __LINE__, status);
- return -EAGAIN;
- }
- if (((status != I2C_STATUS_ADDR_R_ACK) && (command == I2C_CMD_READ)) ||
- ((status != I2C_STATUS_ADDR_W_ACK) && (command == I2C_CMD_WRITE))) {
- /* only in debug, since in boot we try to read the SPD
- * of both DRAM, and we don't want error messages in cas
- * DIMM doesn't exist.
- */
- INFO("%s: ERROR - status %x addr in %s mode.\n", __func__,
- status, (command == I2C_CMD_WRITE) ? "Write" : "Read");
- return -EPERM;
- }
-
- return 0;
-}
-
-/*
- * The I2C module contains a clock divider to generate the SCL clock.
- * This function calculates and sets the <N> and <M> fields in the I2C Baud
- * Rate Register (t=01) to obtain given 'requested_speed'.
- * The requested_speed will be equal to:
- * CONFIG_SYS_TCLK / (10 * (M + 1) * (2 << N))
- * Where M is the value represented by bits[6:3] and N is the value represented
- * by bits[2:0] of "I2C Baud Rate Register".
- * Therefore max M which can be set is 16 (2^4) and max N is 8 (2^3). So the
- * lowest possible baudrate is:
- * CONFIG_SYS_TCLK/(10 * (16 +1) * (2 << 8), which equals to:
- * CONFIG_SYS_TCLK/87040. Assuming that CONFIG_SYS_TCLK=250MHz, the lowest
- * possible frequency is ~2,872KHz.
- */
-static unsigned int marvell_i2c_bus_speed_set(unsigned int requested_speed)
-{
- unsigned int n, m, freq, margin, min_margin = 0xffffffff;
- unsigned int actual_n = 0, actual_m = 0;
- int val;
-
- /* Calculate N and M for the TWSI clock baud rate */
- for (n = 0; n < 8; n++) {
- for (m = 0; m < 16; m++) {
- freq = CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
- val = requested_speed - freq;
- margin = (val > 0) ? val : -val;
-
- if ((freq <= requested_speed) &&
- (margin < min_margin)) {
- min_margin = margin;
- actual_n = n;
- actual_m = m;
- }
- }
- }
- VERBOSE("%s: actual_n = %u, actual_m = %u\n",
- __func__, actual_n, actual_m);
- /* Set the baud rate */
- mmio_write_32((uintptr_t)&base->u.baudrate, (actual_m << 3) | actual_n);
-
- return 0;
-}
-
-#ifdef DEBUG_I2C
-static int marvell_i2c_probe(uint8_t chip)
-{
- int ret = 0;
-
- ret = marvell_i2c_start_bit_set();
- if (ret != 0) {
- marvell_i2c_stop_bit_set();
- ERROR("%s - %d: %s", __func__, __LINE__,
- "marvell_i2c_start_bit_set failed\n");
- return -EPERM;
- }
-
- ret = marvell_i2c_address_set(chip, I2C_CMD_WRITE);
- if (ret != 0) {
- marvell_i2c_stop_bit_set();
- ERROR("%s - %d: %s", __func__, __LINE__,
- "marvell_i2c_address_set failed\n");
- return -EPERM;
- }
-
- marvell_i2c_stop_bit_set();
-
- VERBOSE("%s: successful I2C probe\n", __func__);
-
- return ret;
-}
-#endif
-
-/* regular i2c transaction */
-static int marvell_i2c_data_receive(uint8_t *p_block, uint32_t block_size)
-{
- uint32_t reg, status, block_size_read = block_size;
-
- /* Wait for cause interrupt */
- if (marvell_i2c_wait_interrupt()) {
- ERROR("Start clear bit timeout\n");
- return -ETIMEDOUT;
- }
- while (block_size_read) {
- if (block_size_read == 1) {
- reg = mmio_read_32((uintptr_t)&base->control);
- reg &= ~(I2C_CONTROL_ACK);
- mmio_write_32((uintptr_t)&base->control, reg);
- }
- marvell_i2c_interrupt_clear();
-
- if (marvell_i2c_wait_interrupt()) {
- ERROR("Start clear bit timeout\n");
- return -ETIMEDOUT;
- }
- /* check the status */
- if (marvell_i2c_lost_arbitration(&status)) {
- ERROR("%s - %d: Lost arbitration, got status %x\n",
- __func__, __LINE__, status);
- return -EAGAIN;
- }
- if ((status != I2C_STATUS_DATA_R_ACK) &&
- (block_size_read != 1)) {
- ERROR("Status %x in read transaction\n", status);
- return -EPERM;
- }
- if ((status != I2C_STATUS_DATA_R_NAK) &&
- (block_size_read == 1)) {
- ERROR("Status %x in Rd Terminate\n", status);
- return -EPERM;
- }
-
- /* read the data */
- *p_block = (uint8_t) mmio_read_32((uintptr_t)&base->data);
- VERBOSE("%s: place %d read %x\n", __func__,
- block_size - block_size_read, *p_block);
- p_block++;
- block_size_read--;
- }
-
- return 0;
-}
-
-static int marvell_i2c_data_transmit(uint8_t *p_block, uint32_t block_size)
-{
- uint32_t status, block_size_write = block_size;
-
- if (marvell_i2c_wait_interrupt()) {
- ERROR("Start clear bit timeout\n");
- return -ETIMEDOUT;
- }
-
- while (block_size_write) {
- /* write the data */
- mmio_write_32((uintptr_t)&base->data, (uint32_t) *p_block);
- VERBOSE("%s: index = %d, data = %x\n", __func__,
- block_size - block_size_write, *p_block);
- p_block++;
- block_size_write--;
-
- marvell_i2c_interrupt_clear();
-
- if (marvell_i2c_wait_interrupt()) {
- ERROR("Start clear bit timeout\n");
- return -ETIMEDOUT;
- }
-
- /* check the status */
- if (marvell_i2c_lost_arbitration(&status)) {
- ERROR("%s - %d: Lost arbitration, got status %x\n",
- __func__, __LINE__, status);
- return -EAGAIN;
- }
- if (status != I2C_STATUS_DATA_W_ACK) {
- ERROR("Status %x in write transaction\n", status);
- return -EPERM;
- }
- }
-
- return 0;
-}
-
-static int marvell_i2c_target_offset_set(uint8_t chip, uint32_t addr, int alen)
-{
- uint8_t off_block[2];
- uint32_t off_size;
-
- if (alen == 2) { /* 2-byte addresses support */
- off_block[0] = (addr >> 8) & 0xff;
- off_block[1] = addr & 0xff;
- off_size = 2;
- } else { /* 1-byte addresses support */
- off_block[0] = addr & 0xff;
- off_size = 1;
- }
- VERBOSE("%s: off_size = %x addr1 = %x addr2 = %x\n", __func__,
- off_size, off_block[0], off_block[1]);
- return marvell_i2c_data_transmit(off_block, off_size);
-}
-
-static int marvell_i2c_unstuck(int ret)
-{
- uint32_t v;
-
- if (ret != -ETIMEDOUT)
- return ret;
- VERBOSE("Trying to \"unstuck i2c\"... ");
- i2c_init(base);
- mmio_write_32((uintptr_t)&base->unstuck, I2C_UNSTUCK_TRIGGER);
- do {
- v = mmio_read_32((uintptr_t)&base->unstuck);
- } while (v & I2C_UNSTUCK_ONGOING);
-
- if (v & I2C_UNSTUCK_ERROR) {
- VERBOSE("failed - soft reset i2c\n");
- ret = -EPERM;
- } else {
- VERBOSE("ok\n");
- i2c_init(base);
- ret = -EAGAIN;
- }
- return ret;
-}
-
-/*
- * API Functions
- */
-void i2c_init(void *i2c_base)
-{
- /* For I2C speed and slave address, now we do not set them since
- * we just provide the working speed and slave address in plat_def.h
- * for i2c_init
- */
- base = (struct marvell_i2c_regs *)i2c_base;
-
- /* Reset the I2C logic */
- mmio_write_32((uintptr_t)&base->soft_reset, 0);
-
- udelay(200);
-
- marvell_i2c_bus_speed_set(CONFIG_SYS_I2C_SPEED);
-
- /* Enable the I2C and slave */
- mmio_write_32((uintptr_t)&base->control,
- I2C_CONTROL_TWSIEN | I2C_CONTROL_ACK);
-
- /* set the I2C slave address */
- mmio_write_32((uintptr_t)&base->xtnd_slave_addr, 0);
- mmio_write_32((uintptr_t)&base->slave_address, CONFIG_SYS_I2C_SLAVE);
-
- /* unmask I2C interrupt */
- mmio_write_32((uintptr_t)&base->control,
- mmio_read_32((uintptr_t)&base->control) |
- I2C_CONTROL_INTEN);
-
- udelay(10);
-}
-
-/*
- * i2c_read: - Read multiple bytes from an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be read
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to write the data
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_read(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len)
-{
- int ret = 0;
- uint32_t counter = 0;
-
-#ifdef DEBUG_I2C
- marvell_i2c_probe(chip);
-#endif
-
- do {
- if (ret != -EAGAIN && ret) {
- ERROR("i2c transaction failed, after %d retries\n",
- counter);
- marvell_i2c_stop_bit_set();
- return ret;
- }
-
- /* wait for 1 us for the interrupt clear to take effect */
- if (counter > 0)
- udelay(1);
- counter++;
-
- ret = marvell_i2c_start_bit_set();
- if (ret) {
- ret = marvell_i2c_unstuck(ret);
- continue;
- }
-
- /* if EEPROM device */
- if (alen != 0) {
- ret = marvell_i2c_address_set(chip, I2C_CMD_WRITE);
- if (ret)
- continue;
-
- ret = marvell_i2c_target_offset_set(chip, addr, alen);
- if (ret)
- continue;
- ret = marvell_i2c_start_bit_set();
- if (ret)
- continue;
- }
-
- ret = marvell_i2c_address_set(chip, I2C_CMD_READ);
- if (ret)
- continue;
-
- ret = marvell_i2c_data_receive(buffer, len);
- if (ret)
- continue;
-
- ret = marvell_i2c_stop_bit_set();
- } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT));
-
- if (counter == I2C_MAX_RETRY_CNT) {
- ERROR("I2C transactions failed, got EAGAIN %d times\n",
- I2C_MAX_RETRY_CNT);
- ret = -EPERM;
- }
- mmio_write_32((uintptr_t)&base->control,
- mmio_read_32((uintptr_t)&base->control) |
- I2C_CONTROL_ACK);
-
- udelay(1);
- return ret;
-}
-
-/*
- * i2c_write: - Write multiple bytes to an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be written
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to find the data to be written
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_write(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len)
-{
- int ret = 0;
- uint32_t counter = 0;
-
- do {
- if (ret != -EAGAIN && ret) {
- ERROR("i2c transaction failed\n");
- marvell_i2c_stop_bit_set();
- return ret;
- }
- /* wait for 1 us for the interrupt clear to take effect */
- if (counter > 0)
- udelay(1);
- counter++;
-
- ret = marvell_i2c_start_bit_set();
- if (ret) {
- ret = marvell_i2c_unstuck(ret);
- continue;
- }
-
- ret = marvell_i2c_address_set(chip, I2C_CMD_WRITE);
- if (ret)
- continue;
-
- /* if EEPROM device */
- if (alen != 0) {
- ret = marvell_i2c_target_offset_set(chip, addr, alen);
- if (ret)
- continue;
- }
-
- ret = marvell_i2c_data_transmit(buffer, len);
- if (ret)
- continue;
-
- ret = marvell_i2c_stop_bit_set();
- } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT));
-
- if (counter == I2C_MAX_RETRY_CNT) {
- ERROR("I2C transactions failed, got EAGAIN %d times\n",
- I2C_MAX_RETRY_CNT);
- ret = -EPERM;
- }
-
- udelay(1);
- return ret;
-}
+#include "../../mentor/i2c/mi2cv.c"
diff --git a/drivers/marvell/io_win.c b/drivers/marvell/io_win.c
index 40b1982..c0424e0 100644
--- a/drivers/marvell/io_win.c
+++ b/drivers/marvell/io_win.c
@@ -7,7 +7,7 @@
/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */
-#include <a8k_common.h>
+#include <armada_common.h>
#include <debug.h>
#include <io_win.h>
#include <mmio.h>
diff --git a/drivers/marvell/iob.c b/drivers/marvell/iob.c
index acc4941..e88bc16 100644
--- a/drivers/marvell/iob.c
+++ b/drivers/marvell/iob.c
@@ -7,7 +7,7 @@
/* IOW unit device driver for Marvell CP110 and CP115 SoCs */
-#include <a8k_common.h>
+#include <armada_common.h>
#include <arch_helpers.h>
#include <debug.h>
#include <iob.h>
diff --git a/drivers/marvell/mc_trustzone/mc_trustzone.c b/drivers/marvell/mc_trustzone/mc_trustzone.c
new file mode 100644
index 0000000..0db3b8d
--- /dev/null
+++ b/drivers/marvell/mc_trustzone/mc_trustzone.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <addr_map.h>
+#include <debug.h>
+#include <mmio.h>
+#include <mvebu_def.h>
+#include "mc_trustzone.h"
+
+#define TZ_SIZE(x) ((x) >> 13)
+
+static int fls(int x)
+{
+ if (!x)
+ return 0;
+
+ return 32 - __builtin_clz(x);
+}
+
+/* To not duplicate types, the addr_map_win is used, but the "target"
+ * filed is referring to attributes instead of "target".
+ */
+void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id)
+{
+ int tz_size;
+ uint32_t val, base = win->base_addr;
+
+ if ((win_id < 0) || (win_id > MVEBU_TZ_MAX_WINS)) {
+ ERROR("Enabling wrong MC TrustZone window %d!\n", win_id);
+ return;
+ }
+
+ /* map the window size to trustzone register convention */
+ tz_size = fls(TZ_SIZE(win->win_size));
+
+ VERBOSE("%s: window size = 0x%llx maps to tz_size %d\n",
+ __func__, win->win_size, tz_size);
+ if (tz_size < 0 || tz_size > 31) {
+ ERROR("Using not allowed size for MC TrustZone window %d!\n",
+ win_id);
+ return;
+ }
+
+ if (base & 0xfff) {
+ base = base & ~0xfff;
+ WARN("Attempt to open MC TZ win. at 0x%llx, truncate to 0x%x\n",
+ win->base_addr, base);
+ }
+
+ val = base | (tz_size << 7) | win->target_id | TZ_VALID;
+
+ VERBOSE("%s: base 0x%x, tz_size moved 0x%x, attr 0x%x, val 0x%x\n",
+ __func__, base, (tz_size << 7), win->target_id, val);
+
+ mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), val);
+
+ VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id,
+ MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id),
+ mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id)));
+
+ mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id),
+ (win->base_addr >> 32));
+
+ VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id,
+ MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id),
+ mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id)));
+}
diff --git a/drivers/marvell/mc_trustzone/mc_trustzone.h b/drivers/marvell/mc_trustzone/mc_trustzone.h
new file mode 100644
index 0000000..8a06923
--- /dev/null
+++ b/drivers/marvell/mc_trustzone/mc_trustzone.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef _MC_TRUSTZONE_H
+#define _MC_TRUSTZONE_H
+
+#include <addr_map.h>
+
+#define MVEBU_TZ_MAX_WINS 16
+
+#define TZ_VALID (1 << 0)
+#define TZ_PERM(x) ((x) << 1)
+#define TZ_RZ_ENABLE (1 << 3)
+
+/* tz attr definitions */
+#define TZ_PERM_RW (TZ_PERM(0))
+#define TZ_PERM_RO (TZ_PERM(1))
+#define TZ_PERM_WO (TZ_PERM(2))
+#define TZ_PERM_ABORT (TZ_PERM(3))
+
+void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id);
+
+#endif /* _MC_TRUSTZONE_H */
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index c4cb307..654bb62 100644
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c
@@ -341,10 +341,6 @@
mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0);
mdelay(500);
- /* Reset Time register */
- mmio_write_32(base + MVEBU_RTC_TIME_REG, 0);
- udelay(62);
-
/* Reset Status register */
mmio_write_32(base + MVEBU_RTC_STATUS_REG,
(MVEBU_RTC_STATUS_ALARM1_MASK |
@@ -361,10 +357,6 @@
mmio_write_32(base + MVEBU_RTC_CCR_REG,
MVEBU_RTC_NOMINAL_TIMING);
- /* Reset Time register */
- mmio_write_32(base + MVEBU_RTC_TIME_REG, 0);
- udelay(10);
-
/* Reset Status register */
mmio_write_32(base + MVEBU_RTC_STATUS_REG,
(MVEBU_RTC_STATUS_ALARM1_MASK |
diff --git a/drivers/mentor/i2c/mi2cv.c b/drivers/mentor/i2c/mi2cv.c
new file mode 100644
index 0000000..1b73e6f
--- /dev/null
+++ b/drivers/mentor/i2c/mi2cv.c
@@ -0,0 +1,611 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/*
+ * This driver is for Mentor Graphics Inventra MI2CV IP core, which is used
+ * for Marvell and Allwinner SoCs in ATF.
+ */
+
+#include <debug.h>
+#include <delay_timer.h>
+#include <errno.h>
+#include <mentor/mi2cv.h>
+#include <mmio.h>
+
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+#define DEBUG_I2C
+#endif
+
+#define I2C_TIMEOUT_VALUE 0x500
+#define I2C_MAX_RETRY_CNT 1000
+#define I2C_CMD_WRITE 0x0
+#define I2C_CMD_READ 0x1
+
+#define I2C_DATA_ADDR_7BIT_OFFS 0x1
+#define I2C_DATA_ADDR_7BIT_MASK (0xFF << I2C_DATA_ADDR_7BIT_OFFS)
+
+#define I2C_CONTROL_ACK 0x00000004
+#define I2C_CONTROL_IFLG 0x00000008
+#define I2C_CONTROL_STOP 0x00000010
+#define I2C_CONTROL_START 0x00000020
+#define I2C_CONTROL_TWSIEN 0x00000040
+#define I2C_CONTROL_INTEN 0x00000080
+
+#define I2C_STATUS_START 0x08
+#define I2C_STATUS_REPEATED_START 0x10
+#define I2C_STATUS_ADDR_W_ACK 0x18
+#define I2C_STATUS_DATA_W_ACK 0x28
+#define I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER 0x38
+#define I2C_STATUS_ADDR_R_ACK 0x40
+#define I2C_STATUS_DATA_R_ACK 0x50
+#define I2C_STATUS_DATA_R_NAK 0x58
+#define I2C_STATUS_LOST_ARB_GENERAL_CALL 0x78
+#define I2C_STATUS_IDLE 0xF8
+
+#define I2C_UNSTUCK_TRIGGER 0x1
+#define I2C_UNSTUCK_ONGOING 0x2
+#define I2C_UNSTUCK_ERROR 0x4
+
+static struct mentor_i2c_regs *base;
+
+static int mentor_i2c_lost_arbitration(uint32_t *status)
+{
+ *status = mmio_read_32((uintptr_t)&base->status);
+ if ((*status == I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER) ||
+ (*status == I2C_STATUS_LOST_ARB_GENERAL_CALL))
+ return -EAGAIN;
+
+ return 0;
+}
+
+static void mentor_i2c_interrupt_clear(void)
+{
+ uint32_t reg;
+
+ reg = mmio_read_32((uintptr_t)&base->control);
+#ifndef I2C_INTERRUPT_CLEAR_INVERTED
+ reg &= ~(I2C_CONTROL_IFLG);
+#else
+ reg |= I2C_CONTROL_IFLG;
+#endif
+ mmio_write_32((uintptr_t)&base->control, reg);
+ /* Wait for 1 us for the clear to take effect */
+ udelay(1);
+}
+
+static int mentor_i2c_interrupt_get(void)
+{
+ uint32_t reg;
+
+ /* get the interrupt flag bit */
+ reg = mmio_read_32((uintptr_t)&base->control);
+ reg &= I2C_CONTROL_IFLG;
+ return reg && I2C_CONTROL_IFLG;
+}
+
+static int mentor_i2c_wait_interrupt(void)
+{
+ uint32_t timeout = 0;
+
+ while (!mentor_i2c_interrupt_get() && (timeout++ < I2C_TIMEOUT_VALUE))
+ ;
+ if (timeout >= I2C_TIMEOUT_VALUE)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int mentor_i2c_start_bit_set(void)
+{
+ int is_int_flag = 0;
+ uint32_t status;
+
+ if (mentor_i2c_interrupt_get())
+ is_int_flag = 1;
+
+ /* set start bit */
+ mmio_write_32((uintptr_t)&base->control,
+ mmio_read_32((uintptr_t)&base->control) |
+ I2C_CONTROL_START);
+
+ /* in case that the int flag was set before i.e. repeated start bit */
+ if (is_int_flag) {
+ VERBOSE("%s: repeated start Bit\n", __func__);
+ mentor_i2c_interrupt_clear();
+ }
+
+ if (mentor_i2c_wait_interrupt()) {
+ ERROR("Start clear bit timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ /* check that start bit went down */
+ if ((mmio_read_32((uintptr_t)&base->control) &
+ I2C_CONTROL_START) != 0) {
+ ERROR("Start bit didn't went down\n");
+ return -EPERM;
+ }
+
+ /* check the status */
+ if (mentor_i2c_lost_arbitration(&status)) {
+ ERROR("%s - %d: Lost arbitration, got status %x\n",
+ __func__, __LINE__, status);
+ return -EAGAIN;
+ }
+ if ((status != I2C_STATUS_START) &&
+ (status != I2C_STATUS_REPEATED_START)) {
+ ERROR("Got status %x after enable start bit.\n", status);
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+static int mentor_i2c_stop_bit_set(void)
+{
+ int timeout;
+ uint32_t status;
+
+ /* Generate stop bit */
+ mmio_write_32((uintptr_t)&base->control,
+ mmio_read_32((uintptr_t)&base->control) |
+ I2C_CONTROL_STOP);
+ mentor_i2c_interrupt_clear();
+
+ timeout = 0;
+ /* Read control register, check the control stop bit */
+ while ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_STOP) &&
+ (timeout++ < I2C_TIMEOUT_VALUE))
+ ;
+ if (timeout >= I2C_TIMEOUT_VALUE) {
+ ERROR("Stop bit didn't went down\n");
+ return -ETIMEDOUT;
+ }
+
+ /* check that stop bit went down */
+ if ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_STOP) != 0) {
+ ERROR("Stop bit didn't went down\n");
+ return -EPERM;
+ }
+
+ /* check the status */
+ if (mentor_i2c_lost_arbitration(&status)) {
+ ERROR("%s - %d: Lost arbitration, got status %x\n",
+ __func__, __LINE__, status);
+ return -EAGAIN;
+ }
+ if (status != I2C_STATUS_IDLE) {
+ ERROR("Got status %x after enable stop bit.\n", status);
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+static int mentor_i2c_address_set(uint8_t chain, int command)
+{
+ uint32_t reg, status;
+
+ reg = (chain << I2C_DATA_ADDR_7BIT_OFFS) & I2C_DATA_ADDR_7BIT_MASK;
+ reg |= command;
+ mmio_write_32((uintptr_t)&base->data, reg);
+ udelay(1);
+
+ mentor_i2c_interrupt_clear();
+
+ if (mentor_i2c_wait_interrupt()) {
+ ERROR("Start clear bit timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ /* check the status */
+ if (mentor_i2c_lost_arbitration(&status)) {
+ ERROR("%s - %d: Lost arbitration, got status %x\n",
+ __func__, __LINE__, status);
+ return -EAGAIN;
+ }
+ if (((status != I2C_STATUS_ADDR_R_ACK) && (command == I2C_CMD_READ)) ||
+ ((status != I2C_STATUS_ADDR_W_ACK) && (command == I2C_CMD_WRITE))) {
+ /* only in debug, since in boot we try to read the SPD
+ * of both DRAM, and we don't want error messages in cas
+ * DIMM doesn't exist.
+ */
+ INFO("%s: ERROR - status %x addr in %s mode.\n", __func__,
+ status, (command == I2C_CMD_WRITE) ? "Write" : "Read");
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/*
+ * The I2C module contains a clock divider to generate the SCL clock.
+ * This function calculates and sets the <N> and <M> fields in the I2C Baud
+ * Rate Register (t=01) to obtain given 'requested_speed'.
+ * The requested_speed will be equal to:
+ * CONFIG_SYS_TCLK / (10 * (M + 1) * (2 << N))
+ * Where M is the value represented by bits[6:3] and N is the value represented
+ * by bits[2:0] of "I2C Baud Rate Register".
+ * Therefore max M which can be set is 16 (2^4) and max N is 8 (2^3). So the
+ * lowest possible baudrate is:
+ * CONFIG_SYS_TCLK/(10 * (16 +1) * (2 << 8), which equals to:
+ * CONFIG_SYS_TCLK/87040. Assuming that CONFIG_SYS_TCLK=250MHz, the lowest
+ * possible frequency is ~2,872KHz.
+ */
+static unsigned int mentor_i2c_bus_speed_set(unsigned int requested_speed)
+{
+ unsigned int n, m, freq, margin, min_margin = 0xffffffff;
+ unsigned int actual_n = 0, actual_m = 0;
+ int val;
+
+ /* Calculate N and M for the TWSI clock baud rate */
+ for (n = 0; n < 8; n++) {
+ for (m = 0; m < 16; m++) {
+ freq = CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
+ val = requested_speed - freq;
+ margin = (val > 0) ? val : -val;
+
+ if ((freq <= requested_speed) &&
+ (margin < min_margin)) {
+ min_margin = margin;
+ actual_n = n;
+ actual_m = m;
+ }
+ }
+ }
+ VERBOSE("%s: actual_n = %u, actual_m = %u\n",
+ __func__, actual_n, actual_m);
+ /* Set the baud rate */
+ mmio_write_32((uintptr_t)&base->baudrate, (actual_m << 3) | actual_n);
+
+ return 0;
+}
+
+#ifdef DEBUG_I2C
+static int mentor_i2c_probe(uint8_t chip)
+{
+ int ret = 0;
+
+ ret = mentor_i2c_start_bit_set();
+ if (ret != 0) {
+ mentor_i2c_stop_bit_set();
+ ERROR("%s - %d: %s", __func__, __LINE__,
+ "mentor_i2c_start_bit_set failed\n");
+ return -EPERM;
+ }
+
+ ret = mentor_i2c_address_set(chip, I2C_CMD_WRITE);
+ if (ret != 0) {
+ mentor_i2c_stop_bit_set();
+ ERROR("%s - %d: %s", __func__, __LINE__,
+ "mentor_i2c_address_set failed\n");
+ return -EPERM;
+ }
+
+ mentor_i2c_stop_bit_set();
+
+ VERBOSE("%s: successful I2C probe\n", __func__);
+
+ return ret;
+}
+#endif
+
+/* regular i2c transaction */
+static int mentor_i2c_data_receive(uint8_t *p_block, uint32_t block_size)
+{
+ uint32_t reg, status, block_size_read = block_size;
+
+ /* Wait for cause interrupt */
+ if (mentor_i2c_wait_interrupt()) {
+ ERROR("Start clear bit timeout\n");
+ return -ETIMEDOUT;
+ }
+ while (block_size_read) {
+ if (block_size_read == 1) {
+ reg = mmio_read_32((uintptr_t)&base->control);
+ reg &= ~(I2C_CONTROL_ACK);
+ mmio_write_32((uintptr_t)&base->control, reg);
+ }
+ mentor_i2c_interrupt_clear();
+
+ if (mentor_i2c_wait_interrupt()) {
+ ERROR("Start clear bit timeout\n");
+ return -ETIMEDOUT;
+ }
+ /* check the status */
+ if (mentor_i2c_lost_arbitration(&status)) {
+ ERROR("%s - %d: Lost arbitration, got status %x\n",
+ __func__, __LINE__, status);
+ return -EAGAIN;
+ }
+ if ((status != I2C_STATUS_DATA_R_ACK) &&
+ (block_size_read != 1)) {
+ ERROR("Status %x in read transaction\n", status);
+ return -EPERM;
+ }
+ if ((status != I2C_STATUS_DATA_R_NAK) &&
+ (block_size_read == 1)) {
+ ERROR("Status %x in Rd Terminate\n", status);
+ return -EPERM;
+ }
+
+ /* read the data */
+ *p_block = (uint8_t) mmio_read_32((uintptr_t)&base->data);
+ VERBOSE("%s: place %d read %x\n", __func__,
+ block_size - block_size_read, *p_block);
+ p_block++;
+ block_size_read--;
+ }
+
+ return 0;
+}
+
+static int mentor_i2c_data_transmit(uint8_t *p_block, uint32_t block_size)
+{
+ uint32_t status, block_size_write = block_size;
+
+ if (mentor_i2c_wait_interrupt()) {
+ ERROR("Start clear bit timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ while (block_size_write) {
+ /* write the data */
+ mmio_write_32((uintptr_t)&base->data, (uint32_t) *p_block);
+ VERBOSE("%s: index = %d, data = %x\n", __func__,
+ block_size - block_size_write, *p_block);
+ p_block++;
+ block_size_write--;
+
+ mentor_i2c_interrupt_clear();
+
+ if (mentor_i2c_wait_interrupt()) {
+ ERROR("Start clear bit timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ /* check the status */
+ if (mentor_i2c_lost_arbitration(&status)) {
+ ERROR("%s - %d: Lost arbitration, got status %x\n",
+ __func__, __LINE__, status);
+ return -EAGAIN;
+ }
+ if (status != I2C_STATUS_DATA_W_ACK) {
+ ERROR("Status %x in write transaction\n", status);
+ return -EPERM;
+ }
+ }
+
+ return 0;
+}
+
+static int mentor_i2c_target_offset_set(uint8_t chip, uint32_t addr, int alen)
+{
+ uint8_t off_block[2];
+ uint32_t off_size;
+
+ if (alen == 2) { /* 2-byte addresses support */
+ off_block[0] = (addr >> 8) & 0xff;
+ off_block[1] = addr & 0xff;
+ off_size = 2;
+ } else { /* 1-byte addresses support */
+ off_block[0] = addr & 0xff;
+ off_size = 1;
+ }
+ VERBOSE("%s: off_size = %x addr1 = %x addr2 = %x\n", __func__,
+ off_size, off_block[0], off_block[1]);
+ return mentor_i2c_data_transmit(off_block, off_size);
+}
+
+#ifdef I2C_CAN_UNSTUCK
+static int mentor_i2c_unstuck(int ret)
+{
+ uint32_t v;
+
+ if (ret != -ETIMEDOUT)
+ return ret;
+ VERBOSE("Trying to \"unstuck i2c\"... ");
+ i2c_init(base);
+ mmio_write_32((uintptr_t)&base->unstuck, I2C_UNSTUCK_TRIGGER);
+ do {
+ v = mmio_read_32((uintptr_t)&base->unstuck);
+ } while (v & I2C_UNSTUCK_ONGOING);
+
+ if (v & I2C_UNSTUCK_ERROR) {
+ VERBOSE("failed - soft reset i2c\n");
+ ret = -EPERM;
+ } else {
+ VERBOSE("ok\n");
+ i2c_init(base);
+ ret = -EAGAIN;
+ }
+ return ret;
+}
+#else
+static int mentor_i2c_unstuck(int ret)
+{
+ VERBOSE("Cannot \"unstuck i2c\" - soft reset i2c\n");
+ return -EPERM;
+}
+#endif
+
+/*
+ * API Functions
+ */
+void i2c_init(void *i2c_base)
+{
+ /* For I2C speed and slave address, now we do not set them since
+ * we just provide the working speed and slave address otherwhere
+ * for i2c_init
+ */
+ base = (struct mentor_i2c_regs *)i2c_base;
+
+ /* Reset the I2C logic */
+ mmio_write_32((uintptr_t)&base->soft_reset, 0);
+
+ udelay(200);
+
+ mentor_i2c_bus_speed_set(CONFIG_SYS_I2C_SPEED);
+
+ /* Enable the I2C and slave */
+ mmio_write_32((uintptr_t)&base->control,
+ I2C_CONTROL_TWSIEN | I2C_CONTROL_ACK);
+
+ /* set the I2C slave address */
+ mmio_write_32((uintptr_t)&base->xtnd_slave_addr, 0);
+ mmio_write_32((uintptr_t)&base->slave_address, CONFIG_SYS_I2C_SLAVE);
+
+ /* unmask I2C interrupt */
+ mmio_write_32((uintptr_t)&base->control,
+ mmio_read_32((uintptr_t)&base->control) |
+ I2C_CONTROL_INTEN);
+
+ udelay(10);
+}
+
+/*
+ * i2c_read: - Read multiple bytes from an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip: address of the chip which is to be read
+ * @addr: i2c data address within the chip
+ * @alen: length of the i2c data address (1..2 bytes)
+ * @buffer: where to write the data
+ * @len: how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_read(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len)
+{
+ int ret = 0;
+ uint32_t counter = 0;
+
+#ifdef DEBUG_I2C
+ mentor_i2c_probe(chip);
+#endif
+
+ do {
+ if (ret != -EAGAIN && ret) {
+ ERROR("i2c transaction failed, after %d retries\n",
+ counter);
+ mentor_i2c_stop_bit_set();
+ return ret;
+ }
+
+ /* wait for 1 us for the interrupt clear to take effect */
+ if (counter > 0)
+ udelay(1);
+ counter++;
+
+ ret = mentor_i2c_start_bit_set();
+ if (ret) {
+ ret = mentor_i2c_unstuck(ret);
+ continue;
+ }
+
+ /* if EEPROM device */
+ if (alen != 0) {
+ ret = mentor_i2c_address_set(chip, I2C_CMD_WRITE);
+ if (ret)
+ continue;
+
+ ret = mentor_i2c_target_offset_set(chip, addr, alen);
+ if (ret)
+ continue;
+ ret = mentor_i2c_start_bit_set();
+ if (ret)
+ continue;
+ }
+
+ ret = mentor_i2c_address_set(chip, I2C_CMD_READ);
+ if (ret)
+ continue;
+
+ ret = mentor_i2c_data_receive(buffer, len);
+ if (ret)
+ continue;
+
+ ret = mentor_i2c_stop_bit_set();
+ } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT));
+
+ if (counter == I2C_MAX_RETRY_CNT) {
+ ERROR("I2C transactions failed, got EAGAIN %d times\n",
+ I2C_MAX_RETRY_CNT);
+ ret = -EPERM;
+ }
+ mmio_write_32((uintptr_t)&base->control,
+ mmio_read_32((uintptr_t)&base->control) |
+ I2C_CONTROL_ACK);
+
+ udelay(1);
+ return ret;
+}
+
+/*
+ * i2c_write: - Write multiple bytes to an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip: address of the chip which is to be written
+ * @addr: i2c data address within the chip
+ * @alen: length of the i2c data address (1..2 bytes)
+ * @buffer: where to find the data to be written
+ * @len: how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_write(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len)
+{
+ int ret = 0;
+ uint32_t counter = 0;
+
+ do {
+ if (ret != -EAGAIN && ret) {
+ ERROR("i2c transaction failed\n");
+ mentor_i2c_stop_bit_set();
+ return ret;
+ }
+ /* wait for 1 us for the interrupt clear to take effect */
+ if (counter > 0)
+ udelay(1);
+ counter++;
+
+ ret = mentor_i2c_start_bit_set();
+ if (ret) {
+ ret = mentor_i2c_unstuck(ret);
+ continue;
+ }
+
+ ret = mentor_i2c_address_set(chip, I2C_CMD_WRITE);
+ if (ret)
+ continue;
+
+ /* if EEPROM device */
+ if (alen != 0) {
+ ret = mentor_i2c_target_offset_set(chip, addr, alen);
+ if (ret)
+ continue;
+ }
+
+ ret = mentor_i2c_data_transmit(buffer, len);
+ if (ret)
+ continue;
+
+ ret = mentor_i2c_stop_bit_set();
+ } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT));
+
+ if (counter == I2C_MAX_RETRY_CNT) {
+ ERROR("I2C transactions failed, got EAGAIN %d times\n",
+ I2C_MAX_RETRY_CNT);
+ ret = -EPERM;
+ }
+
+ udelay(1);
+ return ret;
+}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index bf87612..73287ae 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -109,7 +109,7 @@
ret = mmc_send_cmd(MMC_CMD(6),
EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
EXTCSD_VALUE(value) | EXTCSD_CMD_SET_NORMAL,
- 0, NULL);
+ MMC_RESPONSE_R1B, NULL);
if (ret != 0) {
return ret;
}
@@ -333,7 +333,7 @@
}
/* ACMD41: SD_SEND_OP_COND */
- ret = mmc_send_cmd(MMC_ACMD(41), OCR_HCS, MMC_RESPONSE_R(3),
+ ret = mmc_send_cmd(MMC_ACMD(41), OCR_HCS, MMC_RESPONSE_R3,
&resp_data[0]);
if (ret != 0) {
return ret;
@@ -384,7 +384,7 @@
for (n = 0; n < SEND_OP_COND_MAX_RETRIES; n++) {
ret = mmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7,
- MMC_RESPONSE_R(3), &resp_data[0]);
+ MMC_RESPONSE_R3, &resp_data[0]);
if (ret != 0) {
return ret;
}
@@ -539,7 +539,7 @@
} while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_DATA));
if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) {
- ret = mmc_send_cmd(MMC_CMD(12), 0, 0, NULL);
+ ret = mmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL);
if (ret != 0) {
return 0;
}
@@ -606,7 +606,7 @@
} while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_RCV));
if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) {
- ret = mmc_send_cmd(MMC_CMD(12), 0, 0, NULL);
+ ret = mmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL);
if (ret != 0) {
return 0;
}
diff --git a/drivers/synopsys/emmc/dw_mmc.c b/drivers/synopsys/emmc/dw_mmc.c
index b0b0a3f..c544233 100644
--- a/drivers/synopsys/emmc/dw_mmc.c
+++ b/drivers/synopsys/emmc/dw_mmc.c
@@ -259,11 +259,14 @@
switch (cmd->resp_type) {
case 0:
break;
- case MMC_RESPONSE_R(2):
+ case MMC_RESPONSE_R2:
op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC |
CMD_RESP_LEN;
break;
- case MMC_RESPONSE_R(3):
+ case MMC_RESPONSE_R1:
+ case MMC_RESPONSE_R1B:
+ case MMC_RESPONSE_R3:
+ case MMC_RESPONSE_R5:
op |= CMD_RESP_EXPECT;
break;
default:
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index 02ffa02..d0480db 100644
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -191,6 +191,7 @@
void gicv2_set_interrupt_pending(unsigned int id);
void gicv2_clear_interrupt_pending(unsigned int id);
unsigned int gicv2_set_pmr(unsigned int mask);
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
#endif /* __ASSEMBLY__ */
#endif /* __GICV2_H__ */
diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h
index f8f2608..59aeea9 100644
--- a/include/drivers/auth/mbedtls/mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/mbedtls_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -95,4 +95,16 @@
#include "mbedtls/check_config.h"
#endif
+/*
+ * Determine Mbed TLS heap size
+ * 13312 = 13*1024
+ * 7168 = 7*1024
+ */
+#if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA) \
+ || (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)
+#define TF_MBEDTLS_HEAP_SIZE U(13312)
+#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA)
+#define TF_MBEDTLS_HEAP_SIZE U(7168)
+#endif
+
#endif /* __MBEDTLS_CONFIG_H__ */
diff --git a/include/drivers/marvell/aro.h b/include/drivers/marvell/aro.h
index 3627a20..37e211f 100644
--- a/include/drivers/marvell/aro.h
+++ b/include/drivers/marvell/aro.h
@@ -29,6 +29,7 @@
CPU_1800_DDR_1050_RCLK_1050 = 0x7,
CPU_1600_DDR_900_RCLK_900 = 0x0B,
CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
+ CPU_1600_DDR_1200_RCLK_1200 = 0x0D,
CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
CPU_1000_DDR_650_RCLK_650 = 0x13,
CPU_1300_DDR_800_RCLK_800 = 0x14,
diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h
index 1c88980..839efe1 100644
--- a/include/drivers/marvell/mochi/cp110_setup.h
+++ b/include/drivers/marvell/mochi/cp110_setup.h
@@ -20,6 +20,7 @@
#define MVEBU_DEVICE_REV_MASK (0xf << MVEBU_DEVICE_REV_OFFSET)
#define MVEBU_70X0_DEV_ID (0x7040)
#define MVEBU_70X0_CP115_DEV_ID (0x7045)
+#define MVEBU_3900_DEV_ID (0x6025)
#define MVEBU_80X0_DEV_ID (0x8040)
#define MVEBU_80X0_CP115_DEV_ID (0x8045)
#define MVEBU_CP110_SA_DEV_ID (0x110)
diff --git a/include/drivers/marvell/a8k_i2c.h b/include/drivers/mentor/mi2cv.h
similarity index 84%
rename from include/drivers/marvell/a8k_i2c.h
rename to include/drivers/mentor/mi2cv.h
index 8a9abe8..6b03ed7 100644
--- a/include/drivers/marvell/a8k_i2c.h
+++ b/include/drivers/mentor/mi2cv.h
@@ -1,14 +1,15 @@
/*
* Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
-/* This driver provides I2C support for Marvell A8K and compatible SoCs */
+/* This driver provides support for Mentor Graphics MI2CV IP core */
-#ifndef _A8K_I2C_H_
-#define _A8K_I2C_H_
+#ifndef _MI2CV_H_
+#define _MI2CV_H_
#include <stdint.h>
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index 0a513bd..50e0800 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -36,6 +36,20 @@
#define OCR_VDD_MIN_2V0 GENMASK(14, 8)
#define OCR_VDD_MIN_1V7 BIT(7)
+#define MMC_RSP_48 BIT(0)
+#define MMC_RSP_136 BIT(1) /* 136 bit response */
+#define MMC_RSP_CRC BIT(2) /* expect valid crc */
+#define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */
+#define MMC_RSP_BUSY BIT(4) /* device may be busy */
+
+/* JEDEC 4.51 chapter 6.12 */
+#define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC)
+#define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY)
+#define MMC_RESPONSE_R2 (MMC_RSP_136 | MMC_RSP_CRC)
+#define MMC_RESPONSE_R3 (MMC_RSP_48)
+#define MMC_RESPONSE_R4 (MMC_RSP_48)
+#define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC)
+
#define MMC_RESPONSE_R(_x) U(_x)
/* Value randomly chosen for eMMC RCA, it should be > 1 */
diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h
index 6369a5d..5d9c1c1 100644
--- a/include/lib/aarch32/arch_helpers.h
+++ b/include/lib/aarch32/arch_helpers.h
@@ -210,7 +210,12 @@
DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
DEFINE_SYSOP_TYPE_FUNC(dmb, st)
+
+/* dmb ld is not valid for armv7/thumb machines */
+#if ARM_ARCH_MAJOR != 7
DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
+#endif
+
DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
@@ -323,6 +328,11 @@
#define dsb() dsbsy()
#define dmb() dmbsy()
+/* dmb ld is not valid for armv7/thumb machines, so alias it to dmb */
+#if ARM_ARCH_MAJOR == 7
+#define dmbld() dmb()
+#endif
+
#define IS_IN_SECURE() \
(GET_NS_BIT(read_scr()) == 0)
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index d8c4d2e..712a4a4 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,6 +20,20 @@
/* CPU state ids - implementation defined */
#define DENVER_CPU_STATE_POWER_DOWN U(0x3)
+/* Speculative store buffering */
+#define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11)
+#define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18)
+
+/* Speculative memory disambiguation */
+#define DENVER_CPU_DIS_MD_EL3 (U(1) << 9)
+#define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17)
+
+/* Core power management states */
+#define DENVER_CPU_PMSTATE_C1 U(0x1)
+#define DENVER_CPU_PMSTATE_C6 U(0x6)
+#define DENVER_CPU_PMSTATE_C7 U(0x7)
+#define DENVER_CPU_PMSTATE_MASK U(0xF)
+
#ifndef __ASSEMBLY__
/* Disable Dynamic Code Optimisation */
diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h
index a388ed9..9af8f8c 100644
--- a/include/plat/arm/board/common/board_arm_def.h
+++ b/include/plat/arm/board/common/board_arm_def.h
@@ -102,7 +102,7 @@
* little space for growth.
*/
#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE 0x1F000
+# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
#else
# define PLAT_ARM_MAX_BL2_SIZE 0x11000
#endif
diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h
index e5f5373..ce436d2 100644
--- a/include/plat/arm/board/common/v2m_def.h
+++ b/include/plat/arm/board/common/v2m_def.h
@@ -32,6 +32,9 @@
#define V2M_FUNC_SHUTDOWN 0x08
#define V2M_FUNC_REBOOT 0x09
+/* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */
+ #define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS)
+
/*
* V2M sysled bit definitions. The values written to this
* register are defined in arch.h & runtime_svc.h. Only
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index ea9d811..c499417 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -242,6 +242,17 @@
MT_MEMORY | MT_RW | MT_SECURE)
/*
+ * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to
+ * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides
+ * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order
+ * to be able to access the heap.
+ */
+#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \
+ BL1_RW_BASE, \
+ BL1_RW_LIMIT - BL1_RW_BASE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+/*
* If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
* otherwise one region is defined containing both.
*/
diff --git a/include/plat/arm/common/arm_dyn_cfg_helpers.h b/include/plat/arm/common/arm_dyn_cfg_helpers.h
index 382ec60..cb17c95 100644
--- a/include/plat/arm/common/arm_dyn_cfg_helpers.h
+++ b/include/plat/arm/common/arm_dyn_cfg_helpers.h
@@ -6,12 +6,17 @@
#ifndef __ARM_DYN_CFG_HELPERS_H__
#define __ARM_DYN_CFG_HELPERS_H__
+#include <stddef.h>
#include <stdint.h>
-/* Function declaration */
+/* Function declarations */
int arm_dyn_get_config_load_info(void *dtb, int node, unsigned int config_id,
uint64_t *config_addr, uint32_t *config_size);
int arm_dyn_tb_fw_cfg_init(void *dtb, int *node);
int arm_dyn_get_disable_auth(void *dtb, int node, uint32_t *disable_auth);
+int arm_get_dtb_mbedtls_heap_info(void *dtb, void **heap_addr,
+ size_t *heap_size);
+int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr,
+ size_t heap_size);
#endif /* __ARM_DYN_CFG_HELPERS_H__ */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 1af4dd1..53b4a45 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -223,6 +223,8 @@
void arm_load_tb_fw_config(void);
void arm_bl2_set_tb_cfg_addr(void *dtb);
void arm_bl2_dyn_cfg_init(void);
+void arm_bl1_set_mbedtls_heap(void);
+int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
/*
* Mandatory functions required in ARM standard platforms
@@ -243,6 +245,8 @@
void plat_arm_interconnect_enter_coherency(void);
void plat_arm_interconnect_exit_coherency(void);
void plat_arm_program_trusted_mailbox(uintptr_t address);
+int plat_arm_bl1_fwu_needed(void);
+void plat_arm_error_handler(int err);
#if ARM_PLAT_MT
unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index dae9589..e0297ae 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -103,6 +103,7 @@
const char *plat_log_get_prefix(unsigned int log_level);
void bl2_plat_preload_setup(void);
int plat_try_next_boot_source(void);
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
/*******************************************************************************
* Mandatory BL1 functions
diff --git a/include/plat/marvell/a8k/common/a8k_common.h b/include/plat/marvell/a8k/common/armada_common.h
similarity index 100%
rename from include/plat/marvell/a8k/common/a8k_common.h
rename to include/plat/marvell/a8k/common/armada_common.h
diff --git a/include/plat/marvell/a8k/common/marvell_def.h b/include/plat/marvell/a8k/common/marvell_def.h
index 7dacf82..9429753 100644
--- a/include/plat/marvell/a8k/common/marvell_def.h
+++ b/include/plat/marvell/a8k/common/marvell_def.h
@@ -63,6 +63,7 @@
#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \
MARVELL_DRAM_SIZE - 1)
+#define MARVELL_IRQ_PIC0 28
#define MARVELL_IRQ_SEC_PHY_TIMER 29
#define MARVELL_IRQ_SEC_SGI_0 8
diff --git a/include/plat/marvell/a8k/common/plat_marvell.h b/include/plat/marvell/a8k/common/plat_marvell.h
index 81cbf38..9ca68d3 100644
--- a/include/plat/marvell/a8k/common/plat_marvell.h
+++ b/include/plat/marvell/a8k/common/plat_marvell.h
@@ -94,6 +94,14 @@
void plat_marvell_system_reset(void);
/*
+ * Miscellaneous platform SMC routines
+ */
+#ifdef MVEBU_PMU_IRQ_WA
+void mvebu_pmu_interrupt_enable(void);
+void mvebu_pmu_interrupt_disable(void);
+#endif
+
+/*
* Optional functions required in Marvell standard platforms
*/
void plat_marvell_io_setup(void);
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index a981d02..c377b28 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -156,11 +156,12 @@
* ----------------------------------------------------
*/
func denver_enable_dco
- mrs x0, mpidr_el1
- and x0, x0, #0xF
+ mov x3, x30
+ bl plat_my_core_pos
mov x1, #1
lsl x1, x1, x0
msr s3_0_c15_c0_2, x1
+ mov x30, x3
ret
endfunc denver_enable_dco
@@ -170,9 +171,10 @@
*/
func denver_disable_dco
+ mov x3, x30
+
/* turn off background work */
- mrs x0, mpidr_el1
- and x0, x0, #0xF
+ bl plat_my_core_pos
mov x1, #1
lsl x1, x1, x0
lsl x2, x1, #16
@@ -186,6 +188,7 @@
and x2, x2, x1
cbnz x2, 1b
+ mov x30, x3
ret
endfunc denver_disable_dco
@@ -208,6 +211,15 @@
ret
endfunc check_errata_cve_2017_5715
+func check_errata_cve_2018_3639
+#if WORKAROUND_CVE_2018_3639
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
+#endif
+ ret
+endfunc check_errata_cve_2018_3639
+
/* -------------------------------------------------
* The CPU Ops reset function for Denver.
* -------------------------------------------------
@@ -233,6 +245,34 @@
msr vbar_el3, x0
#endif
+#if WORKAROUND_CVE_2018_3639
+ /*
+ * Denver CPUs with DENVER_MIDR_PN3 or earlier, use different
+ * bits in the ACTLR_EL3 register to disable speculative
+ * store buffer and memory disambiguation.
+ */
+ mrs x0, midr_el1
+ mov_imm x1, DENVER_MIDR_PN4
+ cmp x0, x1
+ mrs x0, actlr_el3
+ mov x1, #(DENVER_CPU_DIS_MD_EL3 | DENVER_CPU_DIS_SSB_EL3)
+ mov x2, #(DENVER_PN4_CPU_DIS_MD_EL3 | DENVER_PN4_CPU_DIS_SSB_EL3)
+ csel x3, x1, x2, ne
+ orr x0, x0, x3
+ msr actlr_el3, x0
+ isb
+ dsb sy
+#endif
+
+ /* ----------------------------------------------------
+ * Reset ACTLR.PMSTATE to C1 state
+ * ----------------------------------------------------
+ */
+ mrs x0, actlr_el1
+ bic x0, x0, #DENVER_CPU_PMSTATE_MASK
+ orr x0, x0, #DENVER_CPU_PMSTATE_C1
+ msr actlr_el1, x0
+
/* ----------------------------------------------------
* Enable dynamic code optimizer (DCO)
* ----------------------------------------------------
@@ -282,6 +322,7 @@
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715
+ report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639
ldp x8, x30, [sp], #16
ret
diff --git a/lib/extensions/ras/std_err_record.c b/lib/extensions/ras/std_err_record.c
index 209cb73..9fdfd6b 100644
--- a/lib/extensions/ras/std_err_record.c
+++ b/lib/extensions/ras/std_err_record.c
@@ -56,7 +56,7 @@
((unsigned int) read_erridr_el1()) & ERRIDR_MASK;
assert(idx_start < max_idx);
- assert(check_u32_overflow(idx_start, num_idx));
+ assert(check_u32_overflow(idx_start, num_idx) == 0);
assert((idx_start + num_idx - 1U) < max_idx);
for (i = 0; i < num_idx; i++) {
diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c
index 788ba98..03277c3 100644
--- a/lib/locks/bakery/bakery_lock_coherent.c
+++ b/lib/locks/bakery/bakery_lock_coherent.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -133,7 +133,12 @@
bakery_ticket_number(bakery->lock_data[they]));
}
}
- /* Lock acquired */
+
+ /*
+ * Lock acquired. Ensure that any reads from a shared resource in the
+ * critical section read values after the lock is acquired.
+ */
+ dmbld();
}
@@ -146,9 +151,11 @@
assert(bakery_ticket_number(bakery->lock_data[me]));
/*
- * Release lock by resetting ticket. Then signal other
- * waiting contenders
+ * Ensure that other observers see any stores in the critical section
+ * before releasing the lock. Release the lock by resetting ticket.
+ * Then signal other waiting contenders.
*/
+ dmbst();
bakery->lock_data[me] = 0;
dsb();
sev();
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 630226a..b947da9 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -204,7 +204,12 @@
== bakery_ticket_number(their_bakery_info->lock_data));
}
}
- /* Lock acquired */
+
+ /*
+ * Lock acquired. Ensure that any reads from a shared resource in the
+ * critical section read values after the lock is acquired.
+ */
+ dmbld();
}
void bakery_lock_release(bakery_lock_t *lock)
@@ -220,6 +225,12 @@
assert(is_lock_acquired(my_bakery_info, is_cached));
+ /*
+ * Ensure that other observers see any stores in the critical section
+ * before releasing the lock. Release the lock by resetting ticket.
+ * Then signal other waiting contenders.
+ */
+ dmbst();
my_bakery_info->lock_data = 0;
write_cache_op(my_bakery_info, is_cached);
sev();
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index ecf7cc0..34d095b 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -25,14 +25,15 @@
#define OPTEE_PAGER_IMAGE_ID 0
#define OPTEE_PAGED_IMAGE_ID 1
-#define OPTEE_MAX_IMAGE_NUM 2
+
+#define OPTEE_MAX_NUM_IMAGES 2u
#define TEE_MAGIC_NUM_OPTEE 0x4554504f
/*
* magic: header magic number.
* version: OPTEE header version:
- * 1 - not supported
- * 2 - supported
+ * 1 - not supported
+ * 2 - supported
* arch: OPTEE os architecture type: 0 - AARCH32, 1 - AARCH64.
* flags: unused currently.
* nb_images: number of images.
@@ -53,14 +54,20 @@
******************************************************************************/
static inline int tee_validate_header(optee_header_t *header)
{
+ int valid = 0;
+
if ((header->magic == TEE_MAGIC_NUM_OPTEE) &&
- (header->version == 2) &&
- (header->nb_images <= OPTEE_MAX_IMAGE_NUM)) {
- return 1;
+ (header->version == 2u) &&
+ (header->nb_images > 0u) &&
+ (header->nb_images <= OPTEE_MAX_NUM_IMAGES)) {
+ valid = 1;
}
- WARN("Not a known TEE, use default loading options.\n");
- return 0;
+ else {
+ WARN("Not a known TEE, use default loading options.\n");
+ }
+
+ return valid;
}
/*******************************************************************************
diff --git a/maintainers.rst b/maintainers.rst
index ee6682e..3f64b83 100644
--- a/maintainers.rst
+++ b/maintainers.rst
@@ -24,6 +24,7 @@
:G: `smaeul`_
:F: docs/plat/allwinner.rst
:F: plat/allwinner/
+:F: drivers/allwinner/
Armv7-A architecture port
-------------------------
@@ -97,6 +98,19 @@
:F: docs/plat/ls1043a.rst
:F: plat/layerscape/
+NXP i.MX 7 WaRP7 platform port and SoC drivers
+----------------------------------------------
+:M: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+:G: `bryanodonoghue`_
+:M: Jun Nie <jun.nie@linaro.org>
+:G: `niej`_
+:F: docs/plat/warp7.rst
+:F: plat/imx/common/
+:F: plat/imx/imx7/
+:F: drivers/imx/timer/
+:F: drivers/imx/uart/
+:F: drivers/imx/usdhc/
+
NXP i.MX 8 platform port
------------------------
:M: Anson Huang <Anson.Huang@nxp.com>
@@ -185,6 +199,7 @@
.. _Andre-ARM: https://github.com/Andre-ARM
.. _Anson-Huang: https://github.com/Anson-Huang
.. _antonio-nino-diaz-arm: https://github.com/antonio-nino-diaz-arm
+.. _bryanodonoghue: https://github.com/bryanodonoghue
.. _b49020: https://github.com/b49020
.. _danh-arm: https://github.com/danh-arm
.. _dp-arm: https://github.com/dp-arm
@@ -192,6 +207,7 @@
.. _glneo: https://github.com/glneo
.. _hzhuang1: https://github.com/hzhuang1
.. _jenswi-linaro: https://github.com/jenswi-linaro
+.. _niej: https://github.com/niej
.. _kostapr: https://github.com/kostapr
.. _masahir0y: https://github.com/masahir0y
.. _mtk09422: https://github.com/mtk09422
diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c
index 8ecf490..7e11cec 100644
--- a/plat/allwinner/common/sunxi_bl31_setup.c
+++ b/plat/allwinner/common/sunxi_bl31_setup.c
@@ -93,6 +93,8 @@
sunxi_security_setup();
+ sunxi_pmic_setup();
+
INFO("BL31: Platform setup done\n");
}
diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c
index 2a1f223..e4bb582 100644
--- a/plat/allwinner/common/sunxi_pm.c
+++ b/plat/allwinner/common/sunxi_pm.c
@@ -54,9 +54,7 @@
/* Turn off all secondary CPUs */
sunxi_disable_secondary_cpus(plat_my_core_pos());
- ERROR("PSCI: Full shutdown not implemented, halting\n");
- wfi();
- panic();
+ sunxi_power_down();
}
static void __dead2 sunxi_system_reset(void)
diff --git a/plat/allwinner/common/sunxi_private.h b/plat/allwinner/common/sunxi_private.h
index e45f494..20fa23e 100644
--- a/plat/allwinner/common/sunxi_private.h
+++ b/plat/allwinner/common/sunxi_private.h
@@ -13,6 +13,10 @@
void sunxi_disable_secondary_cpus(unsigned int primary_cpu);
uint16_t sunxi_read_soc_id(void);
+
+void sunxi_pmic_setup(void);
void sunxi_security_setup(void);
+void __dead2 sunxi_power_down(void);
+
#endif /* __SUNXI_PRIVATE_H__ */
diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk
index 236464f..e2868af 100644
--- a/plat/allwinner/sun50i_a64/platform.mk
+++ b/plat/allwinner/sun50i_a64/platform.mk
@@ -30,6 +30,7 @@
${AW_PLAT}/common/sunxi_bl31_setup.c \
${AW_PLAT}/common/sunxi_cpu_ops.c \
${AW_PLAT}/common/sunxi_pm.c \
+ ${AW_PLAT}/sun50i_a64/sunxi_power.c \
${AW_PLAT}/common/sunxi_security.c \
${AW_PLAT}/common/sunxi_topology.c
diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
new file mode 100644
index 0000000..c1907d6
--- /dev/null
+++ b/plat/allwinner/sun50i_a64/sunxi_power.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <debug.h>
+
+int sunxi_pmic_setup(void)
+{
+ /* STUB */
+ NOTICE("BL31: STUB PMIC setup code called\n");
+
+ return 0;
+}
+
+void __dead2 sunxi_power_down(void)
+{
+ ERROR("PSCI: Full shutdown not implemented, halting\n");
+ wfi();
+ panic();
+}
diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk
index c1b26fa..c3901d0 100644
--- a/plat/allwinner/sun50i_h6/platform.mk
+++ b/plat/allwinner/sun50i_h6/platform.mk
@@ -7,6 +7,7 @@
include lib/xlat_tables_v2/xlat_tables.mk
AW_PLAT := plat/allwinner
+AW_DRIVERS := drivers/allwinner
PLAT_INCLUDES := -Iinclude/plat/arm/common \
-Iinclude/plat/arm/common/aarch64 \
@@ -15,6 +16,7 @@
PLAT_BL_COMMON_SOURCES := drivers/console/${ARCH}/console.S \
drivers/ti/uart/${ARCH}/16550_console.S \
+ ${AW_DRIVERS}/sunxi_i2c.c \
${XLAT_TABLES_LIB_SRCS} \
${AW_PLAT}/common/plat_helpers.S \
${AW_PLAT}/common/sunxi_common.c
@@ -30,6 +32,7 @@
${AW_PLAT}/common/sunxi_bl31_setup.c \
${AW_PLAT}/common/sunxi_cpu_ops.c \
${AW_PLAT}/common/sunxi_pm.c \
+ ${AW_PLAT}/sun50i_h6/sunxi_power.c \
${AW_PLAT}/common/sunxi_security.c \
${AW_PLAT}/common/sunxi_topology.c
diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c
new file mode 100644
index 0000000..f109cce
--- /dev/null
+++ b/plat/allwinner/sun50i_h6/sunxi_power.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <debug.h>
+#include <delay_timer.h>
+#include <errno.h>
+#include <mmio.h>
+#include <mentor/mi2cv.h>
+#include <string.h>
+#include <sunxi_mmap.h>
+
+#define AXP805_ADDR 0x36
+#define AXP805_ID 0x03
+
+enum pmic_type {
+ NO_PMIC,
+ AXP805,
+};
+
+enum pmic_type pmic;
+
+static int sunxi_init_r_i2c(void)
+{
+ uint32_t reg;
+
+ /* get currently configured function for pins PL0 and PL1 */
+ reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x00);
+ if ((reg & 0xff) == 0x33) {
+ NOTICE("PMIC: already configured for TWI\n");
+ }
+
+ /* switch pins PL0 and PL1 to I2C */
+ mmio_write_32(SUNXI_R_PIO_BASE + 0x00, (reg & ~0xff) | 0x33);
+
+ /* level 2 drive strength */
+ reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x14);
+ mmio_write_32(SUNXI_R_PIO_BASE + 0x14, (reg & ~0x0f) | 0xa);
+
+ /* set both ports to pull-up */
+ reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x1c);
+ mmio_write_32(SUNXI_R_PIO_BASE + 0x1c, (reg & ~0x0f) | 0x5);
+
+ /* assert & de-assert reset of R_I2C */
+ reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
+ mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, 0);
+ reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
+ mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | 0x00010000);
+
+ /* un-gate R_I2C clock */
+ reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
+ mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | 0x00000001);
+
+ /* call mi2cv driver */
+ i2c_init((void *)SUNXI_R_I2C_BASE);
+
+ return 0;
+}
+
+int axp_i2c_read(uint8_t chip, uint8_t reg, uint8_t *val)
+{
+ int ret;
+
+ ret = i2c_write(chip, 0, 0, ®, 1);
+ if (ret)
+ return ret;
+
+ return i2c_read(chip, 0, 0, val, 1);
+}
+
+int axp_i2c_write(uint8_t chip, uint8_t reg, uint8_t val)
+{
+ return i2c_write(chip, reg, 1, &val, 1);
+}
+
+static int axp805_probe(void)
+{
+ int ret;
+ uint8_t val;
+
+ ret = axp_i2c_write(AXP805_ADDR, 0xff, 0x0);
+ if (ret) {
+ ERROR("PMIC: Cannot put AXP805 to master mode.\n");
+ return -EPERM;
+ }
+
+ ret = axp_i2c_read(AXP805_ADDR, AXP805_ID, &val);
+
+ if (!ret && ((val & 0xcf) == 0x40))
+ NOTICE("PMIC: AXP805 detected\n");
+ else if (ret) {
+ ERROR("PMIC: Cannot communicate with AXP805.\n");
+ return -EPERM;
+ } else {
+ ERROR("PMIC: Non-AXP805 chip attached at AXP805's address.\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int sunxi_pmic_setup(void)
+{
+ int ret;
+
+ sunxi_init_r_i2c();
+
+ NOTICE("PMIC: Probing AXP805\n");
+ pmic = AXP805;
+
+ ret = axp805_probe();
+ if (ret)
+ pmic = NO_PMIC;
+ else
+ pmic = AXP805;
+
+ return 0;
+}
+
+void __dead2 sunxi_power_down(void)
+{
+ uint8_t val;
+
+ switch (pmic) {
+ case AXP805:
+ val = 0x26; /* Default value for REG 32H */
+ axp_i2c_read(AXP805_ADDR, 0x32, &val);
+ val |= 0x80;
+ axp_i2c_write(AXP805_ADDR, 0x32, val);
+ break;
+ default:
+ break;
+ }
+
+ udelay(1000);
+ ERROR("PSCI: Cannot communicate with PMIC, halting\n");
+ wfi();
+ panic();
+}
diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
index 28299f6..ce58938 100644
--- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
@@ -26,5 +26,16 @@
tos_fw_config_max_size = <0x200>;
nt_fw_config_addr = <0x0 0x80000000>;
nt_fw_config_max_size = <0x200>;
+ /*
+ * The following two entries are placeholders for Mbed TLS
+ * heap information. The default values don't matter since
+ * they will be overwritten by BL1.
+ * In case of having shared Mbed TLS heap between BL1 and BL2,
+ * BL1 will populate these two properties with the respective
+ * info about the shared heap. This info will be available for
+ * BL2 in order to locate and re-use the heap.
+ */
+ mbedtls_heap_addr = <0x0 0x0>;
+ mbedtls_heap_size = <0x0>;
};
};
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index af258b0..1b0c764 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -15,6 +15,7 @@
#include <gicv2.h>
#include <mmio.h>
#include <plat_arm.h>
+#include <platform.h>
#include <secure_partition.h>
#include <v2m_def.h>
#include "../fvp_def.h"
@@ -50,7 +51,6 @@
DEVICE2_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-
/*
* Table of memory regions for various BL stages to map using the MMU.
* This doesn't include Trusted SRAM as arm_setup_page_tables() already
@@ -92,7 +92,10 @@
#if TRUSTED_BOARD_BOOT
/* To access the Root of Trust Public Key registers. */
MAP_DEVICE2,
-#endif
+#if LOAD_IMAGE_V2 && !BL2_AT_EL3
+ ARM_MAP_BL1_RW,
+#endif /* LOAD_IMAGE_V2 && !BL2_AT_EL3 */
+#endif /* TRUSTED_BOARD_BOOT */
#if ENABLE_SPM
ARM_SP_IMAGE_MMAP,
#endif
@@ -395,3 +398,13 @@
}
#endif
}
+
+#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
diff --git a/plat/arm/board/juno/juno_bl1_setup.c b/plat/arm/board/juno/juno_bl1_setup.c
index 836a672..3dd2a22 100644
--- a/plat/arm/board/juno/juno_bl1_setup.c
+++ b/plat/arm/board/juno/juno_bl1_setup.c
@@ -5,15 +5,72 @@
*/
#include <bl_common.h>
+#include <debug.h>
#include <errno.h>
#include <plat_arm.h>
#include <platform.h>
+#include <sds.h>
#include <sp805.h>
#include <tbbr_img_def.h>
#include <v2m_def.h>
void juno_reset_to_aarch32_state(void);
+static int is_watchdog_reset(void)
+{
+#if !CSS_USE_SCMI_SDS_DRIVER
+ #define RESET_REASON_WDOG_RESET (0x2)
+ const uint32_t *reset_flags_ptr = (const uint32_t *)SSC_GPRETN;
+
+ if ((*reset_flags_ptr & RESET_REASON_WDOG_RESET) != 0)
+ return 1;
+
+ return 0;
+#else
+ int ret;
+ uint32_t scp_reset_synd_flags;
+
+ ret = sds_init();
+ if (ret != SDS_OK) {
+ ERROR("SCP SDS initialization failed\n");
+ panic();
+ }
+
+ ret = sds_struct_read(SDS_RESET_SYNDROME_STRUCT_ID,
+ SDS_RESET_SYNDROME_OFFSET,
+ &scp_reset_synd_flags,
+ SDS_RESET_SYNDROME_SIZE,
+ SDS_ACCESS_MODE_NON_CACHED);
+ if (ret != SDS_OK) {
+ ERROR("Getting reset reason from SDS failed\n");
+ panic();
+ }
+
+ /* Check if the WATCHDOG_RESET_BIT is set in the reset syndrome */
+ if (scp_reset_synd_flags & SDS_RESET_SYNDROME_AP_WD_RESET_BIT)
+ return 1;
+
+ return 0;
+#endif
+}
+
+/*******************************************************************************
+ * The following function checks if Firmware update is needed,
+ * by checking if TOC in FIP image is valid or watchdog reset happened.
+ ******************************************************************************/
+int plat_arm_bl1_fwu_needed(void)
+{
+ const uint32_t *nv_flags_ptr = (const uint32_t *)V2M_SYS_NVFLAGS_ADDR;
+
+ /* Check if TOC is invalid or watchdog reset happened. */
+ if ((arm_io_is_toc_valid() != 1) ||
+ (((*nv_flags_ptr == -EAUTH) || (*nv_flags_ptr == -ENOENT))
+ && is_watchdog_reset()))
+ return 1;
+
+ return 0;
+}
+
/*******************************************************************************
* On JUNO update the arg2 with address of SCP_BL2U image info.
******************************************************************************/
diff --git a/plat/arm/board/juno/juno_err.c b/plat/arm/board/juno/juno_err.c
new file mode 100644
index 0000000..dd8e278
--- /dev/null
+++ b/plat/arm/board/juno/juno_err.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <errno.h>
+#include <platform.h>
+#include <v2m_def.h>
+
+/*
+ * Juno error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+ uint32_t *flags_ptr = (uint32_t *)V2M_SYS_NVFLAGS_ADDR;
+
+ /* Propagate the err code in the NV-flags register */
+ *flags_ptr = err;
+
+ /* Loop until the watchdog resets the system */
+ for (;;)
+ wfi();
+}
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 16390fa..481844f 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -22,7 +22,12 @@
JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c
endif
-PLAT_INCLUDES := -Iplat/arm/board/juno/include
+# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
+# SCP during power management operations and for SCP RAM Firmware transfer.
+CSS_USE_SCMI_SDS_DRIVER := 1
+
+PLAT_INCLUDES := -Iplat/arm/board/juno/include \
+ -Iplat/arm/css/drivers/sds
PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S
@@ -55,11 +60,13 @@
BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
+ plat/arm/board/juno/juno_err.c \
plat/arm/board/juno/juno_bl1_setup.c \
${JUNO_INTERCONNECT_SOURCES} \
${JUNO_SECURITY_SOURCES}
BL2_SOURCES += lib/utils/mem_region.c \
+ plat/arm/board/juno/juno_err.c \
plat/arm/board/juno/juno_bl2_setup.c \
plat/arm/common/arm_nor_psci_mem_protect.c \
${JUNO_SECURITY_SOURCES}
@@ -76,8 +83,13 @@
${JUNO_GIC_SOURCES} \
${JUNO_INTERCONNECT_SOURCES} \
${JUNO_SECURITY_SOURCES}
+
+ifeq (${CSS_USE_SCMI_SDS_DRIVER},1)
+BL1_SOURCES += plat/arm/css/drivers/sds/sds.c
endif
+endif
+
# Errata workarounds for Cortex-A53:
ERRATA_A53_826319 := 1
ERRATA_A53_835769 := 1
@@ -112,10 +124,6 @@
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
-# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
-# SCP during power management operations and for SCP RAM Firmware transfer.
-CSS_USE_SCMI_SDS_DRIVER := 1
-
include plat/arm/board/common/board_css.mk
include plat/arm/common/arm_common.mk
include plat/arm/soc/common/soc_css.mk
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index d435553..d9104ee 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -23,6 +23,8 @@
#pragma weak bl1_platform_setup
#pragma weak bl1_plat_sec_mem_layout
#pragma weak bl1_plat_prepare_exit
+#pragma weak bl1_plat_get_next_image_id
+#pragma weak plat_arm_bl1_fwu_needed
#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
bl1_tzram_layout.total_base, \
@@ -149,7 +151,11 @@
plat_arm_io_setup();
#if LOAD_IMAGE_V2
arm_load_tb_fw_config();
-#endif
+#if TRUSTED_BOARD_BOOT
+ /* Share the Mbed TLS heap info with other images */
+ arm_bl1_set_mbedtls_heap();
+#endif /* TRUSTED_BOARD_BOOT */
+#endif /* LOAD_IMAGE_V2 */
/*
* Allow access to the System counter timer module and program
* counter frequency for non secure images during FWU
@@ -182,13 +188,22 @@
#endif
}
+/*
+ * On Arm platforms, the FWU process is triggered when the FIP image has
+ * been tampered with.
+ */
+int plat_arm_bl1_fwu_needed(void)
+{
+ return (arm_io_is_toc_valid() != 1);
+}
+
/*******************************************************************************
* The following function checks if Firmware update is needed,
* by checking if TOC in FIP image is valid or not.
******************************************************************************/
unsigned int bl1_plat_get_next_image_id(void)
{
- if (!arm_io_is_toc_valid())
+ if (plat_arm_bl1_fwu_needed() != 0)
return NS_BL1U_IMAGE_ID;
return BL2_IMAGE_ID;
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index b9c73f0..95fe2c5 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -8,6 +8,9 @@
#include <assert.h>
#include <debug.h>
#include <desc_image_load.h>
+#if TRUSTED_BOARD_BOOT
+#include <mbedtls_config.h>
+#endif
#include <plat_arm.h>
#include <platform.h>
#include <platform_def.h>
@@ -16,8 +19,104 @@
#if LOAD_IMAGE_V2
-/* Variable to store the address to TB_FW_CONFIG passed from BL1 */
+/* Variable to store the address of TB_FW_CONFIG file */
static void *tb_fw_cfg_dtb;
+static size_t tb_fw_cfg_dtb_size;
+
+
+#if TRUSTED_BOARD_BOOT
+
+static void *mbedtls_heap_addr;
+static size_t mbedtls_heap_size;
+
+/*
+ * This function is the implementation of the shared Mbed TLS heap between
+ * BL1 and BL2 for Arm platforms. The shared heap address is passed from BL1
+ * to BL2 with a pointer. This pointer resides inside the TB_FW_CONFIG file
+ * which is a DTB.
+ *
+ * This function is placed inside an #if directive for the below reasons:
+ * - To allocate space for the Mbed TLS heap --only if-- Trusted Board Boot
+ * is enabled.
+ * - This implementation requires the DTB to be present so that BL1 has a
+ * mechanism to pass the pointer to BL2. If LOAD_IMAGE_V2=0 then
+ * TB_FW_CONFIG is not present, which means that this implementation
+ * cannot be applied.
+ */
+int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+#if defined(IMAGE_BL1) || BL2_AT_EL3
+
+ /* If in BL1 or BL2_AT_EL3 define a heap */
+ static unsigned char heap[TF_MBEDTLS_HEAP_SIZE];
+
+ *heap_addr = heap;
+ *heap_size = sizeof(heap);
+ mbedtls_heap_addr = heap;
+ mbedtls_heap_size = sizeof(heap);
+
+#elif defined(IMAGE_BL2)
+
+ int err;
+
+ /* If in BL2, retrieve the already allocated heap's info from DTB */
+ if (tb_fw_cfg_dtb != NULL) {
+ err = arm_get_dtb_mbedtls_heap_info(tb_fw_cfg_dtb, heap_addr,
+ heap_size);
+ if (err < 0) {
+ ERROR("BL2: unable to retrieve shared Mbed TLS heap information from DTB\n");
+ panic();
+ }
+ } else {
+ ERROR("BL2: DTB missing, cannot get Mbed TLS heap\n");
+ panic();
+ }
+#endif
+
+ return 0;
+}
+
+/*
+ * Puts the shared Mbed TLS heap information to the DTB.
+ * Executed only from BL1.
+ */
+void arm_bl1_set_mbedtls_heap(void)
+{
+ int err;
+
+ /*
+ * If tb_fw_cfg_dtb==NULL then DTB is not present for the current
+ * platform. As such, we don't attempt to write to the DTB at all.
+ *
+ * If mbedtls_heap_addr==NULL, then it means we are using the default
+ * heap implementation. As such, BL2 will have its own heap for sure
+ * and hence there is no need to pass any information to the DTB.
+ *
+ * In the latter case, if we still wanted to write in the DTB the heap
+ * information, we would need to call plat_get_mbedtls_heap to retrieve
+ * the default heap's address and size.
+ */
+ if ((tb_fw_cfg_dtb != NULL) && (mbedtls_heap_addr != NULL)) {
+ err = arm_set_dtb_mbedtls_heap_info(tb_fw_cfg_dtb,
+ mbedtls_heap_addr, mbedtls_heap_size);
+ if (err < 0) {
+ ERROR("BL1: unable to write shared Mbed TLS heap information to DTB\n");
+ panic();
+ }
+ /*
+ * Ensure that the info written to the DTB is visible to other
+ * images. It's critical because BL2 won't be able to proceed
+ * without the heap info.
+ */
+ flush_dcache_range((uintptr_t)tb_fw_cfg_dtb,
+ tb_fw_cfg_dtb_size);
+ }
+}
+
+#endif /* TRUSTED_BOARD_BOOT */
/*
* Helper function to load TB_FW_CONFIG and populate the load information to
@@ -34,7 +133,8 @@
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t, 0),
.image_info.image_base = ARM_TB_FW_CONFIG_BASE,
- .image_info.image_max_size = ARM_TB_FW_CONFIG_LIMIT - ARM_TB_FW_CONFIG_BASE,
+ .image_info.image_max_size =
+ ARM_TB_FW_CONFIG_LIMIT - ARM_TB_FW_CONFIG_BASE
};
VERBOSE("BL1: Loading TB_FW_CONFIG\n");
@@ -45,7 +145,10 @@
return;
}
+ /* At this point we know that a DTB is indeed available */
config_base = arm_tb_fw_info.image_info.image_base;
+ tb_fw_cfg_dtb = (void *)config_base;
+ tb_fw_cfg_dtb_size = (size_t)arm_tb_fw_info.image_info.image_max_size;
/* The BL2 ep_info arg0 is modified to point to TB_FW_CONFIG */
image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c
index 5a7e20a..d12d09c 100644
--- a/plat/arm/common/arm_dyn_cfg_helpers.c
+++ b/plat/arm/common/arm_dyn_cfg_helpers.c
@@ -11,6 +11,8 @@
#include <libfdt.h>
#include <plat_arm.h>
+#define DTB_PROP_MBEDTLS_HEAP_ADDR "mbedtls_heap_addr"
+#define DTB_PROP_MBEDTLS_HEAP_SIZE "mbedtls_heap_size"
typedef struct config_load_info_prop {
unsigned int config_id;
@@ -164,3 +166,97 @@
VERBOSE("Dyn cfg: Found \"arm,tb_fw\" in the config\n");
return 0;
}
+
+/*
+ * Reads and returns the Mbed TLS shared heap information from the DTB.
+ * This function is supposed to be called *only* when a DTB is present.
+ * This function is supposed to be called only by BL2.
+ *
+ * Returns:
+ * 0 = success
+ * -1 = error. In this case the values of heap_addr, heap_size should be
+ * considered as garbage by the caller.
+ */
+int arm_get_dtb_mbedtls_heap_info(void *dtb, void **heap_addr,
+ size_t *heap_size)
+{
+ int err, dtb_root;
+
+ /* Verify the DTB is valid and get the root node */
+ err = arm_dyn_tb_fw_cfg_init(dtb, &dtb_root);
+ if (err < 0) {
+ ERROR("Invalid TB_FW_CONFIG. Cannot retrieve Mbed TLS heap information from DTB\n");
+ return -1;
+ }
+
+ /* Retrieve the Mbed TLS heap details from the DTB */
+ err = fdtw_read_cells(dtb, dtb_root,
+ DTB_PROP_MBEDTLS_HEAP_ADDR, 2, heap_addr);
+ if (err < 0) {
+ ERROR("Error while reading %s from DTB\n",
+ DTB_PROP_MBEDTLS_HEAP_ADDR);
+ return -1;
+ }
+ err = fdtw_read_cells(dtb, dtb_root,
+ DTB_PROP_MBEDTLS_HEAP_SIZE, 1, heap_size);
+ if (err < 0) {
+ ERROR("Error while reading %s from DTB\n",
+ DTB_PROP_MBEDTLS_HEAP_SIZE);
+ return -1;
+ }
+ return 0;
+}
+
+
+/*
+ * This function writes the Mbed TLS heap address and size in the DTB. When it
+ * is called, it is guaranteed that a DTB is available. However it is not
+ * guaranteed that the shared Mbed TLS heap implementation is used. Thus we
+ * return error code from here and it's the responsibility of the caller to
+ * determine the action upon error.
+ *
+ * This function is supposed to be called only by BL1.
+ *
+ * Returns:
+ * 0 = success
+ * 1 = error
+ */
+int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size)
+{
+ int err, dtb_root;
+
+ /*
+ * Verify that the DTB is valid, before attempting to write to it,
+ * and get the DTB root node.
+ */
+ err = arm_dyn_tb_fw_cfg_init(dtb, &dtb_root);
+ if (err < 0) {
+ ERROR("Invalid TB_FW_CONFIG loaded. Unable to get root node\n");
+ return -1;
+ }
+
+ /*
+ * Write the heap address and size in the DTB.
+ *
+ * NOTE: The variables heap_addr and heap_size are corrupted
+ * by the "fdtw_write_inplace_cells" function. After the
+ * function calls they must NOT be reused.
+ */
+ err = fdtw_write_inplace_cells(dtb, dtb_root,
+ DTB_PROP_MBEDTLS_HEAP_ADDR, 2, &heap_addr);
+ if (err < 0) {
+ ERROR("Unable to write DTB property %s\n",
+ DTB_PROP_MBEDTLS_HEAP_ADDR);
+ return -1;
+ }
+
+ err = fdtw_write_inplace_cells(dtb, dtb_root,
+ DTB_PROP_MBEDTLS_HEAP_SIZE, 1, &heap_size);
+ if (err < 0) {
+ ERROR("Unable to write DTB property %s\n",
+ DTB_PROP_MBEDTLS_HEAP_SIZE);
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/plat/arm/common/arm_err.c b/plat/arm/common/arm_err.c
index 66568e7..e13e51f 100644
--- a/plat/arm/common/arm_err.c
+++ b/plat/arm/common/arm_err.c
@@ -13,10 +13,12 @@
#include <platform_def.h>
#include <stdint.h>
+#pragma weak plat_arm_error_handler
+
/*
* ARM common implementation for error handler
*/
-void plat_error_handler(int err)
+void __dead2 plat_arm_error_handler(int err)
{
int ret;
@@ -44,3 +46,8 @@
for (;;)
wfi();
}
+
+void __dead2 plat_error_handler(int err)
+{
+ plat_arm_error_handler(err);
+}
diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk
index 29dd01d..984c1da 100644
--- a/plat/arm/css/common/css_common.mk
+++ b/plat/arm/css/common/css_common.mk
@@ -85,3 +85,12 @@
# Process CSS_USE_SCMI_SDS_DRIVER flag
$(eval $(call assert_boolean,CSS_USE_SCMI_SDS_DRIVER))
$(eval $(call add_define,CSS_USE_SCMI_SDS_DRIVER))
+
+# Process CSS_NON_SECURE_UART flag
+# This undocumented build option is only to enable debug access to the UART
+# from non secure code, which is useful on some platforms.
+# Default (obviously) is off.
+CSS_NON_SECURE_UART := 0
+$(eval $(call assert_boolean,CSS_NON_SECURE_UART))
+$(eval $(call add_define,CSS_NON_SECURE_UART))
+
diff --git a/plat/arm/css/sgi/fdts/sgi575_tb_fw_config.dts b/plat/arm/css/sgi/fdts/sgi575_tb_fw_config.dts
index 0bb0a94..315fa69 100644
--- a/plat/arm/css/sgi/fdts/sgi575_tb_fw_config.dts
+++ b/plat/arm/css/sgi/fdts/sgi575_tb_fw_config.dts
@@ -11,4 +11,15 @@
compatible = "arm,tb_fw";
hw_config_addr = <0x0 0xFEF00000>;
hw_config_max_size = <0x0100000>;
+ /*
+ * The following two entries are placeholders for Mbed TLS
+ * heap information. The default values don't matter since
+ * they will be overwritten by BL1.
+ * In case of having shared Mbed TLS heap between BL1 and BL2,
+ * BL1 will populate these two properties with the respective
+ * info about the shared heap. This info will be available for
+ * BL2 in order to locate and re-use the heap.
+ */
+ mbedtls_heap_addr = <0x0 0x0>;
+ mbedtls_heap_size = <0x0>;
};
diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c
index 6aa76ef..0a7e319 100644
--- a/plat/arm/css/sgi/sgi_plat.c
+++ b/plat/arm/css/sgi/sgi_plat.c
@@ -6,6 +6,7 @@
#include <arm_def.h>
#include <arm_spm_def.h>
+#include <assert.h>
#include <bl_common.h>
#include <ccn.h>
#include <debug.h>
@@ -64,6 +65,9 @@
#if ENABLE_SPM
ARM_SP_IMAGE_MMAP,
#endif
+#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2 && !BL2_AT_EL3
+ ARM_MAP_BL1_RW,
+#endif
{0}
};
#endif
@@ -143,3 +147,13 @@
return &plat_arm_secure_partition_boot_info;
}
#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
+
+#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
diff --git a/plat/arm/css/sgm/fdts/sgm_tb_fw_config.dts b/plat/arm/css/sgm/fdts/sgm_tb_fw_config.dts
index 9502549..d481018 100644
--- a/plat/arm/css/sgm/fdts/sgm_tb_fw_config.dts
+++ b/plat/arm/css/sgm/fdts/sgm_tb_fw_config.dts
@@ -12,5 +12,16 @@
compatible = "arm,tb_fw";
hw_config_addr = <0x0 0x83000000>;
hw_config_max_size = <0x01000000>;
+ /*
+ * The following two entries are placeholders for Mbed TLS
+ * heap information. The default values don't matter since
+ * they will be overwritten by BL1.
+ * In case of having shared Mbed TLS heap between BL1 and BL2,
+ * BL1 will populate these two properties with the respective
+ * info about the shared heap. This info will be available for
+ * BL2 in order to locate and re-use the heap.
+ */
+ mbedtls_heap_addr = <0x0 0x0>;
+ mbedtls_heap_size = <0x0>;
};
};
diff --git a/plat/arm/css/sgm/sgm_mmap_config.c b/plat/arm/css/sgm/sgm_mmap_config.c
index 009ee64..8a4a8ab 100644
--- a/plat/arm/css/sgm/sgm_mmap_config.c
+++ b/plat/arm/css/sgm/sgm_mmap_config.c
@@ -43,6 +43,9 @@
#ifdef SPD_opteed
ARM_OPTEE_PAGEABLE_LOAD_MEM,
#endif
+#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2 && !BL2_AT_EL3
+ ARM_MAP_BL1_RW,
+#endif
{0}
};
#endif
diff --git a/plat/arm/css/sgm/sgm_plat_config.c b/plat/arm/css/sgm/sgm_plat_config.c
index 809edf6..97b16a8 100644
--- a/plat/arm/css/sgm/sgm_plat_config.c
+++ b/plat/arm/css/sgm/sgm_plat_config.c
@@ -67,3 +67,13 @@
assert(css_plat_info != NULL);
return css_plat_info;
}
+
+#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
diff --git a/plat/arm/soc/common/soc_css_security.c b/plat/arm/soc/common/soc_css_security.c
index 19bd76f..f229679 100644
--- a/plat/arm/soc/common/soc_css_security.c
+++ b/plat/arm/soc/common/soc_css_security.c
@@ -23,7 +23,7 @@
/*
* Allow non-secure access to some SOC regions, excluding UART1, which
- * remains secure.
+ * remains secure (unless CSS_NON_SECURE_UART is set).
* Note: This is the NIC-400 device on the SOC
*/
mmio_write_32(SOC_CSS_NIC400_BASE +
@@ -36,9 +36,15 @@
NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0);
mmio_write_32(SOC_CSS_NIC400_BASE +
NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0);
+#if CSS_NON_SECURE_UART
+ /* Configure UART for non-secure access */
+ mmio_write_32(SOC_CSS_NIC400_BASE +
+ NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), ~0);
+#else
mmio_write_32(SOC_CSS_NIC400_BASE +
NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE),
~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1);
+#endif /* CSS_NON_SECURE_UART */
}
diff --git a/plat/common/plat_bl_common.c b/plat/common/plat_bl_common.c
index b471a7e..95d73e3 100644
--- a/plat/common/plat_bl_common.c
+++ b/plat/common/plat_bl_common.c
@@ -9,6 +9,9 @@
#include <bl_common.h>
#include <debug.h>
#include <errno.h>
+#if TRUSTED_BOARD_BOOT
+#include <mbedtls_config.h>
+#endif
#include <platform.h>
/*
@@ -21,6 +24,7 @@
#pragma weak bl2_plat_handle_pre_image_load
#pragma weak bl2_plat_handle_post_image_load
#pragma weak plat_try_next_boot_source
+#pragma weak plat_get_mbedtls_heap
void bl2_el3_plat_prepare_exit(void)
{
@@ -66,3 +70,22 @@
bl2_early_platform_setup((void *)arg1);
}
#endif
+
+
+#if TRUSTED_BOARD_BOOT
+/*
+ * The following default implementation of the function simply returns the
+ * by-default allocated heap.
+ */
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ static unsigned char heap[TF_MBEDTLS_HEAP_SIZE];
+
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ *heap_addr = heap;
+ *heap_size = sizeof(heap);
+ return 0;
+}
+#endif /* TRUSTED_BOARD_BOOT */
diff --git a/plat/imx/common/imx7_clock.c b/plat/imx/common/imx7_clock.c
new file mode 100644
index 0000000..6bd2e0e
--- /dev/null
+++ b/plat/imx/common/imx7_clock.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <imx_regs.h>
+#include <imx_clock.h>
+
+static void imx7_clock_uart_init(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < MXC_MAX_UART_NUM; i++)
+ imx_clock_disable_uart(i);
+}
+
+static void imx7_clock_wdog_init(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < MXC_MAX_WDOG_NUM; i++)
+ imx_clock_disable_wdog(i);
+}
+
+static void imx7_clock_usb_init(void)
+{
+ /* Disable the clock root */
+ imx_clock_target_clr(CCM_TRT_ID_USB_HSIC_CLK_ROOT, 0xFFFFFFFF);
+}
+
+void imx_clock_init(void)
+{
+ /*
+ * The BootROM hands off to the next stage with the internal 24 MHz XTAL
+ * crystal already clocking the main PLL, which is very handy.
+ * Here we should enable whichever peripherals are required for ATF and
+ * OPTEE.
+ *
+ * Subsequent stages in the boot process such as u-boot and Linux
+ * already have a significant and mature code-base around clocks, so our
+ * objective should be to enable what we need for ATF/OPTEE without
+ * breaking any existing upstream code in Linux and u-boot.
+ */
+
+ /* Initialize UART clocks */
+ imx7_clock_uart_init();
+
+ /* Watchdog clocks */
+
+ imx7_clock_wdog_init();
+
+ /* USB clocks */
+ imx7_clock_usb_init();
+
+}
diff --git a/plat/imx/common/imx_aips.c b/plat/imx/common/imx_aips.c
new file mode 100644
index 0000000..991c262
--- /dev/null
+++ b/plat/imx/common/imx_aips.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <utils_def.h>
+#include <imx_aips.h>
+#include <imx_regs.h>
+
+static void imx_aips_set_default_access(struct aipstz_regs *aips_regs)
+{
+ int i;
+ uintptr_t addr;
+
+ /*
+ * See section 4.7.7.1 AIPSTZ_MPR field descriptions
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
+ * 0111 ->
+ * 0: Write Access from master not buffered
+ * 1: Master is trusted for read access
+ * 1: Master is trsuted for write access
+ * 1: Access from master is not forced to user mode
+ */
+ addr = (uintptr_t)&aips_regs->aipstz_mpr;
+ mmio_write_32(addr, 0x77777777);
+
+ /*
+ * Helpfully the OPACR registers have the logical inversion of the above
+ * See section 4.7.7.1 AIPSTZ_MPR field descriptions
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
+ * 0000 ->
+ * 0: Write Access to the peripheral is not buffered by AIPSTZ
+ * 0: The peripheral does not require supervisor priv to access
+ * 0: Master is trsuted for write access
+ * 0: Access from master is not forced to user mode
+ */
+ for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) {
+ addr = (uintptr_t)&aips_regs->aipstz_opacr[i];
+ mmio_write_32(addr, 0x00000000);
+ }
+}
+
+void imx_aips_init(void)
+{
+ int i;
+ struct aipstz_regs *aips_regs[] = {
+ (struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET),
+ (struct aipstz_regs *)(AIPS2_BASE + AIPSTZ_CONFIG_OFFSET),
+ (struct aipstz_regs *)(AIPS3_BASE + AIPSTZ_CONFIG_OFFSET),
+ };
+
+ for (i = 0; i < ARRAY_SIZE(aips_regs); i++)
+ imx_aips_set_default_access(aips_regs[i]);
+}
diff --git a/plat/imx/common/imx_caam.c b/plat/imx/common/imx_caam.c
new file mode 100644
index 0000000..335e1ed
--- /dev/null
+++ b/plat/imx/common/imx_caam.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdint.h>
+#include <mmio.h>
+#include <imx_caam.h>
+
+void imx_caam_init(void)
+{
+ struct caam_ctrl *caam = (struct caam_ctrl *)CAAM_AIPS_BASE;
+ uint32_t reg;
+ int i;
+
+ for (i = 0; i < CAAM_NUM_JOB_RINGS; i++) {
+ reg = mmio_read_32((uintptr_t)&caam->jr[i].jrmidr_ms);
+ reg |= JROWN_NS | JROWN_MID;
+ mmio_write_32((uintptr_t)&caam->jr[i].jrmidr_ms, reg);
+ }
+}
diff --git a/plat/imx/common/imx_clock.c b/plat/imx/common/imx_clock.c
new file mode 100644
index 0000000..ccf2aeb
--- /dev/null
+++ b/plat/imx/common/imx_clock.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <mmio.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <imx_regs.h>
+#include <imx_clock.h>
+
+void imx_clock_target_set(unsigned int id, uint32_t val)
+{
+ struct ccm *ccm = ((struct ccm *)CCM_BASE);
+ uintptr_t addr;
+
+ if (id > CCM_ROOT_CTRL_NUM)
+ return;
+
+ addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root;
+ mmio_write_32(addr, val);
+}
+
+void imx_clock_target_clr(unsigned int id, uint32_t val)
+{
+ struct ccm *ccm = ((struct ccm *)CCM_BASE);
+ uintptr_t addr;
+
+ if (id > CCM_ROOT_CTRL_NUM)
+ return;
+
+ addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root_clr;
+ mmio_write_32(addr, val);
+}
+
+void imx_clock_gate_enable(unsigned int id, bool enable)
+{
+ struct ccm *ccm = ((struct ccm *)CCM_BASE);
+ uintptr_t addr;
+
+ if (id > CCM_CLK_GATE_CTRL_NUM)
+ return;
+
+ /* TODO: add support for more than DOMAIN0 clocks */
+ if (enable)
+ addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_set;
+ else
+ addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_clr;
+
+ mmio_write_32(addr, CCM_CCGR_SETTING0_DOM_CLK_ALWAYS);
+}
+
+void imx_clock_enable_uart(unsigned int uart_id, uint32_t uart_clk_en_bits)
+{
+ unsigned int ccm_trgt_id = CCM_TRT_ID_UART1_CLK_ROOT + uart_id;
+ unsigned int ccm_ccgr_id = CCM_CCGR_ID_UART1 + uart_id;
+
+ /* Check for error */
+ if (uart_id > MXC_MAX_UART_NUM)
+ return;
+
+ /* Set target register values */
+ imx_clock_target_set(ccm_trgt_id, uart_clk_en_bits);
+
+ /* Enable the clock gate */
+ imx_clock_gate_enable(ccm_ccgr_id, true);
+}
+
+void imx_clock_disable_uart(unsigned int uart_id)
+{
+ unsigned int ccm_trgt_id = CCM_TRT_ID_UART1_CLK_ROOT + uart_id;
+ unsigned int ccm_ccgr_id = CCM_CCGR_ID_UART1 + uart_id;
+
+ /* Check for error */
+ if (uart_id > MXC_MAX_UART_NUM)
+ return;
+
+ /* Disable the clock gate */
+ imx_clock_gate_enable(ccm_ccgr_id, false);
+
+ /* Clear the target */
+ imx_clock_target_clr(ccm_trgt_id, 0xFFFFFFFF);
+}
+
+void imx_clock_enable_usdhc(unsigned int usdhc_id, uint32_t usdhc_clk_en_bits)
+{
+ unsigned int ccm_trgt_id = CCM_TRT_ID_USDHC1_CLK_ROOT + usdhc_id;
+ unsigned int ccm_ccgr_id = CCM_CCGR_ID_USBHDC1 + usdhc_id;
+
+ /* Check for error */
+ if (usdhc_id > MXC_MAX_USDHC_NUM)
+ return;
+
+ /* Set target register values */
+ imx_clock_target_set(ccm_trgt_id, usdhc_clk_en_bits);
+
+ /* Enable the clock gate */
+ imx_clock_gate_enable(ccm_ccgr_id, true);
+}
+
+void imx_clock_enable_wdog(unsigned int wdog_id)
+{
+ unsigned int ccm_ccgr_id = CCM_CCGR_ID_WDOG1 + wdog_id;
+
+ /* Check for error */
+ if (wdog_id > MXC_MAX_WDOG_NUM)
+ return;
+
+ /* Enable the clock gate */
+ imx_clock_gate_enable(ccm_ccgr_id, true);
+}
+
+void imx_clock_disable_wdog(unsigned int wdog_id)
+{
+ unsigned int ccm_trgt_id = CCM_TRT_ID_WDOG_CLK_ROOT;
+ unsigned int ccm_ccgr_id = CCM_CCGR_ID_WDOG1 + wdog_id;
+
+ /* Check for error */
+ if (wdog_id > MXC_MAX_WDOG_NUM)
+ return;
+
+ /* Disable the clock gate */
+ imx_clock_gate_enable(ccm_ccgr_id, false);
+
+ /* Clear the target */
+ imx_clock_target_clr(ccm_trgt_id, 0xFFFFFFFF);
+}
+
+void imx_clock_set_wdog_clk_root_bits(uint32_t wdog_clk_root_en_bits)
+{
+ /* Enable the common clock root just once */
+ imx_clock_target_set(CCM_TRT_ID_WDOG_CLK_ROOT, wdog_clk_root_en_bits);
+}
+
+void imx_clock_enable_usb(unsigned int ccm_ccgr_usb_id)
+{
+ /* Enable the clock gate */
+ imx_clock_gate_enable(ccm_ccgr_usb_id, true);
+}
+
+void imx_clock_disable_usb(unsigned int ccm_ccgr_usb_id)
+{
+ /* Disable the clock gate */
+ imx_clock_gate_enable(ccm_ccgr_usb_id, false);
+}
+
+void imx_clock_set_usb_clk_root_bits(uint32_t usb_clk_root_en_bits)
+{
+ /* Enable the common clock root just once */
+ imx_clock_target_set(CCM_TRT_ID_USB_HSIC_CLK_ROOT, usb_clk_root_en_bits);
+}
diff --git a/plat/imx/common/imx_csu.c b/plat/imx/common/imx_csu.c
new file mode 100644
index 0000000..7c6a63e
--- /dev/null
+++ b/plat/imx/common/imx_csu.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <mmio.h>
+#include <imx_csu.h>
+#include <imx_regs.h>
+
+void imx_csu_init(void)
+{
+ int i;
+ uintptr_t *csl_reg = (uintptr_t *)CSU_BASE;
+
+ for (i = 0; i < MXC_MAX_CSU_REGS; i++, csl_reg++)
+ mmio_write_32((uintptr_t)csl_reg, CSU_CSL_OPEN_ACCESS);
+}
diff --git a/plat/imx/common/imx_io_mux.c b/plat/imx/common/imx_io_mux.c
new file mode 100644
index 0000000..7230647
--- /dev/null
+++ b/plat/imx/common/imx_io_mux.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <imx_regs.h>
+#include <imx_io_mux.h>
+
+void imx_io_muxc_set_pad_alt_function(uint32_t pad_mux_offset, uint32_t alt_function)
+{
+ uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_mux_offset);
+
+ mmio_write_32(addr, alt_function);
+}
+
+void imx_io_muxc_set_pad_features(uint32_t pad_feature_offset, uint32_t pad_features)
+{
+ uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_feature_offset);
+
+ mmio_write_32(addr, pad_features);
+}
diff --git a/plat/imx/common/imx_snvs.c b/plat/imx/common/imx_snvs.c
new file mode 100644
index 0000000..4a2a7d7
--- /dev/null
+++ b/plat/imx/common/imx_snvs.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <imx_regs.h>
+#include <imx_snvs.h>
+
+void imx_snvs_init(void)
+{
+ struct snvs *snvs = (struct snvs *)SNVS_BASE;
+ uintptr_t addr;
+ uint32_t val;
+
+ addr = (uintptr_t)&snvs->hpcomr;
+ val = mmio_read_32(addr);
+ val |= HPCOMR_NPSWA_EN;
+ mmio_write_32(addr, val);
+}
diff --git a/plat/imx/common/imx_wdog.c b/plat/imx/common/imx_wdog.c
new file mode 100644
index 0000000..86813dd
--- /dev/null
+++ b/plat/imx/common/imx_wdog.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <imx_regs.h>
+#include <imx_wdog.h>
+
+static void imx_wdog_power_down(unsigned long base)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)base;
+
+ mmio_write_16((uintptr_t)&wdog->wmcr, 0);
+}
+
+void imx_wdog_init(void)
+{
+ imx_wdog_power_down(WDOG1_BASE);
+ imx_wdog_power_down(WDOG2_BASE);
+ imx_wdog_power_down(WDOG3_BASE);
+ imx_wdog_power_down(WDOG4_BASE);
+}
diff --git a/plat/imx/common/include/imx_aips.h b/plat/imx/common/include/imx_aips.h
new file mode 100644
index 0000000..3c33553
--- /dev/null
+++ b/plat/imx/common/include/imx_aips.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_AIPS_H__
+#define __IMX_AIPS_H__
+
+#include <stdint.h>
+
+#define AIPSTZ_OAPCR_COUNT 0x05
+
+struct aipstz_regs {
+ uint32_t aipstz_mpr;
+ uint32_t res[15];
+ uint32_t aipstz_opacr[AIPSTZ_OAPCR_COUNT];
+};
+
+void imx_aips_init(void);
+
+#endif /* __IMX_AIPS_H__ */
diff --git a/plat/imx/common/include/imx_caam.h b/plat/imx/common/include/imx_caam.h
new file mode 100644
index 0000000..2e1f41a
--- /dev/null
+++ b/plat/imx/common/include/imx_caam.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_CAAM_H__
+#define __IMX_CAAM_H__
+
+#include <stdint.h>
+#include <arch.h>
+#include <imx_regs.h>
+
+struct caam_job_ring {
+ uint32_t jrmidr_ms;
+ uint32_t jrmidr_ls;
+};
+
+struct caam_rtic_mid {
+ uint32_t rticmidr_ms;
+ uint32_t rticmidr_ls;
+};
+
+struct caam_deco {
+ uint32_t deco_mid_ms;
+ uint32_t deco_mid_ls;
+};
+
+#define JOB_RING_OFFSET 0x10
+#define DEBUGCTL_OFFSET 0x58
+#define RES2_SIZE (DEBUGCTL_OFFSET - JOB_RING_OFFSET - \
+ (sizeof(struct caam_job_ring) * CAAM_NUM_JOB_RINGS))
+
+#define RTIC_MID_OFFSET 0x60
+#define DECORR_OFFSET 0x9C
+#define RES3_SIZE (DECORR_OFFSET - RTIC_MID_OFFSET - \
+ (sizeof(struct caam_rtic_mid) * CAAM_NUM_RTIC))
+
+#define DECO_MID_OFFSET 0xA0
+#define DAR_OFFSET 0x120
+#define RES4_SIZE (DAR_OFFSET - DECO_MID_OFFSET - \
+ (sizeof(struct caam_deco) * CAAM_NUM_DECO))
+
+struct caam_ctrl {
+ uint32_t res0;
+ uint32_t mcfgr;
+ uint32_t res1;
+ uint32_t scfgr;
+ struct caam_job_ring jr[CAAM_NUM_JOB_RINGS];
+ uint8_t res2[RES2_SIZE];
+ uint32_t debuctl;
+ uint32_t jrstartr;
+ struct caam_rtic_mid mid[CAAM_NUM_RTIC];
+ uint8_t res3[RES3_SIZE];
+ uint32_t decorr;
+ struct caam_deco deco[CAAM_NUM_DECO];
+ uint8_t res4[RES4_SIZE];
+ uint32_t dar;
+ uint32_t drr;
+} __packed;
+
+/* Job ring control bits */
+#define JROWN_NS BIT(3)
+#define JROWN_MID 0x01
+
+/* Declare CAAM API */
+void imx_caam_init(void);
+
+#endif /* __IMX_CAAM_H__ */
diff --git a/plat/imx/common/include/imx_clock.h b/plat/imx/common/include/imx_clock.h
new file mode 100644
index 0000000..8558638
--- /dev/null
+++ b/plat/imx/common/include/imx_clock.h
@@ -0,0 +1,1002 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __IMX_CLOCK_H__
+#define __IMX_CLOCK_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+struct ccm_pll_ctrl {
+ uint32_t ccm_pll_ctrl;
+ uint32_t ccm_pll_ctrl_set;
+ uint32_t ccm_pll_ctrl_clr;
+ uint32_t ccm_pll_ctrl_tog;
+};
+
+/* Clock gate control */
+struct ccm_clk_gate_ctrl {
+ uint32_t ccm_ccgr;
+ uint32_t ccm_ccgr_set;
+ uint32_t ccm_ccgr_clr;
+ uint32_t ccm_ccgr_tog;
+};
+
+#define CCM_CCGR_SETTING0_DOM_CLK_NONE 0
+#define CCM_CCGR_SETTING0_DOM_CLK_RUN BIT(0)
+#define CCM_CCGR_SETTING0_DOM_CLK_RUN_WAIT BIT(1)
+#define CCM_CCGR_SETTING0_DOM_CLK_ALWAYS (BIT(1) | BIT(0))
+#define CCM_CCGR_SETTING1_DOM_CLK_NONE 0
+#define CCM_CCGR_SETTING1_DOM_CLK_RUN BIT(4)
+#define CCM_CCGR_SETTING1_DOM_CLK_RUN_WAIT BIT(5)
+#define CCM_CCGR_SETTING1_DOM_CLK_ALWAYS (BIT(5) | BIT(4))
+#define CCM_CCGR_SETTING2_DOM_CLK_NONE 0
+#define CCM_CCGR_SETTING2_DOM_CLK_RUN BIT(8)
+#define CCM_CCGR_SETTING2_DOM_CLK_RUN_WAIT BIT(9)
+#define CCM_CCGR_SETTING2_DOM_CLK_ALWAYS (BIT(9) | BIT(8))
+#define CCM_CCGR_SETTING3_DOM_CLK_NONE 0
+#define CCM_CCGR_SETTING3_DOM_CLK_RUN BIT(12)
+#define CCM_CCGR_SETTING3_DOM_CLK_RUN_WAIT BIT(13)
+#define CCM_CCGR_SETTING3_DOM_CLK_ALWAYS (BIT(13) | BIT(12))
+
+enum {
+ CCM_CCGR_ID_ADC = 32,
+ CCM_CCGR_ID_AIPS1TZ = 10,
+ CCM_CCGR_ID_AIPS2TZ = 11,
+ CCM_CCGR_ID_AIPS3TZ = 12,
+ CCM_CCGR_ID_APBHDMA = 20,
+ CCM_CCGR_ID_CAAM = 36,
+ CCM_CCGR_ID_CM4 = 1,
+ CCM_CCGR_ID_CSI = 73,
+ CCM_CCGR_ID_CSU = 45,
+ CCM_CCGR_ID_DAP = 47,
+ CCM_CCGR_ID_DBGMON = 46,
+ CCM_CCGR_ID_DDRC = 19,
+ CCM_CCGR_ID_ECSPI1 = 120,
+ CCM_CCGR_ID_ECSPI2 = 121,
+ CCM_CCGR_ID_ECSPI3 = 122,
+ CCM_CCGR_ID_ECSPI4 = 123,
+ CCM_CCGR_ID_EIM = 22,
+ CCM_CCGR_ID_ENET1 = 112,
+ CCM_CCGR_ID_ENET2 = 113,
+ CCM_CCGR_ID_EPDC = 74,
+ CCM_CCGR_ID_FLEXCAN1 = 116,
+ CCM_CCGR_ID_FLEXCAN2 = 117,
+ CCM_CCGR_ID_FLEXTIMER1 = 128,
+ CCM_CCGR_ID_FLEXTIMER2 = 129,
+ CCM_CCGR_ID_GPIO1 = 160,
+ CCM_CCGR_ID_GPIO2 = 161,
+ CCM_CCGR_ID_GPIO3 = 162,
+ CCM_CCGR_ID_GPIO4 = 163,
+ CCM_CCGR_ID_GPIO5 = 164,
+ CCM_CCGR_ID_GPIO6 = 165,
+ CCM_CCGR_ID_GPIO7 = 166,
+ CCM_CCGR_ID_GPT1 = 124,
+ CCM_CCGR_ID_GPT2 = 125,
+ CCM_CCGR_ID_GPT3 = 126,
+ CCM_CCGR_ID_GPT4 = 127,
+ CCM_CCGR_ID_I2C1 = 136,
+ CCM_CCGR_ID_I2C2 = 137,
+ CCM_CCGR_ID_I2C3 = 138,
+ CCM_CCGR_ID_I2C4 = 139,
+ CCM_CCGR_ID_IOMUXC1 = 168,
+ CCM_CCGR_ID_IOMUXC2 = 169,
+ CCM_CCGR_ID_KPP = 120,
+ CCM_CCGR_ID_LCDIF = 75,
+ CCM_CCGR_ID_MIPI_CSI = 100,
+ CCM_CCGR_ID_MIPI_DSI = 101,
+ CCM_CCGR_ID_MIPI_PHY = 102,
+ CCM_CCGR_ID_MU = 39,
+ CCM_CCGR_ID_OCOTP = 35,
+ CCM_CCGR_ID_OCRAM = 17,
+ CCM_CCGR_ID_OCRAM_S = 18,
+ CCM_CCGR_ID_PCIE = 96,
+ CCM_CCGR_ID_PCIE_PHY = 96,
+ CCM_CCGR_ID_PERFMON1 = 68,
+ CCM_CCGR_ID_PERFMON2 = 69,
+ CCM_CCGR_ID_PWM1 = 132,
+ CCM_CCGR_ID_PWM2 = 133,
+ CCM_CCGR_ID_PWM3 = 134,
+ CCM_CCGR_ID_PMM4 = 135,
+ CCM_CCGR_ID_PXP = 76,
+ CCM_CCGR_ID_QOS1 = 42,
+ CCM_CCGR_ID_QOS2 = 43,
+ CCM_CCGR_ID_QOS3 = 44,
+ CCM_CCGR_ID_QUADSPI = 21,
+ CCM_CCGR_ID_RDC = 38,
+ CCM_CCGR_ID_ROMCP = 16,
+ CCM_CCGR_ID_SAI1 = 140,
+ CCM_CCGR_ID_SAI2 = 141,
+ CCM_CCGR_ID_SAI3 = 142,
+ CCM_CCGR_ID_SCTR = 34,
+ CCM_CCGR_ID_SDMA = 72,
+ CCM_CCGR_ID_SEC = 49,
+ CCM_CCGR_ID_SEMA42_1 = 64,
+ CCM_CCGR_ID_SEMA42_2 = 65,
+ CCM_CCGR_ID_SIM_DISPLAY = 5,
+ CCM_CCGR_ID_SIM_ENET = 6,
+ CCM_CCGR_ID_SIM_M = 7,
+ CCM_CCGR_ID_SIM_MAIN = 4,
+ CCM_CCGR_ID_SIM_S = 8,
+ CCM_CCGR_ID_SIM_WAKEUP = 9,
+ CCM_CCGR_ID_SIM1 = 144,
+ CCM_CCGR_ID_SIM2 = 145,
+ CCM_CCGR_ID_SIM_NAND = 20,
+ CCM_CCGR_ID_DISPLAY_CM4 = 1,
+ CCM_CCGR_ID_DRAM = 19,
+ CCM_CCGR_ID_SNVS = 37,
+ CCM_CCGR_ID_SPBA = 12,
+ CCM_CCGR_ID_TRACE = 48,
+ CCM_CCGR_ID_TZASC = 19,
+ CCM_CCGR_ID_UART1 = 148,
+ CCM_CCGR_ID_UART2 = 149,
+ CCM_CCGR_ID_UART3 = 150,
+ CCM_CCGR_ID_UART4 = 151,
+ CCM_CCGR_ID_UART5 = 152,
+ CCM_CCGR_ID_UART6 = 153,
+ CCM_CCGR_ID_UART7 = 154,
+ CCM_CCGR_ID_USB_HS = 40,
+ CCM_CCGR_ID_USB_IPG = 104,
+ CCM_CCGR_ID_USB_PHY_480MCLK = 105,
+ CCM_CCGR_ID_USB_OTG1_PHY = 106,
+ CCM_CCGR_ID_USB_OTG2_PHY = 107,
+ CCM_CCGR_ID_USBHDC1 = 108,
+ CCM_CCGR_ID_USBHDC2 = 109,
+ CCM_CCGR_ID_USBHDC3 = 110,
+ CCM_CCGR_ID_WDOG1 = 156,
+ CCM_CCGR_ID_WDOG2 = 157,
+ CCM_CCGR_ID_WDOG3 = 158,
+ CCM_CCGR_ID_WDOG4 = 159,
+};
+
+/* Clock target block */
+struct ccm_target_root_ctrl {
+ uint32_t ccm_target_root;
+ uint32_t ccm_target_root_set;
+ uint32_t ccm_target_root_clr;
+ uint32_t ccm_target_root_tog;
+ uint32_t ccm_misc;
+ uint32_t ccm_misc_set;
+ uint32_t ccm_misc_clr;
+ uint32_t ccm_misc_tog;
+ uint32_t ccm_post;
+ uint32_t ccm_post_set;
+ uint32_t ccm_post_clr;
+ uint32_t ccm_post_tog;
+ uint32_t ccm_pre;
+ uint32_t ccm_pre_set;
+ uint32_t ccm_pre_clr;
+ uint32_t ccm_pre_tog;
+ uint32_t reserved[0x0c];
+ uint32_t ccm_access_ctrl;
+ uint32_t ccm_access_ctrl_set;
+ uint32_t ccm_access_ctrl_clr;
+ uint32_t ccm_access_ctrl_tog;
+};
+
+#define CCM_TARGET_ROOT_ENABLE BIT(28)
+#define CCM_TARGET_MUX(x) (((x) - 1) << 24)
+#define CCM_TARGET_PRE_PODF(x) (((x) - 1) << 16)
+#define CCM_TARGET_POST_PODF(x) ((x) - 1)
+
+/* Target root MUX values - selects the clock source for a block */
+/* ARM_A7_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_ARM_PLL BIT(24)
+#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_ENET_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_DDR_PLL (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_SYS_PLL_PFD0 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* ARM_M4_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_ENET_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_SYS_PLL_PFD2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_DDR_PLL_DIV2 BIT(26)
+#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ARM_M4_CLK_ROOTV_IDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* MAIN_AXI_CLK_ROOT */
+
+#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD1 BIT(24)
+#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD5 BIT(26)
+#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
+
+/* DISP_AXI_CLK_ROOT */
+
+#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD1 BIT(24)
+#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD6 BIT(26)
+#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD7 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* ENET_AXI_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_PFD2 BIT(24)
+#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_DIV2 BIT(26)
+#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_PFD4 ((BIT(26) | BIT(25) | BIT(24))
+
+/* NAND_USDHC_BUS_CLK_ROOT */
+
+#define CM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB BIT(24)
+#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(26)
+#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AUDIO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* AHB_CLK_ROOT */
+
+#define CCM_TRGT_MUX_AHB_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_AHB_CLK_ROOT_SYS_PLL_PFD2 BIT(24)
+#define CCM_TRGT_MUX_AHB_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_AHB_CLK_ROOT_SYS_PLL_PFD0 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_AHB_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
+#define CCM_TRGT_MUX_AHB_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_AHB_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* IPG_CLK_ROOT */
+#define CCM_TRGT_MUX_IPG_CLK_ROOT_AHB_CLK_ROOT 0
+
+/* DRAM_PHYM_CLK_ROOT */
+#define CCM_TRGT_MUX_DRAM_PHYM_CLK_ROOT_DDR_PLL 0
+#define CCM_TRGT_MUX_DRAM_PHYM_CLK_ROOT_DRAM_PHYM_ALT_CLK_ROOT BIT(24)
+
+/* DRAM_CLK_ROOT */
+
+#define CCM_TRGT_MUX_DRAM_CLK_ROOT_DDR_PLL 0
+#define CCM_TRGT_MUX_DRAM_CLK_ROOT_DRAM_ALT_CLK_ROOT BIT(24)
+
+/* DRAM_PHYM_ALT_CLK_ROOT */
+#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_DDR_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_SYS_PLL BIT(25)
+#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_USB_PLL BIT(26)
+#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_SYS_PLL_PFD7 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* DRAM_ALT_CLK_ROOT */
+
+#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_DDR_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL BIT(25)
+#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_USB_PLL BIT(26)
+#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL_PFD0 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL_PFD2 ((BIT(26) | BIT(25) | BIT(24))
+
+/* USB_HSIC_CLK_ROOT */
+
+#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL BIT(24)
+#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_USB_PLL BIT(25)
+#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD3 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
+#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD5 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
+
+/* LCDIF_PIXEL_CLK_ROOT */
+
+#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD5 BIT(24)
+#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_EXT_CLK3 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
+#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* MIPI_DSI_CLK_ROOT */
+
+#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD5 BIT(24)
+#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD3 BIT(25)
+#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD0_DIV2 BIT(26)
+#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_DDR_PLL_DIV2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_AUDIO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* MIPI_CSI_CLK_ROOT */
+
+#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD4 BIT(24)
+#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD3 BIT(25)
+#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD0_DIV2 BIT(26)
+#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_DDR_PLL_DIV2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_AUDIO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* MIPI_DPHY_REF_CLK_ROOT */
+
+#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
+#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_SYS_PLL_PFD5 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_REF_1M BIT(26)
+#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
+
+/* SAI1_CLK_ROOT */
+
+#define CCM_TRGT_MUX_SAI1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_SAI1_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_SAI1_CLK_ROOT_AUDIO_PLL BIT(25)
+#define CCM_TRGT_MUX_SAI1_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_SAI1_CLK_ROOT_VIDEO_PLL BIT(26)
+#define CCM_TRGT_MUX_SAI1_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_SAI1_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
+
+/* SAI2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_SAI2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_SAI2_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_SAI2_CLK_ROOT_AUDIO_PLL BIT(25)
+#define CCM_TRGT_MUX_SAI2_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_SAI2_CLK_ROOT_VIDEO_PLL BIT(26)
+#define CCM_TRGT_MUX_SAI2_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_SAI2_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
+
+/* SAI3_CLK_ROOT */
+
+#define CCM_TRGT_MUX_SAI3_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_SAI3_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_SAI3_CLK_ROOT_AUDIO_PLL BIT(25)
+#define CCM_TRGT_MUX_SAI3_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_SAI3_CLK_ROOT_VIDEO_PLL BIT(26)
+#define CCM_TRGT_MUX_SAI3_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_SAI3_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
+
+/* ENET1_REF_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV8 BIT(24)
+#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
+#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV40 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_SYS_PLL_DIV4 BIT(26)
+#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
+
+/* ENET1_TIME_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_AUDIO_PLL BIT(25)
+#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK1 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK2 BIT(26)
+#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* ENET_PHY_REF_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV40 BIT(24)
+#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
+#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV8 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_DDR_PLL_DIV2 BIT(26)
+#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_SYS_PLL_PFD3 ((BIT(26) | BIT(25) | BIT(24))
+
+/* EIM_CLK_ROOT */
+
+#define CCM_TRGT_MUX_EIM_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_EIM_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD2 BIT(26)
+#define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD3 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_EIM_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* NAND_CLK_ROOT */
+
+#define CCM_TRGT_MUX_NAND_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL BIT(24)
+#define CCM_TRGT_MUX_NAND_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL_PFD0 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL_PFD3 BIT(26)
+#define CCM_TRGT_MUX_NAND_CLK_ROOT_ENET_PLL_DIV2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_NAND_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_NAND_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* QSPI_CLK_ROOT */
+
+#define CCM_TRGT_MUX_QSPI_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD4 BIT(24)
+#define CCM_TRGT_MUX_QSPI_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_QSPI_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD3 BIT(26)
+#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
+
+/* USDHC1_CLK_ROOT */
+
+#define CM_TRGT_MUX_USDHC1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD0 BIT(24)
+#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
+#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
+
+/* USDHC2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD0 BIT(24)
+#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
+#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
+
+/* USDHC3_CLK_ROOT */
+
+#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD0 BIT(24)
+#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
+#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
+
+/* CAN1_CLK_ROOT */
+
+#define CCM_TRGT_MUX_CAN1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_CAN1_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
+#define CCM_TRGT_MUX_CAN1_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_CAN1_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_CAN1_CLK_ROOT_ENET_PLL_DIV25 BIT(26)
+#define CCM_TRGT_MUX_CAN1_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
+
+/* CAN2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_CAN2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_CAN2_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
+#define CCM_TRGT_MUX_CAN2_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_CAN2_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_CAN2_CLK_ROOT_ENET_PLL_DIV25 BIT(26)
+#define CCM_TRGT_MUX_CAN2_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_CAN2_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_CAN2_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
+
+/* I2C1_CLK_ROOT */
+
+#define CCM_TRGT_MUX_I2C1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_I2C1_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
+#define CCM_TRGT_MUX_I2C1_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
+#define CCM_TRGT_MUX_I2C1_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_I2C1_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_I2C1_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_I2C1_CLK_ROOT_USB_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_I2C1_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24))
+
+/* I2C2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_I2C2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_I2C2_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
+#define CCM_TRGT_MUX_I2C2_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
+#define CCM_TRGT_MUX_I2C2_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_I2C2_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_I2C2_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_I2C2_CLK_ROOT_USB_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_I2C2_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24))
+
+/* I2C3_CLK_ROOT */
+
+#define CCM_TRGT_MUX_I2C3_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_I2C3_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
+#define CCM_TRGT_MUX_I2C3_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
+#define CCM_TRGT_MUX_I2C3_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_I2C3_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_I2C3_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_I2C3_CLK_ROOT_USB_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_I2C3_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24))
+
+/* I2C4_CLK_ROOT */
+
+#define CCM_TRGT_MUX_I2C4_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_I2C4_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
+#define CCM_TRGT_MUX_I2C4_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
+#define CCM_TRGT_MUX_I2C4_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_I2C4_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_I2C4_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_I2C4_CLK_ROOT_USB_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_I2C4_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24))
+
+/* UART1_CLK_ROOT */
+
+#define CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_UART1_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_UART1_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_UART1_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_UART1_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_UART1_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_UART1_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_UART1_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* UART2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_UART2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_UART2_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_UART2_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_UART2_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_UART2_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_UART2_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_UART2_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_UART2_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* UART3_CLK_ROOT */
+
+#define CCM_TRGT_MUX_UART3_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_UART3_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_UART3_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_UART3_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_UART3_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_UART3_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_UART3_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_UART3_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* UART4_CLK_ROOT */
+
+#define CCM_TRGT_MUX_UART4_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_UART4_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_UART4_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_UART4_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_UART4_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_UART4_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_UART4_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_UART4_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* UART5_CLK_ROOT */
+
+#define CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_UART5_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_UART5_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_UART5_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_UART5_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_UART5_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_UART5_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_UART5_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* UART6_CLK_ROOT */
+
+#define CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_UART6_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_UART6_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_UART6_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_UART6_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_UART6_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_UART6_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_UART6_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* UART7_CLK_ROOT */
+
+#define CCM_TRGT_MUX_UART7_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_UART7_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_UART7_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_UART7_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_UART7_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_UART7_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_UART7_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_UART7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* ECSPI1_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* ECSPI2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* ECSPI3_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* ECSPI4_CLK_ROOT */
+
+#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
+#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL BIT(26)
+#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* PWM1_CLK_ROOT */
+
+#define CCM_TRGT_MUX_PWM1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_PWM1_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_PWM1_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_PWM1_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_PWM1_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_PWM1_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_PWM1_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_PWM1_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* PWM2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_PWM2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_PWM2_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_PWM2_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_PWM2_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_PWM2_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_PWM2_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_PWM2_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_PWM2_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* PWM3_CLK_ROOT */
+
+#define CCM_TRGT_MUX_PWM3_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_PWM3_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_PWM3_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_PWM3_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_PWM3_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_PWM3_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_PWM3_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_PWM3_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* PWM4_CLK_ROOT */
+
+#define CCM_TRGT_MUX_PWM4_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_PWM4_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_PWM4_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_PWM4_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_PWM4_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_PWM4_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_PWM4_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_PWM4_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* FLEXTIMER1_CLK_ROOT */
+
+#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* FLEXTIMER2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_AUDIO_PLL BIT(26)
+#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target SIM1_CLK_ROOT */
+
+#define CCM_TRGT_MUX_SIM1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_SIM1_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_SIM1_CLK_ROOT_USB_PLL BIT(26)
+#define CCM_TRGT_MUX_SIM1_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_SIM1_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target SIM2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_SIM2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_SIM2_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_SIM2_CLK_ROOT_USB_PLL BIT(26)
+#define CCM_TRGT_MUX_SIM2_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_SIM2_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target GPT1_CLK_ROOT */
+
+#define CCM_TRGT_MUX_GPT1_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_GPT1_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_GPT1_CLK_ROOT_SYS_PLL_PFD0 BIT(25)
+#define CCM_TRGT_MUX_GPT1_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_GPT1_CLK_ROOT_VIDEO_PLL BIT(26)
+#define CCM_TRGT_MUX_GPT1_CLK_ROOT_REF_1M (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_GPT1_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_GPT1_CLK_ROOT_EXT_CLK1 ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target GPT2_CLK_ROOT */
+
+#define CCM_TRGT_MUX_GPT2_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_GPT2_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_GPT2_CLK_ROOT_SYS_PLL_PFD0 BIT(25)
+#define CCM_TRGT_MUX_GPT2_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_GPT2_CLK_ROOT_VIDEO_PLL BIT(26)
+#define CCM_TRGT_MUX_GPT2_CLK_ROOT_REF_1M (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_GPT2_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_GPT2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target GPT3_CLK_ROOT */
+
+#define CCM_TRGT_MUX_GPT3_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_GPT3_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_GPT3_CLK_ROOT_SYS_PLL_PFD0 BIT(25)
+#define CCM_TRGT_MUX_GPT3_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_GPT3_CLK_ROOT_VIDEO_PLL BIT(26)
+#define CCM_TRGT_MUX_GPT3_CLK_ROOT_REF_1M (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_GPT3_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_GPT3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
+
+/*Target GPT4_CLK_ROOT */
+
+#define CCM_TRGT_MUX_GPT4_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_GPT4_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
+#define CCM_TRGT_MUX_GPT4_CLK_ROOT_SYS_PLL_PFD0 BIT(25)
+#define CCM_TRGT_MUX_GPT4_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_GPT4_CLK_ROOT_VIDEO_PLL BIT(26)
+#define CCM_TRGT_MUX_GPT4_CLK_ROOT_REF_1M (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_GPT4_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_GPT4_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target TRACE_CLK_ROOT */
+
+#define CCM_TRGT_MUX_TRACE_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_TRACE_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_TRACE_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_TRACE_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_TRACE_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
+#define CCM_TRGT_MUX_TRACE_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_TRACE_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_TRACE_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target WDOG_CLK_ROOT */
+
+#define CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_WDOG_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_WDOG_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
+#define CCM_TRGT_MUX_WDOG_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_WDOG_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD1_DIV2 ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target CSI_MCLK_CLK_ROOT */
+
+#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
+#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target AUDIO_MCLK_CLK_ROOT */
+#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_OSC_24M 0
+#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
+#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
+#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
+#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target CCM_CLKO1 */
+#define CCM_TRGT_MUX_CCM_CLKO1_OSC_24M 0
+#define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL BIT(24)
+#define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_DIV2 BIT(25)
+#define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_PFD0_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_PFD3 BIT(26)
+#define CCM_TRGT_MUX_CCM_CLKO1_ENET_PLL_DIV2 (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_CCM_CLKO1_DDR_PLL_DIV2 (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_CCM_CLKO1_REF_1M ((BIT(26) | BIT(25) | BIT(24))
+
+/* Target CCM_CLKO2 */
+#define CCM_TRGT_MUX_CCM_CLKO2_OSC_24M 0
+#define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_DIV2 BIT(24)
+#define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD0 BIT(25)
+#define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD1_DIV2 (BIT(25) | BIT(24))
+#define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD4 BIT(26)
+#define CCM_TRGT_MUX_CCM_CLKO2_AUDIO_PLL (BIT(26) | BIT(24))
+#define CCM_TRGT_MUX_CCM_CLKO2_VIDEO_PLL (BIT(26) | BIT(25))
+#define CCM_TRGT_MUX_CCM_CLKO2_OSC_32K ((BIT(26) | BIT(25) | BIT(24))
+
+/*
+ * See Table 5-11 in i.MX7 Solo Reference manual rev 0.1
+ * The indices must be calculated by dividing the offset by
+ * sizeof (struct ccm_target_root_ctrl) => 0x80 bytes for each index
+ */
+enum {
+ CCM_TRT_ID_ARM_A7_CLK_ROOT = 0,
+ CCM_TRT_ID_ARM_M4_CLK_ROOT = 1,
+ CCM_TRT_ID_MAIN_AXI_CLK_ROOT = 16,
+ CCM_TRT_ID_DISP_AXI_CLK_ROOT = 17,
+ CCM_TRT_ID_ENET_AXI_CLK_ROOT = 18,
+ CCM_TRT_ID_NAND_USDHC_BUS_CLK_ROOT = 19,
+ CCM_TRT_ID_AHB_CLK_ROOT = 32,
+ CCM_TRT_ID_IPG_CLK_ROOT = 33,
+ CCM_TRT_ID_DRAM_PHYM_CLK_ROOT = 48,
+ CCM_TRT_ID_DRAM_CLK_ROOT = 49,
+ CCM_TRT_ID_DRAM_PHYM_ALT_CLK_ROOT = 64,
+ CCM_TRT_ID_DRAM_ALT_CLK_ROOT = 65,
+ CCM_TRT_ID_USB_HSIC_CLK_ROOT = 66,
+ CCM_TRT_ID_LCDIF_PIXEL_CLK_ROOT = 70,
+ CCM_TRT_ID_MIPI_DSI_CLK_ROOT = 71,
+ CCM_TRT_ID_MIPI_CSI_CLK_ROOT = 72,
+ CCM_TRT_ID_MIPI_DPHY_REF_CLK_ROOT = 73,
+ CCM_TRT_ID_SAI1_CLK_ROOT = 74,
+ CCM_TRT_ID_SAI2_CLK_ROOT = 75,
+ CCM_TRT_ID_SAI3_CLK_ROOT = 76,
+ CCM_TRT_ID_ENET1_REF_CLK_ROOT = 78,
+ CCM_TRT_ID_ENET1_TIME_CLK_ROOT = 79,
+ CCM_TRT_ID_ENET_PHY_REF_CLK_ROOT = 82,
+ CCM_TRT_ID_EIM_CLK_ROOT = 83,
+ CCM_TRT_ID_NAND_CLK_ROOT = 84,
+ CCM_TRT_ID_QSPI_CLK_ROOT = 85,
+ CCM_TRT_ID_USDHC1_CLK_ROOT = 86,
+ CCM_TRT_ID_USDHC2_CLK_ROOT = 87,
+ CCM_TRT_ID_USDHC3_CLK_ROOT = 88,
+ CCM_TRT_ID_CAN1_CLK_ROOT = 89,
+ CCM_TRT_ID_CAN2_CLK_ROOT = 90,
+ CCM_TRT_ID_I2C1_CLK_ROOT = 91,
+ CCM_TRT_ID_I2C2_CLK_ROOT = 92,
+ CCM_TRT_ID_I2C3_CLK_ROOT = 93,
+ CCM_TRT_ID_I2C4_CLK_ROOT = 94,
+ CCM_TRT_ID_UART1_CLK_ROOT = 95,
+ CCM_TRT_ID_UART2_CLK_ROOT = 96,
+ CCM_TRT_ID_UART3_CLK_ROOT = 97,
+ CCM_TRT_ID_UART4_CLK_ROOT = 98,
+ CCM_TRT_ID_UART5_CLK_ROOT = 99,
+ CCM_TRT_ID_UART6_CLK_ROOT = 100,
+ CCM_TRT_ID_UART7_CLK_ROOT = 101,
+ CCM_TRT_ID_ECSPI1_CLK_ROOT = 102,
+ CCM_TRT_ID_ECSPI2_CLK_ROOT = 103,
+ CCM_TRT_ID_ECSPI3_CLK_ROOT = 104,
+ CCM_TRT_ID_ECSPI4_CLK_ROOT = 105,
+ CCM_TRT_ID_PWM1_CLK_ROOT = 106,
+ CCM_TRT_ID_PWM2_CLK_ROOT = 107,
+ CCM_TRT_ID_PWM3_CLK_ROOT = 108,
+ CCM_TRT_ID_PWM4_CLK_ROOT = 109,
+ CCM_TRT_ID_FLEXTIMER1_CLK_ROOT = 110,
+ CCM_TRT_ID_FLEXTIMER2_CLK_ROOT = 111,
+ CCM_TRT_ID_SIM1_CLK_ROOT = 112,
+ CCM_TRT_ID_SIM2_CLK_ROOT = 113,
+ CCM_TRT_ID_GPT1_CLK_ROOT = 114,
+ CCM_TRT_ID_GPT2_CLK_ROOT = 115,
+ CCM_TRT_ID_GPT3_CLK_ROOT = 116,
+ CCM_TRT_ID_GPT4_CLK_ROOT = 117,
+ CCM_TRT_ID_TRACE_CLK_ROOT = 118,
+ CCM_TRT_ID_WDOG_CLK_ROOT = 119,
+ CCM_TRT_ID_CSI_MCLK_CLK_ROOT = 120,
+ CCM_TRT_ID_AUDIO_MCLK_CLK_ROOT = 121,
+ CCM_TRT_ID_CCM_CLKO1 = 123,
+ CCM_TRT_ID_CCM_CLKO2 = 124,
+};
+
+#define CCM_MISC_VIOLATE BIT(8)
+#define CCM_MISC_TIMEOUT BIT(4)
+#define CCM_MISC_AUTHEN_FAIL BIT(0)
+
+#define CCM_POST_BUSY2 BIT(31)
+#define CCM_POST_SELECT_BRANCH_A BIT(28)
+#define CCM_POST_BUSY1 BIT(7)
+#define CCM_POST_POST_PODF(x) ((x) - 1)
+
+#define CCM_PRE_BUSY4 BIT(31)
+#define CCM_PRE_ENABLE_A BIT(28)
+#define CCM_PRE_MUX_A(x) (((x) - 1) << 24)
+#define CCM_PRE_BUSY3 BIT(19)
+#define CCM_PRE_PODF_A(x) (((x) - 1) << 16)
+#define CCM_PRE_BUSY1 BIT(15)
+#define CCM_PRE_ENABLE_B BIT(12)
+#define CCM_PRE_MUX_B(x) (((x) - 1) << 8)
+#define CCM_PRE_BUSY0 BIT(3)
+#define CCM_PRE_POST_PODF(x) ((x) - 1)
+
+#define CCM_ACCESS_CTRL_LOCK BIT(31)
+#define CCM_ACCESS_SEMA_ENABLE BIT(28)
+#define CCM_ACCESS_DOM3_WHITELIST BIT(27)
+#define CCM_ACCESS_DOM2_WHITELIST BIT(26)
+#define CCM_ACCESS_DOM1_WHITELIST BIT(25)
+#define CCM_ACCESS_DOM0_WHITELIST BIT(24)
+#define CCM_ACCESS_MUTEX BIT(20)
+#define CCM_ACCESS_OWNER_ID(x) ((x) << 16)
+#define CCM_ACCESS_DOM3_INFO(x) ((x) << 12)
+#define CCM_ACCESS_DOM2_INFO(x) ((x) << 8)
+#define CCM_ACCESS_DOM1_INFO(x) ((x) << 4)
+#define CCM_ACCESS_DOM0_INFO(x) (x)
+
+#define CCM_PLL_CTRL_NUM 0x21
+#define CCM_CLK_GATE_CTRL_NUM 0xbf
+#define CCM_ROOT_CTRL_NUM 0x79
+
+struct ccm {
+ uint32_t ccm_gpr0;
+ uint32_t ccm_gpr0_set;
+ uint32_t ccm_gpr0_clr;
+ uint32_t ccm_grp0_tog;
+ uint32_t reserved[0x1fc];
+ struct ccm_pll_ctrl ccm_pll_ctrl[CCM_PLL_CTRL_NUM];
+ uint32_t reserved1[0xd7c];
+ struct ccm_clk_gate_ctrl ccm_clk_gate_ctrl[CCM_CLK_GATE_CTRL_NUM];
+ uint32_t reserved2[0xd04];
+ struct ccm_target_root_ctrl ccm_root_ctrl[CCM_ROOT_CTRL_NUM];
+};
+
+void imx_clock_target_set(unsigned int id, uint32_t val);
+void imx_clock_target_clr(unsigned int id, uint32_t val);
+void imx_clock_gate_enable(unsigned int id, bool enable);
+
+void imx_clock_init(void);
+
+void imx_clock_enable_uart(unsigned int uart_id, uint32_t uart_clk_en_bits);
+void imx_clock_disable_uart(unsigned int uart_id);
+void imx_clock_enable_usdhc(unsigned int usdhc_id, uint32_t usdhc_clk_en_bits);
+void imx_clock_set_wdog_clk_root_bits(uint32_t wdog_clk_root_en_bits);
+void imx_clock_enable_wdog(unsigned int wdog_id);
+void imx_clock_disable_wdog(unsigned int wdog_id);
+void imx_clock_enable_usb(unsigned int usb_id);
+void imx_clock_disable_usb(unsigned int usb_id);
+void imx_clock_set_usb_clk_root_bits(uint32_t usb_clk_root_en_bits);
+
+#endif /* __IMX_CLOCK_H__ */
diff --git a/plat/imx/common/include/imx_csu.h b/plat/imx/common/include/imx_csu.h
new file mode 100644
index 0000000..9bf9373
--- /dev/null
+++ b/plat/imx/common/include/imx_csu.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __IMX_CSU_H__
+#define __IMX_CSU_H__
+
+#include <arch.h>
+
+/*
+ * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
+ * Rev. 0, 03/2017 Section 3.3.1
+ *
+ * Config secure level register (CSU_CSLn)
+ */
+#define CSU_CSL_LOCK_S1 BIT(24)
+#define CSU_CSL_NSW_S1 BIT(23)
+#define CSU_CSL_NUW_S1 BIT(22)
+#define CSU_CSL_SSW_S1 BIT(21)
+#define CSU_CSL_SUW_S1 BIT(20)
+#define CSU_CSL_NSR_S1 BIT(19)
+#define CSU_CSL_NUR_S1 BIT(18)
+#define CSU_CSL_SSR_S1 BIT(17)
+#define CSU_CSL_SUR_S1 BIT(16)
+#define CSU_CSL_LOCK_S2 BIT(8)
+#define CSU_CSL_NSW_S2 BIT(7)
+#define CSU_CSL_NUW_S2 BIT(6)
+#define CSU_CSL_SSW_S2 BIT(5)
+#define CSU_CSL_SUW_S2 BIT(4)
+#define CSU_CSL_NSR_S2 BIT(3)
+#define CSU_CSL_NUR_S2 BIT(2)
+#define CSU_CSL_SSR_S2 BIT(1)
+#define CSU_CSL_SUR_S2 BIT(0)
+
+#define CSU_CSL_OPEN_ACCESS (CSU_CSL_NSW_S1 | CSU_CSL_NUW_S1 | CSU_CSL_SSW_S1 |\
+ CSU_CSL_SUW_S1 | CSU_CSL_NSR_S1 | CSU_CSL_NUR_S1 |\
+ CSU_CSL_SSR_S1 | CSU_CSL_SUR_S1 | CSU_CSL_NSW_S2 |\
+ CSU_CSL_NUW_S2 | CSU_CSL_SSW_S2 | CSU_CSL_SUW_S2 |\
+ CSU_CSL_NSR_S2 | CSU_CSL_NUR_S2 | CSU_CSL_SSR_S2 |\
+ CSU_CSL_SUR_S2)
+void imx_csu_init(void);
+
+#endif /* __IMX_CSU_H__ */
diff --git a/plat/imx/common/include/imx_hab.h b/plat/imx/common/include/imx_hab.h
new file mode 100644
index 0000000..e3d266c
--- /dev/null
+++ b/plat/imx/common/include/imx_hab.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __IMX_HAB_H__
+#define __IMX_HAB_H__
+
+#include <imx_hab_arch.h>
+#include <imx_regs.h>
+
+#define HAB_ROM_VECTOR_BASE\
+ (BOOTROM_BASE + HAB_CALLBACK_OFFSET)
+/*
+ * Section 4.5 of the High Assurance Boot Version 4 Application Programming
+ * Interface Reference Manual defines the ROM Vector table as coming after a 4
+ * byte header
+ *
+ * A series of function pointers are enumerated at fixed addresses, which are
+ * described below
+ */
+#define HAB_ROM_VECTOR_TABLE_ENTRY (HAB_ROM_VECTOR_BASE + 0x04)
+#define HAB_ROM_VECTOR_TABLE_EXIT (HAB_ROM_VECTOR_BASE + 0x08)
+#define HAB_ROM_VECTOR_TABLE_CHECK_TARGET (HAB_ROM_VECTOR_BASE + 0x0C)
+#define HAB_ROM_VECTOR_TABLE_AUTHENTICATE_IMAGE (HAB_ROM_VECTOR_BASE + 0x10)
+#define HAB_ROM_VECTOR_TABLE_RUN_DCD (HAB_ROM_VECTOR_BASE + 0x14)
+#define HAB_ROM_VECTOR_TABLE_RUN_CSF (HAB_ROM_VECTOR_BASE + 0x18)
+#define HAB_ROM_VECTOR_TABLE_ASSERT (HAB_ROM_VECTOR_BASE + 0x1C)
+#define HAB_ROM_VECTOR_TABLE_REPORT_EVENT (HAB_ROM_VECTOR_BASE + 0x20)
+#define HAB_ROM_VECTOR_TABLE_REPORT_STATUS (HAB_ROM_VECTOR_BASE + 0x24)
+#define HAB_ROM_VECTOR_TABLE_FAILSAFE (HAB_ROM_VECTOR_BASE + 0x28)
+
+#endif /* __IMX_HAB_H__ */
diff --git a/plat/imx/common/include/imx_io_mux.h b/plat/imx/common/include/imx_io_mux.h
new file mode 100644
index 0000000..44284f6
--- /dev/null
+++ b/plat/imx/common/include/imx_io_mux.h
@@ -0,0 +1,609 @@
+/*
+ * Copyright 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_IO_MUX_H__
+#define __IMX_IO_MUX_H__
+
+#include <stdint.h>
+
+/*
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
+ * Section 8.2.7 IOMUXC Memory Map/Register Definition
+ */
+
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_OFFSET 0x0014
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_OFFSET 0x0018
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_OFFSET 0x001C
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET 0x0020
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET 0x0024
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET 0x0028
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET 0x002C
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET 0x0030
+
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET 0x0034
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_OFFSET 0x0038
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_OFFSET 0x003C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_OFFSET 0x0040
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_OFFSET 0x0044
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_OFFSET 0x0048
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_OFFSET 0x004C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_OFFSET 0x0050
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_OFFSET 0x0054
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_OFFSET 0x0058
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_OFFSET 0x005C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_OFFSET 0x0060
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_OFFSET 0x0064
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_OFFSET 0x0068
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_OFFSET 0x006C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_OFFSET 0x0070
+
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_OFFSET 0x0074
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_OFFSET 0x0078
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_OFFSET 0x007C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_OFFSET 0x0080
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_OFFSET 0x0084
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_OFFSET 0x0088
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_OFFSET 0x008C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_OFFSET 0x0090
+
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_OFFSET 0x0094
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_OFFSET 0x0098
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_OFFSET 0x009C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_OFFSET 0x00A0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_OFFSET 0x00A4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_OFFSET 0x00A8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_OFFSET 0x00AC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x00B0
+
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_OFFSET 0x00B4
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_OFFSET 0x00B8
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_OFFSET 0x00BC
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_OFFSET 0x00C0
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_OFFSET 0x00C4
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_OFFSET 0x00C8
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_OFFSET 0x00CC
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_OFFSET 0x00D0
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_OFFSET 0x00D4
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_OFFSET 0x00D8
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_OFFSET 0x00DC
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_OFFSET 0x00E0
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_OFFSET 0x00E4
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_OFFSET 0x00E8
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_OFFSET 0x00EC
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_OFFSET 0x00F0
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_OFFSET 0x00F4
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_OFFSET 0x00F8
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_OFFSET 0x00FC
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_OFFSET 0x0100
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_OFFSET 0x0104
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_OFFSET 0x0108
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_OFFSET 0x010C
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_OFFSET 0x0110
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_OFFSET 0x0114
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_OFFSET 0x0118
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_OFFSET 0x011C
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_OFFSET 0x0120
+#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_OFFSET 0x0124
+
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET 0x0128
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA 0x00
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT1_I2C1_SCL BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT2_PMIC_READY BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT3_ECSPI1_SS1 (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT4_ENET2_1588_EVENT0_IN BIT(3)
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT5_GPIO4_IO0 (BIT(2) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT6_ENET1_MDIO (BIT(2) | BIT(1))
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION BIT(3)
+
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET 0x012C
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA 0x00
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT1_I2C1_SDA BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT2_SAI3_MCLK BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT3_ECSPI1_SS2 (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT4_ENET2_1588_EVENT0_OUT BIT(3)
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT5_GPIO4_IO1 (BIT(2) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT6_ENET1_MDC (BIT(2) | BIT(1))
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_SION BIT(3)
+
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_OFFSET 0x0130
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_OFFSET 0x0134
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_OFFSET 0x0138
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_OFFSET 0x013C
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_OFFSET 0x0140
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_OFFSET 0x0144
+
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_OFFSET 0x0148
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_OFFSET 0x014C
+#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_OFFSET 0x0150
+#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET 0x0154
+#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET 0x0158
+#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET 0x015C
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET 0x0160
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET 0x0164
+
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET 0x0168
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK 0x00
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT2_SD2_DATA4 BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT3_CSI_DATA2 (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT5_GPIO4_IO16 (BIT(2) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT6_EPDC_PWR_COM (BIT(2) | (BIT(1))
+
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET 0x016C
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT0_ECSPI1_MOSI 0x00
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT2_SD2_DATA5 BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT3_CSI_DATA3 (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT5_GPIO4_IO17 (BIT(2) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT6_EPDC_PWR_STAT (BIT(2) | (BIT(1))
+
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_OFFSET 0x0170
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_OFFSET 0x0174
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_OFFSET 0x0178
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_OFFSET 0x017C
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_OFFSET 0x0180
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_OFFSET 0x0184
+
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_OFFSET 0x0188
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_OFFSET 0x018C
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_OFFSET 0x0190
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_OFFSET 0x0194
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_OFFSET 0x0198
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_OFFSET 0x019C
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_OFFSET 0x01A0
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_OFFSET 0x01A4
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_OFFSET 0x01A8
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_OFFSET 0x01AC
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_OFFSET 0x01B0
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_OFFSET 0x01B4
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_OFFSET 0x01B8
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_OFFSET 0x01BC
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_OFFSET 0x01C0
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET 0x01C4
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET 0x01C8
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET 0x01CC
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET 0x01D0
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET 0x01D4
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET 0x01D8
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET 0x01DC
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET 0x01E0
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET 0x01E4
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET 0x01E8
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET 0x01EC
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET 0x01F0
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET 0x01F4
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_OFFSET 0x01F8
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_OFFSET 0x01FC
+
+#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0200
+#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0204
+#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0208
+#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_OFFSET 0x020C
+#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0210
+#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0214
+#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_OFFSET 0x0218
+#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x021C
+#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0220
+#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0224
+#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0228
+
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x022C
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x0230
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x0234
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x0238
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x023C
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x0240
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x0244
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x0248
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x024C
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x0250
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x0254
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x0258
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_OFFSET 0x025C
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_OFFSET 0x0260
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_OFFSET 0x0264
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_OFFSET 0x0268
+
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_OFFSET 0x026C
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_OFFSET 0x0270
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_OFFSET 0x0274
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_OFFSET 0x0278
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_OFFSET 0x027C
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_OFFSET 0x0280
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET 0x0284
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_OFFSET 0x0288
+
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_OFFSET 0x028C
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_OFFSET 0x0290
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_OFFSET 0x0294
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_OFFSET 0x0298
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_OFFSET 0x029C
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_OFFSET 0x02A0
+
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_OFFSET 0x02A4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_OFFSET 0x02A8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_OFFSET 0x02AC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_OFFSET 0x02B0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_OFFSET 0x02B4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_OFFSET 0x02B8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_OFFSET 0x02BC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_OFFSET 0x02C0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_OFFSET 0x02C4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_OFFSET 0x02C8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_OFFSET 0x02CC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_OFFSET 0x02D0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_OFFSET 0x02D4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_OFFSET 0x02D8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_OFFSET 0x02DC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_OFFSET 0x02E0
+
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_OFFSET 0x02E4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_OFFSET 0x02E8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_OFFSET 0x02EC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_OFFSET 0x02F0
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_OFFSET 0x02F4
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_OFFSET 0x02F8
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_OFFSET 0x02FC
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_OFFSET 0x0300
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_OFFSET 0x0304
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_OFFSET 0x0308
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_OFFSET 0x030C
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_OFFSET 0x0310
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_OFFSET 0x0314
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_OFFSET 0x0318
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_OFFSET 0x031C
+#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x0320
+
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_OFFSET 0x0324
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_OFFSET 0x0328
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_OFFSET 0x032C
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_OFFSET 0x0330
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_OFFSET 0x0334
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_OFFSET 0x0338
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_OFFSET 0x033C
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_OFFSET 0x0340
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_OFFSET 0x0344
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_OFFSET 0x0348
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_OFFSET 0x034C
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_OFFSET 0x0350
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_OFFSET 0x0354
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_OFFSET 0x0358
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_OFFSET 0x035C
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_OFFSET 0x0360
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_OFFSET 0x0364
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_OFFSET 0x0368
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_OFFSET 0x036C
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_OFFSET 0x0370
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_OFFSET 0x0374
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_OFFSET 0x0378
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_OFFSET 0x037C
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_OFFSET 0x0380
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_OFFSET 0x0384
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_OFFSET 0x0388
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_OFFSET 0x038C
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_OFFSET 0x0390
+#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_OFFSET 0x0394
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET 0x0398
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_0_X1 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4 BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_2_X2 BIT(1)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_FAST 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_SLOW BIT(2)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_DIS 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN BIT(3)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_DIS 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN BIT(4)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_0_100K_PD 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_1_5K_PU BIT(5)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_2_47K_PU BIT(6)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU (BIT(6) | BIT(5))
+
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET 0x039C
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_0_X1 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4 BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_2_X2 BIT(1)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_FAST 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_SLOW BIT(2)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_DIS 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN BIT(3)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_DIS 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN BIT(4)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_0_100K_PD 0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_1_5K_PU BIT(5)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_2_47K_PU BIT(6)
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU (BIT(6) | BIT(5))
+
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_OFFSET 0x03A0
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_OFFSET 0x03A4
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_OFFSET 0x03A8
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_OFFSET 0x03AC
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_OFFSET 0x03B0
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_OFFSET 0x03B4
+
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_OFFSET 0x03B8
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_OFFSET 0x03BC
+#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_OFFSET 0x03C0
+#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_OFFSET 0x03C4
+#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_OFFSET 0x03C8
+#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_OFFSET 0x03CC
+#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_OFFSET 0x03D0
+#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_OFFSET 0x03D4
+
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET 0x03D8
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_0_X1 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4 BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_2_X2 BIT(1)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_3_X6 (BIT(1) | BIT(0))
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_FAST 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_SLOW BIT(2)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_DIS 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN BIT(3)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_DIS 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN BIT(4)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_0_100K_PD 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_1_5K_PU BIT(5)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_2_47K_PU BIT(6)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU (BIT(6) | BIT(5))
+
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET 0x03DC
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_0_X1 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4 BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_2_X2 BIT(1)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_3_X6 (BIT(1) | BIT(0))
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_FAST 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_SLOW BIT(2)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_DIS 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN BIT(3)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_DIS 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN BIT(4)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_0_100K_PD 0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_1_5K_PU BIT(5)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_2_47K_PU BIT(6)
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU (BIT(6) | BIT(5))
+
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_OFFSET 0x03E0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_OFFSET 0x03E4
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_OFFSET 0x03E8
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_OFFSET 0x03EC
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_OFFSET 0x03F0
+#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_OFFSET 0x03F4
+
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_OFFSET 0x03F8
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_OFFSET 0x03FC
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_OFFSET 0x0400
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_OFFSET 0x0404
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_OFFSET 0x0408
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_OFFSET 0x040C
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_OFFSET 0x0410
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_OFFSET 0x0414
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_OFFSET 0x0418
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_OFFSET 0x041C
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_OFFSET 0x0420
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_OFFSET 0x0424
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_OFFSET 0x0428
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_OFFSET 0x042C
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_OFFSET 0x0430
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET 0x0434
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET 0x0438
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET 0x043C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET 0x0440
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET 0x0444
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET 0x0448
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET 0x044C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET 0x0450
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET 0x0454
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET 0x0458
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET 0x045C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET 0x0460
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET 0x0464
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET 0x0468
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET 0x046C
+
+#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0470
+#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0474
+#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0478
+#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_OFFSET 0x047C
+#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0480
+#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0484
+#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_OFFSET 0x0488
+#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x048C
+#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0490
+#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0494
+#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0498
+
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x049C
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x04A0
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x04A4
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x04A8
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x04AC
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x04B0
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x04B4
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x04B8
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x04BC
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x04C0
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x04C4
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x04C8
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_OFFSET 0x04CC
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_OFFSET 0x04D0
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_OFFSET 0x04D4
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_OFFSET 0x04D8
+
+#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_OFFSET 0x04DC
+#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_OFFSET 0x04E0
+
+#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_OFFSET 0x04E4
+#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_OFFSET 0x04E8
+#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_OFFSET 0x04EC
+#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_OFFSET 0x04F0
+
+#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_OFFSET 0x04F4
+
+#define IOMUXC_CSI_DATA2_SELECT_INPUT_OFFSET 0x04F8
+#define IOMUXC_CSI_DATA3_SELECT_INPUT_OFFSET 0x04FC
+#define IOMUXC_CSI_DATA4_SELECT_INPUT_OFFSET 0x0500
+#define IOMUXC_CSI_DATA5_SELECT_INPUT_OFFSET 0x0504
+#define IOMUXC_CSI_DATA6_SELECT_INPUT_OFFSET 0x0508
+#define IOMUXC_CSI_DATA7_SELECT_INPUT_OFFSET 0x050C
+#define IOMUXC_CSI_DATA8_SELECT_INPUT_OFFSET 0x0510
+#define IOMUXC_CSI_DATA9_SELECT_INPUT_OFFSET 0x0514
+#define IOMUXC_CSI_HSYNC_SELECT_INPUT_OFFSET 0x0518
+#define IOMUXC_CSI_PIXCLK_SELECT_INPUT_OFFSET 0x051C
+#define IOMUXC_CSI_VSYNC_SELECT_INPUT_OFFSET 0x0520
+
+#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_OFFSET 0x0524
+#define IOMUXC_ECSPI1_MISO_SELECT_INPUT_OFFSET 0x0528
+#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_OFFSET 0x052C
+#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_OFFSET 0x0530
+#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_OFFSET 0x0534
+#define IOMUXC_ECSPI2_MISO_SELECT_INPUT_OFFSET 0x0538
+#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_OFFSET 0x053C
+#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_OFFSET 0x0540
+#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_OFFSET 0x0544
+#define IOMUXC_ECSPI3_MISO_SELECT_INPUT_OFFSET 0x0548
+#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_OFFSET 0x054C
+#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_OFFSET 0x0550
+#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_OFFSET 0x0554
+#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_OFFSET 0x0558
+#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_OFFSET 0x055C
+#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_OFFSET 0x0560
+
+#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_OFFSET 0x0564
+#define IOMUXC_ENET1_MDIO_SELECT_INPUT_OFFSET 0x0568
+#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_OFFSET 0x056C
+#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_OFFSET 0x0570
+#define IOMUXC_ENET2_MDIO_SELECT_INPUT_OFFSET 0x0574
+#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_OFFSET 0x0578
+
+#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_OFFSET 0x057C
+#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_OFFSET 0x0580
+
+#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_OFFSET 0x0584
+#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_OFFSET 0x0588
+#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_OFFSET 0x058C
+#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_OFFSET 0x0590
+#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_OFFSET 0x0594
+#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_OFFSET 0x0598
+#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_OFFSET 0x059C
+#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_OFFSET 0x05A0
+#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_OFFSET 0x05A4
+#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_OFFSET 0x05A8
+#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_OFFSET 0x05AC
+#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_OFFSET 0x05B0
+#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_OFFSET 0x05B4
+#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_OFFSET 0x05B8
+#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_OFFSET 0x05BC
+#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_OFFSET 0x05C0
+#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_OFFSET 0x05C4
+#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_OFFSET 0x05C8
+#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_OFFSET 0x05CC
+#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_OFFSET 0x05D0
+
+#define IOMUXC_I2C1_SCL_SELECT_INPUT_OFFSET 0x05D4
+#define IOMUXC_I2C1_SDA_SELECT_INPUT_OFFSET 0x05D8
+#define IOMUXC_I2C2_SCL_SELECT_INPUT_OFFSET 0x05DC
+#define IOMUXC_I2C2_SDA_SELECT_INPUT_OFFSET 0x05E0
+#define IOMUXC_I2C3_SCL_SELECT_INPUT_OFFSET 0x05E4
+#define IOMUXC_I2C3_SDA_SELECT_INPUT_OFFSET 0x05E8
+#define IOMUXC_I2C4_SCL_SELECT_INPUT_OFFSET 0x05EC
+#define IOMUXC_I2C4_SDA_SELECT_INPUT_OFFSET 0x05F0
+
+#define IOMUXC_KPP_COL0_SELECT_INPUT_OFFSET 0x05F4
+#define IOMUXC_KPP_COL1_SELECT_INPUT_OFFSET 0x05F8
+#define IOMUXC_KPP_COL2_SELECT_INPUT_OFFSET 0x05FC
+#define IOMUXC_KPP_COL3_SELECT_INPUT_OFFSET 0x0600
+#define IOMUXC_KPP_COL4_SELECT_INPUT_OFFSET 0x0604
+#define IOMUXC_KPP_COL5_SELECT_INPUT_OFFSET 0x0608
+#define IOMUXC_KPP_COL6_SELECT_INPUT_OFFSET 0x060C
+#define IOMUXC_KPP_COL7_SELECT_INPUT_OFFSET 0x0610
+#define IOMUXC_KPP_ROW0_SELECT_INPUT_OFFSET 0x0614
+#define IOMUXC_KPP_ROW1_SELECT_INPUT_OFFSET 0x0618
+#define IOMUXC_KPP_ROW2_SELECT_INPUT_OFFSET 0x061C
+#define IOMUXC_KPP_ROW3_SELECT_INPUT_OFFSET 0x0620
+#define IOMUXC_KPP_ROW4_SELECT_INPUT_OFFSET 0x0624
+#define IOMUXC_KPP_ROW5_SELECT_INPUT_OFFSET 0x0628
+#define IOMUXC_KPP_ROW6_SELECT_INPUT_OFFSET 0x062C
+#define IOMUXC_KPP_ROW7_SELECT_INPUT_OFFSET 0x0630
+
+#define IOMUXC_LCD_BUSY_SELECT_INPUT_OFFSET 0x0634
+#define IOMUXC_LCD_DATA00_SELECT_INPUT_OFFSET 0x0638
+#define IOMUXC_LCD_DATA01_SELECT_INPUT_OFFSET 0x063C
+#define IOMUXC_LCD_DATA02_SELECT_INPUT_OFFSET 0x0640
+#define IOMUXC_LCD_DATA03_SELECT_INPUT_OFFSET 0x0644
+#define IOMUXC_LCD_DATA04_SELECT_INPUT_OFFSET 0x0648
+#define IOMUXC_LCD_DATA05_SELECT_INPUT_OFFSET 0x064C
+#define IOMUXC_LCD_DATA06_SELECT_INPUT_OFFSET 0x0650
+#define IOMUXC_LCD_DATA07_SELECT_INPUT_OFFSET 0x0654
+#define IOMUXC_LCD_DATA08_SELECT_INPUT_OFFSET 0x0658
+#define IOMUXC_LCD_DATA09_SELECT_INPUT_OFFSET 0x065C
+#define IOMUXC_LCD_DATA10_SELECT_INPUT_OFFSET 0x0660
+#define IOMUXC_LCD_DATA11_SELECT_INPUT_OFFSET 0x0664
+#define IOMUXC_LCD_DATA12_SELECT_INPUT_OFFSET 0x0668
+#define IOMUXC_LCD_DATA13_SELECT_INPUT_OFFSET 0x066C
+#define IOMUXC_LCD_DATA14_SELECT_INPUT_OFFSET 0x0670
+#define IOMUXC_LCD_DATA15_SELECT_INPUT_OFFSET 0x0674
+#define IOMUXC_LCD_DATA16_SELECT_INPUT_OFFSET 0x0678
+#define IOMUXC_LCD_DATA17_SELECT_INPUT_OFFSET 0x067C
+#define IOMUXC_LCD_DATA18_SELECT_INPUT_OFFSET 0x0680
+#define IOMUXC_LCD_DATA19_SELECT_INPUT_OFFSET 0x0684
+#define IOMUXC_LCD_DATA20_SELECT_INPUT_OFFSET 0x0688
+#define IOMUXC_LCD_DATA21_SELECT_INPUT_OFFSET 0x068C
+#define IOMUXC_LCD_DATA22_SELECT_INPUT_OFFSET 0x0690
+#define IOMUXC_LCD_DATA23_SELECT_INPUT_OFFSET 0x0694
+#define IOMUXC_LCD_VSYNC_SELECT_INPUT_OFFSET 0x0698
+
+#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_OFFSET 0x069C
+#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_OFFSET 0x06A0
+#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_OFFSET 0x06A4
+#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_OFFSET 0x06A8
+#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_OFFSET 0x06AC
+#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_OFFSET 0x06B0
+#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_OFFSET 0x06B4
+#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_OFFSET 0x06B8
+#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_OFFSET 0x06BC
+#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_OFFSET 0x06C0
+#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_OFFSET 0x06C4
+#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_OFFSET 0x06C8
+#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_OFFSET 0x06CC
+#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_OFFSET 0x06D0
+#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_OFFSET 0x06D4
+#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_OFFSET 0x06D8
+#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_OFFSET 0x06DC
+
+#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_OFFSET 0x06E0
+#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06E4
+#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_OFFSET 0x06E8
+#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06EC
+
+#define IOMUXC_UART1_RTS_B_SELECT_INPUT_OFFSET 0x06F0
+#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_OFFSET 0x06F4
+#define IOMUXC_UART2_RTS_B_SELECT_INPUT_OFFSET 0x06F8
+#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_OFFSET 0x06FC
+#define IOMUXC_UART3_RTS_B_SELECT_INPUT_OFFSET 0x0700
+#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_OFFSET 0x0704
+#define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET 0x0708
+#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET 0x070C
+#define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET 0x0710
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET 0x0714
+#define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET 0x0718
+#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET 0x071C
+#define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET 0x0720
+#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_OFFSET 0x0724
+
+#define IOMUXC_USB_OTG2_OC_SELECT_INPUT_OFFSET 0x0728
+#define IOMUXC_USB_OTG1_OC_SELECT_INPUT_OFFSET 0x072C
+#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_OFFSET 0x0730
+#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_OFFSET 0x0734
+#define IOMUXC_SD3_CD_B_SELECT_INPUT_OFFSET 0x0738
+#define IOMUXC_SD3_WP_SELECT_INPUT_OFFSET 0x073C
+
+/* Pad mux/feature set routines */
+
+void imx_io_muxc_set_pad_alt_function(uint32_t pad_mux_offset, uint32_t alt_function);
+void imx_io_muxc_set_pad_features(uint32_t pad_feature_offset, uint32_t pad_features);
+
+#endif /* __IMX_IO_MUX_H__ */
diff --git a/plat/imx/common/include/imx_snvs.h b/plat/imx/common/include/imx_snvs.h
new file mode 100644
index 0000000..081ae8c
--- /dev/null
+++ b/plat/imx/common/include/imx_snvs.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __IMX_SNVS_H__
+#define __IMX_SNVS_H__
+
+#include <stdint.h>
+#include <arch.h>
+
+struct snvs {
+ uint32_t hplr;
+ uint32_t hpcomr;
+ uint32_t hpcr;
+ uint32_t hpsicr;
+ uint32_t hpsvcr;
+ uint32_t hpsr;
+ uint32_t hpsvsr;
+ uint32_t hphacivr;
+ uint32_t hphacr;
+ uint32_t hprtcmr;
+ uint32_t hprtclr;
+ uint32_t hptamr;
+ uint32_t hptalr;
+ uint32_t lplr;
+ uint32_t lpcr;
+ uint32_t lpmkcr;
+ uint32_t lpsvcr;
+ uint32_t lptgfcr;
+ uint32_t lptdcr;
+ uint32_t lpsr;
+ uint32_t lpsrtcmr;
+ uint32_t lpsrtclr;
+ uint32_t lptar;
+ uint32_t lpsmcmr;
+ uint32_t lpsmclr;
+ uint32_t lppgdr;
+ uint32_t lpgpr0_alias;
+ uint8_t lpzmkr[32];
+ uint16_t res0;
+ uint32_t lpgpr0[4];
+ uint32_t lptdc2r;
+ uint32_t lptdsr;
+ uint32_t lptgf1cr;
+ uint32_t lptgf2cr;
+ uint32_t res1[4];
+ uint32_t lpat1cr;
+ uint32_t lpat2cr;
+ uint32_t lpat3cr;
+ uint32_t lpat4cr;
+ uint32_t lpat5cr;
+ uint32_t res2[3];
+ uint32_t lpatctlr;
+ uint32_t lpatclkr;
+ uint32_t lpatrc1r;
+ uint32_t lpatrc2r;
+ uint32_t res3[706];
+ uint32_t hpvidr1;
+ uint32_t hpvidr2;
+} __packed;
+
+/* Define the HPCOMR bits */
+#define HPCOMR_NPSWA_EN BIT(31)
+#define HPCOMR_HAC_STOP BIT(19)
+#define HPCOMR_HAC_CLEAR BIT(18)
+#define HPCOMR_HAC_LOAD BIT(17)
+#define HPCOMR_HAC_EN BIT(16)
+#define HPCOMR_MKS_EN BIT(13)
+#define HPCOMR_PROG_ZMK BIT(12)
+#define HPCOMR_SW_LPSV BIT(10)
+#define HPCOMR_SW_FSV BIT(9)
+#define HPCOMR_SW_SV BIT(8)
+#define HPCOMR_LP_SWR_DIS BIT(5)
+#define HPCOMR_LP_SWR BIT(4)
+#define HPCOMR_SSM_SFNS_DIS BIT(2)
+#define HPCOMR_SSM_ST_DIS BIT(1)
+#define HPCOMR_SSM_ST BIT(0)
+
+void imx_snvs_init(void);
+
+#endif /* __IMX_SNVS_H__ */
diff --git a/plat/imx/common/include/imx_wdog.h b/plat/imx/common/include/imx_wdog.h
new file mode 100644
index 0000000..8033e62
--- /dev/null
+++ b/plat/imx/common/include/imx_wdog.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_WDOG_H__
+#define __IMX_WDOG_H__
+
+#include <arch.h>
+#include <stdint.h>
+
+struct wdog_regs {
+ uint16_t wcr;
+ uint16_t wsr;
+ uint16_t wrsr;
+ uint16_t wicr;
+ uint16_t wmcr;
+};
+
+/* WCR bits */
+#define WCR_WDZST BIT(0)
+#define WCR_WDBG BIT(1)
+#define WCR_WDE BIT(2)
+#define WCR_WDT BIT(3)
+#define WCR_SRS BIT(4)
+#define WCR_WDA BIT(5)
+#define WCR_SRE BIT(6)
+#define WCR_WDW BIT(7)
+#define WCR_WT(x) ((x) << 8)
+
+/* WSR bits */
+#define WSR_FIRST 0x5555
+#define WSR_SECOND 0xAAAA
+
+/* WRSR bits */
+#define WRSR_SFTW BIT(0)
+#define WRSR_TOUT BIT(1)
+#define WRSR_POR BIT(4)
+
+/* WICR bits */
+static inline int wicr_calc_wict(int sec, int half_sec)
+{
+ int wict_bits;
+
+ /* Represents WICR bits 7 - 0 */
+ wict_bits = ((sec << 1) | (half_sec ? 1 : 0));
+
+ return wict_bits;
+}
+
+#define WICR_WTIS BIT(14)
+#define WICR_WIE BIT(15)
+
+/* WMCR bits */
+#define WMCR_PDE BIT(0)
+
+/* External facing API */
+void imx_wdog_init(void);
+
+#endif /* __IMX_WDOG_H__ */
diff --git a/plat/imx/imx7/include/imx_hab_arch.h b/plat/imx/imx7/include/imx_hab_arch.h
new file mode 100644
index 0000000..338a027
--- /dev/null
+++ b/plat/imx/imx7/include/imx_hab_arch.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __IMX_HAB_ARCH_H__
+#define __IMX_HAB_ARCH_H__
+
+/* Define the offset the High Assurance Boot callback table is at */
+#define HAB_CALLBACK_OFFSET 0x100
+
+#endif /* __IMX_HAB_ARCH_H__ */
diff --git a/plat/imx/imx7/include/imx_regs.h b/plat/imx/imx7/include/imx_regs.h
new file mode 100644
index 0000000..aa345cf
--- /dev/null
+++ b/plat/imx/imx7/include/imx_regs.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_REGS_H__
+#define __IMX_REGS_H__
+
+/* Define the processor memory map */
+
+#define OCRAM_S_ALIAS_BASE 0x00000000 /* CM4 Alias Code */
+#define ROM_HIGH_BASE 0x00008000 /* ROM high 64k */
+#define ROM_HIGH_PROT_BASE 0x00017000 /* ROM high 64k protected */
+#define CAAM_BASE 0x00020000 /* CAAM block base address */
+#define OCRAM_S_BASE 0x00180000 /* OCRAM_S */
+#define ROM_LOW_BASE 0x007f8000 /* ROM low 64k */
+#define OCRAM_BASE 0x00900000 /* OCRAM base */
+#define CM4_ALIAS_CODE_BASE 0x04000000 /* CM4 alias code */
+#define TCM_BASE 0x1fff0000 /* TCM */
+#define BOOTROM_CP_BASE 0x20020000 /* Boot ROM (all 96KB) */
+#define CM4_ALIAS_SYSTEM_BASE 0x20100000 /* CM4 Alias system */
+#define EIM_BASE 0x28000000 /* EIM */
+
+/* BootROM absolute base address */
+#define BOOTROM_BASE 0x00000000 /* BootROM */
+
+/* Peripherals like GPIO live in the AIPS range */
+#define AIPS1_BASE 0x30000000 /* AIPS1 */
+#define AIPS2_BASE 0x30400000 /* AIPS2 */
+#define AIPS3_BASE 0x30800000 /* AIPS3 */
+#define AIPS4_BASE 0x30c00000 /* AIPS4 */
+
+/* ARM peripherals like GIC */
+#define ARM_PERIPHERAL_GIC_BASE 0x31000000 /* GIC */
+
+/* Configuration ports */
+#define GPV0_BASE 0x32000000 /* Main config port */
+#define GPV1_BASE 0x32100000 /* Wakeup config port */
+#define GPV2_BASE 0x32200000 /* Per_s config port */
+#define GPV3_BASE 0x32300000 /* Per_m config port */
+#define GPV4_BASE 0x32400000 /* Enet config port */
+#define GPV5_BASE 0x32500000 /* Display config port */
+#define GPV6_BASE 0x32600000 /* M4 conig port */
+
+/* MMAP peripherals - like APBH DMA */
+#define APBH_DMA_BASE 0x33000000 /* APBH DMA block */
+
+/* QSPI RX BUFFERS */
+#define QSPI_RX_BUFFER_BASE 0x34000000 /* QSPI RX buffers */
+
+/* QSPI1 FLASH */
+#define QSPI_FLASH_BASE 0x60000000 /* QSPI1 flash */
+
+/* AIPS1 block addresses */
+#define AIPSTZ_CONFIG_OFFSET 0x001f0000
+#define CCM_BASE (AIPS1_BASE + 0x380000)
+
+/* Define the maximum number of UART blocks on this SoC */
+#define MXC_UART1_BASE (AIPS3_BASE + 0x060000)
+#define MXC_UART2_BASE (AIPS3_BASE + 0x070000)
+#define MXC_UART3_BASE (AIPS3_BASE + 0x080000)
+#define MXC_UART4_BASE (AIPS3_BASE + 0x260000)
+#define MXC_UART5_BASE (AIPS3_BASE + 0x270000)
+#define MXC_UART6_BASE (AIPS3_BASE + 0x280000)
+#define MXC_UART7_BASE (AIPS3_BASE + 0x290000)
+#define MXC_MAX_UART_NUM 0x07
+
+/* Define the maximum number of USDHCI blocks on this SoC */
+#define MXC_MAX_USDHC_NUM 3
+
+/* Define the number of CSU registers for this SoC */
+#define MXC_MAX_CSU_REGS 0x40
+#define CSU_BASE (AIPS1_BASE + 0x3E0000)
+
+/* IO Mux block base */
+#define MXC_IO_MUXC_BASE (AIPS1_BASE + 0x330000)
+
+/* SNVS base */
+#define SNVS_BASE (AIPS1_BASE + 0x370000)
+
+/* GP Timer base */
+#define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000)
+
+/* MMC base */
+#define USDHC1_BASE (AIPS1_BASE + 0xb40000)
+#define USDHC2_BASE (AIPS1_BASE + 0xb50000)
+#define USDHC3_BASE (AIPS1_BASE + 0xb60000)
+
+/* Arm optional memory mapped counter module base address */
+#define SYS_CNTCTL_BASE (AIPS2_BASE + 0x2c0000)
+
+/* Define CAAM AIPS offset */
+#define CAAM_AIPS_BASE (AIPS3_BASE + 0x100000)
+#define CAAM_NUM_JOB_RINGS 0x03
+#define CAAM_NUM_RTIC 0x04
+#define CAAM_NUM_DECO 0x01
+
+/* Define watchdog base addresses */
+#define WDOG1_BASE (AIPS1_BASE + 0x280000)
+#define WDOG2_BASE (AIPS1_BASE + 0x290000)
+#define WDOG3_BASE (AIPS1_BASE + 0x2A0000)
+#define WDOG4_BASE (AIPS1_BASE + 0x280000)
+
+/* Define the maximum number of WDOG blocks on this SoC */
+#define MXC_MAX_WDOG_NUM 0x04
+
+#endif /* __IMX_REGS_H__ */
diff --git a/plat/imx/imx7/warp7/aarch32/warp7_helpers.S b/plat/imx/imx7/warp7/aarch32/warp7_helpers.S
new file mode 100644
index 0000000..b1921cc
--- /dev/null
+++ b/plat/imx/imx7/warp7/aarch32/warp7_helpers.S
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+#include <platform_def.h>
+#include <imx_hab.h>
+
+ .globl platform_mem_init
+ .globl plat_get_my_entrypoint
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+ .globl plat_panic_handler
+
+ /* ---------------------------------------------
+ * int plat_mem_init(void)
+ * Function to initialize memory.
+ * The HAB hands off the DDR controller already
+ * setup and ready to use.
+ * Implement the mandatory function as a NOP
+ * ---------------------------------------------
+ */
+func platform_mem_init
+ bx lr
+endfunc platform_mem_init
+
+func plat_get_my_entrypoint
+ mov r0, #0
+ bx lr
+endfunc plat_get_my_entrypoint
+
+func plat_crash_console_init
+ mov_imm r0, PLAT_WARP7_BOOT_UART_BASE
+ mov_imm r1, PLAT_WARP7_BOOT_UART_CLK_IN_HZ
+ mov_imm r2, PLAT_WARP7_CONSOLE_BAUDRATE
+ b imx_crash_uart_init
+endfunc plat_crash_console_init
+
+func plat_crash_console_putc
+ mov_imm r1, PLAT_WARP7_BOOT_UART_BASE
+ b imx_crash_uart_putc
+endfunc plat_crash_console_putc
+
+func plat_panic_handler
+ mov r3, #HAB_ROM_VECTOR_TABLE_FAILSAFE
+ ldr r3, [r3, #0]
+ blx r3
+endfunc plat_panic_handler
diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h
new file mode 100644
index 0000000..27429c7
--- /dev/null
+++ b/plat/imx/imx7/warp7/include/platform_def.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <arch.h>
+#include <common_def.h>
+#include <tbbr_img_def.h>
+
+#define PLATFORM_STACK_SIZE 0x1000
+
+#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
+#define PLATFORM_CLUSTER_COUNT 1
+#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
+#define PLATFORM_CLUSTER1_CORE_COUNT 0
+
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
+ PLATFORM_CLUSTER1_CORE_COUNT)
+
+#define WARP7_PRIMARY_CPU 0
+
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
+
+#define PLAT_MAX_RET_STATE 1
+#define PLAT_MAX_OFF_STATE 2
+
+/* Local power state for power domains in Run state. */
+#define PLAT_LOCAL_STATE_RUN 0
+
+/* Local power state for retention. Valid only for CPU power domains */
+#define PLAT_LOCAL_STATE_RET 1
+
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains.
+ */
+#define PLAT_LOCAL_STATE_OFF 2
+
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ * i.MX7 has a 32 byte cacheline size
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 pg 244
+ */
+#define CACHE_WRITEBACK_SHIFT 4
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+/*
+ * Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
+ */
+#define BOOT_ROM_BASE 0x00000000
+#define BOOT_ROM_SIZE 0x00020000
+
+#define OCRAM_S_BASE 0x00180000
+#define OCRAM_S_SIZE 0x00008000
+
+/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
+#define DRAM_BASE 0x80000000
+#define DRAM_SIZE 0x20000000
+#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
+
+/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
+#define WARP7_OPTEE_SIZE 0x02000000
+#define WARP7_OPTEE_BASE (DRAM_LIMIT - WARP7_OPTEE_SIZE)
+#define WARP7_OPTEE_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
+
+/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
+#define BL2_RAM_SIZE 0x00100000
+#define BL2_RAM_BASE (WARP7_OPTEE_BASE - BL2_RAM_SIZE)
+#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
+#define SHARED_RAM_SIZE 0x00001000
+#define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE)
+#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE)
+
+/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
+#define WARP7_UBOOT_SIZE 0x00100000
+#define WARP7_UBOOT_BASE (DRAM_BASE + 0x7800000)
+#define WARP7_UBOOT_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
+
+/* Define FIP image absolute location 0x80000000 - 0x80100000 */
+#define WARP7_FIP_SIZE 0x00100000
+#define WARP7_FIP_BASE (DRAM_BASE)
+#define WARP7_FIP_LIMIT (WARP7_FIP_BASE + WARP7_FIP_SIZE)
+
+/* Define FIP image location at 1MB offset */
+#define WARP7_FIP_MMC_BASE (1024 * 1024)
+
+/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
+#define WARP7_DTB_SIZE 0x00100000
+#define WARP7_DTB_BASE (DRAM_BASE + 0x03000000)
+#define WARP7_DTB_LIMIT (WARP7_DTB_BASE + WARP7_DTB_SIZE)
+
+/*
+ * BL2 specific defines.
+ *
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
+#define BL2_BASE BL2_RAM_BASE
+#define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/*
+ * BL3-2/OPTEE
+ */
+# define BL32_BASE WARP7_OPTEE_BASE
+# define BL32_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
+
+/*
+ * BL3-3/U-BOOT
+ */
+#define BL33_BASE WARP7_UBOOT_BASE
+#define BL33_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
+
+/*
+ * ATF's view of memory
+ *
+ * 0xa0000000 +-----------------+
+ * | DDR | BL32/OPTEE
+ * 0x9e000000 +-----------------+
+ * | DDR | BL23 ATF
+ * 0x9df00000 +-----------------+
+ * | DDR | Shared MBOX RAM
+ * 0x9de00000 +-----------------+
+ * | DDR | Unallocated
+ * 0x87900000 +-----------------+
+ * | DDR | BL33/U-BOOT
+ * 0x87800000 +-----------------+
+ * | DDR | Unallocated
+ * 0x83100000 +-----------------+
+ * | DDR | DTB
+ * 0x83000000 +-----------------+
+ * | DDR | Unallocated
+ * 0x80100000 +-----------------+
+ * | DDR | FIP
+ * 0x80000000 +-----------------+
+ * | SOC I/0 |
+ * 0x00a00000 +-----------------+
+ * | OCRAM | Not used
+ * 0x00900000 +-----------------+
+ * | SOC I/0 |
+ * 0x00188000 +-----------------+
+ * | OCRAM_S | Not used
+ * 0x00180000 +-----------------+
+ * | SOC I/0 |
+ * 0x00020000 +-----------------+
+ * | BootROM | BL1
+ * 0x00000000 +-----------------+
+ */
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define MAX_MMAP_REGIONS 10
+#define MAX_XLAT_TABLES 6
+#define MAX_IO_DEVICES 2
+#define MAX_IO_HANDLES 3
+#define MAX_IO_BLOCK_DEVICES 1
+
+/* UART defines */
+#if PLAT_WARP7_UART == 1
+#define PLAT_WARP7_UART_BASE MXC_UART1_BASE
+#elif PLAT_WARP7_UART == 6
+#define IMX_UART_DTE
+#define PLAT_WARP7_UART_BASE MXC_UART6_BASE
+#else
+#error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6"
+#endif
+
+#define PLAT_WARP7_BOOT_UART_BASE PLAT_WARP7_UART_BASE
+#define PLAT_WARP7_BOOT_UART_CLK_IN_HZ 24000000
+#define PLAT_WARP7_CONSOLE_BAUDRATE 115200
+
+/* MMC defines */
+#ifndef PLAT_WARP7_SD
+#define PLAT_WARP7_SD 3
+#endif
+
+#if PLAT_WARP7_SD == 1
+#define PLAT_WARP7_BOOT_MMC_BASE USDHC1_BASE
+#endif /* PLAT_WARP7_SD == 1 */
+
+#if PLAT_WARP7_SD == 2
+#define PLAT_WARP7_BOOT_MMC_BASE USDHC2_BASE
+#endif /* PLAT_WARP7_SD == 2 */
+
+#if PLAT_WARP7_SD == 3
+#define PLAT_WARP7_BOOT_MMC_BASE USDHC3_BASE
+#endif /* PLAT_WARP7_SD == 3 */
+
+/*
+ * GIC related constants
+ */
+#define GICD_BASE 0x31001000
+#define GICC_BASE 0x31002000
+#define GICR_BASE 0
+
+/*
+ * System counter
+ */
+#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/imx/imx7/warp7/platform.mk b/plat/imx/imx7/warp7/platform.mk
new file mode 100644
index 0000000..279b5d2
--- /dev/null
+++ b/plat/imx/imx7/warp7/platform.mk
@@ -0,0 +1,105 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Architecture
+$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
+
+# Tune compiler for Cortex-A7
+ifeq ($(notdir $(CC)),armclang)
+ TF_CFLAGS += -mfpu=neon
+ ASFLAGS += -mfpu=neon
+else ifneq ($(findstring clang,$(notdir $(CC))),)
+ TF_CFLAGS += -mfpu=neon
+ ASFLAGS += -mfpu=neon
+else
+ TF_CFLAGS += -mfpu=neon
+ ASFLAGS += -mfpu=neon
+endif
+
+# Platform
+PLAT_INCLUDES := -Idrivers/imx/uart \
+ -Iinclude/common/tbbr \
+ -Iinclude/plat/arm/common/ \
+ -Iplat/imx/common/include/ \
+ -Iplat/imx/imx7/warp7/include \
+ -Idrivers/imx/timer \
+ -Idrivers/imx/usdhc \
+ -Iplat/imx/imx7/include
+
+# Translation tables library
+include lib/xlat_tables_v2/xlat_tables.mk
+
+BL2_SOURCES += common/desc_image_load.c \
+ drivers/console/aarch32/console.S \
+ drivers/delay_timer/delay_timer.c \
+ drivers/mmc/mmc.c \
+ drivers/io/io_block.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ drivers/imx/timer/imx_gpt.c \
+ drivers/imx/uart/imx_uart.c \
+ drivers/imx/uart/imx_crash_uart.S \
+ drivers/imx/usdhc/imx_usdhc.c \
+ lib/aarch32/arm32_aeabi_divmod.c \
+ lib/aarch32/arm32_aeabi_divmod_a32.S \
+ lib/cpus/aarch32/cortex_a7.S \
+ lib/optee/optee_utils.c \
+ plat/imx/common/imx_aips.c \
+ plat/imx/common/imx_caam.c \
+ plat/imx/common/imx_clock.c \
+ plat/imx/common/imx_csu.c \
+ plat/imx/common/imx_io_mux.c \
+ plat/imx/common/imx_snvs.c \
+ plat/imx/common/imx_wdog.c \
+ plat/imx/common/imx7_clock.c \
+ plat/imx/imx7/warp7/aarch32/warp7_helpers.S \
+ plat/imx/imx7/warp7/warp7_bl2_el3_setup.c \
+ plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c \
+ plat/imx/imx7/warp7/warp7_io_storage.c \
+ plat/imx/imx7/warp7/warp7_image_load.c \
+ ${XLAT_TABLES_LIB_SRCS}
+
+# Build config flags
+# ------------------
+
+WORKAROUND_CVE_2017_5715 := 0
+
+# Disable the PSCI platform compatibility layer by default
+ENABLE_PLAT_COMPAT := 0
+
+# Enable reset to BL31 by default
+RESET_TO_BL31 := 0
+
+# Non-TF Boot ROM
+BL2_AT_EL3 := 1
+
+# Indicate single-core
+COLD_BOOT_SINGLE_CPU := 1
+
+# Have different sections for code and rodata
+SEPARATE_CODE_AND_RODATA := 1
+
+# Use Coherent memory
+USE_COHERENT_MEM := 1
+
+# Enable new version of image loading required for AArch32
+LOAD_IMAGE_V2 := 1
+
+# PLAT_WARP7_UART
+PLAT_WARP7_UART :=1
+$(eval $(call add_define,PLAT_WARP7_UART))
+
+# Verify build config
+# -------------------
+
+ifneq (${LOAD_IMAGE_V2}, 1)
+ $(error Error: warp7 needs LOAD_IMAGE_V2=1)
+endif
+
+ifeq (${ARCH},aarch64)
+ $(error Error: AArch64 not supported on i.mx7)
+endif
diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
new file mode 100644
index 0000000..14f86a1
--- /dev/null
+++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <assert.h>
+#include <bl_common.h>
+#include <console.h>
+#include <debug.h>
+#include <desc_image_load.h>
+#include <mmc.h>
+#include <mmio.h>
+#include <optee_utils.h>
+#include <platform_def.h>
+#include <utils.h>
+#include <xlat_mmu_helpers.h>
+#include <xlat_tables_defs.h>
+#include <imx_aips.h>
+#include <imx_caam.h>
+#include <imx_clock.h>
+#include <imx_csu.h>
+#include <imx_gpt.h>
+#include <imx_io_mux.h>
+#include <imx_uart.h>
+#include <imx_snvs.h>
+#include <imx_usdhc.h>
+#include <imx_wdog.h>
+#include "warp7_private.h"
+
+#define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M)
+
+#define UART6_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M)
+
+#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
+ CCM_TARGET_POST_PODF(2))
+
+#define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
+
+#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
+
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+ return WARP7_UBOOT_BASE;
+}
+
+static uint32_t warp7_get_spsr_for_bl32_entry(void)
+{
+ return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
+ DISABLE_ALL_EXCEPTIONS);
+}
+
+static uint32_t warp7_get_spsr_for_bl33_entry(void)
+{
+ return SPSR_MODE32(MODE32_svc,
+ plat_get_ns_image_entrypoint() & 0x1,
+ SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+}
+
+#ifndef AARCH32_SP_OPTEE
+#error "Must build with OPTEE support included"
+#endif
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+ int err = 0;
+ bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+ bl_mem_params_node_t *hw_cfg_mem_params = NULL;
+
+ bl_mem_params_node_t *pager_mem_params = NULL;
+ bl_mem_params_node_t *paged_mem_params = NULL;
+
+ assert(bl_mem_params);
+
+ switch (image_id) {
+ case BL32_IMAGE_ID:
+ pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ assert(pager_mem_params);
+
+ paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+ assert(paged_mem_params);
+
+ err = parse_optee_header(&bl_mem_params->ep_info,
+ &pager_mem_params->image_info,
+ &paged_mem_params->image_info);
+ if (err != 0)
+ WARN("OPTEE header parse error.\n");
+
+ /*
+ * When ATF loads the DTB the address of the DTB is passed in
+ * arg2, if an hw config image is present use the base address
+ * as DTB address an pass it as arg2
+ */
+ hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
+
+ bl_mem_params->ep_info.args.arg0 =
+ bl_mem_params->ep_info.args.arg1;
+ bl_mem_params->ep_info.args.arg1 = 0;
+ if (hw_cfg_mem_params)
+ bl_mem_params->ep_info.args.arg2 =
+ hw_cfg_mem_params->image_info.image_base;
+ else
+ bl_mem_params->ep_info.args.arg2 = 0;
+ bl_mem_params->ep_info.args.arg3 = 0;
+ bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry();
+ break;
+
+ case BL33_IMAGE_ID:
+ /* AArch32 only core: OP-TEE expects NSec EP in register LR */
+ pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
+ assert(pager_mem_params);
+ pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
+
+ /* BL33 expects to receive the primary CPU MPID (through r0) */
+ bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
+ bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry();
+ break;
+
+ default:
+ /* Do nothing in default case */
+ break;
+ }
+
+ return err;
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+ /* Setup the MMU here */
+}
+
+#define WARP7_UART1_TX_MUX \
+ IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA
+
+#define WARP7_UART1_TX_FEATURES \
+ (IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU | \
+ IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN | \
+ IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN | \
+ IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4)
+
+#define WARP7_UART1_RX_MUX \
+ IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA
+
+#define WARP7_UART1_RX_FEATURES \
+ (IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU | \
+ IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN | \
+ IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN | \
+ IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4)
+
+#define WARP7_UART6_TX_MUX \
+ IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA
+
+#define WARP7_UART6_TX_FEATURES \
+ (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU | \
+ IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN | \
+ IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN | \
+ IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4)
+
+#define WARP7_UART6_RX_MUX \
+ IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA
+
+#define WARP7_UART6_RX_FEATURES \
+ (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU | \
+ IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN | \
+ IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \
+ IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4)
+
+static void warp7_setup_pinmux(void)
+{
+ /* Configure UART1 TX */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET,
+ WARP7_UART1_TX_MUX);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET,
+ WARP7_UART1_TX_FEATURES);
+
+ /* Configure UART1 RX */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET,
+ WARP7_UART1_RX_MUX);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET,
+ WARP7_UART1_RX_FEATURES);
+
+ /* Configure UART6 TX */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET,
+ WARP7_UART6_TX_MUX);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET,
+ WARP7_UART6_TX_FEATURES);
+
+ /* Configure UART6 RX */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET,
+ WARP7_UART6_RX_MUX);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET,
+ WARP7_UART6_RX_FEATURES);
+}
+
+static void warp7_usdhc_setup(void)
+{
+ imx_usdhc_params_t params;
+ struct mmc_device_info info;
+
+ zeromem(¶ms, sizeof(imx_usdhc_params_t));
+ params.reg_base = PLAT_WARP7_BOOT_MMC_BASE;
+ params.clk_rate = 25000000;
+ params.bus_width = MMC_BUS_WIDTH_8;
+ info.mmc_dev_type = MMC_IS_EMMC;
+ imx_usdhc_init(¶ms, &info);
+}
+
+static void warp7_setup_system_counter(void)
+{
+ unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
+
+ /* Set the frequency table index to our target frequency */
+ write_cntfrq(freq);
+
+ /* Enable system counter @ frequency table index 0, halt on debug */
+ mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
+ CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
+}
+
+static void warp7_setup_wdog_clocks(void)
+{
+ uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT;
+
+ imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
+ imx_clock_enable_wdog(0);
+ imx_clock_enable_wdog(1);
+ imx_clock_enable_wdog(2);
+ imx_clock_enable_wdog(3);
+}
+
+static void warp7_setup_usb_clocks(void)
+{
+ uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
+
+ imx_clock_set_usb_clk_root_bits(usb_en_bits);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
+}
+/*
+ * bl2_early_platform_setup()
+ * MMU off
+ */
+void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+ u_register_t arg3, u_register_t arg4)
+{
+ uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT;
+ uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT;
+ uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1;
+
+ /* Initialize the AIPS */
+ imx_aips_init();
+ imx_csu_init();
+ imx_snvs_init();
+ imx_gpt_ops_init(GPT1_BASE_ADDR);
+
+ /* Initialize clocks, regulators, pin-muxes etc */
+ imx_clock_init();
+ imx_clock_enable_uart(0, uart1_en_bits);
+ imx_clock_enable_uart(5, uart6_en_bits);
+ imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
+ warp7_setup_system_counter();
+ warp7_setup_wdog_clocks();
+ warp7_setup_usb_clocks();
+
+ /* Setup pin-muxes */
+ warp7_setup_pinmux();
+
+ /* Init UART, storage and friends */
+ console_init(PLAT_WARP7_BOOT_UART_BASE, PLAT_WARP7_BOOT_UART_CLK_IN_HZ,
+ PLAT_WARP7_CONSOLE_BAUDRATE);
+ warp7_usdhc_setup();
+
+ /* Open handles to persistent storage */
+ plat_warp7_io_setup();
+
+ /* Setup higher-level functionality CAAM, RTC etc */
+ imx_caam_init();
+ imx_wdog_init();
+
+ /* Print out the expected memory map */
+ VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT);
+ VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
+ VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
+ VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT);
+ VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT);
+ VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT);
+}
+
+/*
+ * bl2_platform_setup()
+ * MMU on - enabled by bl2_el3_plat_arch_setup()
+ */
+void bl2_platform_setup(void)
+{
+}
diff --git a/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c b/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c
new file mode 100644
index 0000000..12254d4
--- /dev/null
+++ b/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl_common.h>
+#include <desc_image_load.h>
+#include <platform.h>
+#include <platform_def.h>
+
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ {
+ .image_id = BL32_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL32_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, 0),
+
+ .image_info.image_base = WARP7_OPTEE_BASE,
+ .image_info.image_max_size = WARP7_OPTEE_SIZE,
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+ {
+ .image_id = HW_CONFIG_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = WARP7_DTB_BASE,
+ .image_info.image_max_size = WARP7_DTB_SIZE,
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+ {
+ .image_id = BL32_EXTRA1_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+ .image_info.image_base = WARP7_OPTEE_BASE,
+ .image_info.image_max_size = WARP7_OPTEE_SIZE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+ {
+ /* This is a zero sized image so we don't set base or size */
+ .image_id = BL32_EXTRA2_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t,
+ NON_SECURE | EXECUTABLE),
+ # ifdef PRELOADED_BL33_BASE
+ .ep_info.pc = PRELOADED_BL33_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+ # else
+ .ep_info.pc = BL33_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = WARP7_UBOOT_BASE,
+ .image_info.image_max_size = WARP7_UBOOT_SIZE,
+ # endif /* PRELOADED_BL33_BASE */
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ }
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);
diff --git a/plat/imx/imx7/warp7/warp7_image_load.c b/plat/imx/imx7/warp7/warp7_image_load.c
new file mode 100644
index 0000000..1e3a2b0
--- /dev/null
+++ b/plat/imx/imx7/warp7/warp7_image_load.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl_common.h>
+#include <desc_image_load.h>
+#include <platform.h>
+
+void plat_flush_next_bl_params(void)
+{
+ flush_bl_params_desc();
+}
+
+bl_load_info_t *plat_get_bl_image_load_info(void)
+{
+ return get_bl_load_info_from_mem_params_desc();
+}
+
+bl_params_t *plat_get_next_bl_params(void)
+{
+ return get_next_bl_params_from_mem_params_desc();
+}
diff --git a/plat/imx/imx7/warp7/warp7_io_storage.c b/plat/imx/imx7/warp7/warp7_io_storage.c
new file mode 100644
index 0000000..8354766
--- /dev/null
+++ b/plat/imx/imx7/warp7/warp7_io_storage.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <assert.h>
+#include <debug.h>
+#include <mmc.h>
+#include <firmware_image_package.h>
+#include <io_block.h>
+#include <io_driver.h>
+#include <io_fip.h>
+#include <io_memmap.h>
+#include <platform_def.h>
+
+static const io_dev_connector_t *fip_dev_con;
+static uintptr_t fip_dev_handle;
+
+#ifndef WARP7_FIP_MMAP
+static const io_dev_connector_t *mmc_dev_con;
+static uintptr_t mmc_dev_handle;
+
+static const io_block_spec_t mmc_fip_spec = {
+ .offset = WARP7_FIP_MMC_BASE,
+ .length = WARP7_FIP_SIZE
+};
+
+static const io_block_dev_spec_t mmc_dev_spec = {
+ /* It's used as temp buffer in block driver. */
+ .buffer = {
+ .offset = WARP7_FIP_BASE,
+ /* do we need a new value? */
+ .length = WARP7_FIP_SIZE
+ },
+ .ops = {
+ .read = mmc_read_blocks,
+ .write = mmc_write_blocks,
+ },
+ .block_size = MMC_BLOCK_SIZE,
+};
+
+static int open_mmc(const uintptr_t spec);
+
+#else
+static const io_dev_connector_t *memmap_dev_con;
+static uintptr_t memmap_dev_handle;
+
+static const io_block_spec_t fip_block_spec = {
+ .offset = WARP7_FIP_BASE,
+ .length = WARP7_FIP_SIZE
+};
+static int open_memmap(const uintptr_t spec);
+#endif
+static int open_fip(const uintptr_t spec);
+
+static const io_uuid_spec_t bl32_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32,
+};
+
+static const io_uuid_spec_t hw_config_uuid_spec = {
+ .uuid = UUID_HW_CONFIG,
+};
+
+static const io_uuid_spec_t bl32_extra1_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
+};
+
+static const io_uuid_spec_t bl32_extra2_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
+};
+
+static const io_uuid_spec_t bl33_uuid_spec = {
+ .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
+};
+
+/* TODO: this structure is replicated multiple times. rationalize it ! */
+struct plat_io_policy {
+ uintptr_t *dev_handle;
+ uintptr_t image_spec;
+ int (*check)(const uintptr_t spec);
+};
+
+static const struct plat_io_policy policies[] = {
+#ifndef WARP7_FIP_MMAP
+ [FIP_IMAGE_ID] = {
+ &mmc_dev_handle,
+ (uintptr_t)&mmc_fip_spec,
+ open_mmc
+ },
+#else
+ [FIP_IMAGE_ID] = {
+ &memmap_dev_handle,
+ (uintptr_t)&fip_block_spec,
+ open_memmap
+ },
+#endif
+ [BL32_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_uuid_spec,
+ open_fip
+ },
+ [BL32_EXTRA1_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_extra1_uuid_spec,
+ open_fip
+ },
+ [BL32_EXTRA2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_extra2_uuid_spec,
+ open_fip
+ },
+ [HW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&hw_config_uuid_spec,
+ open_fip
+ },
+ [BL33_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl33_uuid_spec,
+ open_fip
+ }
+};
+
+static int open_fip(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_image_handle;
+
+ /* See if a Firmware Image Package is available */
+ result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
+ if (result == 0) {
+ result = io_open(fip_dev_handle, spec, &local_image_handle);
+ if (result == 0) {
+ VERBOSE("Using FIP\n");
+ io_close(local_image_handle);
+ }
+ }
+ return result;
+}
+
+#ifndef WARP7_FIP_MMAP
+static int open_mmc(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_handle;
+
+ result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
+ if (result == 0) {
+ result = io_open(mmc_dev_handle, spec, &local_handle);
+ if (result == 0)
+ io_close(local_handle);
+ }
+ return result;
+}
+#else
+static int open_memmap(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_image_handle;
+
+ result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
+ if (result == 0) {
+ result = io_open(memmap_dev_handle, spec, &local_image_handle);
+ if (result == 0) {
+ VERBOSE("Using Memmap\n");
+ io_close(local_image_handle);
+ }
+ }
+ return result;
+}
+#endif
+
+int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
+ uintptr_t *image_spec)
+{
+ int result;
+ const struct plat_io_policy *policy;
+
+ assert(image_id < ARRAY_SIZE(policies));
+
+ policy = &policies[image_id];
+ result = policy->check(policy->image_spec);
+ assert(result == 0);
+
+ *image_spec = policy->image_spec;
+ *dev_handle = *policy->dev_handle;
+
+ return result;
+}
+
+void plat_warp7_io_setup(void)
+{
+ int result __unused;
+
+#ifndef WARP7_FIP_MMAP
+ result = register_io_dev_block(&mmc_dev_con);
+ assert(result == 0);
+
+ result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
+ &mmc_dev_handle);
+ assert(result == 0);
+
+#else
+ result = register_io_dev_memmap(&memmap_dev_con);
+ assert(result == 0);
+
+ result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
+ &memmap_dev_handle);
+ assert(result == 0);
+
+#endif
+ result = register_io_dev_fip(&fip_dev_con);
+ assert(result == 0);
+
+ result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
+ &fip_dev_handle);
+ assert(result == 0);
+}
diff --git a/plat/imx/imx7/warp7/warp7_private.h b/plat/imx/imx7/warp7/warp7_private.h
new file mode 100644
index 0000000..c93acac
--- /dev/null
+++ b/plat/imx/imx7/warp7/warp7_private.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __WARP7_PRIVATE_H__
+#define __WARP7_PRIVATE_H__
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_warp7_io_setup(void);
+
+#endif /*__WARP7_PRIVATE_H__ */
diff --git a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c
index 9171986..d126f55 100644
--- a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c
+++ b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c
@@ -5,7 +5,7 @@
* https://spdx.org/licenses
*/
-#include <a8k_common.h>
+#include <armada_common.h>
/*
* If bootrom is currently at BLE there's no need to include the memory
@@ -76,6 +76,8 @@
{0x00000000f7000000, 0x1000000, PEX1_TID},
/* PEX2_X1 window */
{0x00000000f8000000, 0x1000000, PEX2_TID},
+ {0x00000000c0000000, 0x30000000, PEX2_TID},
+ {0x0000000800000000, 0x100000000, PEX2_TID},
/* PEX0_X4 window */
{0x00000000f6000000, 0x1000000, PEX0_TID},
/* SPI1_CS0 (RUNIT) window */
@@ -101,6 +103,8 @@
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
#else
{0x00000000f2000000, 0xe000000, IO_0_TID},
+ {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
+ {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
#endif
};
diff --git a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c
index ec4124c..f8a1c40 100644
--- a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c
+++ b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c
@@ -5,7 +5,7 @@
* https://spdx.org/licenses
*/
-#include <a8k_common.h>
+#include <armada_common.h>
/*
* If bootrom is currently at BLE there's no need to include the memory
diff --git a/plat/marvell/a8k/a80x0/board/dram_port.c b/plat/marvell/a8k/a80x0/board/dram_port.c
index c720c11..a99bf7c 100644
--- a/plat/marvell/a8k/a80x0/board/dram_port.c
+++ b/plat/marvell/a8k/a80x0/board/dram_port.c
@@ -6,8 +6,8 @@
*/
#include <arch_helpers.h>
-#include <a8k_i2c.h>
#include <debug.h>
+#include <mentor/mi2cv.h>
#include <mmio.h>
#include <mv_ddr_if.h>
#include <mvebu_def.h>
diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
index 43beffa..7901dd2 100644
--- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
+++ b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
@@ -5,7 +5,8 @@
* https://spdx.org/licenses
*/
-#include <a8k_common.h>
+#include <armada_common.h>
+
/*
* If bootrom is currently at BLE there's no need to include the memory
* maps structure at this point
@@ -85,7 +86,9 @@
/* PEX2_X1 window */
{0x00000000f8000000, 0x1000000, PEX2_TID},
/* PEX0_X4 window */
- {0x00000000f6000000, 0x1000000, PEX0_TID}
+ {0x00000000f6000000, 0x1000000, PEX0_TID},
+ {0x00000000c0000000, 0x30000000, PEX0_TID},
+ {0x0000000800000000, 0x100000000, PEX0_TID},
};
struct addr_map_win iob_memory_map_cp1[] = {
@@ -129,6 +132,8 @@
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
#else
{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
+ {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
+ {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
#endif
};
diff --git a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c
index b455b83..fa222ee 100644
--- a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c
+++ b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c
@@ -6,8 +6,8 @@
*/
#include <arch_helpers.h>
-#include <a8k_i2c.h>
#include <debug.h>
+#include <mentor/mi2cv.h>
#include <mmio.h>
#include <mv_ddr_if.h>
#include <mvebu_def.h>
diff --git a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c
index 079bd8f..384d0f5 100644
--- a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c
+++ b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c
@@ -5,9 +5,10 @@
* https://spdx.org/licenses
*/
-#include <a8k_common.h>
+#include <armada_common.h>
#include <delay_timer.h>
#include <mmio.h>
+
/*
* If bootrom is currently at BLE there's no need to include the memory
* maps structure at this point
diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk
index 3bcce96..5956737 100644
--- a/plat/marvell/a8k/common/a8k_common.mk
+++ b/plat/marvell/a8k/common/a8k_common.mk
@@ -76,7 +76,8 @@
$(MARVELL_DRV_BASE)/amb_adec.c \
$(MARVELL_DRV_BASE)/ccu.c \
$(MARVELL_DRV_BASE)/cache_llc.c \
- $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c
+ $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
+ $(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c
BL31_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c
diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h
index f7bd23f..06d4fa9 100644
--- a/plat/marvell/a8k/common/include/platform_def.h
+++ b/plat/marvell/a8k/common/include/platform_def.h
@@ -134,6 +134,8 @@
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(MARVELL_IRQ_PIC0, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL)
#define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \
@@ -199,4 +201,6 @@
#define BL32_BASE TRUSTED_DRAM_BASE
+#define MVEBU_PMU_IRQ_WA
+
#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/a8k/common/mss/mss_bl2_setup.c
index 2154185..973c56d 100644
--- a/plat/marvell/a8k/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/a8k/common/mss/mss_bl2_setup.c
@@ -5,7 +5,7 @@
* https://spdx.org/licenses
*/
-#include <a8k_common.h>
+#include <armada_common.h>
#include <bl_common.h>
#include <ccu.h>
#include <cp110_setup.h>
diff --git a/plat/marvell/a8k/common/plat_bl31_setup.c b/plat/marvell/a8k/common/plat_bl31_setup.c
index 6c85fcc..6dfbcbb 100644
--- a/plat/marvell/a8k/common/plat_bl31_setup.c
+++ b/plat/marvell/a8k/common/plat_bl31_setup.c
@@ -5,12 +5,13 @@
* https://spdx.org/licenses
*/
-#include <a8k_common.h>
+#include <armada_common.h>
#include <ap_setup.h>
#include <cp110_setup.h>
#include <debug.h>
#include <marvell_plat_priv.h>
#include <marvell_pm.h>
+#include <mc_trustzone/mc_trustzone.h>
#include <mmio.h>
#include <mci.h>
#include <plat_marvell.h>
@@ -75,6 +76,24 @@
return pm_fw_running;
}
+/* For TrusTzone we treat the "target" field of addr_map_win
+ * struct as attribute
+ */
+static const struct addr_map_win tz_map[] = {
+ {PLAT_MARVELL_ATF_BASE, 0x200000, TZ_PERM_ABORT}
+};
+
+/* Configure MC TrustZone regions */
+static void marvell_bl31_security_setup(void)
+{
+ int tz_nr, win_id;
+
+ tz_nr = ARRAY_SIZE(tz_map);
+
+ for (win_id = 0; win_id < tz_nr; win_id++)
+ tz_enable_win(MVEBU_AP0, tz_map, win_id);
+}
+
/* This function overruns the same function in marvell_bl31_setup.c */
void bl31_plat_arch_setup(void)
{
@@ -116,4 +135,6 @@
/* Configure GPIO */
marvell_gpio_config();
+
+ marvell_bl31_security_setup();
}
diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c
index 0cd62cb..7438f69 100644
--- a/plat/marvell/a8k/common/plat_ble_setup.c
+++ b/plat/marvell/a8k/common/plat_ble_setup.c
@@ -5,8 +5,8 @@
* https://spdx.org/licenses
*/
-#include <a8k_common.h>
#include <ap_setup.h>
+#include <armada_common.h>
#include <aro.h>
#include <ccu.h>
#include <cp110_setup.h>
@@ -43,11 +43,22 @@
#define AVS_EN_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x130)
#define AVS_ENABLE_OFFSET (0)
#define AVS_SOFT_RESET_OFFSET (2)
-#define AVS_LOW_VDD_LIMIT_OFFSET (4)
-#define AVS_HIGH_VDD_LIMIT_OFFSET (12)
#define AVS_TARGET_DELTA_OFFSET (21)
-#define AVS_VDD_LOW_LIMIT_MASK (0xFF << AVS_LOW_VDD_LIMIT_OFFSET)
-#define AVS_VDD_HIGH_LIMIT_MASK (0xFF << AVS_HIGH_VDD_LIMIT_OFFSET)
+
+#ifndef MVEBU_SOC_AP807
+ /* AP806 SVC bits */
+ #define AVS_LOW_VDD_LIMIT_OFFSET (4)
+ #define AVS_HIGH_VDD_LIMIT_OFFSET (12)
+ #define AVS_VDD_LOW_LIMIT_MASK (0xFF << AVS_LOW_VDD_LIMIT_OFFSET)
+ #define AVS_VDD_HIGH_LIMIT_MASK (0xFF << AVS_HIGH_VDD_LIMIT_OFFSET)
+#else
+ /* AP807 SVC bits */
+ #define AVS_LOW_VDD_LIMIT_OFFSET (3)
+ #define AVS_HIGH_VDD_LIMIT_OFFSET (13)
+ #define AVS_VDD_LOW_LIMIT_MASK (0x3FF << AVS_LOW_VDD_LIMIT_OFFSET)
+ #define AVS_VDD_HIGH_LIMIT_MASK (0x3FF << AVS_HIGH_VDD_LIMIT_OFFSET)
+#endif
+
/* VDD limit is 0.9V for A70x0 @ CPU frequency < 1600MHz */
#define AVS_A7K_LOW_CLK_VALUE ((0x80 << AVS_TARGET_DELTA_OFFSET) | \
(0x1A << AVS_HIGH_VDD_LIMIT_OFFSET) | \
@@ -84,11 +95,6 @@
#define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET)
/*
- * - AVS work points in the LD0 eFuse:
- * SVC1 work point: LD0[88:81]
- * SVC2 work point: LD0[96:89]
- * SVC3 work point: LD0[104:97]
- * SVC4 work point: LD0[112:105]
* - Identification information in the LD-0 eFuse:
* DRO: LD0[74:65] - Not used by the SW
* Revision: LD0[78:75] - Not used by the SW
@@ -114,11 +120,30 @@
#define EFUSE_AP_LD0_SWREV_OFFS 50 /* LD0[115:113] */
#define EFUSE_AP_LD0_SWREV_MASK 0x7
+#ifndef MVEBU_SOC_AP807
+ /* AP806 AVS work points in the LD0 eFuse
+ * SVC1 work point: LD0[88:81]
+ * SVC2 work point: LD0[96:89]
+ * SVC3 work point: LD0[104:97]
+ * SVC4 work point: LD0[112:105]
+ */
+ #define EFUSE_AP_LD0_SVC1_OFFS 18 /* LD0[88:81] */
+ #define EFUSE_AP_LD0_SVC2_OFFS 26 /* LD0[96:89] */
+ #define EFUSE_AP_LD0_SVC3_OFFS 34 /* LD0[104:97] */
+ #define EFUSE_AP_LD0_WP_MASK 0xFF
+#else
+ /* AP807 AVS work points in the LD0 eFuse
+ * SVC1 work point: LD0[91:81]
+ * SVC2 work point: LD0[102:92]
+ * SVC3 work point: LD0[113:103]
+ */
+ #define EFUSE_AP_LD0_SVC1_OFFS 17 /* LD0[91:81] */
+ #define EFUSE_AP_LD0_SVC2_OFFS 28 /* LD0[102:92] */
+ #define EFUSE_AP_LD0_SVC3_OFFS 39 /* LD0[113:103] */
+ #define EFUSE_AP_LD0_WP_MASK 0x3FF
+#endif
+
-#define EFUSE_AP_LD0_SVC1_OFFS 18 /* LD0[88:81] */
-#define EFUSE_AP_LD0_SVC2_OFFS 26 /* LD0[96:89] */
-#define EFUSE_AP_LD0_SVC3_OFFS 34 /* LD0[104:97] */
#define EFUSE_AP_LD0_SVC4_OFFS 42 /* LD0[112:105] */
-#define EFUSE_AP_LD0_WP_MASK 0xFF
#define EFUSE_AP_LD0_CLUSTER_DOWN_OFFS 4
@@ -233,16 +258,8 @@
uint32_t reg_val, avs_workpoint, freq_pidi_mode;
uint64_t efuse;
uint32_t device_id, single_cluster;
- uint8_t svc[4], perr[4], i, sw_ver;
-
- /* Due to a bug in A3900 device_id skip SVC config
- * TODO: add SVC config once it is decided for a3900
- */
- if (ble_get_ap_type() == CHIP_ID_AP807) {
- NOTICE("SVC: SVC is not supported on AP807\n");
- ble_plat_avs_config();
- return;
- }
+ uint16_t svc[4], perr[4], i, sw_ver;
+ unsigned int ap_type;
/* Set access to LD0 */
reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
@@ -276,9 +293,19 @@
svc[0] = (efuse >> EFUSE_AP_LD0_SVC1_OFFS) & EFUSE_AP_LD0_WP_MASK;
svc[1] = (efuse >> EFUSE_AP_LD0_SVC2_OFFS) & EFUSE_AP_LD0_WP_MASK;
svc[2] = (efuse >> EFUSE_AP_LD0_SVC3_OFFS) & EFUSE_AP_LD0_WP_MASK;
- svc[3] = (efuse >> EFUSE_AP_LD0_SVC4_OFFS) & EFUSE_AP_LD0_WP_MASK;
- INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n",
- svc[0], svc[1], svc[2], svc[3]);
+
+ /* Fetch AP type to distinguish between AP806 and AP807 */
+ ap_type = ble_get_ap_type();
+
+ if (ap_type != CHIP_ID_AP807) {
+ svc[3] = (efuse >> EFUSE_AP_LD0_SVC4_OFFS)
+ & EFUSE_AP_LD0_WP_MASK;
+ INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n",
+ svc[0], svc[1], svc[2], svc[3]);
+ } else {
+ INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x\n",
+ svc[0], svc[1], svc[2]);
+ }
/* Validate parity of SVC workpoint values */
for (i = 0; i < 4; i++) {
@@ -385,6 +412,26 @@
avs_workpoint = 0;
break;
}
+ } else if (device_id == MVEBU_3900_DEV_ID) {
+ NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
+ "3900", freq_pidi_mode);
+ switch (freq_pidi_mode) {
+ case CPU_1600_DDR_1200_RCLK_1200:
+ if (perr[0])
+ goto perror;
+ avs_workpoint = svc[0];
+ break;
+ case CPU_1300_DDR_800_RCLK_800:
+ if (perr[1])
+ goto perror;
+ avs_workpoint = svc[1];
+ break;
+ default:
+ if (perr[0])
+ goto perror;
+ avs_workpoint = svc[0];
+ break;
+ }
} else {
ERROR("SVC: Unsupported Device ID 0x%x\n", device_id);
return;
@@ -397,7 +444,8 @@
}
/* Remove parity bit */
- avs_workpoint &= 0x7F;
+ if (ap_type != CHIP_ID_AP807)
+ avs_workpoint &= 0x7F;
reg_val = mmio_read_32(AVS_EN_CTRL_REG);
NOTICE("SVC: AVS work point changed from 0x%x to 0x%x\n",
diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c
index c716ee0..0c74b2f 100644
--- a/plat/marvell/a8k/common/plat_pm.c
+++ b/plat/marvell/a8k/common/plat_pm.c
@@ -5,7 +5,7 @@
* https://spdx.org/licenses
*/
-#include <a8k_common.h>
+#include <armada_common.h>
#include <assert.h>
#include <bakery_lock.h>
#include <debug.h>
@@ -379,8 +379,10 @@
*/
static void a8k_cpu_standby(plat_local_state_t cpu_state)
{
- ERROR("%s: needs to be implemented\n", __func__);
- panic();
+ if (!is_pm_fw_running()) {
+ ERROR("%s: needs to be implemented\n", __func__);
+ panic();
+ }
}
/*****************************************************************************
diff --git a/plat/marvell/common/marvell_gicv2.c b/plat/marvell/common/marvell_gicv2.c
index ba8e409..19e1ec0 100644
--- a/plat/marvell/common/marvell_gicv2.c
+++ b/plat/marvell/common/marvell_gicv2.c
@@ -5,7 +5,11 @@
* https://spdx.org/licenses
*/
+#include <bakery_lock.h>
+#include <debug.h>
#include <gicv2.h>
+#include <interrupt_mgmt.h>
+#include <mmio.h>
#include <plat_marvell.h>
#include <platform.h>
#include <platform_def.h>
@@ -17,6 +21,21 @@
#pragma weak plat_marvell_gic_driver_init
#pragma weak plat_marvell_gic_init
+#define A7K8K_PIC_CAUSE_REG 0xf03f0100
+#define A7K8K_PIC0_MASK_REG 0xf03f0108
+
+#define A7K8K_PIC_PMUOF_IRQ_MASK (1 << 17)
+
+#define A7K8K_PIC_MAX_IRQS 32
+#define A7K8K_PIC_MAX_IRQ_MASK ((1UL << A7K8K_PIC_MAX_IRQS) - 1)
+
+#define A7K8K_ODMIN_SET_REG 0xf0300040
+#define A7K8K_ODMI_PMU_IRQ(idx) ((2 + idx) << 12)
+
+#define A7K8K_ODMI_PMU_GIC_IRQ(idx) (130 + idx)
+
+static DEFINE_BAKERY_LOCK(a7k8k_irq_lock);
+
/*
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
@@ -50,6 +69,74 @@
gicv2_driver_init(&marvell_gic_data);
}
+static uint64_t a7k8k_pmu_interrupt_handler(uint32_t id,
+ uint32_t flags,
+ void *handle,
+ void *cookie)
+{
+ unsigned int idx = plat_my_core_pos();
+ uint32_t irq;
+
+ bakery_lock_get(&a7k8k_irq_lock);
+
+ /* Acknowledge IRQ */
+ irq = plat_ic_acknowledge_interrupt();
+
+ plat_ic_end_of_interrupt(irq);
+
+ if (irq != MARVELL_IRQ_PIC0) {
+ bakery_lock_release(&a7k8k_irq_lock);
+ return 0;
+ }
+
+ /* Acknowledge PMU overflow IRQ in PIC0 */
+ mmio_setbits_32(A7K8K_PIC_CAUSE_REG, A7K8K_PIC_PMUOF_IRQ_MASK);
+
+ /* Trigger ODMI Frame IRQ */
+ mmio_write_32(A7K8K_ODMIN_SET_REG, A7K8K_ODMI_PMU_IRQ(idx));
+
+ bakery_lock_release(&a7k8k_irq_lock);
+
+ return 0;
+}
+
+void mvebu_pmu_interrupt_enable(void)
+{
+ unsigned int idx;
+ uint32_t flags;
+ int32_t rc;
+
+ /* Reset PIC */
+ mmio_write_32(A7K8K_PIC_CAUSE_REG, A7K8K_PIC_MAX_IRQ_MASK);
+ /* Unmask PMU overflow IRQ in PIC0 */
+ mmio_clrbits_32(A7K8K_PIC0_MASK_REG, A7K8K_PIC_PMUOF_IRQ_MASK);
+
+ /* Configure ODMI Frame IRQs as edge triggered */
+ for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++)
+ gicv2_interrupt_set_cfg(A7K8K_ODMI_PMU_GIC_IRQ(idx),
+ GIC_INTR_CFG_EDGE);
+
+ /*
+ * Register IRQ handler as INTR_TYPE_S_EL1 as its the only valid type
+ * for GICv2 in ARM-TF.
+ */
+ flags = 0U;
+ set_interrupt_rm_flag((flags), (NON_SECURE));
+ rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
+ a7k8k_pmu_interrupt_handler,
+ flags);
+ if (rc != 0)
+ panic();
+}
+
+void mvebu_pmu_interrupt_disable(void)
+{
+ /* Reset PIC */
+ mmio_write_32(A7K8K_PIC_CAUSE_REG, A7K8K_PIC_MAX_IRQ_MASK);
+ /* Mask PMU overflow IRQ in PIC0 */
+ mmio_setbits_32(A7K8K_PIC0_MASK_REG, A7K8K_PIC_PMUOF_IRQ_MASK);
+}
+
void plat_marvell_gic_init(void)
{
gicv2_distif_init();
diff --git a/plat/marvell/common/mrvl_sip_svc.c b/plat/marvell/common/mrvl_sip_svc.c
index ec293af..a0ca50d 100644
--- a/plat/marvell/common/mrvl_sip_svc.c
+++ b/plat/marvell/common/mrvl_sip_svc.c
@@ -9,6 +9,7 @@
#include <cache_llc.h>
#include <debug.h>
#include <marvell_plat_priv.h>
+#include <plat_marvell.h>
#include <runtime_svc.h>
#include <smcc.h>
#include "comphy/phy-comphy-cp110.h"
@@ -30,6 +31,8 @@
/* Miscellaneous FID's' */
#define MV_SIP_DRAM_SIZE 0x82000010
#define MV_SIP_LLC_ENABLE 0x82000011
+#define MV_SIP_PMU_IRQ_ENABLE 0x82000012
+#define MV_SIP_PMU_IRQ_DISABLE 0x82000013
#define MAX_LANE_NR 6
#define MVEBU_COMPHY_OFFSET 0x441000
@@ -109,6 +112,14 @@
llc_runtime_enable(i);
SMC_RET1(handle, 0);
+#ifdef MVEBU_PMU_IRQ_WA
+ case MV_SIP_PMU_IRQ_ENABLE:
+ mvebu_pmu_interrupt_enable();
+ SMC_RET1(handle, 0);
+ case MV_SIP_PMU_IRQ_DISABLE:
+ mvebu_pmu_interrupt_disable();
+ SMC_RET1(handle, 0);
+#endif
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
diff --git a/plat/marvell/marvell.mk b/plat/marvell/marvell.mk
index 217ad46..2a2da3b 100644
--- a/plat/marvell/marvell.mk
+++ b/plat/marvell/marvell.mk
@@ -48,6 +48,7 @@
${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${DOIMAGEPATH} clean
${DOIMAGETOOL}: mrvl_clean
+ @$(DOIMAGE_LIBS_CHECK)
${Q}${MAKE} --no-print-directory -C ${DOIMAGEPATH} WTMI_IMG=$(WTMI_IMG)
diff --git a/plat/marvell/version.mk b/plat/marvell/version.mk
index 017e119..16b0a16 100644
--- a/plat/marvell/version.mk
+++ b/plat/marvell/version.mk
@@ -1 +1 @@
-SUBVERSION = devel-18.08.0
+SUBVERSION = devel-18.09.1
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index 1d46eec..2ecbec7 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -27,6 +27,9 @@
# Enable new version of image loading on QEMU platforms
LOAD_IMAGE_V2 := 1
+ifneq ($(LOAD_IMAGE_V2),1)
+$(error Error: qemu needs LOAD_IMAGE_V2=1)
+endif
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
@@ -132,12 +135,11 @@
plat/qemu/qemu_io_storage.c \
plat/qemu/${ARCH}/plat_helpers.S \
plat/qemu/qemu_bl2_setup.c \
- plat/qemu/dt.c
-ifeq (${LOAD_IMAGE_V2},1)
-BL2_SOURCES += plat/qemu/qemu_bl2_mem_params_desc.c \
+ plat/qemu/dt.c \
+ plat/qemu/qemu_bl2_mem_params_desc.c \
plat/qemu/qemu_image_load.c \
common/desc_image_load.c
-endif
+
ifeq ($(add-lib-optee),yes)
BL2_SOURCES += lib/optee/optee_utils.c
endif
diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c
index 556aae5..4a5d74a 100644
--- a/plat/qemu/qemu_bl1_setup.c
+++ b/plat/qemu/qemu_bl1_setup.c
@@ -31,14 +31,6 @@
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL_RAM_BASE;
bl1_tzram_layout.total_size = BL_RAM_SIZE;
-
-#if !LOAD_IMAGE_V2
- /* Calculate how much RAM BL1 is using and how much remains free */
- bl1_tzram_layout.free_base = BL_RAM_BASE;
- bl1_tzram_layout.free_size = BL_RAM_SIZE;
- reserve_mem(&bl1_tzram_layout.free_base, &bl1_tzram_layout.free_size,
- BL1_RAM_BASE, BL1_RAM_LIMIT - BL1_RAM_BASE);
-#endif /* !LOAD_IMAGE_V2 */
}
/******************************************************************************
@@ -65,46 +57,3 @@
{
plat_qemu_io_setup();
}
-
-#if !LOAD_IMAGE_V2
-/*******************************************************************************
- * Function that takes a memory layout into which BL2 has been loaded and
- * populates a new memory layout for BL2 that ensures that BL1's data sections
- * resident in secure RAM are not visible to BL2.
- ******************************************************************************/
-void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
- meminfo_t *bl2_mem_layout)
-{
- const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
-
- assert(bl1_mem_layout != NULL);
- assert(bl2_mem_layout != NULL);
-
- /* Check that BL1's memory is lying outside of the free memory */
- assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
- (BL1_RAM_BASE >= (bl1_mem_layout->free_base +
- bl1_mem_layout->free_size)));
-
- /* Remove BL1 RW data from the scope of memory visible to BL2 */
- *bl2_mem_layout = *bl1_mem_layout;
- reserve_mem(&bl2_mem_layout->total_base,
- &bl2_mem_layout->total_size,
- BL1_RAM_BASE,
- bl1_size);
-
- flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
-}
-
-/*******************************************************************************
- * Before calling this function BL2 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL2 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
- entry_point_info_t *bl2_ep)
-{
- SET_SECURITY_STATE(bl2_ep->h.attr, SECURE);
- bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
-}
-#endif /* !LOAD_IMAGE_V2 */
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index 997c85d..b9a30d8 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -117,10 +117,11 @@
}
#endif /* !LOAD_IMAGE_V2 */
-
-
-void bl2_early_platform_setup(meminfo_t *mem_layout)
+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
+ meminfo_t *mem_layout = (void *)arg1;
+
/* Initialize the console to provide early debug support */
qemu_console_init();
diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c
index 1e8b2ec..8b4312c 100644
--- a/plat/qemu/qemu_bl31_setup.c
+++ b/plat/qemu/qemu_bl31_setup.c
@@ -9,6 +9,7 @@
#include <gic_common.h>
#include <gicv2.h>
#include <platform_def.h>
+#include <platform.h>
#include "qemu_private.h"
/*
@@ -35,22 +36,16 @@
* tables. BL2 has flushed this information to memory, so we are guaranteed
* to pick up good data.
******************************************************************************/
-#if LOAD_IMAGE_V2
-void bl31_early_platform_setup(void *from_bl2,
- void *plat_params_from_bl2)
-#else
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
-#endif
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
/* Initialize the console to provide early debug support */
qemu_console_init();
-#if LOAD_IMAGE_V2
/*
* Check params passed from BL2
*/
- bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+ bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
assert(params_from_bl2);
assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
@@ -74,32 +69,6 @@
if (!bl33_image_ep_info.pc)
panic();
-
-#else /* LOAD_IMAGE_V2 */
-
- /*
- * Check params passed from BL2 should not be NULL,
- */
- assert(from_bl2 != NULL);
- assert(from_bl2->h.type == PARAM_BL31);
- assert(from_bl2->h.version >= VERSION_1);
- /*
- * In debug builds, we pass a special value in 'plat_params_from_bl2'
- * to verify platform parameters from BL2 to BL3-1.
- * In release builds, it's not used.
- */
- assert(((unsigned long long)plat_params_from_bl2) ==
- QEMU_BL31_PLAT_PARAM_VAL);
-
- /*
- * Copy BL3-2 (if populated by BL2) and BL3-3 entry point information.
- * They are stored in Secure RAM, in BL2's address space.
- */
- if (from_bl2->bl32_ep_info)
- bl32_image_ep_info = *from_bl2->bl32_ep_info;
- bl33_image_ep_info = *from_bl2->bl33_ep_info;
-
-#endif /* !LOAD_IMAGE_V2 */
}
void bl31_plat_arch_setup(void)
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index 4c501f5..e75ebac 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -76,10 +76,19 @@
void k3_pwr_domain_off(const psci_power_state_t *target_state)
{
+ int core_id, device, ret;
+
/* Prevent interrupts from spuriously waking up this cpu */
k3_gic_cpuif_disable();
- /* TODO: Indicate to System firmware about powering down */
+ core_id = plat_my_core_pos();
+ device = PLAT_PROC_DEVICE_START_ID + core_id;
+
+ ret = ti_sci_device_put(device);
+ if (ret) {
+ ERROR("Request to stop core failed: %d\n", ret);
+ return;
+ }
}
void k3_pwr_domain_on_finish(const psci_power_state_t *target_state)
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index c361270..2f4228f 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -44,19 +44,10 @@
{
unsigned int ver = zynqmp_get_silicon_ver();
- switch (ver) {
- case ZYNQMP_CSU_VERSION_VELOCE:
- return 48000;
- case ZYNQMP_CSU_VERSION_EP108:
- return 25000000;
- case ZYNQMP_CSU_VERSION_QEMU:
+ if (ver == ZYNQMP_CSU_VERSION_QEMU)
return 133000000;
- default:
- /* Do nothing in default case */
- break;
- }
-
- return 100000000;
+ else
+ return 100000000;
}
#if LOG_LEVEL >= LOG_LEVEL_NOTICE
@@ -298,12 +289,6 @@
char *label = "Unknown";
switch (ver) {
- case ZYNQMP_CSU_VERSION_VELOCE:
- label = "VELOCE";
- break;
- case ZYNQMP_CSU_VERSION_EP108:
- label = "EP108";
- break;
case ZYNQMP_CSU_VERSION_QEMU:
label = "QEMU";
break;
@@ -346,17 +331,8 @@
{
unsigned int ver = zynqmp_get_silicon_ver();
- switch (ver) {
- case ZYNQMP_CSU_VERSION_VELOCE:
- return 10000;
- case ZYNQMP_CSU_VERSION_EP108:
- return 4000000;
- case ZYNQMP_CSU_VERSION_QEMU:
+ if (ver == ZYNQMP_CSU_VERSION_QEMU)
return 50000000;
- default:
- /* Do nothing in default case */
- break;
- }
-
- return mmio_read_32(IOU_SCNTRS_BASEFREQ);
+ else
+ return mmio_read_32(IOU_SCNTRS_BASEFREQ);
}
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 3ac9db9..f806d46 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -17,6 +17,10 @@
WORKAROUND_CVE_2017_5715 := 0
+ARM_XLAT_TABLES_LIB_V1 := 1
+$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
+$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
+
ifdef ZYNQMP_ATF_MEM_BASE
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index a41eebb..b175b78 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -25,7 +25,6 @@
#define CLK_TOPOLOGY_NODE_OFFSET U(16)
#define CLK_TOPOLOGY_PAYLOAD_LEN U(12)
#define CLK_PARENTS_PAYLOAD_LEN U(12)
-#define CLK_INIT_ENABLE_SHIFT U(1)
#define CLK_TYPE_SHIFT U(2)
#define CLK_CLKFLAGS_SHIFT U(8)
#define CLK_TYPEFLAGS_SHIFT U(24)
@@ -337,7 +336,8 @@
.width = PERIPH_GATE_WIDTH,
.clkflags = CLK_SET_RATE_PARENT |
CLK_IGNORE_UNUSED |
- CLK_IS_BASIC,
+ CLK_IS_BASIC |
+ CLK_IS_CRITICAL,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -496,7 +496,7 @@
.type = TYPE_DIV1,
.offset = 8,
.width = 6,
- .clkflags = CLK_IS_BASIC,
+ .clkflags = CLK_IS_BASIC | CLK_IS_CRITICAL,
.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
.mult = NA_MULT,
.div = NA_DIV,
@@ -2022,12 +2022,11 @@
},
[CLK_WDT] = {
.name = "wdt",
- .control_reg = IOU_SLCR_WDT_CLK_SEL,
+ .control_reg = FPD_SLCR_WDT_CLK_SEL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_TOPSW_LSBUS,
EXT_CLK_SWDT0 | CLK_EXTERNAL_PARENT,
- EXT_CLK_SWDT1 | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &wdt_nodes,
@@ -2243,12 +2242,6 @@
/* Array of clock which are invalid for this variant */
static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB};
-/* Array of clocks which needs to be enabled at init */
-static uint32_t pm_clk_init_enable_list[] = {
- CLK_ACPU,
- CLK_DDR_REF,
-};
-
/**
* pm_clock_valid - Check if clock is valid or not
* @clock_id Id of the clock to be queried
@@ -2273,37 +2266,32 @@
}
/**
- * pm_clock_init_enable - Check if clock needs to be enabled at init
+ * pm_clock_type - Get clock's type
* @clock_id Id of the clock to be queried
*
- * This function is used to check if given clock needs to be enabled
- * at boot up or not. Some clocks needs to be enabled at init.
+ * This function is used to check type of clock (OUTPUT/EXTERNAL).
*
- * Return: Returns 1 if clock needs to be enabled at boot up else 0.
+ * Return: Returns type of clock (OUTPUT/EXTERNAL).
*/
-static unsigned int pm_clock_init_enable(unsigned int clock_id)
+static unsigned int pm_clock_type(unsigned int clock_id)
{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(pm_clk_init_enable_list); i++)
- if (pm_clk_init_enable_list[i] == clock_id)
- return 1;
-
- return 0;
+ return (clock_id < CLK_MAX_OUTPUT_CLK) ?
+ CLK_TYPE_OUTPUT : CLK_TYPE_EXTERNAL;
}
/**
- * pm_clock_type - Get clock's type
- * @clock_id Id of the clock to be queried
+ * pm_api_clock_get_num_clocks() - PM call to request number of clocks
+ * @nclocks Number of clocks
*
- * This function is used to check type of clock (OUTPUT/EXTERNAL).
+ * This function is used by master to get number of clocks.
*
- * Return: Returns type of clock (OUTPUT/EXTERNAL).
+ * @return Returns success.
*/
-static unsigned int pm_clock_type(unsigned int clock_id)
+enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks)
{
- return (clock_id < CLK_MAX_OUTPUT_CLK) ?
- CLK_TYPE_OUTPUT : CLK_TYPE_EXTERNAL;
+ *nclocks = CLK_MAX;
+
+ return PM_RET_SUCCESS;
}
/**
@@ -2494,9 +2482,6 @@
/* Clock valid bit */
*attr = pm_clock_valid(clock_id);
- /* If clock needs to be enabled during init */
- *attr |= (pm_clock_init_enable(clock_id) << CLK_INIT_ENABLE_SHIFT);
-
/* Clock type (Output/External) */
*attr |= (pm_clock_type(clock_id) << CLK_TYPE_SHIFT);
@@ -2642,10 +2627,11 @@
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT)
return PM_RET_ERROR_NOTSUPPORTED;
- if (ISPLL(clock_id))
- ret = pm_api_pll_bypass_and_reset(clock_id,
- CLK_PLL_RESET_PULSE);
- else
+ /*
+ * PLL type clock should not enable explicitly.
+ * It is done by FSBL on boot-up and by PMUFW whenever required.
+ */
+ if (!ISPLL(clock_id))
ret = pm_api_clk_enable_disable(clock_id, 1);
return ret;
@@ -2671,10 +2657,11 @@
if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT)
return PM_RET_ERROR_NOTSUPPORTED;
- if (ISPLL(clock_id))
- ret = pm_api_pll_bypass_and_reset(clock_id,
- CLK_PLL_RESET_ASSERT);
- else
+ /*
+ * PLL type clock should not be disabled explicitly.
+ * It is done by PMUFW if required.
+ */
+ if (!ISPLL(clock_id))
ret = pm_api_clk_enable_disable(clock_id, 0);
return ret;
@@ -2822,8 +2809,13 @@
unsigned int divider)
{
unsigned int reg = clocks[clock_id].control_reg;
+ enum pm_ret_status ret;
- return pm_mmio_write(reg, PLL_FBDIV_MASK, divider << PLL_FBDIV_SHIFT);
+ pm_api_pll_bypass_and_reset(clock_id, CLK_PLL_RESET_ASSERT);
+ ret = pm_mmio_write(reg, PLL_FBDIV_MASK, divider << PLL_FBDIV_SHIFT);
+ pm_api_pll_bypass_and_reset(clock_id, CLK_PLL_RESET_RELEASE);
+
+ return ret;
}
/**
@@ -2973,7 +2965,7 @@
/**
* pm_api_clock_setparent - Set the clock parent for given id
* @clock_id Id of the clock
- * @parent_id parent id
+ * @parent_idx parent index
*
* This function is used by master to set parent for any clock.
*
@@ -3024,7 +3016,7 @@
/**
* pm_api_clock_getparent - Get the clock parent for given id
* @clock_id Id of the clock
- * @parent_id parent id
+ * @parent_idx parent index
*
* This function is used by master to get parent index
* for any clock.
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
index 56f850a..386f275 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
@@ -276,6 +276,7 @@
enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
+enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks);
enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
unsigned int index,
uint32_t *topology);
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index cdbb515..32c7357 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -453,6 +453,48 @@
}
/**
+ * pm_ioctl_afi() - Ioctl function for writing afi values
+ *
+ * @index AFI register index
+ * @value Register value to be written
+ *
+ *
+ * @return Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_afi(unsigned int index,
+ unsigned int value)
+{
+ unsigned int mask;
+ unsigned int regarr[] = {0xFD360000,
+ 0xFD360014,
+ 0xFD370000,
+ 0xFD370014,
+ 0xFD380000,
+ 0xFD380014,
+ 0xFD390000,
+ 0xFD390014,
+ 0xFD3a0000,
+ 0xFD3a0014,
+ 0xFD3b0000,
+ 0xFD3b0014,
+ 0xFF9b0000,
+ 0xFF9b0014,
+ 0xFD615000,
+ 0xFF419000,
+ };
+
+ if (index >= ARRAY_SIZE(regarr))
+ return PM_RET_ERROR_ARGS;
+
+ if (index < AFIFM6_WRCTRL)
+ mask = FABRIC_WIDTH;
+ else
+ mask = 0xf00;
+
+ return pm_mmio_write(regarr[index], mask, value);
+}
+
+/**
* pm_ioctl_read_pggs() - Ioctl function for reading persistent
* global general storage (pggs)
* @index PGGS register index
@@ -472,6 +514,54 @@
}
/**
+ * pm_ioctl_ulpi_reset() - Ioctl function for performing ULPI reset
+ *
+ * This function peerforms the ULPI reset sequence for resetting
+ * the ULPI transceiver.
+ *
+ * @return Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_ulpi_reset(void)
+{
+ enum pm_ret_status ret;
+
+ ret = pm_mmio_write(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOT_PIN_MASK,
+ ZYNQMP_ULPI_RESET_VAL_HIGH);
+ if (ret != PM_RET_SUCCESS)
+ return ret;
+
+ /* Drive ULPI assert for atleast 1ms */
+ mdelay(1);
+
+ ret = pm_mmio_write(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOT_PIN_MASK,
+ ZYNQMP_ULPI_RESET_VAL_LOW);
+ if (ret != PM_RET_SUCCESS)
+ return ret;
+
+ /* Drive ULPI de-assert for atleast 1ms */
+ mdelay(1);
+
+ ret = pm_mmio_write(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOT_PIN_MASK,
+ ZYNQMP_ULPI_RESET_VAL_HIGH);
+
+ return ret;
+}
+
+/**
+ * pm_ioctl_set_boot_health_status() - Ioctl for setting healthy boot status
+ *
+ * This function sets healthy bit value to indicate boot health status
+ * to firmware.
+ *
+ * @return Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_set_boot_health_status(unsigned int value)
+{
+ return pm_mmio_write(PM_BOOT_HEALTH_STATUS_REG,
+ PM_BOOT_HEALTH_STATUS_MASK, value);
+}
+
+/**
* pm_api_ioctl() - PM IOCTL API for device control and configs
* @node_id Node ID of the device
* @ioctl_id ID of the requested IOCTL
@@ -540,6 +630,15 @@
case IOCTL_READ_PGGS:
ret = pm_ioctl_read_pggs(arg1, value);
break;
+ case IOCTL_ULPI_RESET:
+ ret = pm_ioctl_ulpi_reset();
+ break;
+ case IOCTL_SET_BOOT_HEALTH_STATUS:
+ ret = pm_ioctl_set_boot_health_status(arg1);
+ break;
+ case IOCTL_AFI:
+ ret = pm_ioctl_afi(arg1, arg2);
+ break;
default:
ret = PM_RET_ERROR_NOTSUPPORTED;
break;
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
index 081259f..d68c5e3 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
@@ -32,6 +32,11 @@
IOCTL_READ_GGS,
IOCTL_WRITE_PGGS,
IOCTL_READ_PGGS,
+ /* IOCTL for ULPI reset */
+ IOCTL_ULPI_RESET,
+ /* Set healthy bit value */
+ IOCTL_SET_BOOT_HEALTH_STATUS,
+ IOCTL_AFI,
};
//RPU operation mode
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
index 133043d..e85b2ce 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
@@ -602,6 +602,30 @@
}
/**
+ * pm_aes_engine() - Aes data blob encryption/decryption
+ * This function provides access to the xilsecure library to
+ * encrypt/decrypt data blobs.
+ *
+ * address_low: lower 32-bit address of the AesParams structure
+ *
+ * address_high: higher 32-bit address of the AesParams structure
+ *
+ * value: Returned output value
+ *
+ * @return Returns status, either success or error+reason
+ */
+enum pm_ret_status pm_aes_engine(uint32_t address_high,
+ uint32_t address_low,
+ uint32_t *value)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ PM_PACK_PAYLOAD3(payload, PM_SECURE_AES, address_high, address_low);
+ return pm_ipi_send_sync(primary_proc, payload, value, 1);
+}
+
+/**
* pm_pinctrl_request() - Request Pin from firmware
* @pin Pin number to request
*
@@ -713,6 +737,19 @@
}
/**
+ * pm_clock_get_num_clocks - PM call to request number of clocks
+ * @nclockss: Number of clocks
+ *
+ * This function is used by master to get number of clocks.
+ *
+ * Return: Returns status, either success or error+reason.
+ */
+static enum pm_ret_status pm_clock_get_num_clocks(uint32_t *nclocks)
+{
+ return pm_api_clock_get_num_clocks(nclocks);
+}
+
+/**
* pm_clock_get_name() - PM call to request a clock's name
* @clock_id Clock ID
* @name Name of clock (max 16 bytes)
@@ -1118,6 +1155,10 @@
(uint16_t *)&data[1]);
data[0] = (unsigned int)ret;
break;
+ case PM_QID_CLOCK_GET_NUM_CLOCKS:
+ ret = pm_clock_get_num_clocks(&data[1]);
+ data[0] = (unsigned int)ret;
+ break;
default:
ret = PM_RET_ERROR_ARGS;
WARN("Unimplemented query service call: 0x%x\n", qid);
@@ -1166,3 +1207,33 @@
key_hi, key_lo);
return pm_ipi_send_sync(primary_proc, payload, value, 2);
}
+
+/**
+ * pm_fpga_read - Perform the fpga configuration readback
+ *
+ * @reg_numframes: Configuration register offset (or) Number of frames to read
+ * @address_low: lower 32-bit Linear memory space address
+ * @address_high: higher 32-bit Linear memory space address
+ * @readback_type: Type of fpga readback operation
+ * 0 -- Configuration Register readback
+ * 1 -- Configuration Data readback
+ * @value: Value to read
+ *
+ * This function provides access to the xilfpga library to read
+ * the PL configuration.
+ *
+ * Return: Returns status, either success or error+reason.
+ */
+enum pm_ret_status pm_fpga_read(uint32_t reg_numframes,
+ uint32_t address_low,
+ uint32_t address_high,
+ uint32_t readback_type,
+ uint32_t *value)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ PM_PACK_PAYLOAD5(payload, PM_FPGA_READ, reg_numframes, address_low,
+ address_high, readback_type);
+ return pm_ipi_send_sync(primary_proc, payload, value, 1);
+}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
index 55a8a6e..1c9255e 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
@@ -23,6 +23,7 @@
PM_QID_PINCTRL_GET_FUNCTION_NAME,
PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
PM_QID_PINCTRL_GET_PIN_GROUPS,
+ PM_QID_CLOCK_GET_NUM_CLOCKS,
};
/**********************************************************
@@ -165,4 +166,14 @@
uint32_t key_lo,
uint32_t key_hi,
uint32_t *value);
+
+enum pm_ret_status pm_fpga_read(uint32_t reg_numframes,
+ uint32_t address_low,
+ uint32_t address_high,
+ uint32_t readback_type,
+ uint32_t *value);
+enum pm_ret_status pm_aes_engine(uint32_t address_high,
+ uint32_t address_low,
+ uint32_t *value);
+
#endif /* _PM_API_SYS_H_ */
diff --git a/plat/xilinx/zynqmp/pm_service/pm_defs.h b/plat/xilinx/zynqmp/pm_service/pm_defs.h
index 9a8026f..1fbf6ee 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_defs.h
@@ -89,6 +89,9 @@
PM_CLOCK_SETPARENT,
PM_CLOCK_GETPARENT,
PM_SECURE_IMAGE,
+ /* FPGA PL Readback */
+ PM_FPGA_READ,
+ PM_SECURE_AES,
PM_API_MAX
};
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
index dd9bbc8..7790c97 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -546,6 +546,23 @@
result[1]);
}
+ case PM_FPGA_READ:
+ {
+ uint32_t value;
+
+ ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
+ &value);
+ SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ }
+
+ case PM_SECURE_AES:
+ {
+ uint32_t value;
+
+ ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value);
+ SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ }
+
default:
WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/zynqmp_def.h
index 22256eb..50a7331 100644
--- a/plat/xilinx/zynqmp/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/zynqmp_def.h
@@ -48,6 +48,7 @@
#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C)
+#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250))
#define CRL_APB_CLK_BASE U(0xFF5E0020)
#define CRL_APB_RPU_AMBA_RESET (U(1) << 2)
@@ -56,7 +57,15 @@
#define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4)
#define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0)
+#define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0)
+#define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9)
+#define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1)
+#define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
+#define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
#define ZYNQMP_BOOTMODE_JTAG U(0)
+#define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \
+ CRL_APB_BOOT_DRIVE_PIN_1)
+#define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1
/* system counter registers and bitfields */
#define IOU_SCNTRS_BASE 0xFF260000
@@ -148,8 +157,6 @@
#define ZYNQMP_SILICON_VER_MASK 0xF000
#define ZYNQMP_SILICON_VER_SHIFT 12
#define ZYNQMP_CSU_VERSION_SILICON 0
-#define ZYNQMP_CSU_VERSION_EP108 1
-#define ZYNQMP_CSU_VERSION_VELOCE 2
#define ZYNQMP_CSU_VERSION_QEMU 3
#define ZYNQMP_RTL_VER_MASK 0xFF0
@@ -192,6 +199,7 @@
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
+#define FPD_SLCR_BASEADDR U(0xFD610000)
#define IOU_SLCR_BASEADDR U(0xFF180000)
#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
@@ -316,7 +324,7 @@
#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
-#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
+#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
/* Global general storage register base address */
#define GGS_BASEADDR (0xFFD80030U)
@@ -326,4 +334,12 @@
#define PGGS_BASEADDR (0xFFD80050U)
#define PGGS_NUM_REGS U(4)
+/* Warm restart boot health status register and mask */
+#define PM_BOOT_HEALTH_STATUS_REG (GGS_BASEADDR + U(0x10))
+#define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
+
+/*AFI registers */
+#define AFIFM6_WRCTRL U(13)
+#define FABRIC_WIDTH U(3)
+
#endif /* __ZYNQMP_DEF_H__ */
diff --git a/services/spd/opteed/opteed_pm.c b/services/spd/opteed/opteed_pm.c
index bdacf98..b133651 100644
--- a/services/spd/opteed/opteed_pm.c
+++ b/services/spd/opteed/opteed_pm.c
@@ -66,6 +66,9 @@
assert(optee_vector_table);
assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON);
+ write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), CTX_GPREG_X0,
+ max_off_pwrlvl);
+
/* Program the entry point and enter OPTEE */
cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_suspend_entry);
rc = opteed_synchronous_sp_entry(optee_ctx);
diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index 9b78d7f..990d028 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c
@@ -81,6 +81,17 @@
return NULL;
}
+/* CPU initialisation after wakeup from suspend */
+static void *sdei_cpu_wakeup_init(const void *arg)
+{
+ SDEI_LOG("Events masked on %lx\n", read_mpidr_el1());
+
+ /* All PEs wake up with SDEI events masked */
+ sdei_pe_mask();
+
+ return 0;
+}
+
/* Initialise an SDEI class */
static void sdei_class_init(sdei_class_t class)
{
@@ -1075,3 +1086,6 @@
/* Subscribe to PSCI CPU on to initialize per-CPU SDEI configuration */
SUBSCRIBE_TO_EVENT(psci_cpu_on_finish, sdei_cpu_on_init);
+
+/* Subscribe to PSCI CPU suspend finisher for per-CPU configuration */
+SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, sdei_cpu_wakeup_init);
diff --git a/tools/doimage/doimage.c b/tools/doimage/doimage.c
index 56dabba..6fc23d5 100644
--- a/tools/doimage/doimage.c
+++ b/tools/doimage/doimage.c
@@ -768,7 +768,7 @@
/* CSK index option */
if (config_lookup_int(&sec_cfg, "csk_key_index",
&cfg_int32) != CONFIG_TRUE) {
- fprintf(stderr, "Error obtaining \"flash_id\" element. "
+ fprintf(stderr, "Error obtaining \"flash_id\" element. ");
fprintf(stderr, "Using default - 0x0\n");
cfg_int32 = 0;
}
diff --git a/tools/doimage/secure/aes_key.txt b/tools/doimage/secure/aes_key.txt
new file mode 100644
index 0000000..3e8a888
--- /dev/null
+++ b/tools/doimage/secure/aes_key.txt
@@ -0,0 +1 @@
+ABCDEF1234567890ABCDEF1234567890ABCDEF1234567890ABCDEF1234567890
diff --git a/tools/doimage/secure/csk_priv_pem0.key b/tools/doimage/secure/csk_priv_pem0.key
new file mode 100644
index 0000000..0840c2a
--- /dev/null
+++ b/tools/doimage/secure/csk_priv_pem0.key
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEogIBAAKCAQEAm6jN6o2zQmtyUlvfkfDbSjPJ7Vlpp/KgK/eznoVBBsDIZakX
+cIgf8TSLpNVkc+ZE0f/n8X7mEZIyjuSBObLOm9vbkoZcR7DlKUL7RNNOUCv55Ozl
+hQwrzpH/uIyIJTvmek29G5wroi0wGbPoxzhelIRTjVCibleBWhYCmZQ6SIRmTY8L
+JT8VkX8I/Mhu62DjvxF3BnV6pXuh/FdgDN7MbldzM8Y+GOxVGi5Kcm5WHY7eyMxl
+4Y0Yko31Xv7T1PcXahVBIciT+11w+fLc4wQuCJ6GUf9JbzQ0ZllY/FdRG0AhuRMH
+zN0jAc/sKrIFoAErED6qlcoQg0vl7gmWN5x+2wIDAQABAoIBACtnPFOkw1FH6I6y
+c3qcMGlWW33FKsLb0nGwFfOjsGgTpU1Dgver3UxCnJWPsvzmPlZYBvK9saVAoLxb
+VvUhuJ6ZBXar5FtRJfUFak7cpL+SI5IDxFP++tAUwbtR5DyNoUyFFK/4Mep8sybX
+lZbHTwgWhb2nuEMQP09BR+RPAplpcitkIoPkhmbGfbt9Hsd25I3bb5Z9R4S/2Rcf
+7tmaxndQamij7/pUI7xtd8L6cMESJGIWrgEt/MaT2z8nNPE3EDctDSlH9yKqA2O7
+/LTfrxNDnw5gGRtOgahloThKljVM6pQa4mi91FufD67pHwnKn8urNbt8/3AWg6uU
+x4FzZdECgYEA0k2UYzBM+dU6T1bZZ176YI0cZrP1tbf/JwnZGHicQYS7lPLAqgfO
+u5oRQzuDimOXaV4xCPBO2nadd6aBxbZTXaglR7GG2uCHX6w2DnOr8/d66YTErTVV
+u7/Bf8gMKT9mM4rWPrOEXfXfF0fvcpkBQ+QDynIB37tx/mj2lXRkLx0CgYEAvXuX
+Dbe2QgSK0ajrcH7YJyx3RVx9RonOqL4yjCVCELmaDQd307Ef3j+gkd59XIewm+HA
+mPyeWEUd8EzH+UvjckfKFuF2I4lEUUWtVZTa7me7mvsFqeEOu5KusD4+Hs+B9Kqd
+3Evqcpj2lcMBI519Hvr9BTKfDBcH1EUos6A9rFcCgYAxsyPeTQvj/wBIv72hMFD7
+gF2159GpoFIsZ6dmoRpMYZHzIWtmw3GX5FEwEmCD1AV0YU41TpVUC7QrEq6Yiv4o
+pBQrXUkBcQ6NDaW4xJ1eip4Bkd7pEDGyrR6NlDlLhjAg/i6joskla3XNirKL4pzp
+7nj23vqSZToLZcLgjyEeAQKBgD5EvDo80j9VwMzvpxecB6qv+S4pG94vcWOQxYm6
+wMBATjjT6HP/9EoUPM9S/32F9er0QFfGRL8bT6Blix4I62Dl6KqmQy2gcXwH2tOS
+DHRmUIe40H6oQDAyHwg6HC4B4WInI6N+qzgnvnku0VQD8FdbAgVQQmY1t1PxulN1
+aG8XAoGAPWAr4i8KkVAx4wLlMF8E/ecKcsX1J0+UuKket7Dvk7xJfwtkSLPeV8Bp
+HuoHXMM3KYoZ93Hlto5rAT1VQhYuj7heU10v+9UtYTFHgaitptYmxovoCKKiZICl
+48aPUI377e5jQ6RhhGYy8ltKsJ80K1T9DIkThJPSS+9NAI+jrmg=
+-----END RSA PRIVATE KEY-----
diff --git a/tools/doimage/secure/csk_priv_pem1.key b/tools/doimage/secure/csk_priv_pem1.key
new file mode 100644
index 0000000..91d1aeb
--- /dev/null
+++ b/tools/doimage/secure/csk_priv_pem1.key
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEogIBAAKCAQEAgwHXB0AaIhT15Z9lHpQ2YT1W8i4oMvvRiLGQCrba5l7BJ03E
+ct0x3zagNKZEnpNndT4EAy98ihkhwVlUhxZCparJ2L3JsTs5RgV0wyQkQzwMLM8g
+QI5EMmJCgFAVRHmVICOsisGGfNVUHjGdGwPOipyQCsX2MAm3E139VpB7NYj+Q4IR
+4kvcb+59LZxKuRJTFKRDIqMGJu98P/ga70+YLXPCBPKSfnZnUppuaI86jF1E6xt8
+o7YtfEPCHDd2LXxKPZ670OapVqwo0t7ZSzEG63NkLp56FXc1OpfC69C8VPiZ8JqW
+wxvS/vL8MMCxsBnjSuqnmOAbcNR2GFtUwJOGwwIDAQABAoIBAFcfoiDwQHDp/531
+ownzBzcj0+67Q4Ckd3SwoVp+wJTz7wB0d3DsKX6IlYJuELRk0yjlVUXJDsnIbOpo
+vg4Yf7otGo9JqBh1imFGv6AHKRaNmIs0M/66nh/juNYcbAhd0w7MqrKcgRQDyy1J
+UXHl1jXYaPLBNDg+PcJjf1dSPp4axzmW2Pk2rXnJCsPcZXL/0YmEvqhfOze0GdjR
+hOkbbr6MPPVM66tA00xSwg9XEYJvHtwH6oB0rnANM8ieNK1mtcWkTU5di17CCrjS
+ohIhXQrdVpxt549EJoUqEFSgo8OOMm2npDbFrjlukb5euakvMacwoT1te79blSKf
+hrTvjgECgYEA0VqoFL0Vqe1qleikYDJ7S5xcv1oruEV31TeuBhDuf0c4PADCnBrV
+/RnCEYuXs6wCk60chHg5s0jxg+nGbiY6jRTHkJLRU3ZhDtrtfidEZ78GRzFF3shl
+Uzt7dHkKK1ZdiMH4sWzyRLom91TKWMrNKC1AD7v4/zjEXy6phall3ZcCgYEAoDJa
+0dIKvVCS6dM2E2kMqi/45mJqsJzFvYL1s4mbma/BAC47bBju/YEse90x+iIi3Gg/
+NoXmNfGPrtgdl+/J/Y6Pohxf/e7gGN71tYVETzgc2Jv09wqmzmTjCmo3wyepyWf+
+pIAE39kdhwnqXVw5xwOG1N3xrQ9TomOO+1QiXbUCgYAF84TJqiJehUA9aLKbhXPZ
+z2UXj3GkuFzSs9V/mKWe+qBPnFnr5BtnKX9JzmUOl3ovRoGEBoLlZNJwxIl+ghmx
+/wA5TOMkcz4JFRIhPu6D4HtGNNFepuWyewNkaThvyPG5vIHcUVOFvqDy8PcblRBF
+7xteFyLZ5nw2lHX/NbSOmwKBgFxLZqPIPcPArkPlGhyow1Ex/lbNkOZcDFkZIHHl
+8C3lYm62NCodW2PWjkh2shqInEkcDn9dObsOh1eWz8X/swJQplQhwPROMfJiUnHY
+a/iwPX5WrBXAn0X+Pgh8FdBsA5g0QDOKRkSplCd/APX08pzEXWQ60siAMhE3BuOq
+H3qZAoGAVnzFidlXuyn+fbNaNVepK9hbuoxHHbzYYWSkpi+73EchN8kXktC+AdEf
+owr9TPILbwWWJyisa3wW4xdbMifCgVLTedWZpZ09BENVqC+7g7ksX0pNMGYuFLOh
+Td7mFAgmclxG5UiKexajOLjjdnAsJyrDaNKhHn8NQNN6L93N0sE=
+-----END RSA PRIVATE KEY-----
diff --git a/tools/doimage/secure/csk_priv_pem2.key b/tools/doimage/secure/csk_priv_pem2.key
new file mode 100644
index 0000000..ea47ac5
--- /dev/null
+++ b/tools/doimage/secure/csk_priv_pem2.key
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEogIBAAKCAQEAjxTSTh57/5njUpE200+Qb3ySAn8lKeufgaa0K2Xc6Ri7lDZR
+ZJ2BPuQZV4lYGqgWUf0IOzNf2WnE2lPfVnLMx08h7NhBqJ83yJVajpr+itnOmW+r
+M7h76TFyuna1xz2kw1uhgI5Y4FRnJ4Cg4AexCSyViXSzEN/7LQwxa5z5WGDiNX5N
+3/tgjGu+dzSMOiIQhXwIcK/XaiQNm3WHqqnAhPb5Q9IBuuqBfpZoFfH4XmbFWrC8
+neSMMMxX5Ti9pKhLd1EsiaP0aUNQlF8gNWuC/tNaf+OCtwVelVa3sGSRjRFe06VQ
+sAE9oyXKri11yD5Dwp1xXivbpOrf7xjUe5gILwIDAQABAoIBABTr94CCxqDucKYP
+I9QsSzNyJKuGyfliQdWkea3q3C2ddzhJ5QbwXQjEM8xwAdkMAQ+GD2EQtxBEfgtq
+vjqW2MjAEnbefGNavL5w0GgP0+6bwLEA+ii67iuAFoWbfCMhKWmDiY8RwX8z+E13
+ao63sTRlN4x86v4pskG5CbTxpCg+8m7KklLns4SwRGf5gGQcgKRtNSR5nE4g2UNl
+dghbDdNlvUncm4zxUcTh0kquhF5Tef5w+6L7W8Hv9Pky3b1c2OK1BMhJlxYrtt69
+/zhIJs89CLx5ACfam+DT/xs0uUiuRQq/e1CCQLCnUO02JqpeN/schtDCd0ZWhbtB
+nT7fwTECgYEAx+COhys+7AZI0U+PeuTkI86GUsWHoBislXThxbxyGvMFjgyADZD+
+q/XEGAcxd4eTA1fr0Q9cLuuHZubjGQ7+OIXMZ6arXUsrmMrjRu3kHO+y6K6r4s8j
+5bxN/iQ0bymUtJRfJSLI172plszusiPWhCL5+yhYlNoh4mNZJuJnzXkCgYEAt0Gz
+07P19YPsxk5ow7ZnSNOMOkkEPP0SuHHWekMIK9KMjiRUSygOAk07zTL7MUoFn9Gy
+Prfi0ybFArNhIa4Xio3Fbjfig7rGgaApK4Y3d9A/CGPv/Nj7C2OTepqlEzRLmU9e
+Xw5yhbccCydXLyAYFAET2XHsmbewpvHyeYUSoOcCgYBRMJEUrOdhPmhDxZqVo/Zb
+6R887gnaaUtpZlHzXUnIUqEWA1PcruIT/b/KttlMIWEBQayDfkbGtFuK3AyxeBqh
+4Q+XpucC/W7XIMrTW/yGGIPG6nTdq6B8SFIyAojeArjp5T8Eua11nRAPNm1bJR2V
+DRQYBlp9FGIhMJPdLKhXmQKBgGeywSyR0COfBHPu2K+u3uFB/D7bJI/ScS54FHLY
+zZ3mpeylOCHTR6IbzDRAng31Ihue0KtW6P6tGJx/nv4tAltAADFvZDlAjqW5WLKt
+X2PoLlL0IlBFBEIclc6yBalJVWIqnG9TwJBT3oWdPGOJWLaxKWdJZSZS4J6HmLsV
+B0aPAoGAduLsOt8C5z48jPqmJxyPwsmT0Q424FccPMcvGOJ13yxq3xNsfAsbmg9l
+L2i/ktE0wCMA+Pm7cuFgxwD7xTr67POZgt9022KsOSonjPsIn24UQeP46vAX/Qtx
+Qf3sfvzf57vNy2Hybe38T8RsVOZla+v/QctfSfmb8Y95XL/SZzA=
+-----END RSA PRIVATE KEY-----
diff --git a/tools/doimage/secure/csk_priv_pem3.key b/tools/doimage/secure/csk_priv_pem3.key
new file mode 100644
index 0000000..e40a864
--- /dev/null
+++ b/tools/doimage/secure/csk_priv_pem3.key
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEowIBAAKCAQEAlA/T/5IMTPTu+k5PeesB2oeP80Y6nq0ls8vXLul0TVEJoJ+O
+InbPYNqYPu4dbQQg/u8qp8BeXm2ujtJbBTcdn0jKIiDTKYEnlsGfUt9GHnuuzvFh
+rORSKuAolUqvo/zcSCo1uykaFvSuyTovSPlwllzSixD9XBbHfn3kXneiIUa45vsJ
+AyjTn2qCJt0WgvX42NTxH6Q/OWLeOuKTyRHf25eabucIv77KYy0mlEPq5jjiV5AJ
+gl5F1h5G8n07JCIWjkZ2QV4wr+Hv9uGNaSb0WGppBp4CbdQa0eUI75cKzz4WXqds
+HZaYiX/a8YC+EUfvqDD02vKREIKFL/1zL53P/wIDAQABAoIBAGzBj5w7oBNrGpr7
+qL9KEyt8xg0Q+gAR+Q6vXRlVXBtquiKk8Jd6I+vlxUz8RNsN3FrGPNPJpse/0yeP
+dlJHYNfedLNK3zCucPD4uln6LRw5B3d0sKV5dK2Px9+ZY5iWJQxRDPS0RTi1dCnV
+NmRo7P1Vo0WJLkFVbiYIvRVy1MGRfF9ejN41G6U4MoBAQ9WqLp+JasUMTspZI49a
+z8tOiJPT94MHBwbKnz8Mcq8sy02LR7U5h82+0T7JoRVix/OXiOoiQExNjZ9yGar0
+wBnl0SL1UW5UUaYzbyNH0mlMXLD+qowbDZM2pBWPfqXK+CMOsL6STIwnns7lY+ZJ
+ILbaVmECgYEA2kQXE1PZ25A87a81wCEld402WJ2KegrZC719EWv+xeoS72Ji8uv7
+V0PxVGJQOcG1N+dzJ5tN59SQ/NvVTrjwqNUxQqsygmWq/TcfGb9ONZRmyzcehYLb
+m4xTjqJKQ6Kwm5SoaCYmzEb/xaeLwLS9HmR9MdB1dxtDOLpjaK/8qPECgYEArait
+QhgaknlxG8pcAimPsEUrLHYWSFRE/MUk4+YvZg/5+YJ8csvY0SO2h0tF/ARwUrdI
+DaLEifHm4vqgN03K/0gqj7TKxcNlV16PvVx7Vz97xejdqdHZLDfAo4lcotsgvFQW
+zIqoQGGPLf6WhFixZ8mEYj8xnmzLGPvHQmf1h+8CgYEA0LDl917nIN4qw4ARPqDy
+t/pXCienrcUNfgIxwSSnNwj2DdjejzI+4VNfPbW6y16BLPCp1CbUOGOwNXTj4R9H
+S8Z8ESirZK5c7Tt1CyM1XlmEZ61OC43w+CsWAXz+0OiPQFLFKr+/vPXtvEjUgO7P
+HG4sniKZDccNYQIl5oTOaaECgYAPU4u3AZmWw9EPutRT/IcJ75DX47Qjvgw4os2W
+r4IPZ+mP88w39XW1P4mkdyg+DcY8BqD9Uxg1dHwEHEp3lw4LabsX48Thn1UaWOYm
+uDrKgHfUB7FIg5S/Kkx+ImliliRVerZoZvRiejnAvW9bTtiZaFeetCUU7lUeZ1o2
+qiYpUQKBgHQDfdDhguBGPKpkJ7pVwHkJA/lyRWaN1hwplw4TvX2oH14NsHg5Q5Fd
+lHqHFs2Ry/6X3bKgF0E6q4cx0V1Xnnj9sGsemlrHdiSxplDYRQql7X5OeYPGF/Bg
+ZTTG8rDwy+ey6EP9BZUb03hISx/LyMynOzjGl6uOcdAcy2d9Vno0
+-----END RSA PRIVATE KEY-----
diff --git a/tools/doimage/secure/kak_priv_pem.key b/tools/doimage/secure/kak_priv_pem.key
new file mode 100644
index 0000000..dfceaba
--- /dev/null
+++ b/tools/doimage/secure/kak_priv_pem.key
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEowIBAAKCAQEAsj2cHcrE2pdyCqNr+oVcQULiRx6RivkrhLl2DTqWXpP33BPm
+MP0W0X0z98X7E3kZO+JIGRZ8q+6AWmUpL+53aOGItNeUgT7jQKViPJIo9ZcEnv/n
+PJqdgDd4xFhnwYMgq8uVYN9IPfaKDwB3EoOqjNox2JholUVxvLw6W8DAC8La3zwb
+0hiqtIlirQOQ/KaTHxC6dPYkrai+jSK5uAX7Vt8RKYg5qfDxSdZckmC2xVKYURhV
+bZAlyKki4h6f8CwYCJMQDpHL6mVYCuJ1Ju/OJEXvthDKD0CD2hwILhksdey3qMOC
+I5lHSO1b+sTvnVHGs65wI7A+ZYwnadMNvS9e2QIDAQABAoIBAH2uu9q2FEEe8SdX
+PNiWGQtbojsL7wzTzj/0lq2VVlqyc+AXmAWLMP/fDTn1vKlqhsSXNseZ96c0sgUL
+uBM4T7MA9WivauQH+C6pb6/OUFt8daG4SNGPJOg4NUweGmt1jyAUmeyJBWPL6GXT
+qiK//Q78/JECRxyaryyqfWwdak3flzfwONBJ03tQ9EO+L7hf9gAP7OYnAsuNp+Bz
+tj1xzNMumYYYiHvsEXx8UTe8HGrmYuO53ZY5fBLGB6Jj7hRlAHNfcdVDvvoBU5cI
+Zwi+5YsBuSP2Hr9Gt2Odu+KitH3gFdS0HIiDh44AT+Trj29NMANFDfkDbVHUmE0q
+YBL75NECgYEA2E+fJzdaYyyPIcvQgVM8g52hltR5IRgJICND3NOdB/Zb2teBGZh+
+1XJ6ZqQMDcOQZo0CMbX9UNRnf3NU55k48/EEITxCgUJTx/WdfJeTVlWGspt5+U/r
+hDnQmkePdU1en63+u9eqsla9+VhLwU3fl/pIOpsBAnoEzs3hMQZ1G0cCgYEA0vHH
+ilm3AztIoZlH3wgDAl2Gu5/YopqEofKA8G4Jp89rlkk919P/GNjEc6575wjgztDB
+0Xab+H7Nqxjs3HqQX/DTTuAxzAggBg3j/ijpHnmjrCHLeMT5ciyH+EH5Bg///cLq
++Cwn7aOWuSK1hGdDYxUycHylAYZXXFJzmEIEhN8CgYEA1qTrwPZkctTckyS0GiCG
+g/P/TLQ6HmTDaWiVBqPVxvjn3RjLuqJf+V5Hp2JRs7bDq39xFfMJExQyP34qWkbp
+BOe8uV4agDlY+ar4Q5IFWj40EzfEqWhsxCC6pt0rtbK4mqsFg1BWyfDZQnwjcAXe
+QejRk5YMQnDiJHSXaRaHTjECgYAv6ecvD624ODEJM63VhRZZ5TCDUY19caeKuXB8
+LCJZUY3Ydw5rBaY92I7Wz90o3yVhFJ3RnCVVTkgdAu5aLiS5BhSZJ+dntri/Z0xQ
+IK7C01JP+OUkq2kVe/Pued28eMnms+13LWBsY+oKZ03foyz1Ro1Ma6N3MzKIr9m9
+zdEE9QKBgECfoh0xE2T/cbJrtH0mwMCUM6eMVGq+yQBKNvuuPg6kaQUsah1n1rp6
+OyvjwRAXdhshszEzNTX1WTT6/i+vZX277Ax50pPo9UhQ9kVteVt1frN6+u5sy07V
+fg1f2+m0iFx4BD/irU0fzSyfGE+QkBnmXFBUNSYjp2PSqYIdufmW
+-----END RSA PRIVATE KEY-----
diff --git a/tools/doimage/secure/sec_img_7K.cfg b/tools/doimage/secure/sec_img_7K.cfg
new file mode 100644
index 0000000..459f731
--- /dev/null
+++ b/tools/doimage/secure/sec_img_7K.cfg
@@ -0,0 +1,29 @@
+# Trusted boot image extension definitions
+
+kak_key_file = "tools/doimage/secure/kak_priv_pem.key";
+
+# CSK keys array - 16 entries total.
+# Only a key with csk_key_index will be used for signing the image
+# use "*" string instead of file name for specifying an empty key
+csk_key_file = ["tools/doimage/secure/csk_priv_pem0.key",
+ "tools/doimage/secure/csk_priv_pem1.key",
+ "tools/doimage/secure/csk_priv_pem2.key",
+ "tools/doimage/secure/csk_priv_pem3.key",
+ "*", "*", "*", "*", "*", "*", "*", "*", "*", "*", "*", "*"];
+
+# index of CSK key in the array. Valid range is 0 to 15
+csk_key_index = 3;
+
+# AES-256 symmetric key for image encryption
+aes_key_file = "tools/doimage/secure/aes_key.txt";
+
+efuse_disable = false;
+jtag = { enable = true; delay = 20; };
+
+box_id = 0xdeadbeef;
+flash_id = 0xbaddf00d;
+
+# SecureBootControl and EfuseBurnControl registers array
+# Two register addresses for each connected CP
+# A7K - one CP, two register values
+control = [0xF2441920, 0xF2441940];
diff --git a/tools/doimage/secure/sec_img_8K.cfg b/tools/doimage/secure/sec_img_8K.cfg
new file mode 100644
index 0000000..a849dff
--- /dev/null
+++ b/tools/doimage/secure/sec_img_8K.cfg
@@ -0,0 +1,29 @@
+# Trusted boot image extension definitions
+
+kak_key_file = "tools/doimage/secure/kak_priv_pem.key";
+
+# CSK keys array - 16 entries total.
+# Only a key with csk_key_index will be used for signing the image
+# use "*" string instead of file name for specifying an empty key
+csk_key_file = ["tools/doimage/secure/csk_priv_pem0.key",
+ "tools/doimage/secure/csk_priv_pem1.key",
+ "tools/doimage/secure/csk_priv_pem2.key",
+ "tools/doimage/secure/csk_priv_pem3.key",
+ "*", "*", "*", "*", "*", "*", "*", "*", "*", "*", "*", "*"];
+
+# index of CSK key in the array. Valid range is 0 to 15
+csk_key_index = 3;
+
+# AES-256 symmetric key for image encryption
+aes_key_file = "tools/doimage/secure/aes_key.txt";
+
+efuse_disable = false;
+jtag = { enable = true; delay = 20; };
+
+box_id = 0xdeadbeef;
+flash_id = 0xbaddf00d;
+
+# SecureBootControl and EfuseBurnControl registers array
+# Two register addresses for each connected CP
+# A8K - two CP, four register values
+control = [0xF2441920, 0xF2441940, 0xF4441920, 0xF4441940];