commit bf83b9c291a188e6e372bd24e800dca331699db3
author Siva Durga Prasad Paladugu <sivadur@xilinx.com> Wed Feb 07 13:13:01 2018 +0530
committer Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Thu May 17 15:19:10 2018 +0530
tree dcc9ef3e3d00f8591c1f89a173bac2070ab8fba4
parent 56547879196b073d02894cecfc359b596b23e47e

plat: xilinx: zynqmp: Make fpga load blocking until completed

This patch makes bitstream load blocking call and waits until
bitstream is loaded successfully or return with error.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Avesh Khan <aveshk@xilinx.com>

plat/xilinx/zynqmp/pm_service/pm_api_sys.c

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
index 07c04e7..69bd53b 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
@@ -538,7 +538,7 @@
 	/* Send request to the PMU */
 	PM_PACK_PAYLOAD5(payload, PM_FPGA_LOAD, address_high, address_low,
 						size, flags);
-	return pm_ipi_send(primary_proc, payload);
+	return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 }
 
 /**