Merge pull request #910 from dp-arm/dp/AArch32-juno-port
Add AArch32 support for Juno
diff --git a/Makefile b/Makefile
index 02aa50e..d0568d9 100644
--- a/Makefile
+++ b/Makefile
@@ -50,10 +50,14 @@
# Default values for build configurations, and their dependencies
################################################################################
+ifdef ASM_ASSERTION
+ $(warning ASM_ASSERTION is removed, use ENABLE_ASSERTIONS instead.)
+endif
+
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
-# ASM_ASSERTION enabled for DEBUG builds only
-ASM_ASSERTION := ${DEBUG}
+# Assertions enabled for DEBUG builds by default
+ENABLE_ASSERTIONS := ${DEBUG}
ENABLE_PMF := ${ENABLE_RUNTIME_INSTRUMENTATION}
PLAT := ${DEFAULT_PLAT}
@@ -439,13 +443,13 @@
# Build options checks
################################################################################
-$(eval $(call assert_boolean,ASM_ASSERTION))
$(eval $(call assert_boolean,COLD_BOOT_SINGLE_CPU))
$(eval $(call assert_boolean,CREATE_KEYS))
$(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS))
$(eval $(call assert_boolean,CTX_INCLUDE_FPREGS))
$(eval $(call assert_boolean,DEBUG))
$(eval $(call assert_boolean,DISABLE_PEDANTIC))
+$(eval $(call assert_boolean,ENABLE_ASSERTIONS))
$(eval $(call assert_boolean,ENABLE_PLAT_COMPAT))
$(eval $(call assert_boolean,ENABLE_PMF))
$(eval $(call assert_boolean,ENABLE_PSCI_STAT))
@@ -464,6 +468,7 @@
$(eval $(call assert_boolean,SPIN_ON_BL1_EXIT))
$(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
$(eval $(call assert_boolean,USE_COHERENT_MEM))
+$(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY))
$(eval $(call assert_numeric,ARM_ARCH_MAJOR))
$(eval $(call assert_numeric,ARM_ARCH_MINOR))
@@ -478,10 +483,10 @@
$(eval $(call add_define,ARM_ARCH_MAJOR))
$(eval $(call add_define,ARM_ARCH_MINOR))
$(eval $(call add_define,ARM_GIC_ARCH))
-$(eval $(call add_define,ASM_ASSERTION))
$(eval $(call add_define,COLD_BOOT_SINGLE_CPU))
$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
$(eval $(call add_define,CTX_INCLUDE_FPREGS))
+$(eval $(call add_define,ENABLE_ASSERTIONS))
$(eval $(call add_define,ENABLE_PLAT_COMPAT))
$(eval $(call add_define,ENABLE_PMF))
$(eval $(call add_define,ENABLE_PSCI_STAT))
@@ -501,6 +506,7 @@
$(eval $(call add_define,SPIN_ON_BL1_EXIT))
$(eval $(call add_define,TRUSTED_BOARD_BOOT))
$(eval $(call add_define,USE_COHERENT_MEM))
+$(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY))
# Define the EL3_PAYLOAD_BASE flag only if it is provided.
ifdef EL3_PAYLOAD_BASE
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 89664cd..ebeb39e 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -114,7 +114,7 @@
print_errata_status();
-#if DEBUG
+#if ENABLE_ASSERTIONS
u_register_t val;
/*
* Ensure that MMU/Caches and coherency are turned on
@@ -141,7 +141,7 @@
assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
else
assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
-#endif
+#endif /* ENABLE_ASSERTIONS */
/* Perform remaining generic architectural setup from EL3 */
bl1_arch_setup();
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 6238329..a847ae3 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -185,26 +185,27 @@
*
* The PSCI implementation invokes platform routines that enable CPUs to
* participate in coherency. On a system where CPUs are not
- * cache-coherent out of reset, having caches enabled until such time
- * might lead to coherency issues (resulting from stale data getting
- * speculatively fetched, among others). Therefore we keep data caches
- * disabled while enabling the MMU, thereby forcing data accesses to
- * have non-cacheable, nGnRnE attributes (these will always be coherent
- * with main memory).
+ * cache-coherent without appropriate platform specific programming,
+ * having caches enabled until such time might lead to coherency issues
+ * (resulting from stale data getting speculatively fetched, among
+ * others). Therefore we keep data caches disabled even after enabling
+ * the MMU for such platforms.
*
- * On systems with hardware-assisted coherency, where CPUs are expected
- * to be cache-coherent out of reset without needing explicit software
- * intervention, PSCI need not invoke platform routines to enter
- * coherency (as CPUs already are); and there's no reason to have caches
- * disabled either.
+ * On systems with hardware-assisted coherency, or on single cluster
+ * platforms, such platform specific programming is not required to
+ * enter coherency (as CPUs already are); and there's no reason to have
+ * caches disabled either.
*/
-#if HW_ASSISTED_COHERENCY
- mov x0, #0
-#else
mov x0, #DISABLE_DCACHE
-#endif
bl bl31_plat_enable_mmu
+#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
+ mrs x0, sctlr_el3
+ orr x0, x0, #SCTLR_C_BIT
+ msr sctlr_el3, x0
+ isb
+#endif
+
bl psci_warmboot_entrypoint
#if ENABLE_RUNTIME_INSTRUMENTATION
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index c7f60b5..477b55b 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -236,24 +236,27 @@
*
* The PSCI implementation invokes platform routines that enable CPUs to
* participate in coherency. On a system where CPUs are not
- * cache-coherent out of reset, having caches enabled until such time
- * might lead to coherency issues (resulting from stale data getting
- * speculatively fetched, among others). Therefore we keep data caches
- * disabled while enabling the MMU, thereby forcing data accesses to
- * have non-cacheable, nGnRnE attributes (these will always be coherent
- * with main memory).
+ * cache-coherent without appropriate platform specific programming,
+ * having caches enabled until such time might lead to coherency issues
+ * (resulting from stale data getting speculatively fetched, among
+ * others). Therefore we keep data caches disabled even after enabling
+ * the MMU for such platforms.
*
- * On systems where CPUs are cache-coherent out of reset, however, PSCI
- * need not invoke platform routines to enter coherency (as CPUs already
- * are), and there's no reason to have caches disabled either.
+ * On systems with hardware-assisted coherency, or on single cluster
+ * platforms, such platform specific programming is not required to
+ * enter coherency (as CPUs already are); and there's no reason to have
+ * caches disabled either.
*/
-#if HW_ASSISTED_COHERENCY
- mov r0, #0
-#else
mov r0, #DISABLE_DCACHE
-#endif
bl bl32_plat_enable_mmu
+#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
+ ldcopr r0, SCTLR
+ orr r0, r0, #SCTLR_C_BIT
+ stcopr r0, SCTLR
+ isb
+#endif
+
bl sp_min_warm_boot
/* Program the registers in cpu_context and exit monitor mode */
diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S
index 77298a1..adb6dc3 100644
--- a/common/aarch32/debug.S
+++ b/common/aarch32/debug.S
@@ -90,7 +90,7 @@
no_ret plat_panic_handler
endfunc report_exception
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
.section .rodata.assert_str, "aS"
assert_msg1:
.asciz "ASSERT: File "
@@ -107,6 +107,11 @@
* ---------------------------------------------------------------------------
*/
func asm_assert
+#if LOG_LEVEL >= LOG_LEVEL_INFO
+ /*
+ * Only print the output if LOG_LEVEL is higher or equal to
+ * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
+ */
/* Stash the parameters already in r0 and r1 */
mov r5, r0
mov r6, r1
@@ -147,9 +152,10 @@
bl plat_crash_console_flush
1:
+#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
no_ret plat_panic_handler
endfunc asm_assert
-#endif
+#endif /* ENABLE_ASSERTIONS */
/*
* This function prints a string from address in r4
diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S
index fb6924e..cdb4ec6 100644
--- a/common/aarch64/debug.S
+++ b/common/aarch64/debug.S
@@ -41,7 +41,7 @@
/* The offset to add to get ascii for numerals '0 - 9' */
#define ASCII_OFFSET_NUM 0x30
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
.section .rodata.assert_str, "aS"
assert_msg1:
.asciz "ASSERT: File "
@@ -78,6 +78,11 @@
* ---------------------------------------------------------------------------
*/
func asm_assert
+#if LOG_LEVEL >= LOG_LEVEL_INFO
+ /*
+ * Only print the output if LOG_LEVEL is higher or equal to
+ * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
+ */
mov x5, x0
mov x6, x1
/* Ensure the console is initialized */
@@ -98,9 +103,10 @@
asm_print_line_dec
bl plat_crash_console_flush
_assert_loop:
+#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
no_ret plat_panic_handler
endfunc asm_assert
-#endif
+#endif /* ENABLE_ASSERTIONS */
/*
* This function prints a string from address in x4.
diff --git a/docs/user-guide.md b/docs/user-guide.md
index a1df965..3061fb9 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -203,11 +203,6 @@
in MPIDR is set and access the bit-fields in MPIDR accordingly. Default
value of this flag is 0.
-* `ASM_ASSERTION`: This flag determines whether the assertion checks within
- assembly source files are enabled or not. This option defaults to the
- value of `DEBUG` - that is, by default this is only enabled for a debug
- build of the firmware.
-
* `BL2`: This is an optional build option which specifies the path to BL2
image for the `fip` target. In this case, the BL2 in the ARM Trusted
Firmware will not be built.
@@ -286,6 +281,14 @@
payload. Please refer to the "Booting an EL3 payload" section for more
details.
+* `ENABLE_ASSERTIONS`: This option controls whether or not calls to `assert()`
+ are compiled out. For debug builds, this option defaults to 1, and calls to
+ `assert()` are left in place. For release builds, this option defaults to 0
+ and calls to `assert()` function are compiled out. This option can be set
+ independently of `DEBUG`. It can also be used to hide any auxiliary code
+ that is only required for the assertion and does not fit in the assertion
+ itself.
+
* `ENABLE_PMF`: Boolean option to enable support for optional Performance
Measurement Framework(PMF). Default is 0.
@@ -349,7 +352,8 @@
initiate the operations, and the rest is managed in hardware, minimizing
active software management. In such systems, this boolean option enables ARM
Trusted Firmware to carry out build and run-time optimizations during boot
- and power management operations. This option defaults to 0.
+ and power management operations. This option defaults to 0 and if it is
+ enabled, then it implies `WARMBOOT_ENABLE_DCACHE_EARLY` is also enabled.
* `LOAD_IMAGE_V2`: Boolean option to enable support for new version (v2) of
image loading, which provides more flexibility and scalability around what
@@ -508,6 +512,12 @@
to a string formed by concatenating the version number, build type and build
string.
+* `WARMBOOT_ENABLE_DCACHE_EARLY` : Boolean option to enable D-cache early on
+ the CPU after warm boot. This is applicable for platforms which do not
+ require interconnect programming to enable cache coherency (eg: single
+ cluster platforms). If this option is enabled, then warm boot path
+ enables D-caches immediately after enabling MMU. This option defaults to 0.
+
#### ARM development platform specific build options
* `ARM_BL31_IN_DRAM`: Boolean option to select loading of BL31 in TZC secured
@@ -568,6 +578,10 @@
- `tdram` : Trusted DRAM (if available)
- `dram` : Secure region in DRAM (configured by the TrustZone controller)
+* `ARM_XLAT_TABLES_LIB_V1`: boolean option to compile the Trusted Firmware
+ with version 1 of the translation tables library instead of version 2. It is
+ set to 0 by default, which selects version 2.
+
For a better understanding of these options, the ARM development platform memory
map is explained in the [Firmware Design].
diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c
index 2e773a9..0fcec85 100644
--- a/drivers/arm/cci/cci.c
+++ b/drivers/arm/cci/cci.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -39,7 +39,7 @@
static unsigned int g_max_master_id;
static const int *g_cci_slave_if_map;
-#if DEBUG
+#if ENABLE_ASSERTIONS
static int validate_cci_map(const int *map)
{
unsigned int valid_cci_map = 0;
@@ -54,26 +54,25 @@
continue;
if (slave_if_id >= CCI_SLAVE_INTERFACE_COUNT) {
- tf_printf("Slave interface ID is invalid\n");
+ ERROR("Slave interface ID is invalid\n");
return 0;
}
if (valid_cci_map & (1 << slave_if_id)) {
- tf_printf("Multiple masters are assigned same"
- " slave interface ID\n");
+ ERROR("Multiple masters are assigned same slave interface ID\n");
return 0;
}
valid_cci_map |= 1 << slave_if_id;
}
if (!valid_cci_map) {
- tf_printf("No master is assigned a valid slave interface\n");
+ ERROR("No master is assigned a valid slave interface\n");
return 0;
}
return 1;
}
-#endif /* DEBUG */
+#endif /* ENABLE_ASSERTIONS */
void cci_init(uintptr_t cci_base,
const int *map,
diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c
index ca06182..16c8f60 100644
--- a/drivers/arm/ccn/ccn.c
+++ b/drivers/arm/ccn/ccn.c
@@ -81,7 +81,7 @@
mmio_write_64(region_base + register_offset, value);
}
-#if DEBUG
+#if ENABLE_ASSERTIONS
typedef struct rn_info {
unsigned char node_desc[MAX_RN_NODES];
@@ -224,7 +224,7 @@
info.node_desc[node_id]--;
}
}
-#endif /* DEBUG */
+#endif /* ENABLE_ASSERTIONS */
/*******************************************************************************
* This function validates parameters passed by the platform (in a debug build)
@@ -234,7 +234,7 @@
******************************************************************************/
void ccn_init(const ccn_desc_t *plat_desc)
{
-#if DEBUG
+#if ENABLE_ASSERTIONS
ccn_validate_plat_params(plat_desc);
#endif
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index ca088c3..8c6f8ba 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
#include <mmio.h>
#include <stddef.h>
#include <tzc400.h>
-#include "tzc_common_private.c"
+#include "tzc_common_private.h"
/*
* Macros which will be used by common core functions.
diff --git a/drivers/arm/tzc/tzc_common_private.c b/drivers/arm/tzc/tzc_common_private.h
similarity index 94%
rename from drivers/arm/tzc/tzc_common_private.c
rename to drivers/arm/tzc/tzc_common_private.h
index 8b1ddf4..ee278ec 100644
--- a/drivers/arm/tzc/tzc_common_private.c
+++ b/drivers/arm/tzc/tzc_common_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,6 +28,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef __TZC_COMMON_PRIVATE_H__
+#define __TZC_COMMON_PRIVATE_H__
+
#include <arch.h>
#include <arch_helpers.h>
#include <mmio.h>
@@ -190,8 +193,9 @@
nsaid_permissions); \
}
-#if DEBUG
-static unsigned int _tzc_read_peripheral_id(uintptr_t base)
+#if ENABLE_ASSERTIONS
+
+static inline unsigned int _tzc_read_peripheral_id(uintptr_t base)
{
unsigned int id;
@@ -203,7 +207,7 @@
}
#ifdef AARCH32
-static unsigned long long _tzc_get_max_top_addr(int addr_width)
+static inline unsigned long long _tzc_get_max_top_addr(int addr_width)
{
/*
* Assume at least 32 bit wide address and initialize the max.
@@ -232,4 +236,6 @@
(UINT64_MAX >> (64 - (addr_width)))
#endif /* AARCH32 */
-#endif
+#endif /* ENABLE_ASSERTIONS */
+
+#endif /* __TZC_COMMON_PRIVATE_H__ */
diff --git a/drivers/arm/tzc/tzc_dmc500.c b/drivers/arm/tzc/tzc_dmc500.c
index 24e587c..d696dfd 100644
--- a/drivers/arm/tzc/tzc_dmc500.c
+++ b/drivers/arm/tzc/tzc_dmc500.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
#include <mmio.h>
#include <tzc_dmc500.h>
#include "tzc_common.h"
-#include "tzc_common_private.c"
+#include "tzc_common_private.h"
/*
* Macros which will be used by common core functions.
@@ -257,7 +257,7 @@
static void validate_plat_driver_data(
const tzc_dmc500_driver_data_t *plat_driver_data)
{
-#if DEBUG
+#if ENABLE_ASSERTIONS
int i;
unsigned int dmc_id;
uintptr_t dmc_base;
@@ -273,7 +273,7 @@
dmc_id = _tzc_read_peripheral_id(dmc_base);
assert(dmc_id == DMC500_PERIPHERAL_ID);
}
-#endif /* DEBUG */
+#endif /* ENABLE_ASSERTIONS */
}
diff --git a/drivers/io/io_storage.c b/drivers/io/io_storage.c
index 7cb1a6a..de8c3bf 100644
--- a/drivers/io/io_storage.c
+++ b/drivers/io/io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -51,8 +51,8 @@
/* Number of currently registered devices */
static unsigned int dev_count;
-
-#if DEBUG /* Extra validation functions only used in debug builds */
+/* Extra validation functions only used when asserts are enabled */
+#if ENABLE_ASSERTIONS
/* Return a boolean value indicating whether a device connector is valid */
static int is_valid_dev_connector(const io_dev_connector_t *dev_con)
@@ -89,7 +89,8 @@
return ((mode != IO_SEEK_INVALID) && (mode < IO_SEEK_MAX));
}
-#endif /* End of debug-only validation functions */
+#endif /* ENABLE_ASSERTIONS */
+/* End of extra validation functions only used when asserts are enabled */
/* Open a connection to a specific device */
diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S
index d7e0b3f..9158203 100644
--- a/include/common/aarch32/el3_common_macros.S
+++ b/include/common/aarch32/el3_common_macros.S
@@ -148,7 +148,7 @@
_init_memory, _init_c_runtime, _exception_vectors
/* Make sure we are in Secure Mode */
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
ldcopr r0, SCR
tst r0, #SCR_NS_BIT
ASM_ASSERT(eq)
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index ca868dd..31bf681 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -87,7 +87,7 @@
******************************************************************************/
static inline void cm_set_next_context(void *context)
{
-#if DEBUG
+#if ENABLE_ASSERTIONS
uint64_t sp_mode;
/*
@@ -98,7 +98,7 @@
: "=r" (sp_mode));
assert(sp_mode == MODE_SP_EL0);
-#endif
+#endif /* ENABLE_ASSERTIONS */
__asm__ volatile("msr spsel, #1\n"
"mov sp, %0\n"
diff --git a/include/lib/stdlib/assert.h b/include/lib/stdlib/assert.h
index 5621f8c..1bcd1ea 100644
--- a/include/lib/stdlib/assert.h
+++ b/include/lib/stdlib/assert.h
@@ -34,30 +34,27 @@
* @(#)assert.h 8.2 (Berkeley) 1/21/94
* $FreeBSD$
*/
-
-#include <sys/cdefs.h>
-
/*
- * Unlike other ANSI header files, <assert.h> may usefully be included
- * multiple times, with and without NDEBUG defined.
+ * Portions copyright (c) 2017, ARM Limited and Contributors.
+ * All rights reserved.
*/
-#undef assert
-#undef _assert
+#ifndef _ASSERT_H_
+#define _ASSERT_H_
-#ifdef NDEBUG
-#define assert(e) ((void)0)
-#define _assert(e) ((void)0)
-#else
-#define _assert(e) assert(e)
+#include <sys/cdefs.h>
+#if ENABLE_ASSERTIONS
+#define _assert(e) assert(e)
#define assert(e) ((e) ? (void)0 : __assert(__func__, __FILE__, \
__LINE__, #e))
-#endif /* NDEBUG */
+#else
+#define assert(e) ((void)0)
+#define _assert(e) ((void)0)
+#endif /* ENABLE_ASSERTIONS */
-#ifndef _ASSERT_H_
-#define _ASSERT_H_
__BEGIN_DECLS
void __assert(const char *, const char *, int, const char *) __dead2;
__END_DECLS
+
#endif /* !_ASSERT_H_ */
diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h
index aaa96f3..b843d49 100644
--- a/include/plat/arm/board/common/v2m_def.h
+++ b/include/plat/arm/board/common/v2m_def.h
@@ -30,7 +30,7 @@
#ifndef __V2M_DEF_H__
#define __V2M_DEF_H__
-#include <xlat_tables_v2.h>
+#include <arm_xlat_tables.h>
/* V2M motherboard system registers & offsets */
diff --git a/include/plat/arm/common/arm_xlat_tables.h b/include/plat/arm/common/arm_xlat_tables.h
new file mode 100644
index 0000000..3f7e85f
--- /dev/null
+++ b/include/plat/arm/common/arm_xlat_tables.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if ARM_XLAT_TABLES_LIB_V1
+#include <xlat_tables.h>
+#else
+#include <xlat_tables_v2.h>
+#endif /* ARM_XLAT_TABLES_LIB_V1 */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 5430da0..4ba4a84 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -30,12 +30,12 @@
#ifndef __PLAT_ARM_H__
#define __PLAT_ARM_H__
+#include <arm_xlat_tables.h>
#include <bakery_lock.h>
#include <cassert.h>
#include <cpu_data.h>
#include <stdint.h>
#include <utils.h>
-#include <xlat_tables_v2.h>
/*******************************************************************************
* Forward declarations
diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S
index 5b17c21..03b47ea 100644
--- a/lib/aarch32/misc_helpers.S
+++ b/lib/aarch32/misc_helpers.S
@@ -162,7 +162,7 @@
* --------------------------------------------------------------------------
*/
func memcpy4
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
orr r3, r0, r1
tst r3, #0x3
ASM_ASSERT(eq)
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index 84265e0..74550aa 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -215,7 +215,7 @@
tmp1 .req x4
tmp2 .req x5
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
/*
* Check for M bit (MMU enabled) of the current SCTLR_EL(1|3)
* register value and panic if the MMU is disabled.
@@ -228,7 +228,7 @@
tst tmp1, #SCTLR_M_BIT
ASM_ASSERT(ne)
-#endif /* ASM_ASSERTION */
+#endif /* ENABLE_ASSERTIONS */
/* stop_address is the address past the last to zero */
add stop_address, cursor, length
@@ -247,7 +247,7 @@
mov tmp2, #(1 << 2)
lsl block_size, tmp2, block_size
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
/*
* Assumes block size is at least 16 bytes to avoid manual realignment
* of the cursor at the end of the DCZVA loop.
@@ -444,7 +444,7 @@
* --------------------------------------------------------------------------
*/
func memcpy16
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
orr x3, x0, x1
tst x3, #0xf
ASM_ASSERT(eq)
diff --git a/lib/cpus/aarch32/aem_generic.S b/lib/cpus/aarch32/aem_generic.S
index 3d6064c..7374e25 100644
--- a/lib/cpus/aarch32/aem_generic.S
+++ b/lib/cpus/aarch32/aem_generic.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -35,7 +35,7 @@
func aem_generic_core_pwr_dwn
/* Assert if cache is enabled */
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
@@ -51,7 +51,7 @@
func aem_generic_cluster_pwr_dwn
/* Assert if cache is enabled */
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S
index f631c4c..8cd7933 100644
--- a/lib/cpus/aarch32/cortex_a32.S
+++ b/lib/cpus/aarch32/cortex_a32.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -76,7 +76,7 @@
push {r12, lr}
/* Assert if cache is enabled */
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
@@ -107,7 +107,7 @@
push {r12, lr}
/* Assert if cache is enabled */
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index dc1b6e6..7606b8e 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -53,7 +53,7 @@
/* Get the matching cpu_ops pointer (clobbers: r0 - r5) */
bl get_cpu_ops_ptr
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
cmp r0, #0
ASM_ASSERT(ne)
#endif
@@ -92,7 +92,7 @@
pop {r2, lr}
ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
cmp r0, #0
ASM_ASSERT(ne)
#endif
@@ -118,7 +118,7 @@
cmp r1, #0
bne 1f
bl get_cpu_ops_ptr
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
cmp r0, #0
ASM_ASSERT(ne)
#endif
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 47cb6a2..6a39916 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -55,7 +55,7 @@
/* Get the matching cpu_ops pointer */
bl get_cpu_ops_ptr
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
@@ -94,7 +94,7 @@
mrs x1, tpidr_el3
ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
@@ -120,7 +120,7 @@
cbnz x0, 1f
mov x10, x30
bl get_cpu_ops_ptr
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 675ed66..76e67a3 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -165,7 +165,7 @@
*/
psci_plat_pm_ops->pwr_domain_on_finish(state_info);
-#if !HW_ASSISTED_COHERENCY
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
/*
* Arch. management: Enable data cache and manage stack memory
*/
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index 08c8fd6..bf95df2 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -302,7 +302,7 @@
*/
psci_plat_pm_ops->pwr_domain_suspend_finish(state_info);
-#if !HW_ASSISTED_COHERENCY
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
/* Arch. management: Enable the data cache, stack memory maintenance. */
psci_do_pwrup_cache_maintenance();
#endif
diff --git a/lib/stdlib/assert.c b/lib/stdlib/assert.c
index 3486e50..3c0bd16 100644
--- a/lib/stdlib/assert.c
+++ b/lib/stdlib/assert.c
@@ -32,15 +32,18 @@
#include <debug.h>
#include <platform.h>
-/*
- * This is a basic implementation. This could be improved.
- */
-void __assert (const char *function, const char *file, unsigned int line,
+void __assert(const char *function, const char *file, unsigned int line,
const char *assertion)
{
+#if LOG_LEVEL >= LOG_LEVEL_INFO
+ /*
+ * Only print the output if LOG_LEVEL is higher or equal to
+ * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
+ */
tf_printf("ASSERT: %s <%d> : %s\n", function, line, assertion);
console_flush();
+#endif
plat_panic_handler();
}
diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c
index 316a60e..4fe5bf9 100644
--- a/lib/xlat_tables/aarch32/xlat_tables.c
+++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -85,13 +85,13 @@
static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
-#if DEBUG
+#if ENABLE_ASSERTIONS
static unsigned long long get_max_supported_pa(void)
{
/* Physical address space size for long descriptor format. */
return (1ULL << 40) - 1ULL;
}
-#endif
+#endif /* ENABLE_ASSERTIONS */
void init_xlat_tables(void)
{
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index ecb1202..4f23793 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -127,7 +127,7 @@
return TCR_PS_BITS_4GB;
}
-#if DEBUG
+#if ENABLE_ASSERTIONS
/* Physical Address ranges supported in the AArch64 Memory Model */
static const unsigned int pa_range_bits_arr[] = {
PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
@@ -144,7 +144,7 @@
return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL;
}
-#endif
+#endif /* ENABLE_ASSERTIONS */
void init_xlat_tables(void)
{
diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c
index 81c4dc6..4b25d0e 100644
--- a/lib/xlat_tables/xlat_tables_common.c
+++ b/lib/xlat_tables/xlat_tables_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -109,7 +109,7 @@
assert((base_pa + (unsigned long long)size - 1ULL) <=
(PLAT_PHY_ADDR_SPACE_SIZE - 1));
-#if DEBUG
+#if ENABLE_ASSERTIONS
/* Check for PAs and VAs overlaps with all other regions */
for (mm = mmap; mm->size; ++mm) {
@@ -154,7 +154,7 @@
mm = mmap; /* Restore pointer to the start of the array */
-#endif /* DEBUG */
+#endif /* ENABLE_ASSERTIONS */
/* Find correct place in mmap to insert new region */
while (mm->base_va < base_va && mm->size)
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index ba0e53d..cd7aad8 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -37,13 +37,13 @@
#include <xlat_tables_v2.h>
#include "../xlat_tables_private.h"
-#if DEBUG
+#if ENABLE_ASSERTIONS
static unsigned long long xlat_arch_get_max_supported_pa(void)
{
/* Physical address space size for long descriptor format. */
return (1ull << 40) - 1ull;
}
-#endif /* DEBUG*/
+#endif /* ENABLE_ASSERTIONS*/
int is_mmu_enabled(void)
{
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index 575ac71..24266b2 100644
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -77,7 +77,7 @@
return TCR_PS_BITS_4GB;
}
-#if DEBUG
+#if ENABLE_ASSERTIONS
/* Physical Address ranges supported in the AArch64 Memory Model */
static const unsigned int pa_range_bits_arr[] = {
PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
@@ -94,7 +94,7 @@
return (1ull << pa_range_bits_arr[pa_range]) - 1ull;
}
-#endif /* DEBUG*/
+#endif /* ENABLE_ASSERTIONS*/
int is_mmu_enabled(void)
{
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index e66f511..903363a 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -154,3 +154,9 @@
# Build verbosity
V := 0
+
+# Whether to enable D-Cache early during warm boot. This is usually
+# applicable for platforms wherein interconnect programming is not
+# required to enable cache coherency after warm reset (eg: single cluster
+# platforms).
+WARMBOOT_ENABLE_DCACHE_EARLY := 0
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index ffbf113..c588f96 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -30,13 +30,13 @@
#include <arch.h>
#include <arm_def.h>
+#include <arm_xlat_tables.h>
#include <bl_common.h>
#include <console.h>
#include <platform_def.h>
#include <plat_arm.h>
#include <sp805.h>
#include <utils.h>
-#include <xlat_tables_v2.h>
#include "../../../bl1/bl1_private.h"
/* Weak definitions may be overridden in specific ARM standard platform */
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index aade221..3d67ef7 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -29,12 +29,12 @@
*/
#include <arch.h>
#include <arch_helpers.h>
+#include <arm_xlat_tables.h>
#include <assert.h>
#include <debug.h>
#include <mmio.h>
#include <plat_arm.h>
#include <platform_def.h>
-#include <xlat_tables_v2.h>
extern const mmap_region_t plat_arm_mmap[];
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index f7ec57e..9cf2b7e 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -95,6 +95,11 @@
$(eval $(call assert_boolean,ARM_PLAT_MT))
$(eval $(call add_define,ARM_PLAT_MT))
+# Use translation tables library v2 by default
+ARM_XLAT_TABLES_LIB_V1 := 0
+$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
+$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
+
# Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms
ENABLE_PSCI_STAT := 1
ENABLE_PMF := 1
@@ -113,11 +118,17 @@
PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64
endif
+PLAT_BL_COMMON_SOURCES += plat/arm/common/${ARCH}/arm_helpers.S \
+ plat/arm/common/arm_common.c
+
+ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
+PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/${ARCH}/xlat_tables.c
+else
include lib/xlat_tables_v2/xlat_tables.mk
-PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \
- plat/arm/common/${ARCH}/arm_helpers.S \
- plat/arm/common/arm_common.c
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
+endif
BL1_SOURCES += drivers/arm/sp805/sp805.c \
drivers/io/io_fip.c \
diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S
index e3063d1..322e3bb 100644
--- a/plat/common/aarch64/platform_mp_stack.S
+++ b/plat/common/aarch64/platform_mp_stack.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -131,7 +131,7 @@
* -------------------------------------------------------
*/
func_deprecated platform_get_stack
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
mrs x1, mpidr_el1
cmp x0, x1
ASM_ASSERT(eq)
@@ -150,7 +150,7 @@
* -----------------------------------------------------
*/
func_deprecated platform_set_stack
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
mrs x1, mpidr_el1
cmp x0, x1
ASM_ASSERT(eq)
diff --git a/plat/nvidia/tegra/common/drivers/smmu/smmu.c b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
index a57db8b..e8b0d0b 100644
--- a/plat/nvidia/tegra/common/drivers/smmu/smmu.c
+++ b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
@@ -116,7 +116,7 @@
/* Save SMMU config settings */
memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
- sizeof(smmu_ctx_regs));
+ sizeof(smmu_regs_t));
/* save the SMMU table address */
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,
diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c
index b01dcb0..1e5423d 100644
--- a/plat/nvidia/tegra/common/tegra_sip_calls.c
+++ b/plat/nvidia/tegra/common/tegra_sip_calls.c
@@ -86,7 +86,7 @@
/* Check if this is a SoC specific SiP */
err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
if (err == 0)
- SMC_RET1(handle, err);
+ SMC_RET1(handle, (uint64_t)err);
switch (smc_fid) {
diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
index fa39749..51d3632 100644
--- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
@@ -52,27 +52,27 @@
/*******************************************************************************
* Tegra186 SiP SMCs
******************************************************************************/
-#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01
-#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0x82FFFE02
-#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00
-#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01
-#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02
-#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03
-#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04
-#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05
-#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06
-#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07
-#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08
-#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09
-#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B
-#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C
-#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E
-#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F
-#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10
-#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11
-#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12
+#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01
+#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02
+#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00
+#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01
+#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02
+#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
+#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
+#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
+#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06
+#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
+#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
+#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
+#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A
+#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B
+#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C
+#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D
+#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E
+#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F
+#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10
+#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11
+#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12
/*******************************************************************************
* This function is responsible for handling all T186 SiP calls
@@ -90,9 +90,21 @@
int impl, cpu;
uint32_t base, core_clk_ctr, ref_clk_ctr;
- switch (smc_fid) {
+ if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
+ /* 32-bit function, clear top parameter bits */
+
+ x1 = (uint32_t)x1;
+ x2 = (uint32_t)x2;
+ x3 = (uint32_t)x3;
+ }
/*
+ * Convert SMC FID to SMC64, to support SMC32/SMC64 configurations
+ */
+ smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
+
+ switch (smc_fid) {
+ /*
* Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
* 0x82FFFFFF SiP SMC space
*/
@@ -120,7 +132,8 @@
/* execute the command and store the result */
mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
- write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret);
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0,
+ (uint64_t)mce_ret);
return 0;
@@ -176,8 +189,10 @@
ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET);
/* return the counter values as two different parameters */
- write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, core_clk_ctr);
- write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, ref_clk_ctr);
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1,
+ (uint64_t)core_clk_ctr);
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2,
+ (uint64_t)ref_clk_ctr);
return 0;