tree a225616515156d2e89b35c26556ab335925de21e
parent 89d4538dad5910bb81f705196b177045ad4d409b
author Andre Przywara <andre.przywara@arm.com> 1648123037 +0000
committer Andre Przywara <andre.przywara@arm.com> 1658227510 +0100

fix(morello): dts: fix DP SMMU IRQ ordering

The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@2ce00000: interrupt-names: 'oneOf' conditional failed, one must be fixed:
        ['eventq', 'cmdq-sync', 'gerror'] is too long
        'combined' was expected
        'gerror' was expected
        'priq' was expected
        'cmdq-sync' was expected
        From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
============

Swap the order of the interrupts to improve bindings compliance.

Actually in this case the binding needs to be extended, since PRI is not
implemented in the SMMU in this case, so the PRI IRQ should be optional,
but we still want to describe the CMDQ sync IRQ. A patch for the binding
is pending.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I3978f1c087136cd4c2e8f7fd4d1bba5b95f72726