Merge pull request #1530 from antonio-nino-diaz-arm/an/rpi3-deprecated
rpi3: Migrate from deprecated APIs
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index 9a46a34..ec7d728 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -17,7 +17,8 @@
${MBEDTLS_SOURCES}
ifeq (${ARCH},aarch64)
-BL1_SOURCES += lib/el3_runtime/aarch64/context.S
+BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \
+ lib/el3_runtime/aarch64/context.S
endif
ifeq (${TRUSTED_BOARD_BOOT},1)
diff --git a/bl2/bl2.mk b/bl2/bl2.mk
index 7e33703..af30a81 100644
--- a/bl2/bl2.mk
+++ b/bl2/bl2.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -29,5 +29,10 @@
bl2/${ARCH}/bl2_el3_exceptions.S \
lib/cpus/${ARCH}/cpu_helpers.S \
lib/cpus/errata_report.c
+
+ifeq (${ARCH},aarch64)
+BL2_SOURCES += lib/cpus/aarch64/dsu_helpers.S
+endif
+
BL2_LINKERFILE := bl2/bl2_el3.ld.S
endif
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index bff9653..066c701 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -24,6 +24,7 @@
bl31/bl31_context_mgmt.c \
common/runtime_svc.c \
lib/aarch64/setjmp.S \
+ lib/cpus/aarch64/dsu_helpers.S \
plat/common/aarch64/platform_mp_stack.S \
services/arm_arch_svc/arm_arch_svc_setup.c \
services/std_svc/std_svc_setup.c \
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index c11f640..151c99e 100644
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -68,10 +68,10 @@
with different revisions of a processor has no runtime mechanism available
for it to specify which errata workarounds should be enabled or not.
-The value of the build flags are 0 by default, that is, disabled. Any other
-value will enable it.
+The value of the build flags is 0 by default, that is, disabled. A value of 1
+will enable it.
-For Cortex-A53, following errata build flags are defined :
+For Cortex-A53, the following errata build flags are defined :
- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
@@ -97,7 +97,7 @@
Earlier revisions of the CPU have other errata which require the same
workaround in software, so they should be covered anyway.
-For Cortex-A57, following errata build flags are defined :
+For Cortex-A57, the following errata build flags are defined :
- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
CPU. This needs to be enabled only for revision r0p0 of the CPU.
@@ -127,11 +127,33 @@
CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
-For Cortex-A72, following errata build flags are defined :
+For Cortex-A72, the following errata build flags are defined :
- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
+DSU Errata Workarounds
+----------------------
+
+Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
+Shared Unit) errata. The DSU errata details can be found in the respective Arm
+documentation:
+
+- `Arm DSU Software Developers Errata Notice`_.
+
+Each erratum is identified by an ``ID``, as defined in the DSU errata notice
+document. Thus, the build flags which enable/disable the errata workarounds
+have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
+of DSU errata workarounds are similar to `CPU errata workarounds`_.
+
+For DSU errata, the following build flags are defined:
+
+- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
+ affected DSU configurations. This errata applies only for those DSUs that
+ contain the ACP interface **and** the DSU revision is older than r2p0 (on
+ r2p0 it is fixed). However, please note that this workaround results in
+ increased DSU power consumption on idle.
+
CPU Specific optimizations
--------------------------
@@ -171,3 +193,4 @@
.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
.. _Firmware Design guide: firmware-design.rst
.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
+.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html
\ No newline at end of file
diff --git a/docs/psci-pd-tree.rst b/docs/psci-pd-tree.rst
index 1113abc..9653725 100644
--- a/docs/psci-pd-tree.rst
+++ b/docs/psci-pd-tree.rst
@@ -1,5 +1,5 @@
-PSCI Library Integration guide for Armv8-A AArch32 systems
-==========================================================
+PSCI Power Domain Tree design
+=============================
.. section-numbering::
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 2b90bec..46370ce 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -67,8 +67,9 @@
In addition, the following optional packages and tools may be needed:
-- ``device-tree-compiler`` package if you need to rebuild the Flattened Device
- Tree (FDT) source files (``.dts`` files) provided with this software.
+- ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
+ Tree (FDT) source files (``.dts`` files) provided with this software. The
+ version of dtc must be 1.4.6 or above.
- For debugging, Arm `Development Studio 5 (DS-5)`_.
diff --git a/drivers/console/aarch64/multi_console.S b/drivers/console/aarch64/multi_console.S
index 0464776..7f076c6 100644
--- a/drivers/console/aarch64/multi_console.S
+++ b/drivers/console/aarch64/multi_console.S
@@ -39,10 +39,11 @@
* persistent memory (e.g. the data section).
* In : x0 - address of console_t structure
* Out: x0 - Always 1 (for easier tail calling)
- * Clobber list: x0, x1, x14, x15
+ * Clobber list: x0, x1
* -----------------------------------------------
*/
func console_register
+ stp x21, x30, [sp, #-16]!
#if ENABLE_ASSERTIONS
/* Assert that x0 isn't a NULL pointer */
cmp x0, #0
@@ -59,18 +60,17 @@
not_on_stack:
/* Assert that this struct isn't in the list */
mov x1, x0 /* Preserve x0 and x30 */
- mov x15, x30
bl console_is_registered
cmp x0, #0
ASM_ASSERT(eq)
- mov x30, x15
mov x0, x1
#endif /* ENABLE_ASSERTIONS */
- adrp x14, console_list
- ldr x1, [x14, :lo12:console_list] /* X1 = first struct in list */
- str x0, [x14, :lo12:console_list] /* list head = new console */
+ adrp x21, console_list
+ ldr x1, [x21, :lo12:console_list] /* X1 = first struct in list */
+ str x0, [x21, :lo12:console_list] /* list head = new console */
str x1, [x0, #CONSOLE_T_NEXT] /* new console next ptr = X1 */
mov x0, #1
+ ldp x21, x30, [sp], #16
ret
endfunc console_register
@@ -80,7 +80,7 @@
* of currently active consoles and remove it.
* In: x0 - address of console_t struct to remove
* Out: x0 - removed address, or NULL if not found
- * Clobber list: x0, x1, x14
+ * Clobber list: x0, x1
* -----------------------------------------------
*/
func console_unregister
@@ -89,25 +89,28 @@
cmp x0, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
- adrp x14, console_list
- add x14, x14, :lo12:console_list /* X14 = ptr to first struct */
- ldr x1, [x14] /* X1 = first struct */
+ stp x21, xzr, [sp, #-16]!
+ adrp x21, console_list
+ add x21, x21, :lo12:console_list /* X21 = ptr to first struct */
+ ldr x1, [x21] /* X1 = first struct */
unregister_loop:
cbz x1, unregister_not_found
cmp x0, x1
b.eq unregister_found
- ldr x14, [x14] /* X14 = next ptr of struct */
- ldr x1, [x14] /* X1 = next struct */
+ ldr x21, [x21] /* X21 = next ptr of struct */
+ ldr x1, [x21] /* X1 = next struct */
b unregister_loop
unregister_found:
ldr x1, [x1] /* X1 = next struct */
- str x1, [x14] /* prev->next = cur->next */
+ str x1, [x21] /* prev->next = cur->next */
+ ldp x21, xzr, [sp], #16
ret
unregister_not_found:
mov x0, #0 /* return NULL if not found */
+ ldp x21, xzr, [sp], #16
ret
endfunc console_unregister
@@ -117,7 +120,7 @@
* registered or not.
* In: x0 - address of console_t struct to remove
* Out: x0 - 1 if it is registered, 0 if not.
- * Clobber list: x0, x14
+ * Clobber list: x0
* -----------------------------------------------
*/
func console_is_registered
@@ -126,19 +129,22 @@
cmp x0, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
- adrp x14, console_list
- ldr x14, [x14, :lo12:console_list] /* X14 = first console struct */
+ stp x21, xzr, [sp, #-16]!
+ adrp x21, console_list
+ ldr x21, [x21, :lo12:console_list] /* X21 = first console struct */
check_registered_loop:
- cbz x14, console_not_registered /* Check if end of list */
- cmp x0, x14 /* Check if the pointers are different */
+ cbz x21, console_not_registered /* Check if end of list */
+ cmp x0, x21 /* Check if the pointers are different */
b.eq console_registered
- ldr x14, [x14, #CONSOLE_T_NEXT] /* Get pointer to next struct */
+ ldr x21, [x21, #CONSOLE_T_NEXT] /* Get pointer to next struct */
b check_registered_loop
console_not_registered:
mov x0, #0
+ ldp x21, xzr, [sp], #16
ret
console_registered:
mov x0, #1
+ ldp x21, xzr, [sp], #16
ret
endfunc console_is_registered
@@ -186,38 +192,41 @@
* In : x0 - character to be printed
* Out: x0 - printed character on success, or < 0
if at least one console had an error
- * Clobber list : x0, x1, x2, x12, x13, x14, x15
+ * Clobber list : x0, x1, x2
* ---------------------------------------------
*/
func console_putc
- mov x15, x30
- mov w13, #ERROR_NO_VALID_CONSOLE /* W13 = current return value */
- mov w12, w0 /* W12 = character to print */
- adrp x14, console_list
- ldr x14, [x14, :lo12:console_list] /* X14 = first console struct */
+ stp x21, x30, [sp, #-16]!
+ stp x19, x20, [sp, #-16]!
+ mov w20, #ERROR_NO_VALID_CONSOLE /* W20 = current return value */
+ mov w19, w0 /* W19 = character to print */
+ adrp x21, console_list
+ ldr x21, [x21, :lo12:console_list] /* X21 = first console struct */
putc_loop:
- cbz x14, putc_done
+ cbz x21, putc_done
adrp x1, console_state
ldrb w1, [x1, :lo12:console_state]
- ldr w2, [x14, #CONSOLE_T_FLAGS]
+ ldr w2, [x21, #CONSOLE_T_FLAGS]
tst w1, w2
b.eq putc_continue
- ldr x2, [x14, #CONSOLE_T_PUTC]
+ ldr x2, [x21, #CONSOLE_T_PUTC]
cbz x2, putc_continue
- mov w0, w12
- mov x1, x14
+ mov w0, w19
+ mov x1, x21
blr x2
- cmp w13, #ERROR_NO_VALID_CONSOLE /* update W13 if it's NOVALID */
+ cmp w20, #ERROR_NO_VALID_CONSOLE /* update W20 if it's NOVALID */
ccmp w0, #0, #0x8, ne /* else update it if W0 < 0 */
- csel w13, w0, w13, lt
+ csel w20, w0, w20, lt
putc_continue:
- ldr x14, [x14] /* X14 = next struct */
+ ldr x21, [x21] /* X21 = next struct */
b putc_loop
putc_done:
- mov w0, w13
- ret x15
+ mov w0, w20
+ ldp x19, x20, [sp], #16
+ ldp x21, x30, [sp], #16
+ ret
endfunc console_putc
/* ---------------------------------------------
@@ -230,42 +239,47 @@
* if all active consoles report real errors
* (other than just not having a char available).
* Out : x0 - read character, or < 0 on error
- * Clobber list : x0, x1, x13, x14, x15
+ * Clobber list : x0, x1
* ---------------------------------------------
*/
func console_getc
- mov x15, x30
+ stp x30, xzr, [sp, #-16]!
+ stp x20, x21, [sp, #-16]!
getc_try_again:
- mov w13, #ERROR_NO_VALID_CONSOLE /* W13 = current return value */
- adrp x14, console_list
- ldr x14, [x14, :lo12:console_list] /* X14 = first console struct */
- cbnz x14, getc_loop
- mov w0, w13 /* If no consoles registered */
- ret x15 /* return immediately. */
+ mov w20, #ERROR_NO_VALID_CONSOLE /* W20 = current return value */
+ adrp x21, console_list
+ ldr x21, [x21, :lo12:console_list] /* X21 = first console struct */
+ cbnz x21, getc_loop
+ mov w0, w20 /* If no consoles registered */
+ ldp x20, x21, [sp], #16
+ ldp x30, xzr, [sp], #16
+ ret /* return immediately. */
getc_loop:
adrp x0, console_state
ldrb w0, [x0, :lo12:console_state]
- ldr w1, [x14, #CONSOLE_T_FLAGS]
+ ldr w1, [x21, #CONSOLE_T_FLAGS]
tst w0, w1
b.eq getc_continue
- ldr x1, [x14, #CONSOLE_T_GETC]
+ ldr x1, [x21, #CONSOLE_T_GETC]
cbz x1, getc_continue
- mov x0, x14
+ mov x0, x21
blr x1
cmp w0, #0 /* if X0 >= 0: return */
b.ge getc_found
- cmp w13, #ERROR_NO_PENDING_CHAR /* may update W13 (NOCHAR has */
- csel w13, w13, w0, eq /* precedence vs real errors) */
+ cmp w20, #ERROR_NO_PENDING_CHAR /* may update W20 (NOCHAR has */
+ csel w20, w20, w0, eq /* precedence vs real errors) */
getc_continue:
- ldr x14, [x14] /* X14 = next struct */
- cbnz x14, getc_loop
- cmp w13, #ERROR_NO_PENDING_CHAR /* Keep scanning if at least */
+ ldr x21, [x21] /* X21 = next struct */
+ cbnz x21, getc_loop
+ cmp w20, #ERROR_NO_PENDING_CHAR /* Keep scanning if at least */
b.eq getc_try_again /* one console returns NOCHAR */
- mov w0, w13
+ mov w0, w20
getc_found:
- ret x15
+ ldp x20, x21, [sp], #16
+ ldp x30, xzr, [sp], #16
+ ret
endfunc console_getc
/* ---------------------------------------------
@@ -274,34 +288,37 @@
* data that hasn't been output. Calls all
* console's flush() handlers in succession.
* Out: x0 - 0 on success, < 0 if at least one error
- * Clobber list : x0, x1, x2, x3, x4, x5, x13, x14, x15
+ * Clobber list : x0, x1, x2
* ---------------------------------------------
*/
func console_flush
- mov x15, x30
- mov w13, #ERROR_NO_VALID_CONSOLE /* W13 = current return value */
- adrp x14, console_list
- ldr x14, [x14, :lo12:console_list] /* X14 = first console struct */
+ stp x30, xzr, [sp, #-16]!
+ stp x20, x21, [sp, #-16]!
+ mov w20, #ERROR_NO_VALID_CONSOLE /* W20 = current return value */
+ adrp x21, console_list
+ ldr x21, [x21, :lo12:console_list] /* X21 = first console struct */
flush_loop:
- cbz x14, flush_done
+ cbz x21, flush_done
adrp x1, console_state
ldrb w1, [x1, :lo12:console_state]
- ldr w2, [x14, #CONSOLE_T_FLAGS]
+ ldr w2, [x21, #CONSOLE_T_FLAGS]
tst w1, w2
b.eq flush_continue
- ldr x1, [x14, #CONSOLE_T_FLUSH]
+ ldr x1, [x21, #CONSOLE_T_FLUSH]
cbz x1, flush_continue
- mov x0, x14
+ mov x0, x21
blr x1
- cmp w13, #ERROR_NO_VALID_CONSOLE /* update W13 if it's NOVALID */
+ cmp w20, #ERROR_NO_VALID_CONSOLE /* update W20 if it's NOVALID */
ccmp w0, #0, #0x8, ne /* else update it if W0 < 0 */
- csel w13, w0, w13, lt
+ csel w20, w0, w20, lt
flush_continue:
- ldr x14, [x14] /* X14 = next struct */
+ ldr x21, [x21] /* X21 = next struct */
b flush_loop
flush_done:
- mov w0, w13
- ret x15
+ mov w0, w20
+ ldp x20, x21, [sp], #16
+ ldp x30, xzr, [sp], #16
+ ret
endfunc console_flush
diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
new file mode 100644
index 0000000..0e2d93a
--- /dev/null
+++ b/include/lib/cpus/aarch64/dsu_def.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DSU_DEF_H
+#define DSU_DEF_H
+
+#include <utils_def.h>
+
+/********************************************************************
+ * DSU control registers definitions *
+ ********************************************************************/
+#define CLUSTERCFR_EL1 S3_0_C15_C3_0
+#define CLUSTERIDR_EL1 S3_0_C15_C3_1
+#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
+
+/********************************************************************
+ * DSU control registers bit fields *
+ ********************************************************************/
+#define CLUSTERIDR_REV_SHIFT U(0)
+#define CLUSTERIDR_REV_BITS U(4)
+#define CLUSTERIDR_VAR_SHIFT U(4)
+#define CLUSTERIDR_VAR_BITS U(4)
+#define CLUSTERCFR_ACP_SHIFT U(11)
+
+/********************************************************************
+ * Masks applied for DSU errata workarounds *
+ ********************************************************************/
+#define DSU_ERRATA_936184_MASK (ULL(0x3) << 15)
+
+#endif /* DSU_DEF_H */
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index 741c773..4e9bd9f 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,14 @@
#include <cpu_macros.S>
#include <plat_macros.S>
+func cortex_a55_reset_func
+ mov x19, x30
+#if ERRATA_DSU_936184
+ bl errata_dsu_936184_wa
+#endif
+ ret x19
+endfunc cortex_a55_reset_func
+
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
@@ -27,6 +35,26 @@
ret
endfunc cortex_a55_core_pwr_dwn
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex A55. Must follow AAPCS & can use stack.
+ */
+func cortex_a55_errata_report
+ stp x8, x30, [sp, #-16]!
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision variant information is at x8, where
+ * "report_errata" is expecting it and it doesn't corrupt it.
+ */
+ report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
+
+ ldp x8, x30, [sp], #16
+ ret
+endfunc cortex_a55_errata_report
+#endif
+
/* ---------------------------------------------
* This function provides cortex_a55 specific
* register information for crash reporting.
@@ -47,5 +75,5 @@
endfunc cortex_a55_cpu_reg_dump
declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \
- CPU_NO_RESET_FUNC, \
+ cortex_a55_reset_func, \
cortex_a55_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 73f566f..e121b7d 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -11,6 +11,7 @@
#include <cpu_macros.S>
func cortex_a75_reset_func
+ mov x19, x30
#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_bpiall_vbar
@@ -26,6 +27,10 @@
isb
#endif
+#if ERRATA_DSU_936184
+ bl errata_dsu_936184_wa
+#endif
+
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@@ -49,7 +54,7 @@
msr CPUAMCNTENSET_EL0, x0
isb
#endif
- ret
+ ret x19
endfunc cortex_a75_reset_func
func check_errata_cve_2017_5715
@@ -106,6 +111,7 @@
*/
report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
+ report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 51d0b15..1697c55 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -207,6 +207,7 @@
endfunc cortex_a76_disable_wa_cve_2018_3639
func cortex_a76_reset_func
+ mov x19, x30
#if WORKAROUND_CVE_2018_3639
mrs x0, CORTEX_A76_CPUACTLR2_EL1
orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
@@ -224,7 +225,11 @@
msr vbar_el3, x0
isb
#endif
- ret
+
+#if ERRATA_DSU_936184
+ bl errata_dsu_936184_wa
+#endif
+ ret x19
endfunc cortex_a76_reset_func
/* ---------------------------------------------
@@ -258,6 +263,7 @@
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
+ report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index f04dbd6..a981d02 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -189,6 +189,25 @@
ret
endfunc denver_disable_dco
+func check_errata_cve_2017_5715
+ mov x0, #ERRATA_MISSING
+#if WORKAROUND_CVE_2017_5715
+ /*
+ * Check if the CPU supports the special instruction
+ * required to flush the indirect branch predictor and
+ * RSB. Support for this operation can be determined by
+ * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001.
+ */
+ mrs x1, id_afr0_el1
+ mov x2, #0x10000
+ and x1, x1, x2
+ cbz x1, 1f
+ mov x0, #ERRATA_APPLIES
+1:
+#endif
+ ret
+endfunc check_errata_cve_2017_5715
+
/* -------------------------------------------------
* The CPU Ops reset function for Denver.
* -------------------------------------------------
@@ -248,6 +267,27 @@
ret
endfunc denver_cluster_pwr_dwn
+#if REPORT_ERRATA
+ /*
+ * Errata printing function for Denver. Must follow AAPCS.
+ */
+func denver_errata_report
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715
+
+ ldp x8, x30, [sp], #16
+ ret
+endfunc denver_errata_report
+#endif
+
/* ---------------------------------------------
* This function provides Denver specific
* register information for crash reporting.
@@ -267,27 +307,37 @@
ret
endfunc denver_cpu_reg_dump
-declare_cpu_ops denver, DENVER_MIDR_PN0, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN0, \
denver_reset_func, \
+ check_errata_cve_2017_5715, \
+ CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
-declare_cpu_ops denver, DENVER_MIDR_PN1, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN1, \
denver_reset_func, \
+ check_errata_cve_2017_5715, \
+ CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
-declare_cpu_ops denver, DENVER_MIDR_PN2, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN2, \
denver_reset_func, \
+ check_errata_cve_2017_5715, \
+ CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
-declare_cpu_ops denver, DENVER_MIDR_PN3, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN3, \
denver_reset_func, \
+ check_errata_cve_2017_5715, \
+ CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
-declare_cpu_ops denver, DENVER_MIDR_PN4, \
+declare_cpu_ops_wa denver, DENVER_MIDR_PN4, \
denver_reset_func, \
+ check_errata_cve_2017_5715, \
+ CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/dsu_helpers.S b/lib/cpus/aarch64/dsu_helpers.S
new file mode 100644
index 0000000..293ed24
--- /dev/null
+++ b/lib/cpus/aarch64/dsu_helpers.S
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <dsu_def.h>
+#include <errata_report.h>
+
+/*
+ * DSU erratum 936184
+ * Check the DSU variant, revision and configuration to determine if the
+ * erratum applies. This erratum was fixed in r2p0.
+ *
+ * This function is called from both assembly and C environment. So it
+ * follows AAPCS.
+ *
+ * Clobbers: x0-x3
+ */
+ .globl check_errata_dsu_936184
+ .globl errata_dsu_936184_wa
+
+func check_errata_dsu_936184
+ mov x2, #ERRATA_NOT_APPLIES
+ mov x3, #ERRATA_APPLIES
+
+ /* Erratum applies only if ACP interface is present in DSU */
+ mov x0, x2
+ mrs x1, CLUSTERCFR_EL1
+ ubfx x1, x1, #CLUSTERCFR_ACP_SHIFT, #1
+ cbz x1, 1f
+
+ /* If ACP is present, check if DSU is older than r2p0 */
+ mrs x1, CLUSTERIDR_EL1
+
+ /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */
+ ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\
+ #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS)
+ mov x1, #(0x2 << CLUSTERIDR_REV_BITS)
+ cmp x0, x1
+ csel x0, x2, x3, hs
+1:
+ ret
+endfunc check_errata_dsu_936184
+
+func errata_dsu_936184_wa
+ mov x20, x30
+ bl check_errata_dsu_936184
+ cbz x0, 1f
+
+ /* If erratum applies, we set a mask to a DSU control register */
+ mrs x0, CLUSTERACTLR_EL1
+ ldr x1, =DSU_ERRATA_936184_MASK
+ orr x0, x0, x1
+ msr CLUSTERACTLR_EL1, x0
+ isb
+1:
+ ret x20
+endfunc errata_dsu_936184_wa
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 456e3e5..40a8ac7 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -123,6 +123,11 @@
# only to r0p0 and r1p0 of the Ares cpu.
ERRATA_ARES_1043202 ?=1
+# Flag to apply DSU erratum 936184. This erratum applies to DSUs containing
+# the ACP interface and revision < r2p0. Applying the workaround results in
+# higher DSU power consumption on idle.
+ERRATA_DSU_936184 ?=0
+
# Process ERRATA_A53_826319 flag
$(eval $(call assert_boolean,ERRATA_A53_826319))
$(eval $(call add_define,ERRATA_A53_826319))
@@ -187,6 +192,10 @@
$(eval $(call assert_boolean,ERRATA_ARES_1043202))
$(eval $(call add_define,ERRATA_ARES_1043202))
+# Process ERRATA_DSU_936184 flag
+$(eval $(call assert_boolean,ERRATA_DSU_936184))
+$(eval $(call add_define,ERRATA_DSU_936184))
+
# Errata build flags
ifneq (${ERRATA_A53_843419},0)
TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index d63ae9a..af47c0d 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -12,13 +12,7 @@
BL1_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c
-BL2_SOURCES += lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c \
- plat/arm/board/common/drivers/norflash/norflash.c
-
-BL31_SOURCES += lib/utils/mem_region.c \
- plat/arm/board/common/drivers/norflash/norflash.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
+BL2_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c
ifneq (${TRUSTED_BOARD_BOOT},0)
ifneq (${ARM_CRYPTOCELL_INTEG}, 1)
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 2b1e0ac..fd93b99 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -134,13 +134,17 @@
BL2_SOURCES += drivers/io/io_semihosting.c \
+ lib/utils/mem_region.c \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/arm/board/fvp/fvp_bl2_setup.c \
plat/arm/board/fvp/fvp_io_storage.c \
plat/arm/board/fvp/fvp_trusted_boot.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c \
${FVP_SECURITY_SOURCES}
+
+
ifeq (${BL2_AT_EL3},1)
BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
plat/arm/board/fvp/fvp_bl2_el3_setup.c \
@@ -156,11 +160,14 @@
${FVP_SECURITY_SOURCES}
BL31_SOURCES += drivers/arm/smmu/smmu_v3.c \
+ lib/utils/mem_region.c \
plat/arm/board/fvp/fvp_bl31_setup.c \
plat/arm/board/fvp/fvp_pm.c \
plat/arm/board/fvp/fvp_topology.c \
plat/arm/board/fvp/aarch64/fvp_helpers.S \
plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \
+ plat/arm/board/common/drivers/norflash/norflash.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c \
${FVP_CPU_LIBS} \
${FVP_GIC_SOURCES} \
${FVP_INTERCONNECT_SOURCES} \
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 3ab99ef..16390fa 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -59,7 +59,9 @@
${JUNO_INTERCONNECT_SOURCES} \
${JUNO_SECURITY_SOURCES}
-BL2_SOURCES += plat/arm/board/juno/juno_bl2_setup.c \
+BL2_SOURCES += lib/utils/mem_region.c \
+ plat/arm/board/juno/juno_bl2_setup.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c \
${JUNO_SECURITY_SOURCES}
BL2U_SOURCES += ${JUNO_SECURITY_SOURCES}
@@ -67,7 +69,10 @@
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
+ lib/utils/mem_region.c \
plat/arm/board/juno/juno_topology.c \
+ plat/arm/board/common/drivers/norflash/norflash.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c \
${JUNO_GIC_SOURCES} \
${JUNO_INTERCONNECT_SOURCES} \
${JUNO_SECURITY_SOURCES}
diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk
index 9893ba5..284bae8 100644
--- a/plat/arm/board/sgi575/platform.mk
+++ b/plat/arm/board/sgi575/platform.mk
@@ -5,3 +5,10 @@
#
include plat/arm/css/sgi/sgi-common.mk
+
+BL2_SOURCES += lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES += lib/utils/mem_region.c \
+ plat/arm/board/common/drivers/norflash/norflash.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk
index 71e71e1..633cee6 100644
--- a/plat/arm/board/sgm775/platform.mk
+++ b/plat/arm/board/sgm775/platform.mk
@@ -11,3 +11,10 @@
FDT_SOURCES += ${SGM775_BASE}/fdts/sgm775_tb_fw_config.dts
PLAT_INCLUDES +=-I${SGM775_BASE}/include/
+
+BL2_SOURCES += lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES += lib/utils/mem_region.c \
+ plat/arm/board/common/drivers/norflash/norflash.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index f415f87..f0136b0 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -18,7 +18,7 @@
.globl platform_cpu_warmboot
.globl plat_secondary_cold_boot_setup
.globl plat_report_exception
- .globl platform_is_primary_cpu
+ .globl plat_is_my_cpu_primary
.globl plat_my_core_pos
.globl plat_reset_handler
.globl plat_panic_handler
@@ -73,12 +73,13 @@
b cb_panic
endfunc plat_secondary_cold_boot_setup
-func platform_is_primary_cpu
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
cmp x0, #PLAT_RK_PRIMARY_CPU
cset x0, eq
ret
-endfunc platform_is_primary_cpu
+endfunc plat_is_my_cpu_primary
/* --------------------------------------------------------------------
* void plat_panic_handler(void)
diff --git a/plat/rpi3/include/plat_macros.S b/plat/rpi3/include/plat_macros.S
index f5e057e..c0c3967 100644
--- a/plat/rpi3/include/plat_macros.S
+++ b/plat/rpi3/include/plat_macros.S
@@ -1,13 +1,10 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __PLAT_MACROS_S__
-#define __PLAT_MACROS_S__
-
-#include <arm_macros.S>
-#include <platform_def.h>
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
/* ---------------------------------------------
* The below required platform porting macro
@@ -20,4 +17,4 @@
.macro plat_crash_print_regs
.endm
-#endif /* __PLAT_MACROS_S__ */
+#endif /* PLAT_MACROS_S */
diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk
index 8eb467e..d6d0d56 100644
--- a/plat/rpi3/platform.mk
+++ b/plat/rpi3/platform.mk
@@ -5,8 +5,6 @@
#
PLAT_INCLUDES := -Iinclude/common/tbbr \
- -Iinclude/plat/arm/common/ \
- -Iinclude/plat/arm/common/aarch64/ \
-Iplat/rpi3/include
PLAT_BL_COMMON_SOURCES := drivers/console/aarch64/console.S \