Merge "FDT wrappers: add functions for read/write bytes" into integration
diff --git a/.gitignore b/.gitignore
index 2abfffb..64b389b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -34,3 +34,7 @@
GRTAGS
GSYMS
GTAGS
+
+# Ctags
+tags
+
diff --git a/Makefile b/Makefile
index bd52c0b..5167d2e 100644
--- a/Makefile
+++ b/Makefile
@@ -255,7 +255,7 @@
# General warnings
WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
-Wdisabled-optimization -Wvla -Wshadow \
- -Wno-unused-parameter
+ -Wno-unused-parameter -Wredundant-decls
# Additional warnings
# Level 1
@@ -274,7 +274,6 @@
WARNING3 += -Wconversion
WARNING3 += -Wpacked
WARNING3 += -Wpointer-arith
-WARNING3 += -Wredundant-decls
WARNING3 += -Wswitch-default
ifeq (${W},1)
@@ -604,6 +603,14 @@
endif
endif
+ifeq ($(MEASURED_BOOT),1)
+ ifneq (${TRUSTED_BOARD_BOOT},1)
+ $(error MEASURED_BOOT requires TRUSTED_BOARD_BOOT=1")
+ else
+ $(info MEASURED_BOOT is an experimental feature)
+ endif
+endif
+
################################################################################
# Process platform overrideable behaviour
################################################################################
@@ -695,6 +702,9 @@
PRINT_MEMORY_MAP_PATH ?= tools/memory
PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py
+# Variables for use with documentation build using Sphinx tool
+DOCS_PATH ?= docs
+
################################################################################
# Include BL specific makefiles
################################################################################
@@ -751,6 +761,7 @@
$(eval $(call assert_boolean,GICV2_G0_FOR_EL3))
$(eval $(call assert_boolean,HANDLE_EA_EL3_FIRST))
$(eval $(call assert_boolean,HW_ASSISTED_COHERENCY))
+$(eval $(call assert_boolean,MEASURED_BOOT))
$(eval $(call assert_boolean,NS_TIMER_SWITCH))
$(eval $(call assert_boolean,OVERRIDE_LIBC))
$(eval $(call assert_boolean,PL011_GENERIC_UART))
@@ -817,6 +828,7 @@
$(eval $(call add_define,HANDLE_EA_EL3_FIRST))
$(eval $(call add_define,HW_ASSISTED_COHERENCY))
$(eval $(call add_define,LOG_LEVEL))
+$(eval $(call add_define,MEASURED_BOOT))
$(eval $(call add_define,NS_TIMER_SWITCH))
$(eval $(call add_define,PL011_GENERIC_UART))
$(eval $(call add_define,PLAT_${PLAT}))
@@ -869,7 +881,7 @@
# Build targets
################################################################################
-.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs memmap
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs memmap doc
.SUFFIXES:
all: msg_start
@@ -1009,7 +1021,7 @@
.PHONY: ${CRTTOOL}
${CRTTOOL}:
- ${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} --no-print-directory -C ${CRTTOOLPATH}
+ ${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} --no-print-directory -C ${CRTTOOLPATH}
@${ECHO_BLANK_LINE}
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
@@ -1067,6 +1079,10 @@
memmap: all
${Q}${PYTHON} $(PRINT_MEMORY_MAP) $(BUILD_PLAT)
+doc:
+ @echo " BUILD DOCUMENTATION"
+ ${Q}${MAKE} --no-print-directory -C ${DOCS_PATH} html
+
cscope:
@echo " CSCOPE"
${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
@@ -1107,6 +1123,7 @@
@echo " sptool Build the Secure Partition Package creation tool"
@echo " dtbs Build the Device Tree Blobs (if required for the platform)"
@echo " memmap Print the memory map of the built binaries"
+ @echo " doc Build html based documentation using Sphinx tool"
@echo ""
@echo "Note: most build targets require PLAT to be set to a specific platform."
@echo ""
diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c
index e6efad3..b8cc3de 100644
--- a/bl31/interrupt_mgmt.c
+++ b/bl31/interrupt_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,6 +17,11 @@
* registered interrupt handlers for each interrupt type.
* The field descriptions are:
*
+ * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the
+ * value of the SCR_EL3.IRQ or FIQ bit for each security state.
+ * There are two instances of this field corresponding to the
+ * two security states.
+ *
* 'flags' : Bit[0], Routing model for this interrupt type when execution is
* not in EL3 in the secure state. '1' implies that this
* interrupt will be routed to EL3. '0' implies that this
@@ -28,16 +33,11 @@
* interrupt will be routed to the current exception level.
*
* All other bits are reserved and SBZ.
- *
- * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the
- * value of the SCR_EL3.IRQ or FIQ bit for each security state.
- * There are two instances of this field corresponding to the
- * two security states.
******************************************************************************/
typedef struct intr_type_desc {
interrupt_type_handler_t handler;
+ u_register_t scr_el3[2];
uint32_t flags;
- uint32_t scr_el3[2];
} intr_type_desc_t;
static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES];
@@ -78,9 +78,9 @@
* routing model (expressed through the IRQ and FIQ bits) for a security state
* which was stored through a call to 'set_routing_model()' earlier.
******************************************************************************/
-uint32_t get_scr_el3_from_routing_model(uint32_t security_state)
+u_register_t get_scr_el3_from_routing_model(uint32_t security_state)
{
- uint32_t scr_el3;
+ u_register_t scr_el3;
assert(sec_state_is_valid(security_state));
scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state];
@@ -103,7 +103,7 @@
flag = get_interrupt_rm_flag(interrupt_type_flags, security_state);
bit_pos = plat_interrupt_type_to_line(type, security_state);
- intr_type_descs[type].scr_el3[security_state] = flag << bit_pos;
+ intr_type_descs[type].scr_el3[security_state] = (u_register_t)flag << bit_pos;
/*
* Update scr_el3 only if there is a context available. If not, it
diff --git a/docs/change-log-upcoming.rst b/docs/change-log-upcoming.rst
index 3d7d509..14280cb 100644
--- a/docs/change-log-upcoming.rst
+++ b/docs/change-log-upcoming.rst
@@ -23,7 +23,7 @@
- Example: "Add support for Branch Target Identification (BTI)"
- Build System
- - Example: "Add support for default stack-protector flag"
+ - Add support for documentation build as a target in Makefile
- CPU Support
- Example: "cortex-a55: Workaround for erratum 1221012"
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index fc45455..2f44fe8 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -128,6 +128,9 @@
``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
to be implemented in this case.
+- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
+ Defaults to ``tbbr``.
+
- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
register state when an unexpected exception occurs during execution of
BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
@@ -387,6 +390,11 @@
All log output up to and including the selected log level is compiled into
the build. The default value is 40 in debug builds and 20 in release builds.
+- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
+ feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set.
+ This option defaults to 0 and is an experimental feature in the stage of
+ development.
+
- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
specifies the file that contains the Non-Trusted World private key in PEM
format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index c5625e9..91b1b3a 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst
@@ -56,21 +56,28 @@
Building rendered documentation
-------------------------------
-From the ``docs`` directory of the project, run the following commands. It is
-important to note that you will not get the correct result if the commands are
-run from the project root directory, as that would invoke the top-level Makefile
-for |TF-A| itself.
+Documents can be built into HTML-formatted pages from project root directory by
+running the following command.
.. code:: shell
- make clean
- make html
+ make doc
Output from the build process will be placed in:
::
- <tf-a root>/docs/build/html/
+ docs/build/html/
+
+We also support building documentation in other formats. From the ``docs``
+directory of the project, run the following command to see the supported
+formats. It is important to note that you will not get the correct result if
+the command is run from the project root directory, as that would invoke the
+top-level Makefile for |TF-A| itself.
+
+.. code:: shell
+
+ make help
--------------
diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst
index 4ebe64b..88196bc 100644
--- a/docs/plat/qemu.rst
+++ b/docs/plat/qemu.rst
@@ -10,7 +10,11 @@
BL2 edits the Flattened Device Tree, FDT, generated by QEMU at run-time to
add a node describing PSCI and also enable methods for the CPUs.
-An ARM64 defconfig v4.5 Linux kernel is known to boot, FDT doesn't need to be
+If ``ARM_LINUX_KERNEL_AS_BL33`` is set to 1 then this FDT will be passed to BL33
+via register x0, as expected by a Linux kernel. This allows a Linux kernel image
+to be booted directly as BL33 rather than using a bootloader.
+
+An ARM64 defconfig v5.5 Linux kernel is known to boot, FDT doesn't need to be
provided as it's generated by QEMU.
Current limitations:
@@ -20,7 +24,7 @@
- No instructions for how to load a BL32 (Secure Payload)
``QEMU_EFI.fd`` can be dowloaded from
-http://snapshots.linaro.org/components/kernel/leg-virt-tianocore-edk2-upstream/latest/QEMU-KERNEL-AARCH64/RELEASE_GCC49/QEMU_EFI.fd
+http://snapshots.linaro.org/components/kernel/leg-virt-tianocore-edk2-upstream/latest/QEMU-KERNEL-AARCH64/RELEASE_GCC5/QEMU_EFI.fd
Boot binaries, except BL1, are primarily loaded via semi-hosting so all
binaries has to reside in the same directory as QEMU is started from. This
@@ -29,7 +33,7 @@
- ``bl2.bin`` -> BL2
- ``bl31.bin`` -> BL31
- ``bl33.bin`` -> BL33 (``QEMU_EFI.fd``)
-- ``Image`` -> linux/Image
+- ``Image`` -> linux/arch/arm64/boot/Image
To build:
@@ -37,12 +41,12 @@
make CROSS_COMPILE=aarch64-none-elf- PLAT=qemu
-To start (QEMU v2.6.0):
+To start (QEMU v4.1.0):
.. code:: shell
qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 \
-kernel Image \
- -append console=ttyAMA0,38400 keep_bootcon root=/dev/vda2 \
+ -append "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" \
-initrd rootfs-arm64.cpio.gz -smp 2 -m 1024 -bios bl1.bin \
-d unimp -semihosting-config enable,target=native
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index fb49a57..a672b18 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -235,7 +235,7 @@
void gicv3_cpuif_enable(unsigned int proc_num)
{
uintptr_t gicr_base;
- unsigned int scr_el3;
+ u_register_t scr_el3;
unsigned int icc_sre_el3;
assert(gicv3_driver_data != NULL);
@@ -258,7 +258,7 @@
icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
- scr_el3 = (uint32_t) read_scr_el3();
+ scr_el3 = read_scr_el3();
/*
* Switch to NS state to write Non secure ICC_SRE_EL1 and
diff --git a/drivers/auth/crypto_mod.c b/drivers/auth/crypto_mod.c
index 5e5ac2b..110c504 100644
--- a/drivers/auth/crypto_mod.c
+++ b/drivers/auth/crypto_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -103,3 +103,24 @@
return crypto_lib_desc.verify_hash(data_ptr, data_len,
digest_info_ptr, digest_info_len);
}
+
+#if MEASURED_BOOT
+/*
+ * Calculate a hash
+ *
+ * Parameters:
+ *
+ * alg: message digest algorithm
+ * data_ptr, data_len: data to be hashed
+ * output: resulting hash
+ */
+int crypto_mod_calc_hash(unsigned int alg, void *data_ptr,
+ unsigned int data_len, unsigned char *output)
+{
+ assert(data_ptr != NULL);
+ assert(data_len != 0);
+ assert(output != NULL);
+
+ return crypto_lib_desc.calc_hash(alg, data_ptr, data_len, output);
+}
+#endif /* MEASURED_BOOT */
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c
index 33420fb..04fbc64 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_crypto.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -205,7 +205,32 @@
return CRYPTO_SUCCESS;
}
+#if MEASURED_BOOT
+/*
+ * Calculate a hash
+ *
+ * output points to the computed hash
+ */
+int calc_hash(unsigned int alg, void *data_ptr,
+ unsigned int data_len, unsigned char *output)
+{
+ const mbedtls_md_info_t *md_info;
+
+ md_info = mbedtls_md_info_from_type((mbedtls_md_type_t)alg);
+ if (md_info == NULL) {
+ return CRYPTO_ERR_HASH;
+ }
+
+ /* Calculate the hash of the data */
+ return mbedtls_md(md_info, data_ptr, data_len, output);
+}
+#endif /* MEASURED_BOOT */
+
/*
* Register crypto library descriptor
*/
+#if MEASURED_BOOT
+REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash);
+#else
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash);
+#endif /* MEASURED_BOOT */
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 8bb1bab..935bf77 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -134,7 +134,7 @@
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
-uint32_t get_scr_el3_from_routing_model(uint32_t security_state);
+u_register_t get_scr_el3_from_routing_model(uint32_t security_state);
int32_t set_routing_model(uint32_t type, uint32_t flags);
int32_t register_interrupt_type_handler(uint32_t type,
interrupt_type_handler_t handler,
diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h
index 3a42105..f211035 100644
--- a/include/drivers/auth/crypto_mod.h
+++ b/include/drivers/auth/crypto_mod.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -37,6 +37,13 @@
/* Verify a hash. Return one of the 'enum crypto_ret_value' options */
int (*verify_hash)(void *data_ptr, unsigned int data_len,
void *digest_info_ptr, unsigned int digest_info_len);
+
+#if MEASURED_BOOT
+ /* Calculate a hash. Return hash value */
+ int (*calc_hash)(unsigned int alg, void *data_ptr,
+ unsigned int data_len, unsigned char *output);
+#endif /* MEASURED_BOOT */
+
} crypto_lib_desc_t;
/* Public functions */
@@ -48,7 +55,21 @@
int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len,
void *digest_info_ptr, unsigned int digest_info_len);
+#if MEASURED_BOOT
+int crypto_mod_calc_hash(unsigned int alg, void *data_ptr,
+ unsigned int data_len, unsigned char *output);
+
/* Macro to register a cryptographic library */
+#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \
+ _calc_hash) \
+ const crypto_lib_desc_t crypto_lib_desc = { \
+ .name = _name, \
+ .init = _init, \
+ .verify_signature = _verify_signature, \
+ .verify_hash = _verify_hash, \
+ .calc_hash = _calc_hash \
+ }
+#else
#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash) \
const crypto_lib_desc_t crypto_lib_desc = { \
.name = _name, \
@@ -56,6 +77,7 @@
.verify_signature = _verify_signature, \
.verify_hash = _verify_hash \
}
+#endif /* MEASURED_BOOT */
extern const crypto_lib_desc_t crypto_lib_desc;
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index 7c996d1..17955e3 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,7 +45,7 @@
uint32_t bit_pos,
uint32_t value);
void cm_set_next_eret_context(uint32_t security_state);
-uint32_t cm_get_scr_el3(uint32_t security_state);
+u_register_t cm_get_scr_el3(uint32_t security_state);
/* Inline definitions */
diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h
index 006c7b7..24b030c 100644
--- a/include/lib/semihosting.h
+++ b/include/lib/semihosting.h
@@ -23,6 +23,7 @@
#define SEMIHOSTING_SYS_REMOVE 0x0E
#define SEMIHOSTING_SYS_SYSTEM 0x12
#define SEMIHOSTING_SYS_ERRNO 0x13
+#define SEMIHOSTING_SYS_EXIT 0x18
#define FOPEN_MODE_R 0x0
#define FOPEN_MODE_RB 0x1
@@ -54,5 +55,6 @@
void semihosting_write_char(char character);
void semihosting_write_string(char *string);
char semihosting_read_char(void);
+void semihosting_exit(uint32_t reason, uint32_t subcode);
#endif /* SEMIHOSTING_H */
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index b7908ad..dc4717a 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,7 +66,7 @@
void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
{
unsigned int security_state;
- uint32_t scr_el3;
+ u_register_t scr_el3;
el3_state_t *state;
gp_regs_t *gp_regs;
u_register_t sctlr_elx, actlr_elx;
@@ -87,7 +87,7 @@
* the required value depending on the state of the SPSR_EL3 and the
* Security state and entrypoint attributes of the next EL.
*/
- scr_el3 = (uint32_t)read_scr();
+ scr_el3 = read_scr();
scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
SCR_ST_BIT | SCR_HCE_BIT);
/*
@@ -326,7 +326,7 @@
******************************************************************************/
void cm_prepare_el3_exit(uint32_t security_state)
{
- uint32_t sctlr_elx, scr_el3, mdcr_el2;
+ u_register_t sctlr_elx, scr_el3, mdcr_el2;
cpu_context_t *ctx = cm_get_context(security_state);
bool el2_unused = false;
uint64_t hcr_el2 = 0U;
@@ -334,11 +334,11 @@
assert(ctx != NULL);
if (security_state == NON_SECURE) {
- scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx),
+ scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
CTX_SCR_EL3);
if ((scr_el3 & SCR_HCE_BIT) != 0U) {
/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
- sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx),
+ sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx),
CTX_SCTLR_EL1);
sctlr_elx &= SCTLR_EE_BIT;
sctlr_elx |= SCTLR_EL2_RES1;
@@ -618,7 +618,7 @@
{
cpu_context_t *ctx;
el3_state_t *state;
- uint32_t scr_el3;
+ u_register_t scr_el3;
ctx = cm_get_context(security_state);
assert(ctx != NULL);
@@ -634,9 +634,9 @@
* and set it to its new value.
*/
state = get_el3state_ctx(ctx);
- scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
+ scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
scr_el3 &= ~(1U << bit_pos);
- scr_el3 |= value << bit_pos;
+ scr_el3 |= (u_register_t)value << bit_pos;
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
}
@@ -644,7 +644,7 @@
* This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
* given security state.
******************************************************************************/
-uint32_t cm_get_scr_el3(uint32_t security_state)
+u_register_t cm_get_scr_el3(uint32_t security_state)
{
cpu_context_t *ctx;
el3_state_t *state;
@@ -654,7 +654,7 @@
/* Populate EL3 state so that ERET jumps to the correct entry */
state = get_el3state_ctx(ctx);
- return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
+ return read_ctx_reg(state, CTX_SCR_EL3);
}
/*******************************************************************************
diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c
index 1634e3a..748eedd 100644
--- a/lib/locks/bakery/bakery_lock_coherent.c
+++ b/lib/locks/bakery/bakery_lock_coherent.c
@@ -137,10 +137,11 @@
}
/*
- * Lock acquired. Ensure that any reads from a shared resource in the
- * critical section read values after the lock is acquired.
+ * Lock acquired. Ensure that any reads and writes from a shared
+ * resource in the critical section read/write values after the lock is
+ * acquired.
*/
- dmbld();
+ dmbish();
}
@@ -154,11 +155,14 @@
/*
* Ensure that other observers see any stores in the critical section
- * before releasing the lock. Release the lock by resetting ticket.
- * Then signal other waiting contenders.
+ * before releasing the lock. Also ensure all loads in the critical
+ * section are complete before releasing the lock. Release the lock by
+ * resetting ticket. Then signal other waiting contenders.
*/
- dmbst();
+ dmbish();
bakery->lock_data[me] = 0U;
+
+ /* Required to ensure ordering of the following sev */
dsb();
sev();
}
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index f906f51..caced8f 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -219,10 +219,11 @@
}
/*
- * Lock acquired. Ensure that any reads from a shared resource in the
- * critical section read values after the lock is acquired.
+ * Lock acquired. Ensure that any reads and writes from a shared
+ * resource in the critical section read/write values after the lock is
+ * acquired.
*/
- dmbld();
+ dmbish();
}
void bakery_lock_release(bakery_lock_t *lock)
@@ -240,11 +241,14 @@
/*
* Ensure that other observers see any stores in the critical section
- * before releasing the lock. Release the lock by resetting ticket.
- * Then signal other waiting contenders.
+ * before releasing the lock. Also ensure all loads in the critical
+ * section are complete before releasing the lock. Release the lock by
+ * resetting ticket. Then signal other waiting contenders.
*/
- dmbst();
+ dmbish();
my_bakery_info->lock_data = 0U;
write_cache_op((uintptr_t)my_bakery_info, is_cached);
+
+ /* This sev is ordered by the dsbish in write_cahce_op */
sev();
}
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index ea1a01d..5ab15c6 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -775,7 +775,7 @@
* suspend.
*/
if (psci_get_aff_info_state() == AFF_STATE_OFF) {
- ERROR("Unexpected affinity info state");
+ ERROR("Unexpected affinity info state.\n");
panic();
}
diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c
index 051dd00..60fc52a 100644
--- a/lib/semihosting/semihosting.c
+++ b/lib/semihosting/semihosting.c
@@ -15,7 +15,7 @@
#endif
long semihosting_call(unsigned long operation,
- void *system_block_address);
+ uintptr_t system_block_address);
typedef struct {
const char *file_name;
@@ -53,7 +53,7 @@
open_block.name_length = strlen(file_name);
return semihosting_call(SEMIHOSTING_SYS_OPEN,
- (void *) &open_block);
+ (uintptr_t) &open_block);
}
long semihosting_file_seek(long file_handle, ssize_t offset)
@@ -65,7 +65,7 @@
seek_block.location = offset;
result = semihosting_call(SEMIHOSTING_SYS_SEEK,
- (void *) &seek_block);
+ (uintptr_t) &seek_block);
if (result)
result = semihosting_call(SEMIHOSTING_SYS_ERRNO, 0);
@@ -86,7 +86,7 @@
read_block.length = *length;
result = semihosting_call(SEMIHOSTING_SYS_READ,
- (void *) &read_block);
+ (uintptr_t) &read_block);
if (result == *length) {
return -EINVAL;
@@ -112,7 +112,7 @@
write_block.length = *length;
result = semihosting_call(SEMIHOSTING_SYS_WRITE,
- (void *) &write_block);
+ (uintptr_t) &write_block);
*length = result;
@@ -122,28 +122,28 @@
long semihosting_file_close(long file_handle)
{
return semihosting_call(SEMIHOSTING_SYS_CLOSE,
- (void *) &file_handle);
+ (uintptr_t) &file_handle);
}
long semihosting_file_length(long file_handle)
{
return semihosting_call(SEMIHOSTING_SYS_FLEN,
- (void *) &file_handle);
+ (uintptr_t) &file_handle);
}
char semihosting_read_char(void)
{
- return semihosting_call(SEMIHOSTING_SYS_READC, NULL);
+ return semihosting_call(SEMIHOSTING_SYS_READC, 0);
}
void semihosting_write_char(char character)
{
- semihosting_call(SEMIHOSTING_SYS_WRITEC, (void *) &character);
+ semihosting_call(SEMIHOSTING_SYS_WRITEC, (uintptr_t) &character);
}
void semihosting_write_string(char *string)
{
- semihosting_call(SEMIHOSTING_SYS_WRITE0, (void *) string);
+ semihosting_call(SEMIHOSTING_SYS_WRITE0, (uintptr_t) string);
}
long semihosting_system(char *command_line)
@@ -154,7 +154,7 @@
system_block.command_length = strlen(command_line);
return semihosting_call(SEMIHOSTING_SYS_SYSTEM,
- (void *) &system_block);
+ (uintptr_t) &system_block);
}
long semihosting_get_flen(const char *file_name)
@@ -216,3 +216,15 @@
semihosting_file_close(file_handle);
return ret;
}
+
+void semihosting_exit(uint32_t reason, uint32_t subcode)
+{
+#ifdef __aarch64__
+ uint64_t parameters[] = {reason, subcode};
+
+ (void) semihosting_call(SEMIHOSTING_SYS_EXIT, (uintptr_t) ¶meters);
+#else
+ /* The subcode is not supported on AArch32. */
+ (void) semihosting_call(SEMIHOSTING_SYS_EXIT, reason);
+#endif
+}
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 53832c5..fff336c 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -139,6 +139,9 @@
# Set the default algorithm for the generation of Trusted Board Boot keys
KEY_ALG := rsa
+# Option to build TF with Measured Boot support
+MEASURED_BOOT := 0
+
# NS timer register save and restore
NS_TIMER_SWITCH := 0
@@ -201,6 +204,9 @@
# Build option to choose whether Trusted Firmware uses library at ROM
USE_ROMLIB := 0
+# Chain of trust.
+COT := tbbr
+
# Use tbbr_oid.h instead of platform_oid.h
USE_TBBR_DEFS := 1
diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk
index db41e0e..43c37ff 100644
--- a/plat/arm/board/rde1edge/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -24,6 +24,7 @@
BL31_SOURCES += ${SGI_CPU_SOURCES} \
${RDE1EDGE_BASE}/rde1edge_plat.c \
+ ${RDE1EDGE_BASE}/rde1edge_topology.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/rde1edge/rde1edge_topology.c b/plat/arm/board/rde1edge/rde1edge_topology.c
new file mode 100644
index 0000000..0b56f20
--- /dev/null
+++ b/plat/arm/board/rde1edge/rde1edge_topology.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+static const unsigned char rde1edge_pd_tree_desc[] = {
+ PLAT_ARM_CLUSTER_COUNT,
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ CSS_SGI_MAX_CPUS_PER_CLUSTER
+};
+
+/******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return rde1edge_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+};
diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk
index b44c70a..ca1e95e 100644
--- a/plat/arm/board/rdn1edge/platform.mk
+++ b/plat/arm/board/rdn1edge/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -24,6 +24,7 @@
BL31_SOURCES += ${SGI_CPU_SOURCES} \
${RDN1EDGE_BASE}/rdn1edge_plat.c \
+ ${RDN1EDGE_BASE}/rdn1edge_topology.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/rdn1edge/rdn1edge_topology.c b/plat/arm/board/rdn1edge/rdn1edge_topology.c
new file mode 100644
index 0000000..687ae35
--- /dev/null
+++ b/plat/arm/board/rdn1edge/rdn1edge_topology.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+static const unsigned char rdn1edge_pd_tree_desc[] = {
+ PLAT_ARM_CLUSTER_COUNT,
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ CSS_SGI_MAX_CPUS_PER_CLUSTER
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return rdn1edge_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ 0, 1, 2, 3, 4, 5, 6, 7
+};
diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk
index b9fa099..ce2717f 100644
--- a/plat/arm/board/sgi575/platform.mk
+++ b/plat/arm/board/sgi575/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -24,6 +24,7 @@
BL31_SOURCES += ${SGI_CPU_SOURCES} \
${SGI575_BASE}/sgi575_plat.c \
+ ${SGI575_BASE}/sgi575_topology.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/sgi575/sgi575_topology.c b/plat/arm/board/sgi575/sgi575_topology.c
new file mode 100644
index 0000000..f7c3856
--- /dev/null
+++ b/plat/arm/board/sgi575/sgi575_topology.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+static const unsigned char sgi575_pd_tree_desc[] = {
+ PLAT_ARM_CLUSTER_COUNT,
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ CSS_SGI_MAX_CPUS_PER_CLUSTER
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return sgi575_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ 0, 1, 2, 3, 4, 5, 6, 7
+};
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index 03d842a..255e6b4 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -173,7 +173,7 @@
int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode)
{
uint64_t par, pa;
- uint32_t scr_el3;
+ u_register_t scr_el3;
/* Doing Non-secure address translation requires SCR_EL3.NS set */
scr_el3 = read_scr_el3();
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 9d4f05e..c8b7ab4 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -254,7 +254,13 @@
AUTH_SOURCES := drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot.c \
+
+ # Include the selected chain of trust sources.
+ ifeq (${COT},tbbr)
+ AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot.c
+ else
+ $(error Unknown chain of trust ${COT})
+ endif
BL1_SOURCES += ${AUTH_SOURCES} \
bl1/tbbr/tbbr_img_desc.c \
diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c
index 7aa9e40..1c3b5bf 100644
--- a/plat/arm/css/sgi/sgi_topology.c
+++ b/plat/arm/css/sgi/sgi_topology.c
@@ -1,62 +1,14 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <sgi_variant.h>
-
-/* Topology */
/*
- * The power domain tree descriptor. The cluster power domains are
- * arranged so that when the PSCI generic code creates the power domain tree,
- * the indices of the CPU power domain nodes it allocates match the linear
- * indices returned by plat_core_pos_by_mpidr().
+ * Common topology related methods for SGI and RD based platforms
*/
-const unsigned char sgi_pd_tree_desc[] = {
- PLAT_ARM_CLUSTER_COUNT,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
-};
-
-/* RD-E1-Edge platform consists of 16 physical CPUS and 32 threads */
-const unsigned char rd_e1_edge_pd_tree_desc[] = {
- PLAT_ARM_CLUSTER_COUNT,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU,
- CSS_SGI_MAX_PE_PER_CPU
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM &&
- sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)
- return rd_e1_edge_pd_tree_desc;
- else
- return sgi_pd_tree_desc;
-}
-
/*******************************************************************************
* This function returns the core count within the cluster corresponding to
* `mpidr`.
@@ -66,15 +18,7 @@
return CSS_SGI_MAX_CPUS_PER_CLUSTER;
}
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = {
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
-};
-
+#if ARM_PLAT_MT
/******************************************************************************
* Return the number of PE's supported by the CPU.
*****************************************************************************/
@@ -82,3 +26,4 @@
{
return CSS_SGI_MAX_PE_PER_CPU;
}
+#endif
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c
index c76de64..9232cbc 100644
--- a/plat/imx/imx8qm/imx8qm_bl31_setup.c
+++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,12 +27,13 @@
#include <sci/sci.h>
#include <sec_rsrc.h>
-IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
-IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
-IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
-IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
+static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE;
+static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END;
+static const unsigned long BL31_RO_START = BL_CODE_BASE;
+static const unsigned long BL31_RO_END = BL_CODE_END;
+static const unsigned long BL31_RW_END = BL_END;
+
IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
-IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c
index bfe4052..58c82ce 100644
--- a/plat/imx/imx8qx/imx8qx_bl31_setup.c
+++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,12 +27,13 @@
#include <sci/sci.h>
#include <sec_rsrc.h>
-IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
-IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
-IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
-IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
+static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE;
+static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END;
+static const unsigned long BL31_RO_START = BL_CODE_BASE;
+static const unsigned long BL31_RO_END = BL_CODE_END;
+static const unsigned long BL31_RW_END = BL_END;
+
IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
-IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
index f1637ae..68e30b8 100644
--- a/plat/intel/soc/common/include/socfpga_system_manager.h
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -106,7 +106,6 @@
#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
-void enable_nonsecure_access(void);
void enable_ns_peripheral_access(void);
void enable_ns_bridge_access(void);
diff --git a/plat/mediatek/mt8173/plat_pm.c b/plat/mediatek/mt8173/plat_pm.c
index c8d4599..67f1c73 100644
--- a/plat/mediatek/mt8173/plat_pm.c
+++ b/plat/mediatek/mt8173/plat_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -236,7 +236,7 @@
static void plat_cpu_standby(plat_local_state_t cpu_state)
{
- unsigned int scr;
+ u_register_t scr;
scr = read_scr_el3();
write_scr_el3(scr | SCR_IRQ_BIT);
diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c
index 2358ec6..6094a17 100644
--- a/plat/mediatek/mt8183/plat_pm.c
+++ b/plat/mediatek/mt8183/plat_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2019-2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -197,7 +197,7 @@
static void plat_cpu_standby(plat_local_state_t cpu_state)
{
- unsigned int scr;
+ u_register_t scr;
scr = read_scr_el3();
write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 25fd84c..cbe3377 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,11 +42,12 @@
******************************************************************************/
IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
-IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END);
-IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE);
-IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END);
-IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START);
-IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END);
+
+static const uint64_t BL31_RW_END = BL_END;
+static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE;
+static const uint64_t BL31_RODATA_END = BL_RO_DATA_END;
+static const uint64_t TEXT_START = BL_CODE_BASE;
+static const uint64_t TEXT_END = BL_CODE_END;
extern uint64_t tegra_bl31_phys_base;
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index b6572ff..1fe3aad 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -53,7 +53,6 @@
int32_t nvg_is_sc7_allowed(void);
int32_t nvg_online_core(uint32_t core);
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
-int32_t nvg_roc_clean_cache_trbits(void);
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
int32_t nvg_roc_clean_cache_trbits(void);
void nvg_enable_strict_checking_mode(void);
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 1e49e51..78766fc 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -5,7 +5,7 @@
#
# platform configs
-ENABLE_CONSOLE_SPE := 0
+ENABLE_CONSOLE_SPE := 1
$(eval $(call add_define,ENABLE_CONSOLE_SPE))
ENABLE_STRICT_CHECKING_MODE := 1
diff --git a/plat/qemu/common/aarch32/plat_helpers.S b/plat/qemu/common/aarch32/plat_helpers.S
index aebcfa7..15e860b 100644
--- a/plat/qemu/common/aarch32/plat_helpers.S
+++ b/plat/qemu/common/aarch32/plat_helpers.S
@@ -72,8 +72,14 @@
/* Wait until we have a go */
poll_mailbox:
ldr r1, [r2, r0]
- cmp r1, #0
+ cmp r1, #PLAT_QEMU_HOLD_STATE_WAIT
beq 1f
+
+ /* Clear the mailbox again ready for next time. */
+ mov r1, #PLAT_QEMU_HOLD_STATE_WAIT
+ str r1, [r2, r0]
+
+ /* Jump to the provided entrypoint. */
mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
ldr r1, [r0]
bx r1
diff --git a/plat/qemu/common/aarch64/plat_helpers.S b/plat/qemu/common/aarch64/plat_helpers.S
index 13a5ee4..dbcdc2d 100644
--- a/plat/qemu/common/aarch64/plat_helpers.S
+++ b/plat/qemu/common/aarch64/plat_helpers.S
@@ -70,6 +70,12 @@
poll_mailbox:
ldr x1, [x2, x0]
cbz x1, 1f
+
+ /* Clear the mailbox again ready for next time. */
+ mov x1, #PLAT_QEMU_HOLD_STATE_WAIT
+ str x1, [x2, x0]
+
+ /* Jump to the provided entrypoint. */
mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
ldr x1, [x0]
br x1
diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 166d245..3e289fc 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -51,7 +51,7 @@
static void update_dt(void)
{
int ret;
- void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE;
+ void *fdt = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
if (ret < 0) {
@@ -172,12 +172,12 @@
* OP-TEE expect to receive DTB address in x2.
* This will be copied into x2 by dispatcher.
*/
- bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
+ bl_mem_params->ep_info.args.arg3 = ARM_PRELOADED_DTB_BASE;
#else /* case AARCH32_SP_OPTEE */
bl_mem_params->ep_info.args.arg0 =
bl_mem_params->ep_info.args.arg1;
bl_mem_params->ep_info.args.arg1 = 0;
- bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE;
+ bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE;
bl_mem_params->ep_info.args.arg3 = 0;
#endif
#endif
@@ -192,8 +192,23 @@
pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
#endif
+#if ARM_LINUX_KERNEL_AS_BL33
+ /*
+ * According to the file ``Documentation/arm64/booting.txt`` of
+ * the Linux kernel tree, Linux expects the physical address of
+ * the device tree blob (DTB) in x0, while x1-x3 are reserved
+ * for future use and must be 0.
+ */
+ bl_mem_params->ep_info.args.arg0 =
+ (u_register_t)ARM_PRELOADED_DTB_BASE;
+ bl_mem_params->ep_info.args.arg1 = 0U;
+ bl_mem_params->ep_info.args.arg2 = 0U;
+ bl_mem_params->ep_info.args.arg3 = 0U;
+#else
/* BL33 expects to receive the primary CPU MPID (through r0) */
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
+#endif
+
bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
break;
default:
diff --git a/plat/qemu/common/qemu_gicv2.c b/plat/qemu/common/qemu_gicv2.c
index fb56622..2c358ea 100644
--- a/plat/qemu/common/qemu_gicv2.c
+++ b/plat/qemu/common/qemu_gicv2.c
@@ -37,3 +37,8 @@
/* Enable the gic cpu interface */
gicv2_cpuif_enable();
}
+
+void qemu_pwr_gic_off(void)
+{
+ gicv2_cpuif_disable();
+}
diff --git a/plat/qemu/common/qemu_gicv3.c b/plat/qemu/common/qemu_gicv3.c
index 28572c5..0d35446 100644
--- a/plat/qemu/common/qemu_gicv3.c
+++ b/plat/qemu/common/qemu_gicv3.c
@@ -44,3 +44,9 @@
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
}
+
+void qemu_pwr_gic_off(void)
+{
+ gicv3_cpuif_disable(plat_my_core_pos());
+ gicv3_rdistif_off(plat_my_core_pos());
+}
diff --git a/plat/qemu/common/qemu_pm.c b/plat/qemu/common/qemu_pm.c
index a199688..cf80009 100644
--- a/plat/qemu/common/qemu_pm.c
+++ b/plat/qemu/common/qemu_pm.c
@@ -10,10 +10,13 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/psci/psci.h>
+#include <lib/semihosting.h>
#include <plat/common/platform.h>
#include "qemu_private.h"
+#define ADP_STOPPED_APPLICATION_EXIT 0x20026
+
/*
* The secure entry point to be used on warm reset.
*/
@@ -149,9 +152,18 @@
* Platform handler called when a power domain is about to be turned off. The
* target_state encodes the power state that each level should transition to.
******************************************************************************/
-void qemu_pwr_domain_off(const psci_power_state_t *target_state)
+static void qemu_pwr_domain_off(const psci_power_state_t *target_state)
{
- assert(0);
+ qemu_pwr_gic_off();
+}
+
+void __dead2 plat_secondary_cold_boot_setup(void);
+
+static void __dead2
+qemu_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
+{
+ disable_mmu_el3();
+ plat_secondary_cold_boot_setup();
}
/*******************************************************************************
@@ -191,7 +203,8 @@
******************************************************************************/
static void __dead2 qemu_system_off(void)
{
- ERROR("QEMU System Off: operation not handled.\n");
+ semihosting_exit(ADP_STOPPED_APPLICATION_EXIT, 0);
+ ERROR("QEMU System Off: semihosting call unexpectedly returned.\n");
panic();
}
@@ -205,6 +218,7 @@
.cpu_standby = qemu_cpu_standby,
.pwr_domain_on = qemu_pwr_domain_on,
.pwr_domain_off = qemu_pwr_domain_off,
+ .pwr_domain_pwr_down_wfi = qemu_pwr_domain_pwr_down_wfi,
.pwr_domain_suspend = qemu_pwr_domain_suspend,
.pwr_domain_on_finish = qemu_pwr_domain_on_finish,
.pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish,
diff --git a/plat/qemu/common/qemu_private.h b/plat/qemu/common/qemu_private.h
index 71ea4de..4dc62f5 100644
--- a/plat/qemu/common/qemu_private.h
+++ b/plat/qemu/common/qemu_private.h
@@ -32,5 +32,6 @@
void plat_qemu_gic_init(void);
void qemu_pwr_gic_on_finish(void);
+void qemu_pwr_gic_off(void);
#endif /* QEMU_PRIVATE_H */
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 5fda2cd..b95bf5a 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -151,6 +151,8 @@
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \
${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
${PLAT_QEMU_COMMON_PATH}/topology.c \
@@ -186,5 +188,13 @@
# Process flags
$(eval $(call add_define,BL32_RAM_LOCATION_ID))
+# Don't have the Linux kernel as a BL33 image by default
+ARM_LINUX_KERNEL_AS_BL33 := 0
+$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
+$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
+
+ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
+$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 0d6047d..51832d0 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -71,6 +71,8 @@
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \
${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
${PLAT_QEMU_COMMON_PATH}/topology.c \
@@ -97,5 +99,13 @@
BL32_RAM_LOCATION_ID = SEC_SRAM_ID
$(eval $(call add_define,BL32_RAM_LOCATION_ID))
+# Don't have the Linux kernel as a BL33 image by default
+ARM_LINUX_KERNEL_AS_BL33 := 0
+$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
+$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
+
+ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
+$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index 193d80e..578892e 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -39,12 +39,19 @@
#include "rcar_version.h"
#include "rom_api.h"
-IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE)
-IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT)
+#if RCAR_BL2_DCACHE == 1
+/*
+ * Following symbols are only used during plat_arch_setup() only
+ * when RCAR_BL2_DCACHE is enabled.
+ */
+static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
+static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
#if USE_COHERENT_MEM
-IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE)
-IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT)
+static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
+static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
+#endif
+
#endif
extern void plat_rcar_gic_driver_init(void);
diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c
index bd83c41..7bc0d8e 100644
--- a/plat/renesas/rcar/bl31_plat_setup.c
+++ b/plat/renesas/rcar/bl31_plat_setup.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,12 +22,12 @@
#include "rcar_private.h"
#include "rcar_version.h"
-IMPORT_SYM(uint64_t, __RO_START__, BL31_RO_BASE)
-IMPORT_SYM(uint64_t, __RO_END__, BL31_RO_LIMIT)
+static const uint64_t BL31_RO_BASE = BL_CODE_BASE;
+static const uint64_t BL31_RO_LIMIT = BL_CODE_END;
#if USE_COHERENT_MEM
-IMPORT_SYM(uint64_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_BASE)
-IMPORT_SYM(uint64_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_LIMIT)
+static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
+static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
#endif
extern void plat_rcar_gic_driver_init(void);
diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/rcar/plat_pm.c
index e678da5..6fc47b9 100644
--- a/plat/renesas/rcar/plat_pm.c
+++ b/plat/renesas/rcar/plat_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -56,7 +56,7 @@
static void rcar_cpu_standby(plat_local_state_t cpu_state)
{
- uint32_t scr_el3 = read_scr_el3();
+ u_register_t scr_el3 = read_scr_el3();
write_scr_el3(scr_el3 | SCR_IRQ_BIT);
dsb();
diff --git a/plat/rockchip/common/plat_pm.c b/plat/rockchip/common/plat_pm.c
index c9563c9..6926887 100644
--- a/plat/rockchip/common/plat_pm.c
+++ b/plat/rockchip/common/plat_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -182,7 +182,7 @@
******************************************************************************/
void rockchip_cpu_standby(plat_local_state_t cpu_state)
{
- unsigned int scr;
+ u_register_t scr;
assert(cpu_state == PLAT_MAX_RET_STATE);
diff --git a/plat/socionext/synquacer/sq_psci.c b/plat/socionext/synquacer/sq_psci.c
index 731b19a..0c97fcf 100644
--- a/plat/socionext/synquacer/sq_psci.c
+++ b/plat/socionext/synquacer/sq_psci.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -155,7 +155,7 @@
void sq_cpu_standby(plat_local_state_t cpu_state)
{
- unsigned int scr;
+ u_register_t scr;
assert(cpu_state == SQ_LOCAL_STATE_RET);
diff --git a/plat/st/stm32mp1/include/stm32mp1_boot_device.h b/plat/st/stm32mp1/include/stm32mp1_boot_device.h
deleted file mode 100644
index a745983..0000000
--- a/plat/st/stm32mp1/include/stm32mp1_boot_device.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef STM32MP1_BOOT_DEVICE_H
-#define STM32MP1_BOOT_DEVICE_H
-
-#include <drivers/raw_nand.h>
-#include <drivers/spi_nand.h>
-#include <drivers/spi_nor.h>
-
-int plat_get_raw_nand_data(struct rawnand_device *device);
-int plat_get_spi_nand_data(struct spinand_device *device);
-int plat_get_nor_data(struct nor_device *device);
-
-#endif /* STM32MP1_BOOT_DEVICE_H */
diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c
index 2d8eccf..997335d 100644
--- a/plat/st/stm32mp1/stm32mp1_boot_device.c
+++ b/plat/st/stm32mp1/stm32mp1_boot_device.c
@@ -7,6 +7,9 @@
#include <errno.h>
#include <drivers/nand.h>
+#include <drivers/raw_nand.h>
+#include <drivers/spi_nand.h>
+#include <drivers/spi_nor.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 11b01ab..5dc5206 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -23,7 +23,6 @@
#include <stm32mp_common.h>
#include <stm32mp_dt.h>
#include <stm32mp_shres_helpers.h>
-#include <stm32mp1_boot_device.h>
#include <stm32mp1_dbgmcu.h>
#include <stm32mp1_private.h>
#endif
diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h
index c1a5966..0d45116 100644
--- a/plat/ti/k3/board/generic/include/board_def.h
+++ b/plat/ti/k3/board/generic/include/board_def.h
@@ -27,5 +27,6 @@
#define PLAT_PROC_START_ID 32
#define PLAT_PROC_DEVICE_START_ID 202
+#define PLAT_CLUSTER_DEVICE_START_ID 198
#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
index ac33278..e390efe 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
@@ -20,32 +20,10 @@
#include "ti_sci_protocol.h"
#include "ti_sci.h"
-/**
- * struct ti_sci_desc - Description of SoC integration
- * @host_id: Host identifier representing the compute entity
- * @max_msg_size: Maximum size of data per message that can be handled
- */
-struct ti_sci_desc {
- uint8_t host_id;
- int max_msg_size;
-};
-
-/**
- * struct ti_sci_info - Structure representing a TI SCI instance
- * @desc: SoC description for this instance
- * @seq: Seq id used for verification for tx and rx message
- */
-struct ti_sci_info {
- const struct ti_sci_desc desc;
- uint8_t seq;
-};
-
-static struct ti_sci_info info = {
- .desc = {
- .host_id = TI_SCI_HOST_ID,
- .max_msg_size = TI_SCI_MAX_MESSAGE_SIZE,
- },
-};
+#if USE_COHERENT_MEM
+__section("tzfw_coherent_mem")
+#endif
+static uint8_t message_sequence;
/**
* struct ti_sci_xfer - Structure representing a message flow
@@ -82,16 +60,16 @@
struct ti_sci_msg_hdr *hdr;
/* Ensure we have sane transfer sizes */
- if (rx_message_size > info.desc.max_msg_size ||
- tx_message_size > info.desc.max_msg_size ||
+ if (rx_message_size > TI_SCI_MAX_MESSAGE_SIZE ||
+ tx_message_size > TI_SCI_MAX_MESSAGE_SIZE ||
rx_message_size < sizeof(*hdr) ||
tx_message_size < sizeof(*hdr))
return -ERANGE;
hdr = (struct ti_sci_msg_hdr *)tx_buf;
- hdr->seq = ++info.seq;
+ hdr->seq = ++message_sequence;
hdr->type = msg_type;
- hdr->host = info.desc.host_id;
+ hdr->host = TI_SCI_HOST_ID;
hdr->flags = msg_flags | TI_SCI_FLAG_REQ_ACK_ON_PROCESSED;
xfer->tx_message.buf = tx_buf;
@@ -131,7 +109,7 @@
hdr = (struct ti_sci_msg_hdr *)msg->buf;
/* Sanity check for message response */
- if (hdr->seq == info.seq)
+ if (hdr->seq == message_sequence)
break;
else
WARN("Message with sequence ID %u is not expected\n", hdr->seq);
@@ -141,9 +119,9 @@
return -EINVAL;
}
- if (msg->len > info.desc.max_msg_size) {
+ if (msg->len > TI_SCI_MAX_MESSAGE_SIZE) {
ERROR("Unable to handle %lu xfer (max %d)\n",
- msg->len, info.desc.max_msg_size);
+ msg->len, TI_SCI_MAX_MESSAGE_SIZE);
return -EINVAL;
}
@@ -425,13 +403,13 @@
int ret;
/* Ensure we have sane transfer size */
- if (sizeof(req) > info.desc.max_msg_size)
+ if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE)
return -ERANGE;
hdr = (struct ti_sci_msg_hdr *)&req;
- hdr->seq = ++info.seq;
+ hdr->seq = ++message_sequence;
hdr->type = TI_SCI_MSG_SET_DEVICE_STATE;
- hdr->host = info.desc.host_id;
+ hdr->host = TI_SCI_HOST_ID;
/* Setup with NORESPONSE flag to keep response queue clean */
hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE;
@@ -1408,13 +1386,13 @@
int ret;
/* Ensure we have sane transfer size */
- if (sizeof(req) > info.desc.max_msg_size)
+ if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE)
return -ERANGE;
hdr = (struct ti_sci_msg_hdr *)&req;
- hdr->seq = ++info.seq;
+ hdr->seq = ++message_sequence;
hdr->type = TISCI_MSG_SET_PROC_BOOT_CTRL;
- hdr->host = info.desc.host_id;
+ hdr->host = TI_SCI_HOST_ID;
/* Setup with NORESPONSE flag to keep response queue clean */
hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE;
@@ -1650,13 +1628,13 @@
int ret;
/* Ensure we have sane transfer size */
- if (sizeof(req) > info.desc.max_msg_size)
+ if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE)
return -ERANGE;
hdr = (struct ti_sci_msg_hdr *)&req;
- hdr->seq = ++info.seq;
+ hdr->seq = ++message_sequence;
hdr->type = TISCI_MSG_WAIT_PROC_BOOT_STATUS;
- hdr->host = info.desc.host_id;
+ hdr->host = TI_SCI_HOST_ID;
/* Setup with NORESPONSE flag to keep response queue clean */
hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE;
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
index a921e51..2d23f9a 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
@@ -563,8 +563,13 @@
uint32_t config_flags_clear;
} __packed;
+/* ARMV8 Control Flags */
+#define PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM 0x00000001
+#define PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS 0x00000002
+#define PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ 0x00000100
+
/* R5 Control Flags */
-#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
+#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
/**
* struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
@@ -618,6 +623,8 @@
/* ARMv8 Status Flags */
#define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001
#define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002
+#define PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE 0x00000010
+#define PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 0x00000020
/* R5 Status Flags */
#define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index de9cefe..d6ed766 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,11 +17,15 @@
#include <k3_gicv3.h>
#include <ti_sci.h>
+#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
+#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
+#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
+
uintptr_t k3_sec_entrypoint;
static void k3_cpu_standby(plat_local_state_t cpu_state)
{
- unsigned int scr;
+ u_register_t scr;
scr = read_scr_el3();
/* Enable the Non secure interrupt to wake the CPU */
@@ -37,30 +41,40 @@
static int k3_pwr_domain_on(u_register_t mpidr)
{
- int core_id, proc, device, ret;
+ int core, proc_id, device_id, ret;
- core_id = plat_core_pos_by_mpidr(mpidr);
- if (core_id < 0) {
- ERROR("Could not get target core id: %d\n", core_id);
+ core = plat_core_pos_by_mpidr(mpidr);
+ if (core < 0) {
+ ERROR("Could not get target core id: %d\n", core);
return PSCI_E_INTERN_FAIL;
}
- proc = PLAT_PROC_START_ID + core_id;
- device = PLAT_PROC_DEVICE_START_ID + core_id;
+ proc_id = PLAT_PROC_START_ID + core;
+ device_id = PLAT_PROC_DEVICE_START_ID + core;
- ret = ti_sci_proc_request(proc);
+ ret = ti_sci_proc_request(proc_id);
if (ret) {
ERROR("Request for processor failed: %d\n", ret);
return PSCI_E_INTERN_FAIL;
}
- ret = ti_sci_proc_set_boot_cfg(proc, k3_sec_entrypoint, 0, 0);
+ ret = ti_sci_proc_set_boot_cfg(proc_id, k3_sec_entrypoint, 0, 0);
if (ret) {
ERROR("Request to set core boot address failed: %d\n", ret);
return PSCI_E_INTERN_FAIL;
}
+ /* sanity check these are off before starting a core */
+ ret = ti_sci_proc_set_boot_ctrl(proc_id,
+ 0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ |
+ PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS |
+ PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM);
+ if (ret) {
+ ERROR("Request to clear boot configuration failed: %d\n", ret);
+ return PSCI_E_INTERN_FAIL;
+ }
+
- ret = ti_sci_device_get(device);
+ ret = ti_sci_device_get(device_id);
if (ret) {
ERROR("Request to start core failed: %d\n", ret);
return PSCI_E_INTERN_FAIL;
@@ -71,17 +85,35 @@
void k3_pwr_domain_off(const psci_power_state_t *target_state)
{
- int core_id, proc, device, ret;
+ int core, cluster, proc_id, device_id, cluster_id, ret;
+
+ /* At very least the local core should be powering down */
+ assert(CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
/* Prevent interrupts from spuriously waking up this cpu */
k3_gic_cpuif_disable();
- core_id = plat_my_core_pos();
- proc = PLAT_PROC_START_ID + core_id;
- device = PLAT_PROC_DEVICE_START_ID + core_id;
+ core = plat_my_core_pos();
+ cluster = MPIDR_AFFLVL1_VAL(read_mpidr_el1());
+ proc_id = PLAT_PROC_START_ID + core;
+ device_id = PLAT_PROC_DEVICE_START_ID + core;
+ cluster_id = PLAT_CLUSTER_DEVICE_START_ID + (cluster * 2);
+
+ /*
+ * If we are the last core in the cluster then we take a reference to
+ * the cluster device so that it does not get shutdown before we
+ * execute the entire cluster L2 cleaning sequence below.
+ */
+ if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
+ ret = ti_sci_device_get(cluster_id);
+ if (ret) {
+ ERROR("Request to get cluster failed: %d\n", ret);
+ return;
+ }
+ }
/* Start by sending wait for WFI command */
- ret = ti_sci_proc_wait_boot_status_no_wait(proc,
+ ret = ti_sci_proc_wait_boot_status_no_wait(proc_id,
/*
* Wait maximum time to give us the best chance to get
* to WFI before this command timeouts
@@ -95,11 +127,72 @@
}
/* Now queue up the core shutdown request */
- ret = ti_sci_device_put_no_wait(device);
+ ret = ti_sci_device_put_no_wait(device_id);
if (ret) {
ERROR("Sending core shutdown message failed (%d)\n", ret);
return;
}
+
+ /* If our cluster is not going down we stop here */
+ if (CLUSTER_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
+ return;
+
+ /* set AINACTS */
+ ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
+ PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS, 0);
+ if (ret) {
+ ERROR("Sending set control message failed (%d)\n", ret);
+ return;
+ }
+
+ /* set L2FLUSHREQ */
+ ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
+ PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ, 0);
+ if (ret) {
+ ERROR("Sending set control message failed (%d)\n", ret);
+ return;
+ }
+
+ /* wait for L2FLUSHDONE*/
+ ret = ti_sci_proc_wait_boot_status_no_wait(proc_id,
+ UINT8_MAX, 2, UINT8_MAX, UINT8_MAX,
+ PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE, 0, 0, 0);
+ if (ret) {
+ ERROR("Sending wait message failed (%d)\n", ret);
+ return;
+ }
+
+ /* clear L2FLUSHREQ */
+ ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
+ 0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ);
+ if (ret) {
+ ERROR("Sending set control message failed (%d)\n", ret);
+ return;
+ }
+
+ /* set ACINACTM */
+ ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
+ PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM, 0);
+ if (ret) {
+ ERROR("Sending set control message failed (%d)\n", ret);
+ return;
+ }
+
+ /* wait for STANDBYWFIL2 */
+ ret = ti_sci_proc_wait_boot_status_no_wait(proc_id,
+ UINT8_MAX, 2, UINT8_MAX, UINT8_MAX,
+ PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2, 0, 0, 0);
+ if (ret) {
+ ERROR("Sending wait message failed (%d)\n", ret);
+ return;
+ }
+
+ /* Now queue up the cluster shutdown request */
+ ret = ti_sci_device_put_no_wait(cluster_id);
+ if (ret) {
+ ERROR("Sending cluster shutdown message failed (%d)\n", ret);
+ return;
+ }
}
void k3_pwr_domain_on_finish(const psci_power_state_t *target_state)
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index c03629a..eff929e 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -10,53 +10,41 @@
DEBUG := 0
BINARY := ${PROJECT}${BIN_EXT}
OPENSSL_DIR := /usr
-USE_TBBR_DEFS := 1
+COT := tbbr
+MAKE_HELPERS_DIRECTORY := ../../make_helpers/
+include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
+include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+
+# Common source files.
OBJECTS := src/cert.o \
src/cmd_opt.o \
src/ext.o \
src/key.o \
src/main.o \
- src/sha.o \
- src/tbbr/tbb_cert.o \
- src/tbbr/tbb_ext.o \
- src/tbbr/tbb_key.o
+ src/sha.o
-HOSTCCFLAGS := -Wall -std=c99
-
-MAKE_HELPERS_DIRECTORY := ../../make_helpers/
-include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
-include ${MAKE_HELPERS_DIRECTORY}build_env.mk
-
-ifeq (${USE_TBBR_DEFS},1)
-# In this case, cert_tool is platform-independent
-PLAT_MSG := TBBR Generic
-PLAT_INCLUDE := ../../include/tools_share
+# Chain of trust.
+ifeq (${COT},tbbr)
+ include src/tbbr/tbbr.mk
else
-PLAT_MSG := ${PLAT}
-
-TF_PLATFORM_ROOT := ../../plat/
-include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
-
-PLAT_INCLUDE := $(wildcard ${PLAT_DIR}include)
-
-ifeq ($(PLAT_INCLUDE),)
- $(error "Error: Invalid platform '${PLAT}' has no include directory.")
+ $(error Unknown chain of trust ${COT})
endif
-endif
+
+HOSTCCFLAGS := -Wall -std=c99
ifeq (${DEBUG},1)
HOSTCCFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40
else
HOSTCCFLAGS += -O2 -DLOG_LEVEL=20
endif
+
ifeq (${V},0)
Q := @
else
Q :=
endif
-$(eval $(call add_define,USE_TBBR_DEFS))
HOSTCCFLAGS += ${DEFINES}
# Make soft links and include from local directory otherwise wrong headers
diff --git a/tools/cert_create/src/ext.c b/tools/cert_create/src/ext.c
index 57fb47d..d9a92bb 100644
--- a/tools/cert_create/src/ext.c
+++ b/tools/cert_create/src/ext.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,11 +33,11 @@
IMPLEMENT_ASN1_FUNCTIONS(HASH)
/*
- * This function adds the TBB extensions to the internal extension list
+ * This function adds the CoT extensions to the internal extension list
* maintained by OpenSSL so they can be used later.
*
* It also initializes the methods to print the contents of the extension. If an
- * alias is specified in the TBB extension, we reuse the methods of the alias.
+ * alias is specified in the CoT extension, we reuse the methods of the alias.
* Otherwise, only methods for V_ASN1_INTEGER and V_ASN1_OCTET_STRING are
* provided. Any other type will be printed as a raw ascii string.
*
diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index 863db7b..2ba1101 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c
@@ -47,7 +47,7 @@
do { \
v = OBJ_txt2nid(oid); \
if (v == NID_undef) { \
- ERROR("Cannot find TBB extension %s\n", oid); \
+ ERROR("Cannot find extension %s\n", oid); \
exit(1); \
} \
} while (0)
@@ -335,7 +335,7 @@
/* Initialize the new types and register OIDs for the extensions */
if (ext_init() != 0) {
- ERROR("Cannot initialize TBB extensions\n");
+ ERROR("Cannot initialize extensions\n");
exit(1);
}
diff --git a/tools/cert_create/src/tbbr/tbbr.mk b/tools/cert_create/src/tbbr/tbbr.mk
new file mode 100644
index 0000000..ee82d31
--- /dev/null
+++ b/tools/cert_create/src/tbbr/tbbr.mk
@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+USE_TBBR_DEFS := 1
+$(eval $(call add_define,USE_TBBR_DEFS))
+
+ifeq (${USE_TBBR_DEFS},1)
+# In this case, cert_tool is platform-independent
+PLAT_MSG := TBBR Generic
+PLAT_INCLUDE := ../../include/tools_share
+else
+PLAT_MSG := ${PLAT}
+
+TF_PLATFORM_ROOT := ../../plat/
+include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
+
+PLAT_INCLUDE := $(wildcard ${PLAT_DIR}include)
+
+ifeq ($(PLAT_INCLUDE),)
+ $(error "Error: Invalid platform '${PLAT}' has no include directory.")
+endif
+endif
+
+OBJECTS += src/tbbr/tbb_cert.o \
+ src/tbbr/tbb_ext.o \
+ src/tbbr/tbb_key.o