diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h
index bdbf80f..927c7b8 100644
--- a/bl1/bl1_private.h
+++ b/bl1/bl1_private.h
@@ -9,16 +9,7 @@
 
 #include <stdint.h>
 
-#include <lib/utils_def.h>
-
-/*******************************************************************************
- * Declarations of linker defined symbols which will tell us where BL1 lives
- * in Trusted ROM and RAM
- ******************************************************************************/
-IMPORT_SYM(uintptr_t, __BL1_ROM_END__,   BL1_ROM_END);
-
-IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE);
-IMPORT_SYM(uintptr_t, __BL1_RAM_END__,   BL1_RAM_LIMIT);
+#include <common/bl_common.h>
 
 /******************************************
  * Function prototypes
@@ -36,4 +27,5 @@
 		void *cookie,
 		void *handle,
 		unsigned int flags);
+
 #endif /* BL1_PRIVATE_H */
diff --git a/bl2/bl2_private.h b/bl2/bl2_private.h
index 01f6c6b..b1704d2 100644
--- a/bl2/bl2_private.h
+++ b/bl2/bl2_private.h
@@ -7,22 +7,7 @@
 #ifndef BL2_PRIVATE_H
 #define BL2_PRIVATE_H
 
-#if BL2_IN_XIP_MEM
-
-#include <stdint.h>
-
-/*******************************************************************************
- * Declarations of linker defined symbols which will tell us where BL2 lives
- * in Trusted ROM and RAM
- ******************************************************************************/
-extern uintptr_t __BL2_ROM_END__;
-#define BL2_ROM_END (uintptr_t)(&__BL2_ROM_END__)
-
-extern uintptr_t __BL2_RAM_START__;
-extern uintptr_t __BL2_RAM_END__;
-#define BL2_RAM_BASE (uintptr_t)(&__BL2_RAM_START__)
-#define BL2_RAM_LIMIT (uintptr_t)(&__BL2_RAM_END__)
-#endif
+#include <common/bl_common.h>
 
 /******************************************
  * Forward declarations
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index c09b351..1af1962 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -247,7 +247,7 @@
          * Time-stamps are stored in normal .bss memory
          *
          * The compiler will allocate enough memory for one CPU's time-stamps,
-         * the remaining memory for other CPU's is allocated by the
+         * the remaining memory for other CPUs is allocated by the
          * linker script
          */
         . = ALIGN(CACHE_WRITEBACK_GRANULE);
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 927cda2..da35f75 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -68,7 +68,7 @@
  * before passing control to the bootloader or an Operating System. This
  * function calls runtime_svc_init() which initializes all registered runtime
  * services. The run time services would setup enough context for the core to
- * swtich to the next exception level. When this function returns, the core will
+ * switch to the next exception level. When this function returns, the core will
  * switch to the programmed exception level via. an ERET.
  ******************************************************************************/
 void bl31_main(void)
@@ -96,13 +96,13 @@
 	 * decide which is the next image (BL32 or BL33) and how to execute it.
 	 * If the SPD runtime service is present, it would want to pass control
 	 * to BL32 first in S-EL1. In that case, SPD would have registered a
-	 * function to intialize bl32 where it takes responsibility of entering
+	 * function to initialize bl32 where it takes responsibility of entering
 	 * S-EL1 and returning control back to bl31_main. Once this is done we
 	 * can prepare entry into BL33 as normal.
 	 */
 
 	/*
-	 * If SPD had registerd an init hook, invoke it.
+	 * If SPD had registered an init hook, invoke it.
 	 */
 	if (bl32_init != NULL) {
 		INFO("BL31: Initializing BL32\n");
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S
index ba9d342..3cd427d 100644
--- a/bl32/sp_min/sp_min.ld.S
+++ b/bl32/sp_min/sp_min.ld.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -167,7 +167,7 @@
          * Time-stamps are stored in normal .bss memory
          *
          * The compiler will allocate enough memory for one CPU's time-stamps,
-         * the remaining memory for other CPU's is allocated by the
+         * the remaining memory for other CPUs is allocated by the
          * linker script
          */
         . = ALIGN(CACHE_WRITEBACK_GRANULE);
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index 3cb1990..f39e33b 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -35,7 +35,7 @@
 static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT];
 
 /******************************************************************************
- * Define the smccc helper library API's
+ * Define the smccc helper library APIs
  *****************************************************************************/
 void *smc_get_ctx(unsigned int security_state)
 {
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 24efa61..e042d96 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -362,7 +362,7 @@
 
 	/*
 	 * Request a service back from dispatcher/secure monitor. This call
-	 * return and thereafter resume exectuion
+	 * return and thereafter resume execution
 	 */
 	tsp_get_magic(service_args);
 
@@ -395,7 +395,7 @@
 }
 
 /*******************************************************************************
- * TSP smc abort handler. This function is called when aborting a preemtped
+ * TSP smc abort handler. This function is called when aborting a preempted
  * yielding SMC request. It should cleanup all resources owned by the SMC
  * handler such as locks or dynamically allocated memory so following SMC
  * request are executed in a clean environment.
diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c
index 3592863..d1ff2b0 100644
--- a/bl32/tsp/tsp_timer.c
+++ b/bl32/tsp/tsp_timer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -80,7 +80,7 @@
 }
 
 /*******************************************************************************
- * This function restores the timer context post cpu resummption
+ * This function restores the timer context post cpu resumption
  ******************************************************************************/
 void tsp_generic_timer_restore(void)
 {
diff --git a/common/backtrace/backtrace.c b/common/backtrace/backtrace.c
index bf60a08..ecc65c9 100644
--- a/common/backtrace/backtrace.c
+++ b/common/backtrace/backtrace.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -231,7 +231,7 @@
  * Usage of the trace: addr2line can be used to map the addresses to function
  * and source code location when given the ELF file compiled with debug
  * information. The "-i" flag is highly recommended to improve display of
- * inlined function. The *.dump files generated when buildidng each image can
+ * inlined function. The *.dump files generated when building each image can
  * also be used.
  *
  * WARNING: In case of corrupted stack, this function could display security
diff --git a/docs/auth-framework.rst b/docs/auth-framework.rst
index c934824..e0b569f 100644
--- a/docs/auth-framework.rst
+++ b/docs/auth-framework.rst
@@ -160,7 +160,7 @@
 particular image in BL1 or BL2. For each BL image that requires authentication,
 the Generic code asks recursively the Authentication module what is the parent
 image until either an authenticated image or the ROT is reached. Then the
-Generic code calls the IO framewotk to load the image and calls the
+Generic code calls the IO framework to load the image and calls the
 Authentication module to authenticate it, following the CoT from ROT to Image.
 
 TF-A Platform Port (PP)
@@ -422,7 +422,7 @@
 -  ``_name``: a string containing the IPL name for debugging purposes.
 -  ``_init``: initialization function pointer.
 -  ``_check_int``: check image integrity function pointer.
--  ``_get_param``: extract authentication parameter funcion pointer.
+-  ``_get_param``: extract authentication parameter function pointer.
 
 The ``init()`` function will be used to initialize the IPL.
 
@@ -925,7 +925,7 @@
 The mbedTLS library algorithm support is configured by the
 ``TF_MBEDTLS_KEY_ALG`` variable which can take in 3 values: `rsa`, `ecdsa` or
 `rsa+ecdsa`. This variable allows the Makefile to include the corresponding
-sources in the build for the various algorthms. Setting the variable to
+sources in the build for the various algorithms. Setting the variable to
 `rsa+ecdsa` enables support for both rsa and ecdsa algorithms in the mbedTLS
 library.
 
diff --git a/docs/change-log.rst b/docs/change-log.rst
index d329e83..11fcf21 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -10,7 +10,7 @@
 New Features
 ------------
 
--  Removal of a number of deprecated API's
+-  Removal of a number of deprecated APIs
 
    -  A new Platform Compatibility Policy document has been created which
       references a wiki page that maintains a listing of deprecated
@@ -20,7 +20,7 @@
       from the code base.
 
    -  Various Arm and partner platforms have been updated to remove the use of
-      removed API's in this release.
+      removed APIs in this release.
 
    -  This release is otherwise unchanged from 1.6 release
 
@@ -130,7 +130,7 @@
       the clang linker is not used because it is unable to link TF-A objects
       due to immaturity of clang linker functionality at this time.
 
--  Refactor support API's into Libraries
+-  Refactor support APIs into Libraries
 
    -  Evolve libfdt, mbed TLS library and standard C library sources as
       proper libraries that TF-A may be linked against.
@@ -435,7 +435,7 @@
 
    -  Introduced APIs to get and set the memory attributes of a region.
 
-   -  Added support to manage both priviledge levels in translation regimes that
+   -  Added support to manage both privilege levels in translation regimes that
       describe translations for 2 Exception levels, specifically the EL1&0
       translation regime, and extended the memory map region attributes to
       include specifying Non-privileged access.
@@ -683,7 +683,7 @@
 -  Enhancements to Firmware Update feature:
 
    -  The FWU logic now checks for overlapping images to prevent execution of
-      unauthenticated arbitary code.
+      unauthenticated arbitrary code.
 
    -  Introduced new FWU_SMC_IMAGE_RESET SMC that changes the image loading
       state machine to go from COPYING, COPIED or AUTHENTICATED states to
@@ -855,7 +855,7 @@
 
    -  Essential control registers are fully initialised on EL3 start-up, when
       initialising the non-secure and secure context structures and when
-      preparing to leave EL3 for a lower EL. This gives better alignement with
+      preparing to leave EL3 for a lower EL. This gives better alignment with
       the Arm ARM which states that software must initialise RES0 and RES1
       fields with 0 / 1.
 
@@ -1345,7 +1345,7 @@
 -  It is now possible to specify the name of the FIP at build time by defining
    the ``FIP_NAME`` variable.
 
--  Issues with depedencies on the 'fiptool' makefile target have been
+-  Issues with dependencies on the 'fiptool' makefile target have been
    rectified. The ``fip_create`` tool is now rebuilt whenever its source files
    change.
 
@@ -1376,7 +1376,7 @@
       the secure world. This can be done by setting the build flag
       ``FVP_TSP_RAM_LOCATION`` to the value ``dram``.
 
--  Separate transation tables are created for each boot loader image. The
+-  Separate translation tables are created for each boot loader image. The
    ``IMAGE_BLx`` build options are used to do this. This allows each stage to
    create mappings only for areas in the memory map that it needs.
 
@@ -1530,7 +1530,7 @@
    -  Clarified the platform porting interface to the TSP.
 
    -  Reworked the TSPD setup code to support the alternate BL3-2
-      intialization flow where BL3-1 generic code hands control to BL3-2,
+      initialization flow where BL3-1 generic code hands control to BL3-2,
       rather than expecting the TSPD to hand control directly to BL3-2.
 
    -  Considerable rework to PSCI generic code to support CPU specific
@@ -1569,7 +1569,7 @@
 
 -  Removed the concept of top/bottom image loading. The image loader now
    automatically detects the position of the image inside the current memory
-   layout and updates the layout to minimize fragementation. This resolves the
+   layout and updates the layout to minimize fragmentation. This resolves the
    image loader limitations of previously releases. There are currently no
    plans to support dynamic image loading.
 
diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst
index 21a4d53..c79f03d 100644
--- a/docs/firmware-design.rst
+++ b/docs/firmware-design.rst
@@ -203,7 +203,7 @@
 
    The ``plat_report_exception()`` implementation on the Arm FVP port programs
    the Versatile Express System LED register in the following format to
-   indicate the occurence of an unexpected exception:
+   indicate the occurrence of an unexpected exception:
 
    ::
 
@@ -1991,7 +1991,7 @@
 The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
 tree information for state management of power domains. By default, this data
 structure is allocated in the coherent memory region in TF-A because it can be
-accessed by multple CPUs, either with caches enabled or disabled.
+accessed by multiple CPUs, either with caches enabled or disabled.
 
 .. code:: c
 
@@ -2031,7 +2031,7 @@
 
 The field ``local_state`` can be concurrently accessed by multiple CPUs in
 different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure
-mutual exlusion to this field and a clean and invalidate is needed after it
+mutual exclusion to this field and a clean and invalidate is needed after it
 is written.
 
 Bakery lock data
@@ -2225,7 +2225,7 @@
 execute-never.
 
 This has an impact on memory footprint, as padding bytes need to be introduced
-between the code and read-only data to ensure the segragation of the two. To
+between the code and read-only data to ensure the segregation of the two. To
 limit the memory cost, this flag also changes the memory layout such that the
 code and exception vectors are now contiguous, like so:
 
@@ -2352,12 +2352,12 @@
 
 The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code
 with a ``.text.init.*`` attribute which can be filtered and placed suitably
-within the BL image for later reclaimation by the platform. The platform can
-specify the fiter and the memory region for this init section in BL31 via the
+within the BL image for later reclamation by the platform. The platform can
+specify the filter and the memory region for this init section in BL31 via the
 plat.ld.S linker script. For example, on the FVP, this section is placed
 overlapping the secondary CPU stacks so that after the cold boot is done, this
 memory can be reclaimed for the stacks. The init memory section is initially
-mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initilization has
+mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has
 completed, the FVP changes the attributes of this section to ``RW``,
 ``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes
 are changed within the ``bl31_plat_runtime_setup`` platform hook. The init
@@ -2553,7 +2553,7 @@
 
 Platform implementing an Armv7-A system can to define from its target
 Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their
-``plaform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a
+``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a
 Cortex-A15 target.
 
 Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support.
diff --git a/docs/firmware-update.rst b/docs/firmware-update.rst
index e10e148..3ee57bc 100644
--- a/docs/firmware-update.rst
+++ b/docs/firmware-update.rst
@@ -266,14 +266,14 @@
         if (image_id is invalid) return -EPERM
         if (secure world caller)
             if (image_id state is not RESET) return -EPERM
-            if (image_addr/image_size is not mappped into BL1) return -ENOMEM
+            if (image_addr/image_size is not mapped into BL1) return -ENOMEM
         else // normal world caller
             if (image_id is secure image)
                 if (image_id state is not COPIED) return -EPERM
             else // image_id is non-secure image
                 if (image_id state is not RESET) return -EPERM
                 if (image_addr/image_size is in secure memory) return -ENOMEM
-                if (image_addr/image_size not mappped into BL1) return -ENOMEM
+                if (image_addr/image_size not mapped into BL1) return -ENOMEM
 
 This SMC authenticates the image specified by ``image_id``. If the image is in the
 RESET state, BL1 authenticates the image in place using the provided
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index f1a26f4..7fc5297 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -390,7 +390,7 @@
 -  **#define : SCP\_BL2\_IMAGE\_ID**
 
    SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory
-   from platform storage before being transfered to the SCP.
+   from platform storage before being transferred to the SCP.
 
 -  **#define : SCP\_FW\_KEY\_CERT\_ID**
 
@@ -439,9 +439,9 @@
 -  **#define : TSP\_SEC\_MEM\_SIZE**
 
    Defines the size of the secure memory used by the BL32 image on the
-   platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate
-   the memory required by the BL32 image, defined by ``BL32_BASE`` and
-   ``BL32_LIMIT``.
+   platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
+   accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
+   and ``BL32_LIMIT``.
 
 -  **#define : TSP\_IRQ\_SEC\_PHY\_TIMER**
 
@@ -821,11 +821,11 @@
     Argument : void
     Return   : unsigned int
 
-This funtion returns the index of the calling CPU which is used as a
+This function returns the index of the calling CPU which is used as a
 CPU-specific linear index into blocks of memory (for example while allocating
 per-CPU stacks). This function will be invoked very early in the
 initialization sequence which mandates that this function should be
-implemented in assembly and should not rely on the avalability of a C
+implemented in assembly and should not rely on the availability of a C
 runtime environment. This function can clobber x0 - x8 and must preserve
 x9 - x29.
 
@@ -929,7 +929,7 @@
 
 A platform may need to do additional initialization after reset. This function
 allows the platform to do the platform specific intializations. Platform
-specific errata workarounds could also be implemented here. The api should
+specific errata workarounds could also be implemented here. The API should
 preserve the values of callee saved registers x19 to x29.
 
 The default implementation doesn't do anything. If a platform needs to override
@@ -1543,7 +1543,7 @@
 process and is executed only by the primary CPU. BL1 passes control to BL2U at
 ``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
 
-#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure
+#. (Optional) Transferring the optional SCP\_BL2U binary image from AP secure
    memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1.
    ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U
    should be copied from. Subsequent handling of the SCP\_BL2U image is
@@ -1649,7 +1649,7 @@
    implementation.
 
 #. Optionally passing control to the BL32 image, pre-loaded at a platform-
-   specific address by BL2. BL31 exports a set of apis that allow runtime
+   specific address by BL2. BL31 exports a set of APIs that allow runtime
    services to specify the security state in which the next image should be
    executed and run the corresponding image. On ARM platforms, BL31 uses the
    ``bl_params`` list populated by BL2 in memory to do this.
@@ -1800,7 +1800,7 @@
 ``include/lib/xlat_tables/xlat_mmu_helpers.h``.
 
 On DynamIQ systems, this function must not use stack while enabling MMU, which
-is how the function in xlat table library version 2 is implementated.
+is how the function in xlat table library version 2 is implemented.
 
 Function : plat\_get\_syscnt\_freq2() [mandatory]
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -2030,7 +2030,7 @@
 
 This function returns a pointer to the byte array containing the power domain
 topology tree description. The format and method to construct this array are
-described in `Power Domain Topology Design`_. The BL31 PSCI initilization code
+described in `Power Domain Topology Design`_. The BL31 PSCI initialization code
 requires this array to be described by the platform, either statically or
 dynamically, to initialize the power domain topology tree. In case the array
 is populated dynamically, then plat\_core\_pos\_by\_mpidr() and
@@ -2070,7 +2070,7 @@
 
 Perform the platform-specific actions to enter the standby state for a cpu
 indicated by the passed argument. This provides a fast path for CPU standby
-wherein overheads of PSCI state management and lock acquistion is avoided.
+wherein overheads of PSCI state management and lock acquisition is avoided.
 For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
 the suspend state type specified in the ``power-state`` parameter should be
 STANDBY and the target power domain level specified should be the CPU. The
@@ -2345,7 +2345,7 @@
 described in the `IMF Design Guide`_
 
 A platform should export the following APIs to support the IMF. The following
-text briefly describes each api and its implementation in Arm standard
+text briefly describes each API and its implementation in Arm standard
 platforms. The API implementation depends upon the type of interrupt controller
 present in the platform. Arm standard platform layer supports both
 `Arm Generic Interrupt Controller version 2.0 (GICv2)`_
@@ -2552,7 +2552,7 @@
 
 BL31 implements a crash reporting mechanism which prints the various registers
 of the CPU to enable quick crash analysis and debugging. This mechanism relies
-on the platform implementating ``plat_crash_console_init``,
+on the platform implementing ``plat_crash_console_init``,
 ``plat_crash_console_putc`` and ``plat_crash_console_flush``.
 
 The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
diff --git a/docs/psci-lib-integration-guide.rst b/docs/psci-lib-integration-guide.rst
index d86fc29..1be2240 100644
--- a/docs/psci-lib-integration-guide.rst
+++ b/docs/psci-lib-integration-guide.rst
@@ -240,7 +240,7 @@
 the EL3 Runtime Software may want to perform some bookkeeping during power
 management operations. This function is used to register the ``spd_pm_ops_t``
 (first argument) callbacks with the PSCI library which will be called
-ppropriately during power management. Calling this function is optional and
+appropriately during power management. Calling this function is optional and
 need to be called by the primary CPU during the cold boot sequence after
 ``psci_setup()`` has completed.
 
diff --git a/docs/ras.rst b/docs/ras.rst
index 4c82022..cea74e9 100644
--- a/docs/ras.rst
+++ b/docs/ras.rst
@@ -203,8 +203,8 @@
 Engaging the RAS framework
 --------------------------
 
-Enabling RAS support is a platform choice conjunctional of three distinct but
-related build options:
+Enabling RAS support is a platform choice constructed from three distinct, but
+related, build options:
 
 -  ``RAS_EXTENSION=1`` includes the RAS framework in the run time firmware;
 
@@ -244,7 +244,7 @@
 
 .. __: exception-handling.rst#partitioning-priority-levels
 
-Handling of both `interrrupt`__ and `non-interrupt`__ exceptions follow the
+Handling of both `interrupt`__ and `non-interrupt`__ exceptions follow the
 sequences outlined in the |EHF| documentation. I.e., for interrupts, the
 priority management is implicit; but for non-interrupt exceptions, they're
 explicit using `EHF APIs`__.
diff --git a/docs/secure-partition-manager-design.rst b/docs/secure-partition-manager-design.rst
index 73406b2..3c301d0 100644
--- a/docs/secure-partition-manager-design.rst
+++ b/docs/secure-partition-manager-design.rst
@@ -309,7 +309,7 @@
 allows the Secure Partition to:
 
 - Register with the SPM a service that it provides.
-- Indicate completion of a service request delagated by the SPM
+- Indicate completion of a service request delegated by the SPM
 
 Miscellaneous interfaces
 ------------------------
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 103f1c7..b50de37 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -108,7 +108,7 @@
    ``CC`` needs to point to the clang or armclang binary, which will
    also select the clang or armclang assembler. Be aware that the
    GNU linker is used by default.  In case of being needed the linker
-   can be overriden using the ``LD`` variable. Clang linker version 6 is
+   can be overridden using the ``LD`` variable. Clang linker version 6 is
    known to work with TF-A.
 
    In both cases ``CROSS_COMPILE`` should be set as described above.
@@ -357,8 +357,8 @@
    supports the format used by GCC when T32 interworking is disabled. For this
    reason enabling this option in AArch32 will force the compiler to only
    generate A32 code. This option is enabled by default only in AArch64 debug
-   builds, but this behaviour can be overriden in each platform's Makefile or in
-   the build command line.
+   builds, but this behaviour can be overridden in each platform's Makefile or
+   in the build command line.
 
 -  ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
    feature. MPAM is an optional Armv8.4 extension that enables various memory
@@ -428,7 +428,7 @@
    handled at EL3, and a panic will result. This is supported only for AArch64
    builds.
 
--  ``FAULT_INJECTION_SUPPORT``: ARMv8.4 externsions introduced support for fault
+-  ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
    injection from lower ELs, and this build option enables lower ELs to use
    Error Records accessed via System Registers to inject faults. This is
    applicable only to AArch64 builds.
diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c
index 64b1626..d184054 100644
--- a/drivers/arm/ccn/ccn.c
+++ b/drivers/arm/ccn/ccn.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -370,7 +370,7 @@
  * system. The state is expected to be one of NO_L3, SF_ONLY, L3_HAM or
  * L3_FAM. Instead of comparing the states reported by all HN-Fs, the state of
  * the first present HN-F node is reported. Since the driver does not export an
- * interface to program them seperately, there is no reason to perform this
+ * interface to program them separately, there is no reason to perform this
  * check. An HN-F could report that the L3 cache is transitioning from one mode
  * to another e.g. HNF_PM_NOL3_2_SFONLY. In this case, the function waits for
  * the transition to complete and reports the final state.
@@ -383,7 +383,7 @@
 	assert(ccn_plat_desc->periphbase);
 
 	/*
-	 * Wait for a L3 cache paritition to enter any run mode. The pstate
+	 * Wait for a L3 cache partition to enter any run mode. The pstate
 	 * parameter is read from an HN-F P-state status register. A non-zero
 	 * value in bits[1:0] means that the cache is transitioning to a run
 	 * mode.
@@ -428,7 +428,7 @@
 	region_id = HNF_REGION_ID_START;
 	FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) {
 		/*
-		 * Wait for a L3 cache paritition to enter a target run
+		 * Wait for a L3 cache partition to enter a target run
 		 * mode. The pstate parameter is read from an HN-F P-state
 		 * status register.
 		 */
@@ -584,7 +584,7 @@
 		return;
 	}
 
-	/* Setting the value of Auxilary Control Register of the Node */
+	/* Setting the value of Auxiliary Control Register of the Node */
 	ccn_reg_write(ccn_plat_desc->periphbase, region_id, reg_offset, val);
 	VERBOSE("Value is successfully written at address 0x%lx.\n",
 			(ccn_plat_desc->periphbase
@@ -611,7 +611,7 @@
 		return ULL(0);
 	}
 
-	/* Setting the value of Auxilary Control Register of the Node */
+	/* Setting the value of Auxiliary Control Register of the Node */
 	val = ccn_reg_read(ccn_plat_desc->periphbase, region_id, reg_offset);
 	VERBOSE("Value is successfully read from address 0x%lx.\n",
 			(ccn_plat_desc->periphbase
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 50e87c1..450bd0b 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -405,7 +405,7 @@
 			return 0;
 		}
 
-		mdelay(1);
+		mdelay(10);
 	}
 
 	ERROR("CMD1 failed after %d retries\n", SEND_OP_COND_MAX_RETRIES);
diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c
index 07869ac..630c1d8 100644
--- a/drivers/partition/partition.c
+++ b/drivers/partition/partition.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -75,7 +75,7 @@
 
 /*
  * Load GPT header and check the GPT signature.
- * If partiton numbers could be found, check & update it.
+ * If partition numbers could be found, check & update it.
  */
 static int load_gpt_header(uintptr_t image_handle)
 {
diff --git a/drivers/renesas/rcar/auth/auth_mod.c b/drivers/renesas/rcar/auth/auth_mod.c
index d9446d9..f7d8ec0 100644
--- a/drivers/renesas/rcar/auth/auth_mod.c
+++ b/drivers/renesas/rcar/auth/auth_mod.c
@@ -113,7 +113,7 @@
 	}
 #if RCAR_BL2_DCACHE == 1
 	/* clean and disable */
-	write_sctlr_el1(read_sctlr_el1() & ~SCTLR_C_BIT);
+	write_sctlr_el3(read_sctlr_el3() & ~SCTLR_C_BIT);
 	dcsw_op_all(DCCISW);
 #endif
 	ret = (mmio_read_32(RCAR_BOOT_KEY_CERT_NEW) == RCAR_CERT_MAGIC_NUM) ?
@@ -124,7 +124,7 @@
 
 #if RCAR_BL2_DCACHE == 1
 	/* enable */
-	write_sctlr_el1(read_sctlr_el1() | SCTLR_C_BIT);
+	write_sctlr_el3(read_sctlr_el3() | SCTLR_C_BIT);
 #endif
 
 #endif
diff --git a/drivers/renesas/rcar/cpld/ulcb_cpld.c b/drivers/renesas/rcar/cpld/ulcb_cpld.c
index d7192f4..6b03614 100644
--- a/drivers/renesas/rcar/cpld/ulcb_cpld.c
+++ b/drivers/renesas/rcar/cpld/ulcb_cpld.c
@@ -5,6 +5,7 @@
  */
 
 #include <lib/mmio.h>
+#include "ulcb_cpld.h"
 
 #define SCLK			8	/* GP_6_8 */
 #define SSTBZ			3	/* GP_2_3 */
diff --git a/drivers/renesas/rcar/cpld/ulcb_cpld.h b/drivers/renesas/rcar/cpld/ulcb_cpld.h
new file mode 100644
index 0000000..1616d71
--- /dev/null
+++ b/drivers/renesas/rcar/cpld/ulcb_cpld.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RCAR_ULCB_CPLD_H__
+#define RCAR_ULCB_CPLD_H__
+
+extern void rcar_cpld_reset_cpu(void);
+
+#endif /* RCAR_ULCB_CPLD_H__ */
diff --git a/drivers/renesas/rcar/delay/micro_delay.S b/drivers/renesas/rcar/delay/micro_delay.S
deleted file mode 100644
index 978973c..0000000
--- a/drivers/renesas/rcar/delay/micro_delay.S
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include "micro_delay.h"
-
-#define CPG_BASE		(0xE6150000)
-#define CPG_SMSTPCR1		(0x0134)
-#define CPG_CPGWPR		(0x0900)
-
-/* Module bit for TMU ch3-5 */
-#define MSTPCR1_TMU1		(1 << 24)
-
-#define TMU3_BASE		(0xE6FC0000)
-#define TMU_TSTR		(0x0004)
-#define TMU_TCOR		(0x0008)
-#define TMU_TCNT		(0x000C)
-#define TMU_TCR		(0x0010)
-/* Start bit for TMU ch3 */
-#define TSTR1_TMU3		(1 << 0)
-
-#define MIDR_CA57		(0x0D07 << MIDR_PN_SHIFT)
-#define MIDR_CA53		(0x0D03 << MIDR_PN_SHIFT)
-
-	.globl	rcar_micro_delay
-#if (TMU3_MEASUREMENT == 1)
-	.globl	tmu3_init
-	.globl	tmu3_start
-	.globl	tmu3_stop
-	.globl	tcnt3_snapshot
-#endif
-	/* Aligned with the cache line */
-	.align	6
-
-func rcar_micro_delay
-	cbz	x0, micro_delay_e
-	mrs	x1, midr_el1
-	and	x1, x1, #MIDR_PN_MASK << MIDR_PN_SHIFT
-	mov	w2, #MIDR_CA53
-	cmp	w1, w2
-	b.eq	micro_delay_ca53
-	b	micro_delay_ca57
-micro_delay_e:
-	ret
-endfunc rcar_micro_delay
-
-func micro_delay_ca57
-ca57_loop_1:
-	mov	x1, #185
-ca57_loop_2:
-	subs	x1, x1, #1
-	b.ne	ca57_loop_2
-	subs	x0, x0, #1
-	b.ne	ca57_loop_1
-	ret
-endfunc micro_delay_ca57
-
-func micro_delay_ca53
-ca53_loop_1:
-	mov	x1, #134
-ca53_loop_2:
-	subs	x1, x1, #1
-	b.ne	ca53_loop_2
-	subs	x0, x0, #1
-	b.ne	ca53_loop_1
-	ret
-endfunc micro_delay_ca53
-
-#if (TMU3_MEASUREMENT == 1)
-func tmu3_init
-	ldr	x2, =CPG_BASE
-	ldr	w0, [x2, #CPG_SMSTPCR1]
-	ldr	w1, [x2, #CPG_MSTPSR1]
-	ldr	w2, #MSTPCR1_TMU1
-	bl	mstpcr_write
-	ret
-endfunc tmu3_init
-
-func tmu3_start
-	ldr	x0, =TMU3_BASE
-	mov	w1, #0xFFFFFFFF
-	str	w1, [x0, TMU_TCNT]
-
-	ldr	x0, =TMU3_BASE
-	ldrb	w1, [x0, TMU_TSTR]
-	orr	w1, w1, #TSTR1_TMU3
-	strb	w1, [x0, TMU_TSTR]
-	ret
-endfunc tmu3_start
-
-func tcnt3_snapshot
-	ldr	x0, =TMU3_BASE
-	ldr	w0, [x0, TMU_TCNT]
-	ret
-endfunc tcnt3_snapshot
-
-
-func tmu3_stop
-	ldr	x0, =TMU3_BASE
-	ldrb	w1, [x0, TMU_TSTR]
-	and	w1, w1, #~TSTR1_TMU3
-	strb	w1, [x0, TMU_TSTR]
-	ret
-endfunc tmu3_stop
-#endif
diff --git a/drivers/renesas/rcar/delay/micro_delay.c b/drivers/renesas/rcar/delay/micro_delay.c
new file mode 100644
index 0000000..aced589
--- /dev/null
+++ b/drivers/renesas/rcar/delay/micro_delay.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include "micro_delay.h"
+
+#define RCAR_CONV_MICROSEC		1000000U
+
+void
+#if IMAGE_BL31
+	__attribute__ ((section (".system_ram")))
+#endif
+	rcar_micro_delay(uint64_t micro_sec)
+{
+	uint64_t freq;
+	uint64_t base_count;
+	uint64_t get_count;
+	uint64_t wait_time = 0U;
+
+	freq = read_cntfrq_el0();
+	base_count = read_cntpct_el0();
+	while (micro_sec > wait_time) {
+		get_count = read_cntpct_el0();
+		wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC) / freq;
+	}
+}
diff --git a/drivers/renesas/rcar/delay/micro_delay.h b/drivers/renesas/rcar/delay/micro_delay.h
index 4e4b28b..193daba 100644
--- a/drivers/renesas/rcar/delay/micro_delay.h
+++ b/drivers/renesas/rcar/delay/micro_delay.h
@@ -7,20 +7,9 @@
 #ifndef MICRO_DELAY_H
 #define MICRO_DELAY_H
 
-#define TMU3_MEASUREMENT	(0)
-
 #ifndef __ASSEMBLY__
 #include <stdint.h>
-void rcar_micro_delay(uint32_t count_us);
-
-#if (TMU3_MEASUREMENT == 1)
-void tmu3_start(void);
-void tmu3_init(void);
-void tmu3_stop(void);
-
-uint32_t tcnt3_snapshot(void);
-#endif
-
+void rcar_micro_delay(uint64_t micro_sec);
 #endif
 
 #endif /* MICRO_DELAY_H */
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
index 8cdfe75..b005caf 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -17,6 +17,7 @@
 #include "iic_dvfs.h"
 #include "rcar_def.h"
 #include "rcar_private.h"
+#include "micro_delay.h"
 #include "pwrc.h"
 
 /*
@@ -122,7 +123,6 @@
 #define	RST_BASE				(0xE6160000U)
 #define	RST_MODEMR				(RST_BASE + 0x0060U)
 #define	RST_MODEMR_BIT0				(0x00000001U)
-#define RCAR_CONV_MICROSEC			(1000000U)
 
 #if PMIC_ROHM_BD9571
 #define	BIT_BKUP_CTRL_OUT			((uint8_t)(1U << 4))
@@ -143,23 +143,6 @@
 IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
 #endif
 
-#if RCAR_SYSTEM_SUSPEND
-static void __attribute__ ((section (".system_ram")))
-	rcar_pwrc_micro_delay(uint64_t micro_sec)
-{
-	uint64_t freq, base, val;
-	uint64_t wait_time = 0;
-
-	freq = read_cntfrq_el0();
-	base = read_cntpct_el0();
-
-	while (micro_sec > wait_time) {
-		val = read_cntpct_el0() - base;
-		wait_time = val * RCAR_CONV_MICROSEC / freq;
-	}
-}
-#endif
-
 uint32_t rcar_pwrc_status(uint64_t mpidr)
 {
 	uint32_t ret = 0;
@@ -414,7 +397,7 @@
 	mmio_write_32(DBSC4_REG_DBACEN, 0);
 
 	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
-		rcar_pwrc_micro_delay(100);
+		rcar_micro_delay(100);
 	else if (product == RCAR_PRODUCT_H3) {
 		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
 		DBCAM_FLUSH(0);
@@ -465,7 +448,7 @@
 
 	/* Set the auto-refresh enable register */
 	mmio_write_32(DBSC4_REG_DBRFEN, 0U);
-	rcar_pwrc_micro_delay(1U);
+	rcar_micro_delay(1U);
 
 	if (product == RCAR_PRODUCT_M3)
 		return;
@@ -650,7 +633,6 @@
 				       DEVICE_SRAM_STACK_SIZE);
 	uint32_t sctlr;
 
-	rcar_pwrc_code_copy_to_system_ram();
 	rcar_pwrc_save_generic_timer(rcar_stack_generic_timer);
 
 	/* disable MMU */
@@ -665,10 +647,7 @@
 {
 #if PMIC_ROHM_BD9571
 	uint8_t mode;
-#endif
-	rcar_pwrc_code_copy_to_system_ram();
 
-#if PMIC_ROHM_BD9571
 	if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
 		panic();
 
@@ -683,7 +662,6 @@
 #if RCAR_SYSTEM_RESET_KEEPON_DDR
 	int32_t error;
 
-	rcar_pwrc_code_copy_to_system_ram();
 	error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
 	if (error) {
 		ERROR("Failed send KEEP10 init ret=%d \n", error);
diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/rcar/scif/scif.S
index 1cc0d59..09dc90b 100644
--- a/drivers/renesas/rcar/scif/scif.S
+++ b/drivers/renesas/rcar/scif/scif.S
@@ -75,6 +75,8 @@
 #if SCIF_CLK == SCIF_EXTARNAL_CLK
 #define	SCSCR_CKE_INT_CLK	(SCSCR_CKE_BRG)
 #else
+#define	SCFSR_TEND_MASK		(1 << 6)
+#define	SCFSR_TEND_TRANS_END	(0x0040)
 #define	SCSCR_CKE_INT_CLK	(SCSCR_CKE_INT)
 #endif
 #define	SCFSR_INIT_DATA		(0x0000)
@@ -281,6 +283,11 @@
 	bcs	2b
 	strb	w0, [x1, #SCIF_SCFTDR]
 
+	/* Clear TEND flag */
+	ldrh	w2, [x1, #SCIF_SCFSR]
+	and	w2, w2, #~SCFSR_TEND_MASK
+	strh	w2, [x1, #SCIF_SCFSR]
+
 	ret
 endfunc console_core_putc
 
@@ -309,16 +316,12 @@
 func console_flush
 	ldr	x0, =SCIF2_BASE
 1:
-	ldrh	w1, [x0, #SCIF_SCFDR]
-	ubfx	w1, w1, #8, #5
-	cmp	w1, #0
+	/* Check TEND flag */
+	ldrh	w1, [x0, #SCIF_SCFSR]
+	and	w1, w1, #SCFSR_TEND_MASK
+	cmp	w1, #SCFSR_TEND_TRANS_END
 	bne	1b
 
-	mov x0, #100
-	mov x3, x30
-	bl rcar_micro_delay
-	mov x30, x3
-
 	ldr	x0, =SCIF2_BASE
 	ldrh	w1, [x0, #SCIF_SCSCR]
 	and	w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)
diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/rcar/watchdog/swdt.c
index 42f8653..7793ae5 100644
--- a/drivers/renesas/rcar/watchdog/swdt.c
+++ b/drivers/renesas/rcar/watchdog/swdt.c
@@ -133,7 +133,11 @@
 	    (ARM_IRQ_SEC_WDT & ~ITARGET_MASK);
 	uint32_t i;
 
+	/* Disable FIQ interrupt */
 	write_daifset(DAIF_FIQ_BIT);
+	/* FIQ interrupts are not taken to EL3 */
+	write_scr_el3(read_scr_el3() & ~SCR_FIQ_BIT);
+
 	swdt_disable();
 	gicv2_cpuif_disable();
 
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
index 74677f6..62997bc 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
@@ -48,701 +48,787 @@
  ******************************************************************************/
 uint32_t init_ddr(void)
 {
-
    uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
    uint32_t ddr_md;
 
 /* rev.0.08 */
-   uint32_t RegVal,j;
+   uint32_t RegVal, j;
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
-   uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
+   uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
+/* rev.0.10 */
+   uint32_t pdr_ctl;
+/* rev.0.11 */
+   uint32_t byp_ctl;
 
 /* rev.0.08 */
    if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
      pdqsr_ctl  = 1;
      lcdl_ctl   = 1;
-    }else {
+     pdr_ctl    = 1;  /* rev.0.10 */
+     byp_ctl    = 1;  /* rev.0.11 */
+    } else {
      pdqsr_ctl  = 0;
      lcdl_ctl   = 0;
+     pdr_ctl    = 0;  /* rev.0.10 */
+     byp_ctl    = 0;  /* rev.0.11 */
    }
 
    /*  Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
-   ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
+   ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0;
 
    /*  1584Mbps setting */
-   if (ddr_md==0){
+   if (ddr_md == 0) {
       /* CPG setting ===============================================*/
-      WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
-      WriteReg_32(CPG_CPGWPCR,0xA5A50000);
+      WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF);
+      WriteReg_32(CPG_CPGWPCR, 0xA5A50000);
 
-      WriteReg_32(CPG_SRCR4,0x20000000);
+      WriteReg_32(CPG_SRCR4, 0x20000000);
 
-      WriteReg_32(0xE61500DC,0xe2200000);  /*  Change to 1584Mbps */
-      while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
+      WriteReg_32(0xE61500DC, 0xe2200000);  /*  Change to 1584Mbps */
+      while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0);
 
-      WriteReg_32(CPG_SRSTCLR4,0x20000000);
+      WriteReg_32(CPG_SRSTCLR4, 0x20000000);
 
-      WriteReg_32(CPG_CPGWPCR,0xA5A50001);
+      WriteReg_32(CPG_CPGWPCR, 0xA5A50001);
 
       /* CPG setting ===============================================*/
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
-   WriteReg_32(DBSC_E3_DBKIND,0x00000007);
-
+   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
+   WriteReg_32(DBSC_E3_DBKIND, 0x00000007);
 
 #if RCAR_DRAM_DDR3L_MEMCONF == 0
-   WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02); /*  1GB */
+   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /*  1GB */
 #elif RCAR_DRAM_DDR3L_MEMCONF == 1
-   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /*  2GB(default) */
+   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /*  2GB(default) */
 #elif RCAR_DRAM_DDR3L_MEMCONF == 2
-   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02); /*  4GB */
+   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); /*  4GB */
 #else
-   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /*  2GB */
+   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /*  2GB */
 #endif
 
 #if RCAR_DRAM_DDR3L_MEMDUAL == 1
-         RegVal_R2 = (ReadReg_32(0xE6790614));
-         WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /*  MCS1_N/MODT1 are activated. */
+	 RegVal_R2 = (ReadReg_32(0xE6790614));
+         WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /*  MCS1_N/MODT1 are activated. */
 #endif
 
 
-
-   WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
-      WriteReg_32(DBSC_E3_DBTR1,0x00000008);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR0, 0x0000000B);
+      WriteReg_32(DBSC_E3_DBTR1, 0x00000008);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
-      WriteReg_32(DBSC_E3_DBTR1,0x00000009);
+      WriteReg_32(DBSC_E3_DBTR0, 0x0000000D);
+      WriteReg_32(DBSC_E3_DBTR1, 0x00000009);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR2,0x00000000);
+   WriteReg_32(DBSC_E3_DBTR2, 0x00000000);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
-      WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
-      WriteReg_32(DBSC_E3_DBTR5,0x00000027);
-      WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR3, 0x0000000B);
+      WriteReg_32(DBSC_E3_DBTR4, 0x000B000B);
+      WriteReg_32(DBSC_E3_DBTR5, 0x00000027);
+      WriteReg_32(DBSC_E3_DBTR6, 0x0000001C);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
-      WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
-      WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
-      WriteReg_32(DBSC_E3_DBTR6,0x00000020);
+      WriteReg_32(DBSC_E3_DBTR3, 0x0000000D);
+      WriteReg_32(DBSC_E3_DBTR4, 0x000D000D);
+      WriteReg_32(DBSC_E3_DBTR5, 0x0000002D);
+      WriteReg_32(DBSC_E3_DBTR6, 0x00000020);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR7,0x00060006);
+   WriteReg_32(DBSC_E3_DBTR7, 0x00060006);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR8,0x00000020);
-      WriteReg_32(DBSC_E3_DBTR9,0x00000006);
-      WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
-      WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
-      WriteReg_32(DBSC_E3_DBTR12,0x00120012);
-      WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
-      WriteReg_32(DBSC_E3_DBTR14,0x00140005);
-      WriteReg_32(DBSC_E3_DBTR15,0x00050004);
-      WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
-      WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR8, 0x00000020);
+      WriteReg_32(DBSC_E3_DBTR9, 0x00000006);
+      WriteReg_32(DBSC_E3_DBTR10, 0x0000000C);
+      WriteReg_32(DBSC_E3_DBTR11, 0x0000000A);
+      WriteReg_32(DBSC_E3_DBTR12, 0x00120012);
+      WriteReg_32(DBSC_E3_DBTR13, 0x000000CE);
+      WriteReg_32(DBSC_E3_DBTR14, 0x00140005);
+      WriteReg_32(DBSC_E3_DBTR15, 0x00050004);
+      WriteReg_32(DBSC_E3_DBTR16, 0x071F0305);
+      WriteReg_32(DBSC_E3_DBTR17, 0x040C0000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR8,0x00000021);
-      WriteReg_32(DBSC_E3_DBTR9,0x00000007);
-      WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
-      WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
-      WriteReg_32(DBSC_E3_DBTR12,0x00140014);
-      WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
-      WriteReg_32(DBSC_E3_DBTR14,0x00170006);
-      WriteReg_32(DBSC_E3_DBTR15,0x00060005);
-      WriteReg_32(DBSC_E3_DBTR16,0x09210507);
-      WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
+      WriteReg_32(DBSC_E3_DBTR8, 0x00000021);
+      WriteReg_32(DBSC_E3_DBTR9, 0x00000007);
+      WriteReg_32(DBSC_E3_DBTR10, 0x0000000E);
+      WriteReg_32(DBSC_E3_DBTR11, 0x0000000C);
+      WriteReg_32(DBSC_E3_DBTR12, 0x00140014);
+      WriteReg_32(DBSC_E3_DBTR13, 0x000000F2);
+      WriteReg_32(DBSC_E3_DBTR14, 0x00170006);
+      WriteReg_32(DBSC_E3_DBTR15, 0x00060005);
+      WriteReg_32(DBSC_E3_DBTR16, 0x09210507);
+      WriteReg_32(DBSC_E3_DBTR17, 0x040E0000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR18,0x00000200);
+   WriteReg_32(DBSC_E3_DBTR18, 0x00000200);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR19,0x01000040);
-      WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR19, 0x01000040);
+      WriteReg_32(DBSC_E3_DBTR20, 0x020000D6);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
-      WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
+      WriteReg_32(DBSC_E3_DBTR19, 0x0129004B);
+      WriteReg_32(DBSC_E3_DBTR20, 0x020000FB);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR21,0x00040004);
-   WriteReg_32(DBSC_E3_DBBL,0x00000000);
-   WriteReg_32(DBSC_E3_DBODT0,0x00000001);
-   WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
-   WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
-   WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
-   WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
-   WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
+   WriteReg_32(DBSC_E3_DBTR21, 0x00040004);
+   WriteReg_32(DBSC_E3_DBBL, 0x00000000);
+   WriteReg_32(DBSC_E3_DBODT0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBADJ0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002);
+   WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010);
+   WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001);
+   WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
-      WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03);
+      WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
-      WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
+      WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03);
+      WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C);
    } /*  ddr_md */
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step0( INITBYP )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
-   WriteReg_32(DBSC_E3_DBCMD,0x01840001);
-   WriteReg_32(DBSC_E3_DBCMD,0x08840000);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A);
+   WriteReg_32(DBSC_E3_DBCMD, 0x01840001);
+   WriteReg_32(DBSC_E3_DBCMD, 0x08840000);
+   NOTICE("BL2: [COLD_BOOT]\n");	/* rev.0.11 */
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058904);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058904);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A04);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A04);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step2( DRAMRST/DRAMINT training )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
-   while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
+   if (byp_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720);
+   } else {
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700);
+   }
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
+   while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
+      WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
+   if (ddr_md == 0) {                                 /*  1584Mbps */
       if (REFRESH_RATE > 3900) {
-          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018);  /*            [7]SRT=0 */
+          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018);  /*            [7]SRT=0 */
       } else {
-          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098);  /*            [7]SRT=1 */
+          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098);  /*            [7]SRT=1 */
       }
    } else {                                        /*  1856Mbps */
       if (REFRESH_RATE > 3900) {
-          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020);  /*            [7]SRT=0 */
+          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020);  /*            [7]SRT=0 */
       } else {
-          WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0);  /*            [7]SRT=1 */
+          WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0);  /*            [7]SRT=1 */
       } /*  REFRESH_RATE */
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010181);
-   WriteReg_32(DBSC_E3_DBCMD,0x08840001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010181);
+   WriteReg_32(DBSC_E3_DBCMD, 0x08840001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step3( WL/QSG training )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010601);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010601);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   /*  rev.0.03 add Comment */
-   /****************************************************************************
-    *  Initial_Step4( WLADJ training )
-    ***************************************************************************/
-   for ( i = 0; i<4; i++){
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+   for (i = 0; i < 4; i++) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
       RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
       RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
       RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
-      if ( RegVal_R6 > 0 ){
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
+      if (RegVal_R6 > 0) {
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6);
       } else {
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
       } /*  RegVal_R6 */
    } /*  for i */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
+   /*  rev.0.10 move Comment */
+   /****************************************************************************
+    *  Initial_Step4( WLADJ training )
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0);
 
    /* rev.0.08 */
-   if (pdqsr_ctl == 1){}else{
-
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   if (pdqsr_ctl == 1){} else {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   }
 
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   /*  rev.0.03 add Comment */
    /****************************************************************************
-    *  Initial_Step5678( RdWrbitRdWreye )
+    *  Initial_Step5(Read Data Bit Deskew)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8);
 
    /* rev.0.08 */
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-if (pdqsr_ctl == 1){
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+if (pdqsr_ctl == 1) {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
 }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+   }
+
+   /****************************************************************************
+    *  Initial_Step6(Write Data Bit Deskew)
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-if (pdqsr_ctl == 1){
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   /****************************************************************************
+    *  Initial_Step7(Read Data Eye Training)
+    ***************************************************************************/
+if (pdqsr_ctl == 1) {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
 }
 
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+   }
+
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-if (pdqsr_ctl == 1){
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+if (pdqsr_ctl == 1) {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
 }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+   }
 
-   /*  rev.0.03 add Comment */
    /****************************************************************************
-    *  Initial_Step3_2( DQS Gate Training )
+    *  Initial_Step8(Write Data Eye Training)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
-    *  Initial_Step5-2_7-2( Rd bit Rd eye )
+    *  Initial_Step3_2( DQS Gate Training )
     ***************************************************************************/
-   for ( i = 0; i < 4; i++){
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+
+   for (i = 0; i < 4; i++) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
       RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
       RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
       RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
       RegVal_R12 = (RegVal_R5 >> 0x2);
-      if ( RegVal_R12 < RegVal_R6 ){
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+      if (RegVal_R12 < RegVal_R6) {
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
       } else {
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
       } /*  RegVal_R12 < RegVal_R6 */
    } /*  for i */
 
+   /*  rev.0.10 move Comment */
+   /****************************************************************************
+    *  Initial_Step5-2_7-2( Rd bit Rd eye )
+    ***************************************************************************/
 /* rev.0.08 */
-   if (pdqsr_ctl == 1){}else{
-
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-
+   if (pdqsr_ctl == 1){} else {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+   }
 
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
 /* rev.0.08 */
-   if (lcdl_ctl == 1){
-       for (i=0; i< 4; i++) {
-          WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-          dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-          WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
-          bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
-          bdlcount_0c_div2  = (bdlcount_0c >> 1);
-          bdlcount_0c_div4  = (bdlcount_0c >> 2);
-          bdlcount_0c_div8  = (bdlcount_0c >> 3);
-          bdlcount_0c_div16 = (bdlcount_0c >> 4);
+   if (lcdl_ctl == 1) {
+       for (i = 0; i < 4; i++) {
+          WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	  dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
+          WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
+	  bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
+	  bdlcount_0c_div2  = (bdlcount_0c >> 1);
+	  bdlcount_0c_div4  = (bdlcount_0c >> 2);
+	  bdlcount_0c_div8  = (bdlcount_0c >> 3);
+	  bdlcount_0c_div16 = (bdlcount_0c >> 4);
 
-          if (ddr_md==0){                                 /*  1584Mbps */
-             lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
-             lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
-          } else {                                        /*  1856Mbps */
-             lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
-             lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
-          } /*  ddr_md */
+          if (ddr_md == 0) {                                 /*  1584Mbps */
+	     lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8;
+	     lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16;
+	  } else {                                        /*  1856Mbps */
+	     lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4;
+	     lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4;
+	  } /*  ddr_md */
 
-          if (dqsgd_0c > lcdl_judge1) {
-             if (dqsgd_0c <= lcdl_judge2) {
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-                WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
-              } else {
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-                gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-                WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
-                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
-                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
-                WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
-                rbd_0c[0] = (RegVal      ) & 0x0000001f;
-                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
-                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
-                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
-                for (j=0; j< 4; j++) {
-                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
-                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
-                    RegVal = RegVal | (rbd_0c[j] <<8*j);
-                }
-                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
-                rbd_0c[0] = (RegVal      ) & 0x0000001f;
-                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
-                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
-                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
-                for (j=0; j< 4; j++) {
-                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
-                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
-                    RegVal = RegVal | (rbd_0c[j] <<8*j);
-                }
-                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-             }
-          }
+	  if (dqsgd_0c > lcdl_judge1) {
+	     if (dqsgd_0c <= lcdl_judge2) {
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+                WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
+	      } else {
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+		WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+		gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+                WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+		rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
+		rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
+                WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rbd_0c[0] = (RegVal) &0x0000001f;
+		rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
+		rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
+		rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+                for (j = 0; j < 4; j++) {
+		    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
+		    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
+                    RegVal = RegVal | (rbd_0c[j] << 8 * j);
+		}
+		WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rbd_0c[0] = (RegVal) &0x0000001f;
+		rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
+		rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
+		rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+                for (j = 0; j < 4; j++) {
+		    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
+		    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
+                    RegVal = RegVal | (rbd_0c[j] << 8 * j);
+		}
+		WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+	     }
+	  }
        }
-       WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
-       WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
+       WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002);
+       WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37);
    }
 
-
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
-   while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
+   if (byp_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720);
+   } else {
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700);
+   }
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
+   while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E);
 
-   WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
-   WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
+   WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010);
+   WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
+      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
-   WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
-   WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
-   WriteReg_32(DBSC_E3_DBACEN,0x00000001);
+   WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000);
+   WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001);
+   WriteReg_32(DBSC_E3_DBRFEN, 0x00000001);
+   WriteReg_32(DBSC_E3_DBACEN, 0x00000001);
 
 /* rev.0.08 */
-   if (pdqsr_ctl == 1){
-   WriteReg_32(0xE67F0018,0x00000001);
+   if (pdqsr_ctl == 1) {
+   WriteReg_32(0xE67F0018, 0x00000001);
    RegVal = ReadReg_32(0x40000000);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
-   WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000);
+   WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
    }
 
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+   }
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step9( Initial End )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
-   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
+   WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000);
+   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
 
 #ifdef ddr_qos_init_setting /*  only for non qos_init */
-   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
-   WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
-   WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
-   WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
-   WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
-   WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
-   WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
-   WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
-   WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
-   WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
-   WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
-   WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
-   WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
-   WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
-   WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
-   WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
-   WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
-   WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
-   WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
-   WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
-   WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
+   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
+   WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218);
+   WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4);
+   WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037);
+   WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111);
+   WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123);
+   WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00);
+   WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00);
+   WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000);
+   WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000);
+   WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300);
+   WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200);
+   WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0);
+   WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080);
+   WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030);
+   WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020);
+   WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010);
 
 /* rev.0.08 */
-   if (pdqsr_ctl == 1){}else{
-   WriteReg_32(0xE67F0018,0x00000001);
+   if (pdqsr_ctl == 1){} else {
+   WriteReg_32(0xE67F0018, 0x00000001);
    }
 
-   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
+   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
 #endif
 
    return 1;   /*  rev.0.04 Restore the return code */
@@ -752,7 +838,6 @@
 /*  rev.0.04 add function */
 uint32_t recovery_from_backup_mode(void)
 {
-
    /****************************************************************************
     *  recovery_Step0(DBSC Setting 1) / same "init_ddr"
     ***************************************************************************/
@@ -760,733 +845,810 @@
    uint32_t ddr_md;
    uint32_t err;
 
-
 /* rev.0.08 */
-   uint32_t RegVal,j;
+   uint32_t RegVal, j;
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
-   uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
+   uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
+   /* rev.0.10 */
+   uint32_t pdr_ctl;
+   /* rev.0.11 */
+   uint32_t byp_ctl;
 
 /* rev.0.08 */
    if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
      pdqsr_ctl  = 1;
      lcdl_ctl   = 1;
-    }else {
+     pdr_ctl    = 1;  /* rev.0.10 */
+     byp_ctl    = 1;  /* rev.0.11 */
+    } else {
      pdqsr_ctl  = 0;
      lcdl_ctl   = 0;
+     pdr_ctl    = 0;  /* rev.0.10 */
+     byp_ctl    = 0;  /* rev.0.11 */
    }
 
-
    /*  Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
-   ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
+   ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0;
 
    /*  1584Mbps setting */
-   if (ddr_md==0){
+   if (ddr_md == 0) {
    /* CPG setting ===============================================*/
-   WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
-   WriteReg_32(CPG_CPGWPCR,0xA5A50000);
+   WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF);
+   WriteReg_32(CPG_CPGWPCR, 0xA5A50000);
 
-   WriteReg_32(CPG_SRCR4,0x20000000);
+   WriteReg_32(CPG_SRCR4, 0x20000000);
 
-   WriteReg_32(0xE61500DC,0xe2200000);  /*  Change to 1584Mbps */
-   while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
+   WriteReg_32(0xE61500DC, 0xe2200000);  /*  Change to 1584Mbps */
+   while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0);
 
-   WriteReg_32(CPG_SRSTCLR4,0x20000000);
+   WriteReg_32(CPG_SRSTCLR4, 0x20000000);
 
-   WriteReg_32(CPG_CPGWPCR,0xA5A50001);
+   WriteReg_32(CPG_CPGWPCR, 0xA5A50001);
 
    /* CPG setting ===============================================*/
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
-   WriteReg_32(DBSC_E3_DBKIND,0x00000007);
+   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
+   WriteReg_32(DBSC_E3_DBKIND, 0x00000007);
 
 #if RCAR_DRAM_DDR3L_MEMCONF == 0
-   WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02);
+   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02);
 #elif RCAR_DRAM_DDR3L_MEMCONF == 1
-   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
+   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
 #elif RCAR_DRAM_DDR3L_MEMCONF == 2
-   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02);
+   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02);
 #else
-   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
+   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
 #endif
 
 /* rev.0.08 */
 #if RCAR_DRAM_DDR3L_MEMDUAL == 1
-         RegVal_R2 = (ReadReg_32(0xE6790614));
-         WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /*  MCS1_N/MODT1 are activated. */
+	 RegVal_R2 = (ReadReg_32(0xE6790614));
+         WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /*  MCS1_N/MODT1 are activated. */
 #endif
 
-   WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
-      WriteReg_32(DBSC_E3_DBTR1,0x00000008);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR0, 0x0000000B);
+      WriteReg_32(DBSC_E3_DBTR1, 0x00000008);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
-      WriteReg_32(DBSC_E3_DBTR1,0x00000009);
+      WriteReg_32(DBSC_E3_DBTR0, 0x0000000D);
+      WriteReg_32(DBSC_E3_DBTR1, 0x00000009);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR2,0x00000000);
+   WriteReg_32(DBSC_E3_DBTR2, 0x00000000);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
-      WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
-      WriteReg_32(DBSC_E3_DBTR5,0x00000027);
-      WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR3, 0x0000000B);
+      WriteReg_32(DBSC_E3_DBTR4, 0x000B000B);
+      WriteReg_32(DBSC_E3_DBTR5, 0x00000027);
+      WriteReg_32(DBSC_E3_DBTR6, 0x0000001C);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
-      WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
-      WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
-      WriteReg_32(DBSC_E3_DBTR6,0x00000020);
+      WriteReg_32(DBSC_E3_DBTR3, 0x0000000D);
+      WriteReg_32(DBSC_E3_DBTR4, 0x000D000D);
+      WriteReg_32(DBSC_E3_DBTR5, 0x0000002D);
+      WriteReg_32(DBSC_E3_DBTR6, 0x00000020);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR7,0x00060006);
+   WriteReg_32(DBSC_E3_DBTR7, 0x00060006);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR8,0x00000020);
-      WriteReg_32(DBSC_E3_DBTR9,0x00000006);
-      WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
-      WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
-      WriteReg_32(DBSC_E3_DBTR12,0x00120012);
-      WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
-      WriteReg_32(DBSC_E3_DBTR14,0x00140005);
-      WriteReg_32(DBSC_E3_DBTR15,0x00050004);
-      WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
-      WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR8, 0x00000020);
+      WriteReg_32(DBSC_E3_DBTR9, 0x00000006);
+      WriteReg_32(DBSC_E3_DBTR10, 0x0000000C);
+      WriteReg_32(DBSC_E3_DBTR11, 0x0000000A);
+      WriteReg_32(DBSC_E3_DBTR12, 0x00120012);
+      WriteReg_32(DBSC_E3_DBTR13, 0x000000CE);
+      WriteReg_32(DBSC_E3_DBTR14, 0x00140005);
+      WriteReg_32(DBSC_E3_DBTR15, 0x00050004);
+      WriteReg_32(DBSC_E3_DBTR16, 0x071F0305);
+      WriteReg_32(DBSC_E3_DBTR17, 0x040C0000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR8,0x00000021);
-      WriteReg_32(DBSC_E3_DBTR9,0x00000007);
-      WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
-      WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
-      WriteReg_32(DBSC_E3_DBTR12,0x00140014);
-      WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
-      WriteReg_32(DBSC_E3_DBTR14,0x00170006);
-      WriteReg_32(DBSC_E3_DBTR15,0x00060005);
-      WriteReg_32(DBSC_E3_DBTR16,0x09210507);
-      WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
+      WriteReg_32(DBSC_E3_DBTR8, 0x00000021);
+      WriteReg_32(DBSC_E3_DBTR9, 0x00000007);
+      WriteReg_32(DBSC_E3_DBTR10, 0x0000000E);
+      WriteReg_32(DBSC_E3_DBTR11, 0x0000000C);
+      WriteReg_32(DBSC_E3_DBTR12, 0x00140014);
+      WriteReg_32(DBSC_E3_DBTR13, 0x000000F2);
+      WriteReg_32(DBSC_E3_DBTR14, 0x00170006);
+      WriteReg_32(DBSC_E3_DBTR15, 0x00060005);
+      WriteReg_32(DBSC_E3_DBTR16, 0x09210507);
+      WriteReg_32(DBSC_E3_DBTR17, 0x040E0000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR18,0x00000200);
+   WriteReg_32(DBSC_E3_DBTR18, 0x00000200);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR19,0x01000040);
-      WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR19, 0x01000040);
+      WriteReg_32(DBSC_E3_DBTR20, 0x020000D6);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
-      WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
+      WriteReg_32(DBSC_E3_DBTR19, 0x0129004B);
+      WriteReg_32(DBSC_E3_DBTR20, 0x020000FB);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR21,0x00040004);
-   WriteReg_32(DBSC_E3_DBBL,0x00000000);
-   WriteReg_32(DBSC_E3_DBODT0,0x00000001);
-   WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
-   WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
-   WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
-   WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
-   WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
+   WriteReg_32(DBSC_E3_DBTR21, 0x00040004);
+   WriteReg_32(DBSC_E3_DBBL, 0x00000000);
+   WriteReg_32(DBSC_E3_DBODT0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBADJ0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002);
+   WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010);
+   WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001);
+   WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
-      WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03);
+      WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
-      WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
+      WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03);
+      WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C);
    } /*  ddr_md */
 
    /****************************************************************************
     *  recovery_Step1(PHY setting 1)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
-   WriteReg_32(DBSC_E3_DBCMD,0x01840001);
-   WriteReg_32(DBSC_E3_DBCMD,0x0A840000);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008); /*  DDR_PLLCR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003); /*  DDR_PGCR1 */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020); /*  DDR_DXCCR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A); /*  DDR_ACIOCR0 */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
-   while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A);
+   WriteReg_32(DBSC_E3_DBCMD, 0x01840001);
+   WriteReg_32(DBSC_E3_DBCMD, 0x0A840000);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); /*  DDR_PLLCR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); /*  DDR_PGCR1 */
+   if (byp_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720);
+   } else {
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700);
+   }
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); /*  DDR_DXCCR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); /*  DDR_ACIOCR0 */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
+   while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
+      WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
+   if (ddr_md == 0) {                                 /*  1584Mbps */
       if (REFRESH_RATE > 3900) {
-          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018);  /*            [7]SRT=0 */
+          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018);  /*            [7]SRT=0 */
       } else {
-          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098);  /*            [7]SRT=1 */
+          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098);  /*            [7]SRT=1 */
       }
    } else {                                        /*  1856Mbps */
       if (REFRESH_RATE > 3900) {
-          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020);  /*            [7]SRT=0 */
+          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020);  /*            [7]SRT=0 */
       } else {
-          WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0);  /*            [7]SRT=1 */
+          WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0);  /*            [7]SRT=1 */
       } /*  REFRESH_RATE */
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021); /*  DDR_DSGCR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); /*  DDR_DSGCR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x40010000);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x40010000);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /*  DDR_ZQ0DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /*  DDR_ZQ1DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0xC4285FBF);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /*  DDR_ZQ2DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /*  DDR_ZQCR */
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /*  DDR_ZQ0DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /*  DDR_ZQ1DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC4285FBF);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /*  DDR_ZQ2DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /*  DDR_ZQCR */
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00050001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00050001);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
    /*  ddr backupmode end */
-   if(ddrBackup) {
+   if (ddrBackup) {
       NOTICE("[WARM_BOOT]");
    } else {
       NOTICE("[COLD_BOOT]");
    } /*  ddrBackup */
-   err=rcar_dram_update_boot_status(ddrBackup);
-   if(err){
+   err = rcar_dram_update_boot_status(ddrBackup);
+   if (err) {
       NOTICE("[BOOT_STATUS_UPDATE_ERROR]");
       return INITDRAM_ERR_I;
    } /*  err */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /*  DDR_ZQ0DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /*  DDR_ZQ1DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x04285FBF);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /*  DDR_ZQ2DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /*  DDR_ZQ0DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /*  DDR_ZQ1DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x04285FBF);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /*  DDR_ZQ2DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x08000000);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x08000000);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00000003);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000003);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /*  DDR_ZQCR */
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /*  DDR_ZQCR */
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
    } /*  ddr_md */
 
 /* rev0.08 */
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000000C);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x18000040);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000000C);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x18000040);
 
    /****************************************************************************
     *  recovery_Step2(PHY setting 2)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
 
-   WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
-   WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
+   WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
+   WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010);
 
    /*  Select setting value in bps */
-   if (ddr_md==0){                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
+   if (ddr_md == 0) {                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
+      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
-   WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
-   WriteReg_32(DBSC_E3_DBCMD,0x0A840001);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
+   WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000);
+   WriteReg_32(DBSC_E3_DBRFEN, 0x00000001);
+   WriteReg_32(DBSC_E3_DBCMD, 0x0A840001);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0);
 
-   WriteReg_32(DBSC_E3_DBCMD,0x00000000);
+   WriteReg_32(DBSC_E3_DBCMD, 0x00000000);
 
-   WriteReg_32(DBSC_E3_DBCMD,0x04840010);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
+   WriteReg_32(DBSC_E3_DBCMD, 0x04840010);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010701);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010701);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   for ( i = 0; i<4; i++)
+   for (i = 0; i < 4; i++)
    {
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
       RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
       RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
       RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
 
-      if ( RegVal_R6 > 0 ){
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
+      if (RegVal_R6 > 0) {
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6);
       } else {
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
       } /*  RegVal_R6 */
    } /*  for i */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0);
 
    /* rev.0.08 */
-   if (pdqsr_ctl == 1){}else{
-
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-
+   if (pdqsr_ctl == 1){} else {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+   }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8);
 
    /* rev.0.08 */
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-if (pdqsr_ctl == 1){
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+if (pdqsr_ctl == 1) {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
 }
 
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+   }
+
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-if (pdqsr_ctl == 1){
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+if (pdqsr_ctl == 1) {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
 }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+   }
+
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-if (pdqsr_ctl == 1){
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+if (pdqsr_ctl == 1) {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
 }
 
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+   }
+
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
-   for ( i = 0; i < 4; i++){
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+   for (i = 0; i < 4; i++) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
       RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
       RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
       RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
       RegVal_R12 = (RegVal_R5 >> 0x2);
 
-      if ( RegVal_R12 < RegVal_R6 ){
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+      if (RegVal_R12 < RegVal_R6) {
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
       } else {
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
       } /*  RegVal_R12 < RegVal_R6 */
    } /*  for i */
 
 /* rev.0.08 */
-   if (pdqsr_ctl == 1){}else{
-
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-
+   if (pdqsr_ctl == 1){} else {
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
-   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+   }
 
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
+   while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
 
 /* rev.0.08 */
-   if (lcdl_ctl == 1){
-       for (i=0; i< 4; i++) {
-          WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
-          dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-          WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
-          bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
-          bdlcount_0c_div2  = (bdlcount_0c >> 1);
-          bdlcount_0c_div4  = (bdlcount_0c >> 2);
-          bdlcount_0c_div8  = (bdlcount_0c >> 3);
-          bdlcount_0c_div16 = (bdlcount_0c >> 4);
+   if (lcdl_ctl == 1) {
+       for (i = 0; i < 4; i++) {
+          WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+	  dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
+          WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
+	  bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
+	  bdlcount_0c_div2  = (bdlcount_0c >> 1);
+	  bdlcount_0c_div4  = (bdlcount_0c >> 2);
+	  bdlcount_0c_div8  = (bdlcount_0c >> 3);
+	  bdlcount_0c_div16 = (bdlcount_0c >> 4);
 
-          if (ddr_md==0){                                 /*  1584Mbps */
-             lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
-             lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
-          } else {                                        /*  1856Mbps */
-             lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
-             lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
-          } /*  ddr_md */
+          if (ddr_md == 0) {                                 /*  1584Mbps */
+	     lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8;
+	     lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16;
+	  } else {                                        /*  1856Mbps */
+	     lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4;
+	     lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4;
+	  } /*  ddr_md */
 
-          if (dqsgd_0c > lcdl_judge1) {
-             if (dqsgd_0c <= lcdl_judge2) {
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-                WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
-              } else {
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-                gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-                WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
-                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
-                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
-                WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
-                rbd_0c[0] = (RegVal      ) & 0x0000001f;
-                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
-                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
-                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
-                for (j=0; j< 4; j++) {
-                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
-                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
-                    RegVal = RegVal | (rbd_0c[j] <<8*j);
-                }
-                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
-                rbd_0c[0] = (RegVal      ) & 0x0000001f;
-                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
-                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
-                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
-                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
-                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
-                for (j=0; j< 4; j++) {
-                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
-                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
-                    RegVal = RegVal | (rbd_0c[j] <<8*j);
-                }
-                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-             }
-          }
+	  if (dqsgd_0c > lcdl_judge1) {
+	     if (dqsgd_0c <= lcdl_judge2) {
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+                WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
+	      } else {
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+		WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+		gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+                WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+		rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
+		rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
+                WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rbd_0c[0] = (RegVal) &0x0000001f;
+		rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
+		rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
+		rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+                for (j = 0; j < 4; j++) {
+		    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
+		    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
+                    RegVal = RegVal | (rbd_0c[j] << 8 * j);
+		}
+		WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rbd_0c[0] = (RegVal) &0x0000001f;
+		rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
+		rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
+		rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
+		WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
+		RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+                for (j = 0; j < 4; j++) {
+		    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
+		    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
+                    RegVal = RegVal | (rbd_0c[j] << 8 * j);
+		}
+		WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+	     }
+	  }
        }
-       WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
-       WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
+       WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002);
+       WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37);
    }
 
 
-
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
-   while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
+   if (byp_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720);
+   } else {
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700);
+   }
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
+   while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E);
 
    /****************************************************************************
     *  recovery_Step3(DBSC Setting 2)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
-   WriteReg_32(DBSC_E3_DBACEN,0x00000001);
+   WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001);
+   WriteReg_32(DBSC_E3_DBACEN, 0x00000001);
 
 /* rev.0.08 */
-   if (pdqsr_ctl == 1){
-   WriteReg_32(0xE67F0018,0x00000001);
+   if (pdqsr_ctl == 1) {
+   WriteReg_32(0xE67F0018, 0x00000001);
    RegVal = ReadReg_32(0x40000000);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
-   WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
-
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000);
+   WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
    }
 
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+   }
 
-   WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
-   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
+   WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000);
+   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
 
 #ifdef ddr_qos_init_setting /*  only for non qos_init */
-   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
-   WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
-   WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
-   WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
-   WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
-   WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
-   WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
-   WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
-   WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
-   WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
-   WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
-   WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
-   WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
-   WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
-   WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
-   WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
-   WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
-   WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
-   WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
-   WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
-   WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
+   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
+   WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218);
+   WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4);
+   WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037);
+   WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001);
+   WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111);
+   WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123);
+   WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00);
+   WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00);
+   WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000);
+   WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000);
+   WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300);
+   WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200);
+   WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0);
+   WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0);
+   WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0);
+   WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080);
+   WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030);
+   WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020);
+   WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010);
 
 /* rev.0.08 */
-   if (pdqsr_ctl == 1){}else{
-   WriteReg_32(0xE67F0018,0x00000001);
+   if (pdqsr_ctl == 1){} else {
+   WriteReg_32(0xE67F0018, 0x00000001);
    }
 
-   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
+   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
 #endif
 
    return 1;
@@ -1504,38 +1666,37 @@
 {
     uint32_t dataL;
     uint32_t failcount;
-    uint32_t md=0;
-    uint32_t ddr=0;
+    uint32_t md = 0;
+    uint32_t ddr = 0;
 
     md = *((volatile uint32_t*)RST_MODEMR);
     ddr = (md & 0x00080000) >> 19;
-    if(ddr == 0x0){
-        NOTICE("BL2: DDR1584(%s)", RCAR_E3_DDR_VERSION);
-    }
-    else if(ddr == 0x1){
-        NOTICE("BL2: DDR1856(%s)", RCAR_E3_DDR_VERSION);
+    if (ddr == 0x0) {
+	NOTICE("BL2: DDR1584(%s)", RCAR_E3_DDR_VERSION);
+    } else if(ddr == 0x1){
+	NOTICE("BL2: DDR1856(%s)", RCAR_E3_DDR_VERSION);
     } /*  ddr */
 
     rcar_dram_get_boot_status(&ddrBackup);
 
-    if(ddrBackup==DRAM_BOOT_STATUS_WARM){
-        dataL=recovery_from_backup_mode(); /*  WARM boot */
+    if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
+        dataL = recovery_from_backup_mode(); /*  WARM boot */
     } else {
-        dataL=init_ddr();                  /*  COLD boot */
+        dataL = init_ddr();                  /*  COLD boot */
     } /*  ddrBackup */
 
-    if(dataL==1){
-        failcount =0;
+    if (dataL == 1) {
+        failcount = 0;
     } else {
-        failcount =1;
+        failcount = 1;
     } /*  dataL */
 
-    NOTICE("..%d\n",failcount); /*  rev.0.05 */
+    NOTICE("..%d\n", failcount); /*  rev.0.05 */
 
-    if(failcount==0){
-        return INITDRAM_OK;
+    if (failcount == 0) {
+	return INITDRAM_OK;
     } else {
-        return INITDRAM_NG;
+	return INITDRAM_NG;
     } /*  failcount */
 } /*  InitDram */
 
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
index 47fe07b..2e9a5bf 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
@@ -9,7 +9,7 @@
 
 #include <stdint.h>
 
-#define RCAR_E3_DDR_VERSION    "rev.0.09"
+#define RCAR_E3_DDR_VERSION    "rev.0.11"
 
 #ifdef ddr_qos_init_setting
    #define REFRESH_RATE  3900               /*  Average periodic refresh interval[ns]. Support 3900,7800 */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
index 841eeb4..78f0f11 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -87,21 +87,11 @@
 static uint32_t ddr_mbpsdiv;
 static uint32_t ddr_tccd;
 static struct _boardcnf *Boardcnf;
-uint32_t ddr_phyvalid;
-uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
+static uint32_t ddr_phyvalid;
+static uint32_t ddr_phycaslice;
+static volatile uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
 static uint32_t ch_have_this_cs[CS_CNT];
 static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
-static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
-static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
-static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
-static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2];
-
-static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
-static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
-static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
-static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
 static uint32_t max_density;
 static uint32_t ddr0800_mul;
 static uint32_t ddr_mul;
@@ -260,9 +250,6 @@
 static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
 static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p);
-/* NOT USED
-static uint32_t ddr_getval_ach_s(uint32_t slice, uint32_t regdef, uint32_t *p);
-*/
 static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p);
 static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size);
 static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val);
@@ -284,7 +271,7 @@
 static uint32_t dfi_init_start(void);
 static void change_lpddr4_en(uint32_t mode);
 static uint32_t set_term_code(void);
-static void ddr_register_set(uint32_t ch);
+static void ddr_register_set(void);
 static inline uint32_t wait_freqchgreq(uint32_t assert);
 static inline void set_freqchgack(uint32_t assert);
 static inline void set_dfifrequency(uint32_t freq);
@@ -293,12 +280,8 @@
 static uint32_t pi_training_go(void);
 static uint32_t init_ddr(void);
 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick);
-static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
 static uint32_t wdqdm_man1(void);
 static uint32_t wdqdm_man(void);
-static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
 static uint32_t rdqdm_man1(void);
 static uint32_t rdqdm_man(void);
 
@@ -325,6 +308,24 @@
  ******************************************************************************/
 #include "boot_init_dram_config.c"
 
+#ifndef DDR_FAST_INIT
+static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2];
+static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
+
+static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
+static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
+static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
+static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
+#endif/* DDR_FAST_INIT */
+
 /*******************************************************************************
  *	macro for channel selection loop
  ******************************************************************************/
@@ -363,95 +364,121 @@
 {
 	uint32_t dataL, dataDIV, dataMUL, tmpDIV;
 
-	/* PLL3 disable */
-	dataL = mmio_read_32(CPG_PLLECR);
-	dataL &= ~CPG_PLLECR_PLL3E_BIT;
-	cpg_write_32(CPG_PLLECR, dataL);
-	dsb_sev();
-	cpg_write_32(CPG_FRQCRD, 0x00030003);	/* PLL3 DIV resetting */
-	dsb_sev();
-
-	/* PLL3 enable */
-	dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
-	cpg_write_32(CPG_ZB3CKCR, dataL);	/* zb3 clk stop */
-	dsb_sev();
-
-	/* PLL3 Restart */
-	dataL = mmio_read_32(CPG_PLLECR);
-	dataL |= CPG_PLLECR_PLL3E_BIT;
-	cpg_write_32(CPG_PLLECR, dataL);
-	dsb_sev();
-
-	do {
-		dataL = mmio_read_32(CPG_PLLECR);
-	} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
-	dsb_sev();
-
 	if (high) {
-		/* High frequency */
 		tmpDIV =
 		    (1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
 		    (ddr_mul * brd_clk * ddr_mbpsdiv + 1);
 		dataMUL =
-		    ((ddr_mul * (tmpDIV + 1) - 1) << 24) | (brd_clkdiva << 7);
-		if (tmpDIV) {
-			dataDIV = tmpDIV + 1;
-		} else {
-			dataDIV = 0;
-		}
+		    (ddr_mul * (tmpDIV + 1) - 1) << 24;
 		Pll3Mode = 1;
 		loop_max = 2;
 	} else {
-		/* Low frequency */
 		tmpDIV =
 		    (1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
 		    (ddr0800_mul * brd_clk * ddr_mbpsdiv + 1);
 		dataMUL =
-		    ((ddr0800_mul * (tmpDIV + 1) -
-		      1) << 24) | (brd_clkdiva << 7);
-		if (tmpDIV) {
-			dataDIV = tmpDIV + 1;
-		} else {
-			dataDIV = 0;
-		}
+		    (ddr0800_mul * (tmpDIV + 1) - 1) << 24;
 		Pll3Mode = 0;
 		loop_max = 8;
 	}
+	if (tmpDIV) {
+		dataDIV = tmpDIV + 1;
+	} else {
+		dataDIV = 0;
+	}
+	dataMUL = dataMUL | (brd_clkdiva << 7);
 
-	dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-	cpg_write_32(CPG_FRQCRD, dataL);	/* PLL3 DIV resetting */
+	/* PLL3 disable */
+	dataL = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
+	cpg_write_32(CPG_PLLECR, dataL);
 	dsb_sev();
 
-	dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-	cpg_write_32(CPG_FRQCRB, dataL);	/* DIV SET KICK */
-	dsb_sev();
+	if ((Prr_Product == PRR_PRODUCT_M3) ||
+	    ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+		/* PLL3 DIV resetting(Lowest value:3) */
+		dataL = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+		cpg_write_32(CPG_FRQCRD, dataL);
+		dsb_sev();
 
-	/* PLL3 FREQ */
-	cpg_write_32(CPG_PLL3CR, dataMUL);	/* Set PLL3 freq */
-	dsb_sev();
+		/* zb3 clk stop */
+		dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
+		cpg_write_32(CPG_ZB3CKCR, dataL);
+		dsb_sev();
 
-	do {
-		dataL = mmio_read_32(CPG_PLLECR);
-	} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
-	dsb_sev();
+		/* PLL3 enable */
+		dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+		cpg_write_32(CPG_PLLECR, dataL);
+		dsb_sev();
 
-	dataL =
-	    (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-	cpg_write_32(CPG_FRQCRD, dataL);	/* PLL3 DIV resetting */
-	dsb_sev();
+		do {
+			dataL = mmio_read_32(CPG_PLLECR);
+		} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+		dsb_sev();
 
-	dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-	cpg_write_32(CPG_FRQCRB, dataL);	/* DIV SET KICK */
-	dsb_sev();
+		/* PLL3 DIV resetting (Highest value:0) */
+		dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+		cpg_write_32(CPG_FRQCRD, dataL);
+		dsb_sev();
 
-	do {
-		dataL = mmio_read_32(CPG_PLLECR);
-	} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
-	dsb_sev();
+		/* DIV SET KICK */
+		dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+		cpg_write_32(CPG_FRQCRB, dataL);
+		dsb_sev();
 
-	dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
-	cpg_write_32(CPG_ZB3CKCR, dataL);	/* zb3 clk start */
-	dsb_sev();
+		/* PLL3 multiplie set */
+		cpg_write_32(CPG_PLL3CR, dataMUL);
+		dsb_sev();
+
+		do {
+			dataL = mmio_read_32(CPG_PLLECR);
+		} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+		dsb_sev();
+
+		/* PLL3 DIV resetting(Target value) */
+		dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+		cpg_write_32(CPG_FRQCRD, dataL);
+		dsb_sev();
+
+		/* DIV SET KICK */
+		dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+		cpg_write_32(CPG_FRQCRB, dataL);
+		dsb_sev();
+
+		do {
+			dataL = mmio_read_32(CPG_PLLECR);
+		} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+		dsb_sev();
+
+		/* zb3 clk start */
+		dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
+		cpg_write_32(CPG_ZB3CKCR, dataL);
+		dsb_sev();
+
+	} else { /*  H3Ver.3.0/M3N/V3H */
+
+		/* PLL3 multiplie set */
+		cpg_write_32(CPG_PLL3CR, dataMUL);
+		dsb_sev();
+
+		/* PLL3 DIV set(Target value) */
+		dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+		cpg_write_32(CPG_FRQCRD, dataL);
+
+		/* DIV SET KICK */
+		dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+		cpg_write_32(CPG_FRQCRB, dataL);
+		dsb_sev();
+
+		/* PLL3 enable */
+		dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+		cpg_write_32(CPG_PLLECR, dataL);
+		dsb_sev();
+
+		do {
+			dataL = mmio_read_32(CPG_PLLECR);
+		} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+		dsb_sev();
+	}
 
 	return;
 }
@@ -647,11 +674,6 @@
 	return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]);
 }
 
-static inline uint32_t ddr_regdef_len(uint32_t _regdef)
-{
-	return DDR_REGDEF_LEN(pDDR_REGDEF_TBL[_regdef]);
-}
-
 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
 			 uint32_t val)
 {
@@ -740,17 +762,6 @@
 	return p[0];
 }
 
-/* NOT_USED
-static uint32_t ddr_getval_ach_s(uint32_t slice, uint32_t regdef, uint32_t *p)
-{
-	uint32_t ch;
-
-	foreach_vch(ch)
-		p[ch] = ddr_getval_s(ch, slice, regdef);
-	return p[0];
-}
-*/
-
 static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p)
 {
 	uint32_t ch, slice;
@@ -925,9 +936,8 @@
 
 #define JS2_tRCpb (JS2_TBLCNT)
 #define JS2_tRCab (JS2_TBLCNT+1)
-#define JS2_tRFCpb (JS2_TBLCNT+2)
-#define JS2_tRFCab (JS2_TBLCNT+3)
-#define JS2_CNT (JS2_TBLCNT+4)
+#define JS2_tRFCab (JS2_TBLCNT+2)
+#define JS2_CNT (JS2_TBLCNT+3)
 
 #ifndef JS2_DERATE
 #define JS2_DERATE 0
@@ -982,13 +992,9 @@
 	     }
 };
 
-/* pb, ab */
-const uint16_t jedec_spec2_tRFC_pb_ab[2][7] = {
+const uint16_t jedec_spec2_tRFC_ab[7] = {
 /*	4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non)	*/
-	{
-	 60, 90, 90, 140, 140, 280, 280},
-	{
-	 130, 180, 180, 280, 280, 560, 560}
+	 130, 180, 180, 280, 280, 560, 560
 };
 
 static uint32_t js1_ind;
@@ -1409,46 +1415,26 @@
 	}
 
 	/***********************************************************************
-	Adjust PI paramters
+	Adjust PI parameters
 	***********************************************************************/
 #ifdef _def_LPDDR4_ODT
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_0,
-		      _def_LPDDR4_ODT);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_1,
-		      _def_LPDDR4_ODT);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_2,
-		      _def_LPDDR4_ODT);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_3,
-		      _def_LPDDR4_ODT);
-
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_0,
-		      _def_LPDDR4_ODT);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_1,
-		      _def_LPDDR4_ODT);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_2,
-		      _def_LPDDR4_ODT);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_3,
-		      _def_LPDDR4_ODT);
+	for (i = 0; i < 2; i++) {
+		for (csab = 0; csab < CSAB_CNT; csab++) {
+			ddrtbl_setval(_cnf_DDR_PI_REGSET,
+				      _reg_PI_MR11_DATA_Fx_CSx[i][csab],
+				      _def_LPDDR4_ODT);
+		}
+	}
 #endif /* _def_LPDDR4_ODT */
 
 #ifdef _def_LPDDR4_VREFCA
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_0,
-		      _def_LPDDR4_VREFCA);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_1,
-		      _def_LPDDR4_VREFCA);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_2,
-		      _def_LPDDR4_VREFCA);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_3,
-		      _def_LPDDR4_VREFCA);
-
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_0,
-		      _def_LPDDR4_VREFCA);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_1,
-		      _def_LPDDR4_VREFCA);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_2,
-		      _def_LPDDR4_VREFCA);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_3,
-		      _def_LPDDR4_VREFCA);
+	for (i = 0; i < 2; i++) {
+		for (csab = 0; csab < CSAB_CNT; csab++) {
+			ddrtbl_setval(_cnf_DDR_PI_REGSET,
+				      _reg_PI_MR12_DATA_Fx_CSx[i][csab],
+				      _def_LPDDR4_VREFCA);
+		}
+	}
 #endif /* _def_LPDDR4_VREFCA */
 	if ((Prr_Product == PRR_PRODUCT_M3N)
 	    || (Prr_Product == PRR_PRODUCT_V3H)) {
@@ -1563,6 +1549,32 @@
 		reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
 	}
 
+	if (((Prr_Product == PRR_PRODUCT_M3)
+	    || (Prr_Product == PRR_PRODUCT_M3N)) &&
+	    ((0x00ffffff & (uint32_t)((Boardcnf->ch[0].ca_swap) >> 40))
+	    != 0x00)) {
+		adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
+		for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
+			reg_ddrphy_write_a(adr + i,
+					   _cnf_DDR_PHY_ADR_V_REGSET[i]);
+		}
+		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_ADR_DISABLE, 0x02);
+		DDR_PHY_ADR_I_NUM -= 1;
+		ddr_phycaslice = 1;
+
+#ifndef _def_LPDDR4_ODT
+		for (i = 0; i < 2; i++) {
+			for (csab = 0; csab < CSAB_CNT; csab++) {
+				ddrtbl_setval(_cnf_DDR_PI_REGSET,
+					      _reg_PI_MR11_DATA_Fx_CSx[i][csab],
+					      0x66);
+			}
+		}
+#endif/* _def_LPDDR4_ODT */
+	} else {
+		ddr_phycaslice = 0;
+	}
+
 	if (DDR_PHY_ADR_I_NUM > 0) {
 		for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) {
 			adr =
@@ -1631,7 +1643,9 @@
 		BOARD SETTINGS (CA,ADDR_SEL)
 	***********************************************************************/
 		const uint32_t _par_CALVL_DEVICE_MAP = 1;
-		dataL = Boardcnf->ch[ch].ca_swap | 0x00888888;
+
+		dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) |
+			0x00888888;
 
 		/* --- ADR_CALVL_SWIZZLE --- */
 		if (Prr_Product == PRR_PRODUCT_M3) {
@@ -1663,6 +1677,38 @@
 			}
 		}
 		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL);
+		if (ddr_phycaslice == 1) {
+			/* ----------- adr slice2 swap ----------- */
+			tmp  = (uint32_t)((Boardcnf->ch[ch].ca_swap) >> 40);
+			dataL = (tmp & 0x00ffffff) | 0x00888888;
+
+			/* --- ADR_CALVL_SWIZZLE --- */
+			if (Prr_Product == PRR_PRODUCT_M3) {
+				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
+				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
+					     0x00000000);
+				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
+				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
+					     0x00000000);
+				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP,
+					     _par_CALVL_DEVICE_MAP);
+			} else {
+				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
+				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1,
+					     0x00000000);
+				ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP,
+					     _par_CALVL_DEVICE_MAP);
+			}
+
+			/* --- ADR_ADDR_SEL --- */
+			dataL = 0;
+			for (i = 0; i < 6; i++) {
+				dataL |= ((tmp & 0x0f) << (i * 5));
+				tmp = tmp >> 4;
+			}
+
+			ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, dataL);
+		}
 
 	/***********************************************************************
 		BOARD SETTINGS (BYTE_ORDER_SEL)
@@ -1710,7 +1756,7 @@
 		if (tgt == tmp)
 			break;
 	}
-	tmp = Boardcnf->ch[ch].ca_swap;
+	tmp = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
 	if (slice % 2)
 		tmp |= 0x00888888;
 	*p_swz = tmp;
@@ -1755,7 +1801,7 @@
 	/***********************************************************************
 		BOARD SETTINGS (CA,ADDR_SEL)
 	***********************************************************************/
-		ca = Boardcnf->ch[ch].ca_swap;
+		ca = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
 		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
 		ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap);
 
@@ -1864,6 +1910,16 @@
 			ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
 				   dataL + adj);
 		}
+		if (ddr_phycaslice == 1) {
+			for (i = 0; i < 6; i++) {
+				adj =
+				    _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i +
+				    _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+					     dataL + adj);
+			}
+		}
 	}
 	set_dfifrequency(0x00);
 
@@ -1974,20 +2030,13 @@
 	/* RFC */
 	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20)
 	    && (max_density == 0)) {
-		js2[JS2_tRFCpb] =
-		    _f_scale(ddr_mbps, ddr_mbpsdiv,
-			     1UL * jedec_spec2_tRFC_pb_ab[0][1] * 1000, 0);
 		js2[JS2_tRFCab] =
 		    _f_scale(ddr_mbps, ddr_mbpsdiv,
-			     1UL * jedec_spec2_tRFC_pb_ab[1][1] * 1000, 0);
+			     1UL * jedec_spec2_tRFC_ab[1] * 1000, 0);
 	} else {
-		js2[JS2_tRFCpb] = _f_scale(ddr_mbps, ddr_mbpsdiv,
-					   1UL *
-					   jedec_spec2_tRFC_pb_ab[0]
-					   [max_density] * 1000, 0);
 		js2[JS2_tRFCab] =
 		    _f_scale(ddr_mbps, ddr_mbpsdiv,
-			     1UL * jedec_spec2_tRFC_pb_ab[1][max_density] *
+			     1UL * jedec_spec2_tRFC_ab[max_density] *
 			     1000, 0);
 	}
 
@@ -2032,7 +2081,7 @@
 	dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR];
 	mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL);
 
-	/* DBTR13.TRFCPB,TRFCAB : tRFCpb, tRFCab */
+	/* DBTR13.TRFCAB : tRFCab */
 	mmio_write_32(DBSC_DBTR(13), (js2[JS2_tRFCab]));
 
 	/* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
@@ -2061,7 +2110,11 @@
 	/* WRCSGAP = 5 */
 	tmp[1] = 5;
 	/* RDCSLAT = RDLAT_ADJ +2 */
-	tmp[2] = tmp[3] + 2;
+	if (Prr_Product == PRR_PRODUCT_M3) {
+		tmp[2] = tmp[3];
+	} else {
+		tmp[2] = tmp[3] + 2;
+	}
 	/* RDCSGAP = 6 */
 	if (Prr_Product == PRR_PRODUCT_M3) {
 		tmp[3] = 4;
@@ -2428,20 +2481,7 @@
 	uint32_t dataL;
 	const uint32_t RETRY_MAX = 0x10000;
 
-	/***********************************************************************
-	set IE=1 when init_start_disable==0
-	***********************************************************************/
-	if (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CAL_MODE_0) &
-	    0x01) {
-		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00);
-	} else {
-		ddr_setval_ach_as(_reg_PHY_IE_MODE,
-				  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						_reg_PHY_IE_MODE));
-	}
-
 	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
-
 	/***********************************************************************
 		PLL3 Disable
 	***********************************************************************/
@@ -2535,8 +2575,8 @@
 		_reg_PHY_PAD_CS_DRIVE
 	};
 
-	for (i = 0; i < 3; i++) {
-		foreach_vch(ch) {
+	foreach_vch(ch) {
+		for (i = 0; i < 3; i++) {
 			dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
 			if (mode) {
 				dataL |= (1U << 14);
@@ -2591,9 +2631,6 @@
 		   && (Prr_Cut == PRR_PRODUCT_10)) {
 		/*  non */
 	} else {
-		ddr_setval_ach_as(_reg_PHY_IE_MODE,
-				  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						_reg_PHY_IE_MODE));
 		ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
 			       (ddrtbl_getval
 				(_cnf_DDR_PHY_ADR_G_REGSET,
@@ -2664,48 +2701,46 @@
 /*******************************************************************************
  *	DDR mode register setting
  ******************************************************************************/
-static void ddr_register_set(uint32_t ch)
+static void ddr_register_set(void)
 {
 	int32_t fspwp;
-	uint32_t chind;
 	uint32_t tmp;
 
-	chind = ch << 20;
 	for (fspwp = 1; fspwp >= 0; fspwp--) {
 		/*MR13,fspwp */
-		send_dbcmd(0x0e040d08 | chind | (fspwp << 6));
+		send_dbcmd(0x0e840d08 | (fspwp << 6));
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
 				  _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]);
-		send_dbcmd(0x0e040100 | chind | tmp);
+		send_dbcmd(0x0e840100 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
 				  _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]);
-		send_dbcmd(0x0e040200 | chind | tmp);
+		send_dbcmd(0x0e840200 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
 				  _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]);
-		send_dbcmd(0x0e040300 | chind | tmp);
+		send_dbcmd(0x0e840300 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
 				  _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]);
-		send_dbcmd(0x0e040b00 | chind | tmp);
+		send_dbcmd(0x0e840b00 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
 				  _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]);
-		send_dbcmd(0x0e040c00 | chind | tmp);
+		send_dbcmd(0x0e840c00 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
 				  _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]);
-		send_dbcmd(0x0e040e00 | chind | tmp);
+		send_dbcmd(0x0e840e00 | tmp);
 		/* MR22 */
-		send_dbcmd(0x0e041600 | chind | 0x16);
+		send_dbcmd(0x0e841616);
 	}
 }
 
@@ -2904,7 +2939,7 @@
 	int32_t i;
 	uint32_t dataL;
 	uint32_t phytrainingok;
-	uint32_t ch;
+	uint32_t ch, slice;
 	uint32_t err;
 
 	MSG_LF("init_ddr:0\n");
@@ -3011,12 +3046,8 @@
 		return (INITDRAM_ERR_O);
 	MSG_LF("init_ddr:5\n");
 
-	/***********************************************************************
-	set ie_mode=1
-	***********************************************************************/
-	ddr_setval_ach_as(_reg_PHY_IE_MODE,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_IE_MODE));
+	/* PDX */
+	send_dbcmd(0x08840001);
 
 	/***********************************************************************
 	check register i/f is alive
@@ -3037,38 +3068,22 @@
 	/* CMOS MODE */
 	change_lpddr4_en(0);
 
-	ch = 0x08;
-
-	/* PDE */
-	send_dbcmd(0x08040000 | (0x00100000 * ch));
-
-	/* PDX */
-	send_dbcmd(0x08040001 | (0x00100000 * ch));
-
-	/* MR22 (ODTCS & RQZ */
-	send_dbcmd(0x0e041600 | (0x00100000 * ch) | 0x16);
+	/* MRS */
+	ddr_register_set();
 
 	/* ZQCAL start */
-	send_dbcmd(0x0d04004F | (0x00100000 * ch));
-	rcar_micro_delay(100);
+	send_dbcmd(0x0d84004F);
 
 	/* ZQLAT */
-	send_dbcmd(0x0d040051 | (0x00100000 * ch));
+	send_dbcmd(0x0d840051);
 
 	/***********************************************************************
 	Thermal sensor setting
 	***********************************************************************/
-	/* THCTR Bit6: PONM=0 , Bit0: THSST=1   */
-	dataL =
-	    ((*((volatile uint32_t *)THS1_THCTR)) & 0xFFFFFFBF) | 0x00000001;
-	*((volatile uint32_t *)THS1_THCTR) = dataL;
+	/* THCTR Bit6: PONM=0 , Bit0: THSST=1  */
+	dataL = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
+	mmio_write_32(THS1_THCTR, dataL);
 
-	/***********************************************************************
-	setup DDR mode registers
-	***********************************************************************/
-	foreach_vch(ch) {
-		ddr_register_set(ch);
-	}
 	/* LPDDR4 MODE */
 	change_lpddr4_en(1);
 
@@ -3079,8 +3094,6 @@
 	***********************************************************************/
 	foreach_vch(ch) {
 		dataL = ddr_getval(ch, _reg_PI_CS_MAP);
-		if (!(ch_have_this_cs[0] & (1U << ch)))
-			dataL = dataL & 0x0a;
 		if (!(ch_have_this_cs[1] & (1U << ch)))
 			dataL = dataL & 0x05;
 		ddr_setval(ch, _reg_PI_CS_MAP, dataL);
@@ -3090,7 +3103,19 @@
 	exec pi_training
 	***********************************************************************/
 	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
+
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
 	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
+	} else {
+		foreach_vch(ch) {
+			for (slice = 0; slice < SLICE_CNT; slice++) {
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_PER_CS_TRAINING_EN,
+					     ((ch_have_this_cs[1]) >> ch)
+					     & 0x01);
+			}
+		}
+	}
 
 	phytrainingok = pi_training_go();
 
@@ -3111,7 +3136,17 @@
 			ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
 				   dataL + adj);
 		}
+
+		if (ddr_phycaslice == 1) {
+			for (i = 0; i < 6; i++) {
+				adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+				ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+					     dataL + adj
+				);
+			}
+		}
 	}
+
 	update_dly();
 	MSG_LF("init_ddr:9\n");
 
@@ -3132,15 +3167,16 @@
 	/***********************************************************************
 	RDQLVL Training
 	***********************************************************************/
-	if ((Prr_Product == PRR_PRODUCT_H3) || (Prr_Product == PRR_PRODUCT_M3)) {
+	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) {
 		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
-	} else {
-		ddr_setval_ach_as(_reg_PHY_IE_MODE,
-				  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						_reg_PHY_IE_MODE));
 	}
 
 	err = rdqdm_man();
+
+	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) {
+		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00);
+	}
+
 	if (err) {
 		return (INITDRAM_ERR_T);
 	}
@@ -3229,6 +3265,7 @@
 /*******************************************************************************
  *	WDQ TRAINING
  ******************************************************************************/
+#ifndef DDR_FAST_INIT
 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
 {
 	int32_t i, k;
@@ -3284,7 +3321,6 @@
 
 		cs = ddr_csn % 2;
 		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
-		ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
 		for (i = 0; i < 9; i++) {
 			dq = slice * 8 + i;
 			if (i == 8)
@@ -3325,10 +3361,16 @@
 				err = 2;
 		}
 		wdqdm_win[ch][cs][slice] = min_win;
+		if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
 		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01);
+		} else {
+			ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
+				     ((ch_have_this_cs[1]) >> ch) & 0x01);
+		}
 	}
 	return err;
 }
+#endif/* DDR_FAST_INIT */
 
 static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
 {
@@ -3375,26 +3417,26 @@
 	uint32_t ddr_csn;
 	uint32_t dataL;
 	uint32_t err;
+	uint32_t high_dq[DRAM_CH_CNT];
+	uint32_t mr14_csab0_bak[DRAM_CH_CNT];
+#ifndef DDR_FAST_INIT
 	uint32_t err_flg;
+#endif/* DDR_FAST_INIT */
 
 	/***********************************************************************
 	manual execution of training
 	***********************************************************************/
-	uint32_t high_dq[DRAM_CH_CNT];
-	uint32_t mr14_csab0_bak[DRAM_CH_CNT];
-
-	foreach_vch(ch) {
-		high_dq[ch] = 0;
-		for (slice = 0; slice < SLICE_CNT; slice++) {
-			k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
-			if (k >= 2)
-				high_dq[ch] |= (1U << slice);
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		foreach_vch(ch) {
+			high_dq[ch] = 0;
+			for (slice = 0; slice < SLICE_CNT; slice++) {
+				k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+				if (k >= 2)
+					high_dq[ch] |= (1U << slice);
+			}
+			ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00);
 		}
 	}
-
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-		ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x00);
-
 	err = 0;
 	/* CLEAR PREV RESULT */
 	for (cs = 0; cs < CS_CNT; cs++) {
@@ -3412,8 +3454,9 @@
 	}
 	ddrphy_regif_idle();
 
+#ifndef DDR_FAST_INIT
 	err_flg = 0;
-
+#endif/* DDR_FAST_INIT */
 	for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
 		if ((Prr_Product == PRR_PRODUCT_H3)
 		    && (Prr_Cut <= PRR_PRODUCT_11)) {
@@ -3458,6 +3501,7 @@
 			ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0],
 				   mr14_csab0_bak[ch]);
 			}
+#ifndef DDR_FAST_INIT
 		foreach_vch(ch) {
 			if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
 				wdqdm_clr1(ch, ddr_csn);
@@ -3468,16 +3512,22 @@
 				err_flg |= (1U << (ddr_csn * 4 + ch));
 			ddrphy_regif_idle();
 		}
+#endif/* DDR_FAST_INIT */
 	}
 err_exit:
-	ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01);
-	foreach_vch(ch) {
-		dataL = mmio_read_32(DBSC_DBDFICNT(ch));
-		dataL &= ~(0x00ffU << 16);
-		mmio_write_32(DBSC_DBDFICNT(ch), dataL);
-		ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
+#ifndef DDR_FAST_INIT
+	err |= err_flg;
+#endif/* DDR_FAST_INIT */
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01);
+		foreach_vch(ch) {
+			dataL = mmio_read_32(DBSC_DBDFICNT(ch));
+			dataL &= ~(0x00ffU << 16);
+			mmio_write_32(DBSC_DBDFICNT(ch), dataL);
+			ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
+		}
 	}
-	return (err_flg | err);
+	return (err);
 }
 
 static uint32_t wdqdm_man(void)
@@ -3591,6 +3641,7 @@
 /*******************************************************************************
  *	RDQ TRAINING
  ******************************************************************************/
+#ifndef DDR_FAST_INIT
 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
 {
 	int32_t i, k;
@@ -3740,11 +3791,15 @@
 	}
 	return (err);
 }
+#endif/* DDR_FAST_INIT */
 
 static uint32_t rdqdm_man1(void)
 {
 	uint32_t ch;
 	uint32_t ddr_csn;
+#ifdef DDR_FAST_INIT
+	uint32_t slice;
+#endif/* DDR_FAST_INIT */
 	uint32_t err;
 
 	/***********************************************************************
@@ -3752,12 +3807,12 @@
 	***********************************************************************/
 	err = 0;
 
-	for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
+	for (ddr_csn = 0; ddr_csn < CS_CNT; ddr_csn++) {
 		/* KICK RDQLVL */
 		err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
 		if (err)
 			goto err_exit;
-
+#ifndef DDR_FAST_INIT
 		foreach_vch(ch) {
 			if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
 				rdqdm_clr1(ch, ddr_csn);
@@ -3769,7 +3824,50 @@
 			if (err)
 				goto err_exit;
 		}
+#else/* DDR_FAST_INIT */
+		foreach_vch(ch) {
+			if (ch_have_this_cs[ddr_csn] & (1U << ch)) {
+				for (slice = 0; slice < SLICE_CNT; slice++) {
+					if (ddr_getval_s(ch, slice,
+					    _reg_PHY_RDLVL_STATUS_OBS) !=
+					    0x0D00FFFF) {
+						err = (1U << ch) |
+							(0x10U << slice);
+						goto err_exit;
+					}
+				}
+			}
+			if (((Prr_Product == PRR_PRODUCT_H3)
+			    && (Prr_Cut <= PRR_PRODUCT_11))
+			    || ((Prr_Product == PRR_PRODUCT_M3)
+			    && (Prr_Cut <= PRR_PRODUCT_10))) {
+				uint32_t i, adj, dataL;
+
+				for (slice = 0; slice < SLICE_CNT; slice++) {
+					for (i = 0; i <= 8; i++) {
+						if (i == 8)
+							adj = _f_scale_adj(Boardcnf->ch[ch].dm_adj_r[slice]);
+						else
+							adj = _f_scale_adj(Boardcnf->ch[ch].dq_adj_r[slice * 8 + i]);
+						ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
+						dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
+						ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL);
+						rdqdm_dly[ch][ddr_csn][slice][i] = dataL;
+						rdqdm_dly[ch][ddr_csn | 1][slice][i] = dataL;
+
+						dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
+						ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL);
+						rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = dataL;
+						rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = dataL;
+					}
+				}
+			}
+		}
+		ddrphy_regif_idle();
+
+#endif/* DDR_FAST_INIT */
 	}
+
 err_exit:
 	return (err);
 }
@@ -3867,7 +3965,6 @@
 	return tmp;
 }
 
-/* #define RX_OFFSET_FAST */
 static uint32_t rx_offset_cal(void)
 {
 	uint32_t index;
@@ -3878,11 +3975,7 @@
 	uint32_t tmp;
 	uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
 	uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
-#ifdef RX_OFFSET_FAST
-	uint32_t adr_st;
-	adr_st = ddr_regdef_adr(_reg_PHY_RX_CAL_X[0]);
-#endif
-	ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
+
 	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
 	foreach_vch(ch) {
 		for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -3894,19 +3987,9 @@
 
 	for (code = 0; code < CODE_MAX / CODE_STEP; code++) {
 		tmp = _rx_offset_cal_updn(code * CODE_STEP);
-#ifdef RX_OFFSET_FAST
-		tmp = tmp | (tmp << 16);
-		for (index = 0; index < (_reg_PHY_RX_CAL_X_NUM + 1) / 2;
-		     index++) {
-			for (slice = 0; slice < 4; slice++)
-				reg_ddrphy_write_a(adr_st + 0x80 * slice +
-						   index, tmp);
-		}
-#else
 		for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
 			ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
 		}
-#endif
 		dsb_sev();
 		ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as);
 
@@ -3945,9 +4028,6 @@
 		}
 	}
 	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
-	ddr_setval_ach_as(_reg_PHY_IE_MODE,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_IE_MODE));
 
 	return 0;
 }
@@ -3960,7 +4040,6 @@
 	uint32_t tmp;
 	uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
 
-	ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
 	ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00);
 	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
 	ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f);
@@ -3997,9 +4076,6 @@
 
 		retry++;
 	}
-	ddr_setval_ach_as(_reg_PHY_IE_MODE,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_IE_MODE));
 
 	return (complete == 0);
 }
@@ -4095,17 +4171,16 @@
 	/***********************************************************************
 	Thermal sensor setting
 	***********************************************************************/
-	dataL = *((volatile uint32_t *)CPG_MSTPSR5);
+	dataL = mmio_read_32(CPG_MSTPSR5);
 	if (dataL & BIT22) {	/*  case THS/TSC Standby */
 		dataL &= ~(BIT22);
-		*((volatile uint32_t *)CPG_CPGWPR) = ~dataL;
-		*((volatile uint32_t *)CPG_SMSTPCR5) = dataL;
-		while ((BIT22) & *((volatile uint32_t *)CPG_MSTPSR5)) ;	/*  wait bit=0 */
+		cpg_write_32(CPG_SMSTPCR5, dataL);
+		while ((BIT22) & mmio_read_32(CPG_MSTPSR5));  /*  wait bit=0 */
 	}
 
 	/* THCTR Bit6: PONM=0 , Bit0: THSST=0   */
-	dataL = (*((volatile uint32_t *)THS1_THCTR)) & 0xFFFFFFBE;
-	*((volatile uint32_t *)THS1_THCTR) = dataL;
+	dataL = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
+	mmio_write_32(THS1_THCTR, dataL);
 
 	/***********************************************************************
 	Judge product and cut
@@ -4136,7 +4211,7 @@
 		   || (Prr_Product == PRR_PRODUCT_V3H)) {
 		pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[3][0];
 	} else {
-		FATAL_MSG("DDR:Unknown Product");
+		FATAL_MSG("BL2: DDR:Unknown Product\n");
 		return 0xff;
 	}
 
@@ -4152,7 +4227,7 @@
 	***********************************************************************/
 	_cnf_BOARDTYPE = boardcnf_get_brd_type();
 	if (_cnf_BOARDTYPE >= BOARDNUM) {
-		FATAL_MSG("DDR:Unknown Board");
+		FATAL_MSG("BL2: DDR:Unknown Board\n");
 		return 0xff;
 	}
 	Boardcnf = (struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
@@ -4254,7 +4329,7 @@
 	else
 		ddr_tccd = tmp_tccd;
 
-	NOTICE("BL2: DDR%d(%s)", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
+	NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
 
 	MSG_LF("Start\n");
 
@@ -4273,8 +4348,6 @@
 		failcount = 1;
 	}
 
-	NOTICE("..%d\n", failcount);
-
 	foreach_vch(ch)
 	    mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
 	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
@@ -4294,6 +4367,7 @@
 void pvtcode_update(void)
 {
 	uint32_t ch;
+	uint32_t dataL;
 	uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
 	int32_t pvtp_tmp, pvtn_tmp;
 
@@ -4321,58 +4395,39 @@
 		}
 		if ((Prr_Product == PRR_PRODUCT_H3)
 		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+			dataL = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
-								       tcomp_cal
-								       [ch] &
-								       0xfffff000));
+					 dataL | 0x00020000);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
-								       tcomp_cal
-								       [ch] &
-								       0xfffff000));
+					 dataL);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
-								       tcomp_cal
-								       [ch] &
-								       0xfffff000));
+					 dataL);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
-								       tcomp_cal
-								       [ch] &
-								       0xfffff000));
+					 dataL);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
-								       tcomp_cal
-								       [ch] &
-								       0xfffff000));
+					 dataL);
 		} else {
+			dataL = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) |
-					 0x00035000);
+					 dataL | 0x00020000);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) |
-					 0x00015000);
+					 dataL);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) |
-					 0x00015000);
-
+					 dataL);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) |
-					 0x00015000);
+					 dataL);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-					 pvtp[ch] | (pvtn[ch] << 6) |
-					 0x00015000);
+					 dataL);
 		}
 	}
 }
@@ -4412,7 +4467,7 @@
 	}
 
 	if (!override) {
-		dataL = *((volatile uint32_t *)THS1_TEMP);
+		dataL = mmio_read_32(THS1_TEMP);
 		if (dataL < 2800) {
 			tcal.init_temp =
 			    (143 * (int32_t) dataL - 359000) / 1000;
@@ -4459,7 +4514,6 @@
 /*  for QoS init */
 uint8_t get_boardcnf_phyvalid(void)
 {
-/*       return Boardcnf->phyvalid; */
 	return ddr_phyvalid;
 }
 #endif /* ddr_qos_init_setting */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
index 3d94da5..8040d93 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -4,24 +4,33 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define BOARDNUM 16
+#define BOARDNUM 18
 #define BOARD_JUDGE_AUTO
 
+#ifdef BOARD_JUDGE_AUTO
 static uint32_t _board_judge(void);
 
 static uint32_t boardcnf_get_brd_type(void)
 {
 	return _board_judge();
 }
+#else
+static uint32_t boardcnf_get_brd_type(void)
+{
+	return (1);
+}
+#endif
+
+#define DDR_FAST_INIT
 
 struct _boardcnf_ch {
 	uint8_t ddr_density[CS_CNT];
-	uint32_t ca_swap;
+	uint64_t ca_swap;
 	uint16_t dqs_swap;
 	uint32_t dq_swap[SLICE_CNT];
 	uint8_t dm_swap[SLICE_CNT];
 	uint16_t wdqlvl_patt[16];
-	int8_t cacs_adj[10];
+	int8_t cacs_adj[16];
 	int8_t dm_adj_w[SLICE_CNT];
 	int8_t dq_adj_w[SLICE_CNT * 8];
 	int8_t dm_adj_r[SLICE_CNT];
@@ -876,7 +885,11 @@
 	 0x0a0,
 	 {
 	  {
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
+	   {0x04, 0x04},
+#else
 	   {0x02, 0x02},
+#endif
 	   0x00342501,
 	   0x3201,
 	   {0x10672534, 0x43257106, 0x34527601, 0x71605243},
@@ -1227,7 +1240,89 @@
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   }
 	  }
+	 },
+/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
+	{
+	 0x03,
+	 0x01,
+	 0x0320,
+	 0,
+	 0x0300,
+	 0x00a0,
+	 {
+	  {
+	   {0x04, 0x04},
+	    0x520314FFFF523041,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x04, 0x04},
+	    0x314250FFFF312405,
+	    0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
+	{
+	 0x01,
+	 0x01,
+	 0x0300,
+	 0,
+	 0x0300,
+	 0x00a0,
+	 {
+	  {
+	   {0x04, 0x04},
+	    0x520314FFFF523041,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	  }
 	 }
+	}
 };
 
 void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
@@ -1258,6 +1353,7 @@
 			break;
 		}
 	}
+	(void)brd;
 }
 
 void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
@@ -1284,6 +1380,7 @@
 		*div = 1;
 		break;
 	}
+	(void)brd;
 }
 
 #define _def_REFPERIOD  1890
@@ -1393,10 +1490,10 @@
 	if (down == up) {
 		/* Same = Connect */
 		return 0;
+	} else {
+		/* Diff = Open */
+		return 1;
 	}
-
-	/* Diff = Open */
-	return 1;
 }
 
 #endif
@@ -1431,6 +1528,7 @@
 	usb2_ovc_open = opencheck_SSI_WS6();
 
 	/* RENESAS Eva-borad */
+	brd = 99;
 	if (Prr_Product == PRR_PRODUCT_V3H) {
 		/* RENESAS Condor board */
 		brd = 12;
@@ -1441,10 +1539,12 @@
 		} else if (Prr_Product == PRR_PRODUCT_M3) {
 			/* RENESAS Kriek board with M3-W */
 			brd = 1;
-		} else if (Prr_Cut <= PRR_PRODUCT_11) {
+		} else if ((Prr_Product == PRR_PRODUCT_H3)
+			   && (Prr_Cut<=PRR_PRODUCT_11)) {
 			/* RENESAS Kriek board with PM3 */
 			brd = 13;
-		} else {
+		} else if ((Prr_Product == PRR_PRODUCT_H3)
+			   && (Prr_Cut > PRR_PRODUCT_20)) {
 			/* RENESAS Kriek board with H3N */
 			brd = 15;
 		}
@@ -1467,12 +1567,13 @@
 		} else if (Prr_Product == PRR_PRODUCT_M3N) {
 			/* RENESAS SALVATOR-X (M3-N/SIP) */
 			brd = 11;
-		} else {
+		} else if (Prr_Product == PRR_PRODUCT_M3) {
 			/* RENESAS SALVATOR-X (M3-W/SIP) */
 			brd = 0;
 		}
 	}
 #endif
+
 	return brd;
 }
 #endif
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
index 91562b0..d72959b 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define RCAR_DDR_VERSION        "rev.0.33"
+#define RCAR_DDR_VERSION        "rev.0.34"
 #define DRAM_CH_CNT		(0x04)
 #define SLICE_CNT		(0x04)
 #define CS_CNT			(0x02)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
index f8ff0fd..a9569ee 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
@@ -267,7 +267,7 @@
 /*0bb9*/ 0x00000000,
 /*0bba*/ 0x00000000,
 /*0bbb*/ 0x00000000,
-/*0bbc*/ 0x00000065,
+/*0bbc*/ 0x00000265,
 /*0bbd*/ 0x00000000,
 /*0bbe*/ 0x00040401,
 /*0bbf*/ 0x00000000,
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
index 82aa7f8..6739b0d 100644
--- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
+++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
@@ -19,10 +19,11 @@
 #define PRR_PRODUCT_V3H			(0x00005600U)	/* R-Car V3H */
 
 #if RCAR_SYSTEM_SUSPEND
-#include "iic_dvfs.h"
-
+/* Local defines */
 #define DRAM_BACKUP_GPIO_USE		(0)
+#include "iic_dvfs.h"
 #if PMIC_ROHM_BD9571
+#define	PMIC_SLAVE_ADDR			(0x30U)
 #define	PMIC_BKUP_MODE_CNT		(0x20U)
 #define	PMIC_QLLM_CNT			(0x27U)
 #define	BIT_BKUP_CTRL_OUT		((uint8_t)(1U << 4U))
@@ -52,40 +53,53 @@
 void rcar_dram_get_boot_status(uint32_t * status)
 {
 #if RCAR_SYSTEM_SUSPEND
-	uint32_t shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
-	uint32_t gpio = GPIO_INDT1;
-	uint32_t reg, product;
 
-	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+	uint32_t reg_data;
+	uint32_t product;
+	uint32_t shift;
+	uint32_t gpio;
 
+	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
 	if (product == PRR_PRODUCT_V3H) {
 		shift = GPIO_BKUP_TRG_SHIFT_CONDOR;
 		gpio = GPIO_INDT3;
 	} else if (product == PRR_PRODUCT_E3) {
 		shift = GPIO_BKUP_TRG_SHIFT_EBISU;
 		gpio = GPIO_INDT6;
+	} else {
+		shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
+		gpio = GPIO_INDT1;
 	}
 
-	reg = mmio_read_32(gpio) & (1U << shift);
-	*status = reg ? DRAM_BOOT_STATUS_WARM : DRAM_BOOT_STATUS_COLD;
-#else
+	reg_data = mmio_read_32(gpio);
+	if (0U != (reg_data & ((uint32_t)1U << shift))) {
+		*status = DRAM_BOOT_STATUS_WARM;
+	} else {
+		*status = DRAM_BOOT_STATUS_COLD;
+	}
+#else	/* RCAR_SYSTEM_SUSPEND */
 	*status = DRAM_BOOT_STATUS_COLD;
-#endif
+#endif	/* RCAR_SYSTEM_SUSPEND */
 }
 
 int32_t rcar_dram_update_boot_status(uint32_t status)
 {
 	int32_t ret = 0;
 #if RCAR_SYSTEM_SUSPEND
+	uint32_t reg_data;
 #if PMIC_ROHM_BD9571
 #if DRAM_BACKUP_GPIO_USE == 0
-	uint8_t mode = 0U;
+	uint8_t bkup_mode_cnt = 0U;
 #else
 	uint32_t reqb, outd;
 #endif
-	uint8_t qllm = 0;
+	uint8_t qllm_cnt = 0U;
+	int32_t i2c_dvfs_ret = -1;
 #endif
-	uint32_t i, product, trg, gpio;
+	uint32_t loop_count;
+	uint32_t product;
+	uint32_t trg;
+	uint32_t gpio;
 
 	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
 	if (product == PRR_PRODUCT_V3H) {
@@ -111,50 +125,58 @@
 		gpio = GPIO_INDT1;
 	}
 
-	if (status != DRAM_BOOT_STATUS_WARM)
-		goto cold;
-
+	if (status == DRAM_BOOT_STATUS_WARM) {
 #if DRAM_BACKUP_GPIO_USE==1
 	mmio_setbits_32(outd, 1U << reqb);
 #else
-
 #if PMIC_ROHM_BD9571
-	if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) {
-		ERROR("BKUP mode cnt READ ERROR.\n");
-		return DRAM_UPDATE_STATUS_ERR;
-	}
-
-	mode &= ~BIT_BKUP_CTRL_OUT;
-	if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) {
-		ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", mode);
-		return DRAM_UPDATE_STATUS_ERR;
+		/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
+		i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
+				PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
+		if (0 != i2c_dvfs_ret) {
+			ERROR("BKUP mode cnt READ ERROR.\n");
+			ret = DRAM_UPDATE_STATUS_ERR;
+		} else {
+			bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
+			i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
+					PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
+			if (0 != i2c_dvfs_ret) {
+				ERROR("BKUP mode cnt WRITE ERROR. "
+					"value = %d\n", bkup_mode_cnt);
+				ret = DRAM_UPDATE_STATUS_ERR;
+			}
+		}
+#endif /* PMIC_ROHM_BD9571 */
+#endif /* DRAM_BACKUP_GPIO_USE==1 */
+		/* Wait BKUP_TRG=Low */
+		loop_count = DRAM_BKUP_TRG_LOOP_CNT;
+		while (0U < loop_count) {
+			reg_data = mmio_read_32(gpio);
+			if ((reg_data &
+				((uint32_t)1U << trg)) == 0U) {
+				break;
+			}
+			loop_count--;
+		}
+		if (0U == loop_count) {
+			ERROR(	"\nWarm booting...\n" \
+				" The potential of BKUP_TRG did not switch " \
+				"to Low.\n If you expect the operation of " \
+				"cold boot,\n check the board configuration" \
+				" (ex, Dip-SW) and/or the H/W failure.\n");
+			ret = DRAM_UPDATE_STATUS_ERR;
+		}
 	}
-#endif
-#endif
-	for (i = 0; i < DRAM_BKUP_TRG_LOOP_CNT; i++) {
-		if (mmio_read_32(gpio) & (1U << trg))
-			continue;
-
-		goto cold;
-	}
-
-	ERROR("\nWarm booting Error...\n"
-	      " The potential of BKUP_TRG did not switch "
-	      "to Low.\n If you expect the operation of "
-	      "cold boot,\n check the board configuration"
-	      " (ex, Dip-SW) and/or the H/W failure.\n");
-
-	return DRAM_UPDATE_STATUS_ERR;
-
-cold:
 #if PMIC_ROHM_BD9571
-	if (ret)
-		return ret;
-
-	qllm = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
-	if (rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, qllm)) {
-		ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm);
-		ret = DRAM_UPDATE_STATUS_ERR;
+	if(0 == ret) {
+		qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
+		i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
+				PMIC_QLLM_CNT, qllm_cnt);
+		if (0 != i2c_dvfs_ret) {
+			ERROR("QLLM cnt WRITE ERROR. "
+				"value = %d\n", qllm_cnt);
+			ret = DRAM_UPDATE_STATUS_ERR;
+		}
 	}
 #endif
 #endif
diff --git a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
index 47fa837..1fc13de 100644
--- a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
+++ b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
@@ -490,7 +490,8 @@
 		      | MOD_SEL0_REMOCON_A
 		      | MOD_SEL0_SCIF_A
 		      | MOD_SEL0_SCIF0_A
-		      | MOD_SEL0_SCIF2_A | MOD_SEL0_SPEED_PULSE_IF_A);
+		      | MOD_SEL0_SCIF2_A
+		      | MOD_SEL0_SPEED_PULSE_IF_A);
 	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
 		      | MOD_SEL1_SSI2_A
 		      | MOD_SEL1_TIMER_TMU_A
@@ -507,135 +508,137 @@
 		      | MOD_SEL1_SCIF4_A
 		      | MOD_SEL1_SCIF5_A
 		      | MOD_SEL1_VIN4_A
-		      | MOD_SEL1_VIN5_A | MOD_SEL1_ADGC_A | MOD_SEL1_SSI9_A);
+		      | MOD_SEL1_VIN5_A
+		      | MOD_SEL1_ADGC_A
+		      | MOD_SEL1_SSI9_A);
 
 	/* initialize peripheral function select */
 	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)	/* QSPI1_MISO/IO1 */
-		      |IPSR_24_FUNC(0)	/* QSPI1_MOSI/IO0 */
-		      |IPSR_20_FUNC(0)	/* QSPI1_SPCLK */
-		      |IPSR_16_FUNC(0)	/* QSPI0_IO3 */
-		      |IPSR_12_FUNC(0)	/* QSPI0_IO2 */
-		      |IPSR_8_FUNC(0)	/* QSPI0_MISO/IO1 */
-		      |IPSR_4_FUNC(0)	/* QSPI0_MOSI/IO0 */
-		      |IPSR_0_FUNC(0));	/* QSPI0_SPCLK */
+		      | IPSR_24_FUNC(0)	/* QSPI1_MOSI/IO0 */
+		      | IPSR_20_FUNC(0)	/* QSPI1_SPCLK */
+		      | IPSR_16_FUNC(0)	/* QSPI0_IO3 */
+		      | IPSR_12_FUNC(0)	/* QSPI0_IO2 */
+		      | IPSR_8_FUNC(0)	/* QSPI0_MISO/IO1 */
+		      | IPSR_4_FUNC(0)	/* QSPI0_MOSI/IO0 */
+		      | IPSR_0_FUNC(0));	/* QSPI0_SPCLK */
 	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)	/* AVB_RD2 */
-		      |IPSR_24_FUNC(0)	/* AVB_RD1 */
-		      |IPSR_20_FUNC(0)	/* AVB_RD0 */
-		      |IPSR_16_FUNC(0)	/* RPC_RESET# */
-		      |IPSR_12_FUNC(0)	/* RPC_INT# */
-		      |IPSR_8_FUNC(0)	/* QSPI1_SSL */
-		      |IPSR_4_FUNC(0)	/* QSPI1_IO3 */
-		      |IPSR_0_FUNC(0));	/* QSPI1_IO2 */
+		      | IPSR_24_FUNC(0)	/* AVB_RD1 */
+		      | IPSR_20_FUNC(0)	/* AVB_RD0 */
+		      | IPSR_16_FUNC(0)	/* RPC_RESET# */
+		      | IPSR_12_FUNC(0)	/* RPC_INT# */
+		      | IPSR_8_FUNC(0)	/* QSPI1_SSL */
+		      | IPSR_4_FUNC(0)	/* QSPI1_IO3 */
+		      | IPSR_0_FUNC(0));	/* QSPI1_IO2 */
 	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1)	/* IRQ0 */
-		      |IPSR_24_FUNC(0)
+		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(0)
 		      | IPSR_16_FUNC(2)	/* AVB_LINK */
-		      |IPSR_12_FUNC(0)
+		      | IPSR_12_FUNC(0)
 		      | IPSR_8_FUNC(0)	/* AVB_MDC */
-		      |IPSR_4_FUNC(0)	/* AVB_MDIO */
-		      |IPSR_0_FUNC(0));	/* AVB_TXCREFCLK */
+		      | IPSR_4_FUNC(0)	/* AVB_MDIO */
+		      | IPSR_0_FUNC(0));	/* AVB_TXCREFCLK */
 	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5)	/* DU_HSYNC */
-		      |IPSR_24_FUNC(0)
+		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(0)
 		      | IPSR_16_FUNC(0)
 		      | IPSR_12_FUNC(5)	/* DU_DG4 */
-		      |IPSR_8_FUNC(5)	/* DU_DOTCLKOUT0 */
-		      |IPSR_4_FUNC(5)	/* DU_DISP */
-		      |IPSR_0_FUNC(1));	/* IRQ1 */
+		      | IPSR_8_FUNC(5)	/* DU_DOTCLKOUT0 */
+		      | IPSR_4_FUNC(5)	/* DU_DISP */
+		      | IPSR_0_FUNC(1));	/* IRQ1 */
 	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5)	/* DU_DB5 */
-		      |IPSR_24_FUNC(5)	/* DU_DB4 */
-		      |IPSR_20_FUNC(5)	/* DU_DB3 */
-		      |IPSR_16_FUNC(5)	/* DU_DB2 */
-		      |IPSR_12_FUNC(5)	/* DU_DG6 */
-		      |IPSR_8_FUNC(5)	/* DU_VSYNC */
-		      |IPSR_4_FUNC(5)	/* DU_DG5 */
-		      |IPSR_0_FUNC(5));	/* DU_DG7 */
+		      | IPSR_24_FUNC(5)	/* DU_DB4 */
+		      | IPSR_20_FUNC(5)	/* DU_DB3 */
+		      | IPSR_16_FUNC(5)	/* DU_DB2 */
+		      | IPSR_12_FUNC(5)	/* DU_DG6 */
+		      | IPSR_8_FUNC(5)	/* DU_VSYNC */
+		      | IPSR_4_FUNC(5)	/* DU_DG5 */
+		      | IPSR_0_FUNC(5));	/* DU_DG7 */
 	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5)	/* DU_DR3 */
-		      |IPSR_24_FUNC(5)	/* DU_DB7 */
-		      |IPSR_20_FUNC(5)	/* DU_DR2 */
-		      |IPSR_16_FUNC(5)	/* DU_DR1 */
-		      |IPSR_12_FUNC(5)	/* DU_DR0 */
-		      |IPSR_8_FUNC(5)	/* DU_DB1 */
-		      |IPSR_4_FUNC(5)	/* DU_DB0 */
-		      |IPSR_0_FUNC(5));	/* DU_DB6 */
+		      | IPSR_24_FUNC(5)	/* DU_DB7 */
+		      | IPSR_20_FUNC(5)	/* DU_DR2 */
+		      | IPSR_16_FUNC(5)	/* DU_DR1 */
+		      | IPSR_12_FUNC(5)	/* DU_DR0 */
+		      | IPSR_8_FUNC(5)	/* DU_DB1 */
+		      | IPSR_4_FUNC(5)	/* DU_DB0 */
+		      | IPSR_0_FUNC(5));	/* DU_DB6 */
 	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5)	/* DU_DG1 */
-		      |IPSR_24_FUNC(5)	/* DU_DG0 */
-		      |IPSR_20_FUNC(5)	/* DU_DR7 */
-		      |IPSR_16_FUNC(2)	/* IRQ5 */
-		      |IPSR_12_FUNC(5)	/* DU_DR6 */
-		      |IPSR_8_FUNC(5)	/* DU_DR5 */
-		      |IPSR_4_FUNC(0)
+		      | IPSR_24_FUNC(5)	/* DU_DG0 */
+		      | IPSR_20_FUNC(5)	/* DU_DR7 */
+		      | IPSR_16_FUNC(2)	/* IRQ5 */
+		      | IPSR_12_FUNC(5)	/* DU_DR6 */
+		      | IPSR_8_FUNC(5)	/* DU_DR5 */
+		      | IPSR_4_FUNC(0)
 		      | IPSR_0_FUNC(5));	/* DU_DR4 */
 	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)	/* SD0_CLK */
-		      |IPSR_24_FUNC(0)
+		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(5)	/* DU_DOTCLKIN0 */
-		      |IPSR_16_FUNC(5)	/* DU_DG3 */
-		      |IPSR_12_FUNC(0)
+		      | IPSR_16_FUNC(5)	/* DU_DG3 */
+		      | IPSR_12_FUNC(0)
 		      | IPSR_8_FUNC(0)
 		      | IPSR_4_FUNC(0)
 		      | IPSR_0_FUNC(5));	/* DU_DG2 */
 	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)	/* SD1_DAT0 */
-		      |IPSR_24_FUNC(0)	/* SD1_CMD */
-		      |IPSR_20_FUNC(0)	/* SD1_CLK */
-		      |IPSR_16_FUNC(0)	/* SD0_DAT3 */
-		      |IPSR_12_FUNC(0)	/* SD0_DAT2 */
-		      |IPSR_8_FUNC(0)	/* SD0_DAT1 */
-		      |IPSR_4_FUNC(0)	/* SD0_DAT0 */
-		      |IPSR_0_FUNC(0));	/* SD0_CMD */
+		      | IPSR_24_FUNC(0)	/* SD1_CMD */
+		      | IPSR_20_FUNC(0)	/* SD1_CLK */
+		      | IPSR_16_FUNC(0)	/* SD0_DAT3 */
+		      | IPSR_12_FUNC(0)	/* SD0_DAT2 */
+		      | IPSR_8_FUNC(0)	/* SD0_DAT1 */
+		      | IPSR_4_FUNC(0)	/* SD0_DAT0 */
+		      | IPSR_0_FUNC(0));	/* SD0_CMD */
 	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)	/* SD3_DAT2 */
-		      |IPSR_24_FUNC(0)	/* SD3_DAT1 */
-		      |IPSR_20_FUNC(0)	/* SD3_DAT0 */
-		      |IPSR_16_FUNC(0)	/* SD3_CMD */
-		      |IPSR_12_FUNC(0)	/* SD3_CLK */
-		      |IPSR_8_FUNC(0)	/* SD1_DAT3 */
-		      |IPSR_4_FUNC(0)	/* SD1_DAT2 */
-		      |IPSR_0_FUNC(0));	/* SD1_DAT1 */
+		      | IPSR_24_FUNC(0)	/* SD3_DAT1 */
+		      | IPSR_20_FUNC(0)	/* SD3_DAT0 */
+		      | IPSR_16_FUNC(0)	/* SD3_CMD */
+		      | IPSR_12_FUNC(0)	/* SD3_CLK */
+		      | IPSR_8_FUNC(0)	/* SD1_DAT3 */
+		      | IPSR_4_FUNC(0)	/* SD1_DAT2 */
+		      | IPSR_0_FUNC(0));	/* SD1_DAT1 */
 	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)	/* SD0_WP */
-		      |IPSR_24_FUNC(0)	/* SD0_CD */
-		      |IPSR_20_FUNC(0)	/* SD3_DS */
-		      |IPSR_16_FUNC(0)	/* SD3_DAT7 */
-		      |IPSR_12_FUNC(0)	/* SD3_DAT6 */
-		      |IPSR_8_FUNC(0)	/* SD3_DAT5 */
-		      |IPSR_4_FUNC(0)	/* SD3_DAT4 */
-		      |IPSR_0_FUNC(0));	/* SD3_DAT3 */
+		      | IPSR_24_FUNC(0)	/* SD0_CD */
+		      | IPSR_20_FUNC(0)	/* SD3_DS */
+		      | IPSR_16_FUNC(0)	/* SD3_DAT7 */
+		      | IPSR_12_FUNC(0)	/* SD3_DAT6 */
+		      | IPSR_8_FUNC(0)	/* SD3_DAT5 */
+		      | IPSR_4_FUNC(0)	/* SD3_DAT4 */
+		      | IPSR_0_FUNC(0));	/* SD3_DAT3 */
 	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
 		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(2)	/* AUDIO_CLKOUT1_A */
-		      |IPSR_16_FUNC(2)	/* AUDIO_CLKOUT_A */
-		      |IPSR_12_FUNC(0)
+		      | IPSR_16_FUNC(2)	/* AUDIO_CLKOUT_A */
+		      | IPSR_12_FUNC(0)
 		      | IPSR_8_FUNC(0)
 		      | IPSR_4_FUNC(0)	/* SD1_WP */
-		      |IPSR_0_FUNC(0));	/* SD1_CD */
+		      | IPSR_0_FUNC(0));	/* SD1_CD */
 	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
 		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(0)
 		      | IPSR_16_FUNC(0)
 		      | IPSR_12_FUNC(0)	/* RX2_A */
-		      |IPSR_8_FUNC(0)	/* TX2_A */
-		      |IPSR_4_FUNC(2)	/* AUDIO_CLKB_A */
-		      |IPSR_0_FUNC(0));
+		      | IPSR_8_FUNC(0)	/* TX2_A */
+		      | IPSR_4_FUNC(2)	/* AUDIO_CLKB_A */
+		      | IPSR_0_FUNC(0));
 	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
 		      | IPSR_24_FUNC(0)
 		      | IPSR_20_FUNC(0)
 		      | IPSR_16_FUNC(0)
 		      | IPSR_12_FUNC(0)
 		      | IPSR_8_FUNC(2)	/* AUDIO_CLKC_A */
-		      |IPSR_4_FUNC(1)	/* HTX2_A */
-		      |IPSR_0_FUNC(1));	/* HRX2_A */
+		      | IPSR_4_FUNC(1)	/* HTX2_A */
+		      | IPSR_0_FUNC(1));	/* HRX2_A */
 	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3)	/* USB0_PWEN_B */
-		      |IPSR_24_FUNC(0)	/* SSI_SDATA4 */
-		      |IPSR_20_FUNC(0)	/* SSI_SDATA3 */
-		      |IPSR_16_FUNC(0)	/* SSI_WS349 */
-		      |IPSR_12_FUNC(0)	/* SSI_SCK349 */
-		      |IPSR_8_FUNC(0)
+		      | IPSR_24_FUNC(0)	/* SSI_SDATA4 */
+		      | IPSR_20_FUNC(0)	/* SSI_SDATA3 */
+		      | IPSR_16_FUNC(0)	/* SSI_WS349 */
+		      | IPSR_12_FUNC(0)	/* SSI_SCK349 */
+		      | IPSR_8_FUNC(0)
 		      | IPSR_4_FUNC(0)	/* SSI_SDATA1 */
-		      |IPSR_0_FUNC(0));	/* SSI_SDATA0 */
+		      | IPSR_0_FUNC(0));	/* SSI_SDATA0 */
 	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)	/* USB30_OVC */
-		      |IPSR_24_FUNC(0)	/* USB30_PWEN */
-		      |IPSR_20_FUNC(0)	/* AUDIO_CLKA */
-		      |IPSR_16_FUNC(1)	/* HRTS2#_A */
-		      |IPSR_12_FUNC(1)	/* HCTS2#_A */
-		      |IPSR_8_FUNC(0)
+		      | IPSR_24_FUNC(0)	/* USB30_PWEN */
+		      | IPSR_20_FUNC(0)	/* AUDIO_CLKA */
+		      | IPSR_16_FUNC(1)	/* HRTS2#_A */
+		      | IPSR_12_FUNC(1)	/* HCTS2#_A */
+		      | IPSR_8_FUNC(0)
 		      | IPSR_4_FUNC(0)
 		      | IPSR_0_FUNC(3));	/* USB0_OVC_B */
 
@@ -648,7 +651,11 @@
 		      | GPSR0_D8
 		      | GPSR0_D7
 		      | GPSR0_D6
-		      | GPSR0_D5 | GPSR0_D3 | GPSR0_D2 | GPSR0_D1 | GPSR0_D0);
+		      | GPSR0_D5
+		      | GPSR0_D3
+		      | GPSR0_D2
+		      | GPSR0_D1
+		      | GPSR0_D0);
 	pfc_reg_write(PFC_GPSR1, GPSR1_WE0
 		      | GPSR1_CS0
 		      | GPSR1_A19
@@ -663,7 +670,11 @@
 		      | GPSR1_A10
 		      | GPSR1_A9
 		      | GPSR1_A8
-		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
 	pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERCED
 		      | GPSR2_BIT26_REVERCED
 		      | GPSR2_RD
@@ -687,7 +698,8 @@
 		      | GPSR2_QSPI0_IO3
 		      | GPSR2_QSPI0_IO2
 		      | GPSR2_QSPI0_MISO_IO1
-		      | GPSR2_QSPI0_MOSI_IO0 | GPSR2_QSPI0_SPCLK);
+		      | GPSR2_QSPI0_MOSI_IO0
+		      | GPSR2_QSPI0_SPCLK);
 	pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
 		      | GPSR3_SD1_CD
 		      | GPSR3_SD0_WP
@@ -701,7 +713,9 @@
 		      | GPSR3_SD0_DAT3
 		      | GPSR3_SD0_DAT2
 		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
 	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
 		      | GPSR4_SD3_DAT7
 		      | GPSR4_SD3_DAT6
@@ -710,13 +724,17 @@
 		      | GPSR4_SD3_DAT3
 		      | GPSR4_SD3_DAT2
 		      | GPSR4_SD3_DAT1
-		      | GPSR4_SD3_DAT0 | GPSR4_SD3_CMD | GPSR4_SD3_CLK);
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK);
 	pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
 		      | GPSR5_MSIOF0_SS2
 		      | GPSR5_MSIOF0_SS1
 		      | GPSR5_RX2_A
 		      | GPSR5_TX2_A
-		      | GPSR5_SCK2_A | GPSR5_RTS0_TANS_A | GPSR5_CTS0_A);
+		      | GPSR5_SCK2_A
+		      | GPSR5_RTS0_TANS_A
+		      | GPSR5_CTS0_A);
 	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
 		      | GPSR6_SSI_SDATA6
 		      | GPSR6_SSI_WS6
@@ -730,7 +748,8 @@
 		      | GPSR6_SSI_SCK349
 		      | GPSR6_SSI_SDATA1
 		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS01239 | GPSR6_SSI_SCK01239);
+		      | GPSR6_SSI_WS01239
+		      | GPSR6_SSI_SCK01239);
 
 	/* initialize POC control */
 	reg = mmio_read_32(PFC_IOCTRL30);
@@ -743,7 +762,9 @@
 	       | POC_SD0_DAT3_33V
 	       | POC_SD0_DAT2_33V
 	       | POC_SD0_DAT1_33V
-	       | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+	       | POC_SD0_DAT0_33V
+	       | POC_SD0_CMD_33V
+	       | POC_SD0_CLK_33V);
 	pfc_reg_write(PFC_IOCTRL30, reg);
 	reg = mmio_read_32(PFC_IOCTRL32);
 	reg = (reg & IOCTRL32_MASK);
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
index f31d99e..2f62bb2 100644
--- a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
@@ -802,7 +802,9 @@
 		      | MOD_SEL0_DRIF2_A
 		      | MOD_SEL0_DRIF1_A
 		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A | MOD_SEL0_5LINE_A);
+		      | MOD_SEL0_CANFD0_A
+		      | MOD_SEL0_ADG_A
+		      | MOD_SEL0_5LINE_A);
 	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
 		      | MOD_SEL1_TSIF0_A
 		      | MOD_SEL1_TIMER_TMU_A
@@ -822,9 +824,13 @@
 		      | MOD_SEL1_PWM6_A
 		      | MOD_SEL1_PWM5_A
 		      | MOD_SEL1_PWM4_A
-		      | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+		      | MOD_SEL1_PWM3_A
+		      | MOD_SEL1_PWM2_A
+		      | MOD_SEL1_PWM1_A);
 	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
-		      | MOD_SEL2_I2C_3_A | MOD_SEL2_I2C_0_A | MOD_SEL2_VIN4_A);
+		      | MOD_SEL2_I2C_3_A
+		      | MOD_SEL2_I2C_0_A
+		      | MOD_SEL2_VIN4_A);
 
 	/* initialize peripheral function select */
 	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@@ -971,7 +977,10 @@
 		      | GPSR0_D14
 		      | GPSR0_D13
 		      | GPSR0_D12
-		      | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8);
 	pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
 		      | GPSR1_A19
 		      | GPSR1_A18
@@ -984,7 +993,11 @@
 		      | GPSR1_A7
 		      | GPSR1_A6
 		      | GPSR1_A5
-		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
 	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
 		      | GPSR2_AVB_AVTP_MATCH_A
 		      | GPSR2_AVB_LINK
@@ -994,7 +1007,10 @@
 		      | GPSR2_PWM1_A
 		      | GPSR2_IRQ5
 		      | GPSR2_IRQ4
-		      | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+		      | GPSR2_IRQ3
+		      | GPSR2_IRQ2
+		      | GPSR2_IRQ1
+		      | GPSR2_IRQ0);
 	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
 		      | GPSR3_SD0_CD
 		      | GPSR3_SD1_DAT3
@@ -1004,7 +1020,9 @@
 		      | GPSR3_SD0_DAT3
 		      | GPSR3_SD0_DAT2
 		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
 	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
 		      | GPSR4_SD3_DAT6
 		      | GPSR4_SD3_DAT3
@@ -1017,7 +1035,9 @@
 		      | GPSR4_SD2_DAT3
 		      | GPSR4_SD2_DAT2
 		      | GPSR4_SD2_DAT1
-		      | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+		      | GPSR4_SD2_DAT0
+		      | GPSR4_SD2_CMD
+		      | GPSR4_SD2_CLK);
 	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
 		      | GPSR5_MSIOF0_SS1
 		      | GPSR5_MSIOF0_SYNC
@@ -1032,7 +1052,9 @@
 		      | GPSR5_RTS1_TANS
 		      | GPSR5_CTS1
 		      | GPSR5_TX1_A
-		      | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+		      | GPSR5_RX1_A
+		      | GPSR5_RTS0_TANS
+		      | GPSR5_SCK0);
 	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
 		      | GPSR6_USB30_PWEN
 		      | GPSR6_USB1_OVC
@@ -1052,9 +1074,12 @@
 		      | GPSR6_SSI_SCK4
 		      | GPSR6_SSI_SDATA1_A
 		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+		      | GPSR6_SSI_WS0129
+		      | GPSR6_SSI_SCK0129);
 	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-		      | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+		      | GPSR7_HDMI0_CEC
+		      | GPSR7_AVS2
+		      | GPSR7_AVS1);
 
 	/* initialize POC control register */
 	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@@ -1071,7 +1096,9 @@
 		      | POC_SD0_DAT3_33V
 		      | POC_SD0_DAT2_33V
 		      | POC_SD0_DAT1_33V
-		      | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+		      | POC_SD0_DAT0_33V
+		      | POC_SD0_CMD_33V
+		      | POC_SD0_CLK_33V);
 
 	/* initialize DRV control register */
 	reg = mmio_read_32(PFC_DRVCTRL0);
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
index e53235a..116fd82 100644
--- a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
@@ -833,7 +833,8 @@
 		      | MOD_SEL0_DRIF2_A
 		      | MOD_SEL0_DRIF1_A
 		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
+		      | MOD_SEL0_CANFD0_A
+		      | MOD_SEL0_ADG_A_A);
 	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
 		      | MOD_SEL1_TSIF0_A
 		      | MOD_SEL1_TIMER_TMU_A
@@ -853,7 +854,9 @@
 		      | MOD_SEL1_PWM6_A
 		      | MOD_SEL1_PWM5_A
 		      | MOD_SEL1_PWM4_A
-		      | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+		      | MOD_SEL1_PWM3_A
+		      | MOD_SEL1_PWM2_A
+		      | MOD_SEL1_PWM1_A);
 	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
 		      | MOD_SEL2_I2C_3_A
 		      | MOD_SEL2_I2C_0_A
@@ -864,7 +867,9 @@
 		      | MOD_SEL2_SSI2_A
 		      | MOD_SEL2_SSI9_A
 		      | MOD_SEL2_TIMER_TMU2_A
-		      | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
+		      | MOD_SEL2_ADG_B_A
+		      | MOD_SEL2_ADG_C_A
+		      | MOD_SEL2_VIN4_A);
 
 	/* initialize peripheral function select */
 	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@@ -1019,7 +1024,10 @@
 		      | GPSR0_D14
 		      | GPSR0_D13
 		      | GPSR0_D12
-		      | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8);
 	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
 		      | GPSR1_EX_WAIT0_A
 		      | GPSR1_A19
@@ -1033,7 +1041,11 @@
 		      | GPSR1_A7
 		      | GPSR1_A6
 		      | GPSR1_A5
-		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
 	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
 		      | GPSR2_AVB_AVTP_MATCH_A
 		      | GPSR2_AVB_LINK
@@ -1043,7 +1055,10 @@
 		      | GPSR2_PWM1_A
 		      | GPSR2_IRQ5
 		      | GPSR2_IRQ4
-		      | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+		      | GPSR2_IRQ3
+		      | GPSR2_IRQ2
+		      | GPSR2_IRQ1
+		      | GPSR2_IRQ0);
 	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
 		      | GPSR3_SD0_CD
 		      | GPSR3_SD1_DAT3
@@ -1053,7 +1068,9 @@
 		      | GPSR3_SD0_DAT3
 		      | GPSR3_SD0_DAT2
 		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
 	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
 		      | GPSR4_SD3_DAT6
 		      | GPSR4_SD3_DAT3
@@ -1066,7 +1083,9 @@
 		      | GPSR4_SD2_DAT3
 		      | GPSR4_SD2_DAT2
 		      | GPSR4_SD2_DAT1
-		      | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+		      | GPSR4_SD2_DAT0
+		      | GPSR4_SD2_CMD
+		      | GPSR4_SD2_CLK);
 	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
 		      | GPSR5_MSIOF0_SS1
 		      | GPSR5_MSIOF0_SYNC
@@ -1081,7 +1100,9 @@
 		      | GPSR5_RTS1_TANS
 		      | GPSR5_CTS1
 		      | GPSR5_TX1_A
-		      | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+		      | GPSR5_RX1_A
+		      | GPSR5_RTS0_TANS
+		      | GPSR5_SCK0);
 	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
 		      | GPSR6_USB30_PWEN
 		      | GPSR6_USB1_OVC
@@ -1101,9 +1122,12 @@
 		      | GPSR6_SSI_SCK4
 		      | GPSR6_SSI_SDATA1_A
 		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+		      | GPSR6_SSI_WS0129
+		      | GPSR6_SSI_SCK0129);
 	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-		      | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+		      | GPSR7_HDMI0_CEC
+		      | GPSR7_AVS2
+		      | GPSR7_AVS1);
 
 	/* initialize POC control register */
 	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@@ -1120,7 +1144,9 @@
 		      | POC_SD0_DAT3_33V
 		      | POC_SD0_DAT2_33V
 		      | POC_SD0_DAT1_33V
-		      | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+		      | POC_SD0_DAT0_33V
+		      | POC_SD0_CMD_33V
+		      | POC_SD0_CLK_33V);
 
 	/* initialize DRV control register */
 	reg = mmio_read_32(PFC_DRVCTRL0);
diff --git a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
index f7e66f2..fc12cd6 100644
--- a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
+++ b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -867,7 +867,9 @@
 		/* Set transfer parameter, Start transfer */
 		mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
 			      | RDMCHCR_RPT_TCR
-			      | RDMCHCR_TS_2 | RDMCHCR_RS_AUTO | RDMCHCR_DE);
+			      | RDMCHCR_TS_2
+			      | RDMCHCR_RS_AUTO
+			      | RDMCHCR_DE);
 	}
 }
 
@@ -913,7 +915,8 @@
 		      | MOD_SEL0_DRIF2_A
 		      | MOD_SEL0_DRIF1_A
 		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
+		      | MOD_SEL0_CANFD0_A
+		      | MOD_SEL0_ADG_A_A);
 	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
 		      | MOD_SEL1_TSIF0_A
 		      | MOD_SEL1_TIMER_TMU_A
@@ -933,7 +936,9 @@
 		      | MOD_SEL1_PWM6_A
 		      | MOD_SEL1_PWM5_A
 		      | MOD_SEL1_PWM4_A
-		      | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+		      | MOD_SEL1_PWM3_A
+		      | MOD_SEL1_PWM2_A
+		      | MOD_SEL1_PWM1_A);
 	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
 		      | MOD_SEL2_I2C_3_A
 		      | MOD_SEL2_I2C_0_A
@@ -944,7 +949,9 @@
 		      | MOD_SEL2_SSI2_A
 		      | MOD_SEL2_SSI9_A
 		      | MOD_SEL2_TIMER_TMU2_A
-		      | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
+		      | MOD_SEL2_ADG_B_A
+		      | MOD_SEL2_ADG_C_A
+		      | MOD_SEL2_VIN4_A);
 
 	/* initialize peripheral function select */
 	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@@ -1099,7 +1106,10 @@
 		      | GPSR0_D14
 		      | GPSR0_D13
 		      | GPSR0_D12
-		      | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8);
 	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
 		      | GPSR1_EX_WAIT0_A
 		      | GPSR1_A19
@@ -1113,7 +1123,11 @@
 		      | GPSR1_A7
 		      | GPSR1_A6
 		      | GPSR1_A5
-		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
 	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
 		      | GPSR2_AVB_AVTP_MATCH_A
 		      | GPSR2_AVB_LINK
@@ -1123,7 +1137,10 @@
 		      | GPSR2_PWM1_A
 		      | GPSR2_IRQ5
 		      | GPSR2_IRQ4
-		      | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+		      | GPSR2_IRQ3
+		      | GPSR2_IRQ2
+		      | GPSR2_IRQ1
+		      | GPSR2_IRQ0);
 	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
 		      | GPSR3_SD0_CD
 		      | GPSR3_SD1_DAT3
@@ -1133,7 +1150,9 @@
 		      | GPSR3_SD0_DAT3
 		      | GPSR3_SD0_DAT2
 		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
 	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
 		      | GPSR4_SD3_DAT6
 		      | GPSR4_SD3_DAT3
@@ -1146,7 +1165,9 @@
 		      | GPSR4_SD2_DAT3
 		      | GPSR4_SD2_DAT2
 		      | GPSR4_SD2_DAT1
-		      | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+		      | GPSR4_SD2_DAT0
+		      | GPSR4_SD2_CMD
+		      | GPSR4_SD2_CLK);
 	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
 		      | GPSR5_MSIOF0_SS1
 		      | GPSR5_MSIOF0_SYNC
@@ -1161,7 +1182,9 @@
 		      | GPSR5_RTS1_TANS
 		      | GPSR5_CTS1
 		      | GPSR5_TX1_A
-		      | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+		      | GPSR5_RX1_A
+		      | GPSR5_RTS0_TANS
+		      | GPSR5_SCK0);
 	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
 		      | GPSR6_USB30_PWEN
 		      | GPSR6_USB1_OVC
@@ -1181,9 +1204,12 @@
 		      | GPSR6_SSI_SCK4
 		      | GPSR6_SSI_SDATA1_A
 		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+		      | GPSR6_SSI_WS0129
+		      | GPSR6_SSI_SCK0129);
 	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-		      | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+		      | GPSR7_HDMI0_CEC
+		      | GPSR7_AVS2
+		      | GPSR7_AVS1);
 
 	/* initialize POC control register */
 	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@@ -1200,7 +1226,9 @@
 		      | POC_SD0_DAT3_33V
 		      | POC_SD0_DAT2_33V
 		      | POC_SD0_DAT1_33V
-		      | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+		      | POC_SD0_DAT0_33V
+		      | POC_SD0_CMD_33V
+		      | POC_SD0_CLK_33V);
 
 	/* initialize DRV control register */
 	reg = mmio_read_32(PFC_DRVCTRL0);
diff --git a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
index e6b8a4f..07f08fa 100644
--- a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+++ b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
@@ -821,7 +821,8 @@
 		      | MOD_SEL0_DRIF2_A
 		      | MOD_SEL0_DRIF1_A
 		      | MOD_SEL0_DRIF0_A
-		      | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
+		      | MOD_SEL0_CANFD0_A
+		      | MOD_SEL0_ADG_A_A);
 	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
 		      | MOD_SEL1_TSIF0_A
 		      | MOD_SEL1_TIMER_TMU_A
@@ -841,7 +842,9 @@
 		      | MOD_SEL1_PWM6_A
 		      | MOD_SEL1_PWM5_A
 		      | MOD_SEL1_PWM4_A
-		      | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+		      | MOD_SEL1_PWM3_A
+		      | MOD_SEL1_PWM2_A
+		      | MOD_SEL1_PWM1_A);
 	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
 		      | MOD_SEL2_I2C_3_A
 		      | MOD_SEL2_I2C_0_A
@@ -852,7 +855,9 @@
 		      | MOD_SEL2_SSI2_A
 		      | MOD_SEL2_SSI9_A
 		      | MOD_SEL2_TIMER_TMU2_A
-		      | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
+		      | MOD_SEL2_ADG_B_A
+		      | MOD_SEL2_ADG_C_A
+		      | MOD_SEL2_VIN4_A);
 
 	/* initialize peripheral function select */
 	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@@ -1007,7 +1012,10 @@
 		      | GPSR0_D14
 		      | GPSR0_D13
 		      | GPSR0_D12
-		      | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8);
 	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
 		      | GPSR1_EX_WAIT0_A
 		      | GPSR1_A19
@@ -1021,7 +1029,11 @@
 		      | GPSR1_A7
 		      | GPSR1_A6
 		      | GPSR1_A5
-		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+		      | GPSR1_A4
+		      | GPSR1_A3
+		      | GPSR1_A2
+		      | GPSR1_A1
+		      | GPSR1_A0);
 	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
 		      | GPSR2_AVB_AVTP_MATCH_A
 		      | GPSR2_AVB_LINK
@@ -1031,7 +1043,10 @@
 		      | GPSR2_PWM1_A
 		      | GPSR2_IRQ5
 		      | GPSR2_IRQ4
-		      | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+		      | GPSR2_IRQ3
+		      | GPSR2_IRQ2
+		      | GPSR2_IRQ1
+		      | GPSR2_IRQ0);
 	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
 		      | GPSR3_SD0_CD
 		      | GPSR3_SD1_DAT3
@@ -1041,7 +1056,9 @@
 		      | GPSR3_SD0_DAT3
 		      | GPSR3_SD0_DAT2
 		      | GPSR3_SD0_DAT1
-		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+		      | GPSR3_SD0_DAT0
+		      | GPSR3_SD0_CMD
+		      | GPSR3_SD0_CLK);
 	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
 		      | GPSR4_SD3_DAT6
 		      | GPSR4_SD3_DAT3
@@ -1054,7 +1071,9 @@
 		      | GPSR4_SD2_DAT3
 		      | GPSR4_SD2_DAT2
 		      | GPSR4_SD2_DAT1
-		      | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+		      | GPSR4_SD2_DAT0
+		      | GPSR4_SD2_CMD
+		      | GPSR4_SD2_CLK);
 	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
 		      | GPSR5_MSIOF0_SS1
 		      | GPSR5_MSIOF0_SYNC
@@ -1069,7 +1088,9 @@
 		      | GPSR5_RTS1_TANS
 		      | GPSR5_CTS1
 		      | GPSR5_TX1_A
-		      | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+		      | GPSR5_RX1_A
+		      | GPSR5_RTS0_TANS
+		      | GPSR5_SCK0);
 	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
 		      | GPSR6_USB30_PWEN
 		      | GPSR6_USB1_OVC
@@ -1089,9 +1110,12 @@
 		      | GPSR6_SSI_SCK4
 		      | GPSR6_SSI_SDATA1_A
 		      | GPSR6_SSI_SDATA0
-		      | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+		      | GPSR6_SSI_WS0129
+		      | GPSR6_SSI_SCK0129);
 	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-		      | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+		      | GPSR7_HDMI0_CEC
+		      | GPSR7_AVS2
+		      | GPSR7_AVS1);
 
 	/* initialize POC control register */
 	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@@ -1108,7 +1132,9 @@
 		      | POC_SD0_DAT3_33V
 		      | POC_SD0_DAT2_33V
 		      | POC_SD0_DAT1_33V
-		      | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+		      | POC_SD0_DAT0_33V
+		      | POC_SD0_CMD_33V
+		      | POC_SD0_CLK_33V);
 
 	/* initialize DRV control register */
 	reg = mmio_read_32(PFC_DRVCTRL0);
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
index 593fefb..db51912 100644
--- a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
+++ b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
@@ -12,7 +12,7 @@
 #include "../qos_reg.h"
 #include "qos_init_e3_v10.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.02"
+#define	RCAR_QOS_VERSION		"rev.0.05"
 
 #define QOSCTRL_EARLYR			(QOS_BASE1 + 0x0060U)
 #define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
@@ -134,14 +134,6 @@
 		}
 	}
 
-	/* 3DG bus Leaf setting */
-	io_write_32(GPU_ACT_GRD, 0x00001234U);
-	io_write_32(GPU_ACT0, 0x00000000U);
-	io_write_32(GPU_ACT1, 0x00000000U);
-	io_write_32(GPU_ACT2, 0x00000000U);
-	io_write_32(GPU_ACT3, 0x00000000U);
-	io_write_32(GPU_ACT_GRD, 0x00000000U);
-
 	/* RT bus Leaf setting */
 	io_write_32(RT_ACT0, 0x00000000U);
 	io_write_32(RT_ACT1, 0x00000000U);
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
index cf376a2..d7f9d14 100644
--- a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
+++ b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
@@ -27,20 +27,20 @@
 	/* 0x0098, */ 0x0000000000000000UL,
 	/* 0x00a0, */ 0x000C08380000FFFFUL,
 	/* 0x00a8, */ 0x000C04110000FFFFUL,
-	/* 0x00b0, */ 0x000C04110000FFFFUL,
+	/* 0x00b0, */ 0x000C04150000FFFFUL,
 	/* 0x00b8, */ 0x0000000000000000UL,
 	/* 0x00c0, */ 0x000C08380000FFFFUL,
 	/* 0x00c8, */ 0x000C04110000FFFFUL,
-	/* 0x00d0, */ 0x000C04110000FFFFUL,
+	/* 0x00d0, */ 0x000C04150000FFFFUL,
 	/* 0x00d8, */ 0x0000000000000000UL,
 	/* 0x00e0, */ 0x0000000000000000UL,
 	/* 0x00e8, */ 0x0000000000000000UL,
 	/* 0x00f0, */ 0x001018580000FFFFUL,
-	/* 0x00f8, */ 0x000C04400000FFFFUL,
+	/* 0x00f8, */ 0x000C084F0000FFFFUL,
 	/* 0x0100, */ 0x0000000000000000UL,
 	/* 0x0108, */ 0x0000000000000000UL,
 	/* 0x0110, */ 0x001008580000FFFFUL,
-	/* 0x0118, */ 0x000C19660000FFFFUL,
+	/* 0x0118, */ 0x000C21E40000FFFFUL,
 	/* 0x0120, */ 0x0000000000000000UL,
 	/* 0x0128, */ 0x0000000000000000UL,
 	/* 0x0130, */ 0x0000000000000000UL,
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
index 002a664..439cafe 100644
--- a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
+++ b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
@@ -27,20 +27,20 @@
 	/* 0x0098, */ 0x0000000000000000UL,
 	/* 0x00a0, */ 0x000C10700000FFFFUL,
 	/* 0x00a8, */ 0x000C08210000FFFFUL,
-	/* 0x00b0, */ 0x000C08210000FFFFUL,
+	/* 0x00b0, */ 0x000C082A0000FFFFUL,
 	/* 0x00b8, */ 0x0000000000000000UL,
 	/* 0x00c0, */ 0x000C10700000FFFFUL,
 	/* 0x00c8, */ 0x000C08210000FFFFUL,
-	/* 0x00d0, */ 0x000C08210000FFFFUL,
+	/* 0x00d0, */ 0x000C082A0000FFFFUL,
 	/* 0x00d8, */ 0x0000000000000000UL,
 	/* 0x00e0, */ 0x0000000000000000UL,
 	/* 0x00e8, */ 0x0000000000000000UL,
 	/* 0x00f0, */ 0x00102CAF0000FFFFUL,
-	/* 0x00f8, */ 0x000C087F0000FFFFUL,
+	/* 0x00f8, */ 0x000C0C9D0000FFFFUL,
 	/* 0x0100, */ 0x0000000000000000UL,
 	/* 0x0108, */ 0x0000000000000000UL,
 	/* 0x0110, */ 0x00100CAF0000FFFFUL,
-	/* 0x0118, */ 0x000C32CC0000FFFFUL,
+	/* 0x0118, */ 0x000C43C80000FFFFUL,
 	/* 0x0120, */ 0x0000000000000000UL,
 	/* 0x0128, */ 0x0000000000000000UL,
 	/* 0x0130, */ 0x0000000000000000UL,
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
index f27a7dc..c4f8701 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
@@ -12,7 +12,8 @@
 #include "../qos_reg.h"
 #include "qos_init_h3_v20.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.19"
+
+#define	RCAR_QOS_VERSION		"rev.0.20"
 
 #define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
 
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
index b3e65df..95f4810 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
@@ -12,7 +12,8 @@
 #include "../qos_reg.h"
 #include "qos_init_h3_v30.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.07"
+
+#define	RCAR_QOS_VERSION		"rev.0.10"
 
 #define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
 
@@ -226,8 +227,6 @@
 	io_write_32(AXI_TR3CR, 0x00010000U);
 	io_write_32(AXI_TR4CR, 0x00010000U);
 
-	/* 3DG bus Leaf setting */
-
 	/* RT bus Leaf setting */
 	io_write_32(RT_ACT0, 0x00000000U);
 	io_write_32(RT_ACT1, 0x00000000U);
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
index daa4076..28a240f 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
@@ -36,12 +36,12 @@
 	/* 0x00e0, */ 0x00100C090000FFFFUL,
 	/* 0x00e8, */ 0x0000000000000000UL,
 	/* 0x00f0, */ 0x001024090000FFFFUL,
-	/* 0x00f8, */ 0x000C08080000FFFFUL,
+	/* 0x00f8, */ 0x000C100D0000FFFFUL,
 	/* 0x0100, */ 0x0000000000000000UL,
 	/* 0x0108, */ 0x0000000000000000UL,
 	/* 0x0110, */ 0x00100C090000FFFFUL,
-	/* 0x0118, */ 0x000C18180000FFFFUL,
-	/* 0x0120, */ 0x000C18180000FFFFUL,
+	/* 0x0118, */ 0x000C1C1B0000FFFFUL,
+	/* 0x0120, */ 0x000C1C1B0000FFFFUL,
 	/* 0x0128, */ 0x0000000000000000UL,
 	/* 0x0130, */ 0x0000000000000000UL,
 	/* 0x0138, */ 0x00100C0B0000FFFFUL,
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
index f72165c..def6585 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
@@ -36,12 +36,12 @@
 	/* 0x00e0, */ 0x001014110000FFFFUL,
 	/* 0x00e8, */ 0x0000000000000000UL,
 	/* 0x00f0, */ 0x001044110000FFFFUL,
-	/* 0x00f8, */ 0x000C10100000FFFFUL,
+	/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
 	/* 0x0100, */ 0x0000000000000000UL,
 	/* 0x0108, */ 0x0000000000000000UL,
 	/* 0x0110, */ 0x001014110000FFFFUL,
-	/* 0x0118, */ 0x000C302F0000FFFFUL,
-	/* 0x0120, */ 0x000C302F0000FFFFUL,
+	/* 0x0118, */ 0x000C38360000FFFFUL,
+	/* 0x0120, */ 0x000C38360000FFFFUL,
 	/* 0x0128, */ 0x0000000000000000UL,
 	/* 0x0130, */ 0x0000000000000000UL,
 	/* 0x0138, */ 0x001018150000FFFFUL,
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
index e4909b9..71e0396 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
@@ -12,7 +12,8 @@
 #include "../qos_reg.h"
 #include "qos_init_h3n_v30.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.03"
+
+#define	RCAR_QOS_VERSION		"rev.0.06"
 
 #define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
 
@@ -220,14 +221,6 @@
 	io_write_32(AXI_TR3CR, 0x00010000U);
 	io_write_32(AXI_TR4CR, 0x00010000U);
 
-	/* 3DG bus Leaf setting */
-	io_write_32(GPU_ACT_GRD, 0x00001234U);
-	io_write_32(GPU_ACT0, 0x00000000U);
-	io_write_32(GPU_ACT1, 0x00000000U);
-	io_write_32(GPU_ACT2, 0x00000000U);
-	io_write_32(GPU_ACT3, 0x00000000U);
-	io_write_32(GPU_ACT_GRD, 0x00000000U);
-
 	/* RT bus Leaf setting */
 	io_write_32(RT_ACT0, 0x00000000U);
 	io_write_32(RT_ACT1, 0x00000000U);
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
index b73e90b..6dbc88a 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
@@ -36,12 +36,12 @@
 	/* 0x00e0, */ 0x00100C090000FFFFUL,
 	/* 0x00e8, */ 0x0000000000000000UL,
 	/* 0x00f0, */ 0x001024090000FFFFUL,
-	/* 0x00f8, */ 0x000C08080000FFFFUL,
+	/* 0x00f8, */ 0x000C100D0000FFFFUL,
 	/* 0x0100, */ 0x0000000000000000UL,
 	/* 0x0108, */ 0x0000000000000000UL,
 	/* 0x0110, */ 0x00100C090000FFFFUL,
-	/* 0x0118, */ 0x000C18180000FFFFUL,
-	/* 0x0120, */ 0x000C18180000FFFFUL,
+	/* 0x0118, */ 0x000C1C1B0000FFFFUL,
+	/* 0x0120, */ 0x000C1C1B0000FFFFUL,
 	/* 0x0128, */ 0x0000000000000000UL,
 	/* 0x0130, */ 0x0000000000000000UL,
 	/* 0x0138, */ 0x00100C0B0000FFFFUL,
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
index 1b7c383..880211c 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
@@ -36,12 +36,12 @@
 	/* 0x00e0, */ 0x001014110000FFFFUL,
 	/* 0x00e8, */ 0x0000000000000000UL,
 	/* 0x00f0, */ 0x001044110000FFFFUL,
-	/* 0x00f8, */ 0x000C10100000FFFFUL,
+	/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
 	/* 0x0100, */ 0x0000000000000000UL,
 	/* 0x0108, */ 0x0000000000000000UL,
 	/* 0x0110, */ 0x001014110000FFFFUL,
-	/* 0x0118, */ 0x000C302F0000FFFFUL,
-	/* 0x0120, */ 0x000C302F0000FFFFUL,
+	/* 0x0118, */ 0x000C38360000FFFFUL,
+	/* 0x0120, */ 0x000C38360000FFFFUL,
 	/* 0x0128, */ 0x0000000000000000UL,
 	/* 0x0130, */ 0x0000000000000000UL,
 	/* 0x0138, */ 0x001018150000FFFFUL,
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
index 3186cf6..10fa6b4 100644
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
@@ -12,7 +12,8 @@
 #include "../qos_reg.h"
 #include "qos_init_m3_v11.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.17"
+#define	RCAR_QOS_VERSION		"rev.0.18"
+
 
 #define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
 
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
index 0be68c3..52a3ca2 100644
--- a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
@@ -12,7 +12,7 @@
 #include "../qos_reg.h"
 #include "qos_init_m3n_v10.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.06"
+#define	RCAR_QOS_VERSION		"rev.0.08"
 
 #define QOSCTRL_EARLYR			(QOS_BASE1 + 0x0060U)
 #define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
@@ -198,14 +198,6 @@
 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
 	}
 
-	/* 3DG bus Leaf setting */
-	io_write_32(GPU_ACT_GRD, 0x00001234U);
-	io_write_32(GPU_ACT0, 0x00000000U);
-	io_write_32(GPU_ACT1, 0x00000000U);
-	io_write_32(GPU_ACT2, 0x00000000U);
-	io_write_32(GPU_ACT3, 0x00000000U);
-	io_write_32(GPU_ACT_GRD, 0x00000000U);
-
 	/* RT bus Leaf setting */
 	io_write_32(RT_ACT0, 0x00000000U);
 	io_write_32(RT_ACT1, 0x00000000U);
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
index d30e95f..9b8b9e9 100644
--- a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
@@ -27,11 +27,11 @@
 	/* 0x0098, */ 0x0000000000000000UL,
 	/* 0x00a0, */ 0x000C041D0000FFFFUL,
 	/* 0x00a8, */ 0x000C04090000FFFFUL,
-	/* 0x00b0, */ 0x000C04090000FFFFUL,
+	/* 0x00b0, */ 0x000C040B0000FFFFUL,
 	/* 0x00b8, */ 0x0000000000000000UL,
 	/* 0x00c0, */ 0x000C041D0000FFFFUL,
 	/* 0x00c8, */ 0x000C04090000FFFFUL,
-	/* 0x00d0, */ 0x000C04090000FFFFUL,
+	/* 0x00d0, */ 0x000C040B0000FFFFUL,
 	/* 0x00d8, */ 0x0000000000000000UL,
 	/* 0x00e0, */ 0x0000000000000000UL,
 	/* 0x00e8, */ 0x0000000000000000UL,
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
index 0dc37ca..19143ed 100644
--- a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
@@ -27,11 +27,11 @@
 	/* 0x0098, */ 0x0000000000000000UL,
 	/* 0x00a0, */ 0x000C08390000FFFFUL,
 	/* 0x00a8, */ 0x000C04110000FFFFUL,
-	/* 0x00b0, */ 0x000C04110000FFFFUL,
+	/* 0x00b0, */ 0x000C04150000FFFFUL,
 	/* 0x00b8, */ 0x0000000000000000UL,
 	/* 0x00c0, */ 0x000C08390000FFFFUL,
 	/* 0x00c8, */ 0x000C04110000FFFFUL,
-	/* 0x00d0, */ 0x000C04110000FFFFUL,
+	/* 0x00d0, */ 0x000C04150000FFFFUL,
 	/* 0x00d8, */ 0x0000000000000000UL,
 	/* 0x00e0, */ 0x0000000000000000UL,
 	/* 0x00e8, */ 0x0000000000000000UL,
diff --git a/drivers/staging/renesas/rcar/qos/qos_common.h b/drivers/staging/renesas/rcar/qos/qos_common.h
index 0174d5b..9bad424 100644
--- a/drivers/staging/renesas/rcar/qos/qos_common.h
+++ b/drivers/staging/renesas/rcar/qos/qos_common.h
@@ -9,6 +9,15 @@
 
 #define RCAR_REF_DEFAULT		(0U)
 
+/* define used for get_refperiod. */
+/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
+/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF default */
+#define REFPERIOD_CYCLE		((126 * BASE_SUB_SLOT_NUM * 1000U)/400)	/* unit:ns */
+#else					/* REF option */
+#define REFPERIOD_CYCLE		((252 * BASE_SUB_SLOT_NUM * 1000U)/400)	/* unit:ns */
+#endif
+
 #if (RCAR_LSI == RCAR_E3)
 /* define used for E3 */
 #if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 3.9usec */
@@ -19,7 +28,7 @@
 
 #define OPERATING_FREQ_E3		(266U)	/* MHz */
 #define SL_INIT_SSLOTCLK_E3		(SUB_SLOT_CYCLE_E3 -1U)
-#define QOSWT_WTSET0_CYCLE_E3		((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3)	/* unit:ns */
+/* #define QOSWT_WTSET0_CYCLE_E3		((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */	/* unit:ns */
 #endif
 
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
diff --git a/drivers/staging/renesas/rcar/qos/qos_init.c b/drivers/staging/renesas/rcar/qos/qos_init.c
index 1d1bcd5..be4487a 100644
--- a/drivers/staging/renesas/rcar/qos/qos_init.c
+++ b/drivers/staging/renesas/rcar/qos/qos_init.c
@@ -238,6 +238,7 @@
 #endif
 }
 
+#if !(RCAR_LSI == RCAR_E3)
 uint32_t get_refperiod(void)
 {
 	uint32_t refperiod = QOSWT_WTSET0_CYCLE;
@@ -254,11 +255,9 @@
 		case PRR_PRODUCT_11:
 			break;
 		case PRR_PRODUCT_20:
-			refperiod = QOSWT_WTSET0_CYCLE_H3_20;
-			break;
 		case PRR_PRODUCT_30:
 		default:
-			refperiod = QOSWT_WTSET0_CYCLE_H3_30;
+			refperiod = REFPERIOD_CYCLE;
 			break;
 		}
 		break;
@@ -267,7 +266,7 @@
 		switch (reg & PRR_CUT_MASK) {
 		case PRR_PRODUCT_30:
 		default:
-			refperiod = QOSWT_WTSET0_CYCLE_H3N;
+			refperiod = REFPERIOD_CYCLE;
 			break;
 		}
 		break;
@@ -277,21 +276,16 @@
 		switch (reg & PRR_CUT_MASK) {
 		case PRR_PRODUCT_10:
 			break;
-		case PRR_PRODUCT_20:	/* M3 Cut 11 */
+		case PRR_PRODUCT_20: /* M3 Cut 11 */
 		default:
-			refperiod = QOSWT_WTSET0_CYCLE_M3_11;
+			refperiod = REFPERIOD_CYCLE;
 			break;
 		}
 		break;
 #endif
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
 	case PRR_PRODUCT_M3N:
-		refperiod = QOSWT_WTSET0_CYCLE_M3N;
-		break;
-#endif
-#if (RCAR_LSI == RCAR_E3)
-	case PRR_PRODUCT_E3:
-		refperiod = QOSWT_WTSET0_CYCLE_E3;
+		refperiod = REFPERIOD_CYCLE;
 		break;
 #endif
 	default:
@@ -302,28 +296,25 @@
 	/* H3 Cut 10 */
 #elif RCAR_LSI_CUT == RCAR_CUT_11
 	/* H3 Cut 11 */
-#elif RCAR_LSI_CUT == RCAR_CUT_20
-	/* H3 Cut 20 */
-	refperiod = QOSWT_WTSET0_CYCLE_H3_20;
 #else
+	/* H3 Cut 20 */
 	/* H3 Cut 30 or later */
-	refperiod = QOSWT_WTSET0_CYCLE_H3_30;
+	refperiod = REFPERIOD_CYCLE;
 #endif
 #elif RCAR_LSI == RCAR_H3N
 	/* H3N Cut 30 or later */
-	refperiod = QOSWT_WTSET0_CYCLE_H3N;
+	refperiod = REFPERIOD_CYCLE;
 #elif RCAR_LSI == RCAR_M3
 #if RCAR_LSI_CUT == RCAR_CUT_10
 	/* M3 Cut 10 */
 #else
 	/* M3 Cut 11 or later */
-	refperiod = QOSWT_WTSET0_CYCLE_M3_11;
+	refperiod = REFPERIOD_CYCLE;
 #endif
 #elif RCAR_LSI == RCAR_M3N	/* for M3N */
-	refperiod = QOSWT_WTSET0_CYCLE_M3N;
-#elif RCAR_LSI == RCAR_E3	/* for E3 */
-	refperiod = QOSWT_WTSET0_CYCLE_E3;
+	refperiod = REFPERIOD_CYCLE;
 #endif
 
 	return refperiod;
 }
+#endif
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index cbe272c..4af3e90 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -94,12 +94,16 @@
 /* CSSELR definitions */
 #define LEVEL_SHIFT		U(1)
 
-/* ID_PFR0 AMU definitions */
+/* ID_MMFR4 definitions */
+#define ID_MMFR4_CNP_SHIFT	U(12)
+#define ID_MMFR4_CNP_LENGTH	U(4)
+#define ID_MMFR4_CNP_MASK	U(0xf)
+
+/* ID_PFR0 definitions */
 #define ID_PFR0_AMU_SHIFT	U(20)
 #define ID_PFR0_AMU_LENGTH	U(4)
 #define ID_PFR0_AMU_MASK	U(0xf)
 
-/* ID_PFR0 DIT definitions */
 #define ID_PFR0_DIT_SHIFT	U(24)
 #define ID_PFR0_DIT_LENGTH	U(4)
 #define ID_PFR0_DIT_MASK	U(0xf)
@@ -475,6 +479,7 @@
 #define DCISW		p15, 0, c7, c6, 2
 #define CTR		p15, 0, c0, c0, 1
 #define CNTFRQ		p15, 0, c14, c0, 0
+#define ID_MMFR4	p15, 0, c0, c2, 6
 #define ID_PFR0		p15, 0, c0, c1, 0
 #define ID_PFR1		p15, 0, c0, c1, 1
 #define MAIR0		p15, 0, c10, c2, 0
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
new file mode 100644
index 0000000..d934102
--- /dev/null
+++ b/include/arch/aarch32/arch_features.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARCH_FEATURES_H
+#define ARCH_FEATURES_H
+
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+
+static inline bool is_armv8_2_ttcnp_present(void)
+{
+	return ((read_id_mmfr4() >> ID_MMFR4_CNP_SHIFT) &
+		ID_MMFR4_CNP_MASK) != 0U;
+}
+
+#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index c2773c1..64ddc86 100644
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -214,6 +214,7 @@
  ******************************************************************************/
 DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
 DEFINE_COPROCR_READ_FUNC(midr, MIDR)
+DEFINE_COPROCR_READ_FUNC(id_mmfr4, ID_MMFR4)
 DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0)
 DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
 DEFINE_COPROCR_READ_FUNC(isr, ISR)
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 8a44d83..9e2bffa 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -156,10 +156,6 @@
 #define ID_AA64PFR0_GIC_WIDTH	U(4)
 #define ID_AA64PFR0_GIC_MASK	((ULL(1) << ID_AA64PFR0_GIC_WIDTH) - ULL(1))
 
-/* ID_AA64MMFR0_EL1 definitions */
-#define ID_AA64MMFR0_EL1_PARANGE_SHIFT	U(0)
-#define ID_AA64MMFR0_EL1_PARANGE_MASK	ULL(0xf)
-
 /* ID_AA64ISAR1_EL1 definitions */
 #define ID_AA64ISAR1_GPI_SHIFT	U(28)
 #define ID_AA64ISAR1_GPI_WIDTH	U(4)
@@ -179,6 +175,10 @@
 #define ID_AA64ISAR1_APA_MASK \
 	(((ULL(1) << ID_AA64ISAR1_APA_WIDTH) - ULL(1)) << ID_AA64ISAR1_APA_SHIFT)
 
+/* ID_AA64MMFR0_EL1 definitions */
+#define ID_AA64MMFR0_EL1_PARANGE_SHIFT	U(0)
+#define ID_AA64MMFR0_EL1_PARANGE_MASK	ULL(0xf)
+
 #define PARANGE_0000	U(32)
 #define PARANGE_0001	U(36)
 #define PARANGE_0010	U(40)
@@ -202,6 +202,11 @@
 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED	ULL(0x1)
 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED	ULL(0x0)
 
+/* ID_AA64MMFR2_EL1 definitions */
+#define ID_AA64MMFR2_EL1		S3_0_C0_C7_2
+#define ID_AA64MMFR2_EL1_CNP_SHIFT	U(0)
+#define ID_AA64MMFR2_EL1_CNP_MASK	ULL(0xf)
+
 /* ID_AA64PFR1_EL1 definitions */
 #define ID_AA64PFR1_EL1_SSBS_SHIFT	U(4)
 #define ID_AA64PFR1_EL1_SSBS_MASK	ULL(0xf)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
new file mode 100644
index 0000000..2b09ba0
--- /dev/null
+++ b/include/arch/aarch64/arch_features.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARCH_FEATURES_H
+#define ARCH_FEATURES_H
+
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+
+static inline bool is_armv8_2_ttcnp_present(void)
+{
+	return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
+		ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
+}
+
+#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index b912b42..d3f0df7 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -449,6 +449,9 @@
 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
 
+/* Armv8.2 Registers */
+DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
+
 /* Armv8.3 Pointer Authentication Registers */
 DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1)
 
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index c12b08b..f7b3b9c 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -78,7 +78,12 @@
 IMPORT_SYM(unsigned long, __RO_END__,		BL_CODE_END);
 #endif
 
-#if defined(IMAGE_BL2)
+#if defined(IMAGE_BL1)
+IMPORT_SYM(uintptr_t, __BL1_ROM_END__,   BL1_ROM_END);
+
+IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE);
+IMPORT_SYM(uintptr_t, __BL1_RAM_END__,   BL1_RAM_LIMIT);
+#elif defined(IMAGE_BL2)
 IMPORT_SYM(unsigned long, __BL2_END__,		BL2_END);
 #elif defined(IMAGE_BL2U)
 IMPORT_SYM(unsigned long, __BL2U_END__,		BL2U_END);
@@ -89,6 +94,17 @@
 IMPORT_SYM(unsigned long, __BL32_END__,		BL32_END);
 #endif /* IMAGE_BLX */
 
+/* The following symbols are only exported from the BL2 at EL3 linker script. */
+#if BL2_IN_XIP_MEM && defined(IMAGE_BL2)
+extern uintptr_t __BL2_ROM_END__;
+#define BL2_ROM_END (uintptr_t)(&__BL2_ROM_END__)
+
+extern uintptr_t __BL2_RAM_START__;
+extern uintptr_t __BL2_RAM_END__;
+#define BL2_RAM_BASE (uintptr_t)(&__BL2_RAM_START__)
+#define BL2_RAM_LIMIT (uintptr_t)(&__BL2_RAM_END__)
+#endif /* BL2_IN_XIP_MEM */
+
 /*
  * The next 2 constants identify the extents of the coherent memory region.
  * These addresses are used by the MMU setup code and therefore they must be
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 4e9c70a..e27dd80 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -6,8 +6,6 @@
 #ifndef ARM_DEF_H
 #define ARM_DEF_H
 
-#include <platform_def.h>
-
 #include <arch.h>
 #include <common/interrupt_props.h>
 #include <common/tbbr/tbbr_img_def.h>
diff --git a/include/plat/arm/common/arm_spm_def.h b/include/plat/arm/common/arm_spm_def.h
index c17b565..997e156 100644
--- a/include/plat/arm/common/arm_spm_def.h
+++ b/include/plat/arm/common/arm_spm_def.h
@@ -9,8 +9,6 @@
 #include <lib/utils_def.h>
 #include <lib/xlat_tables/xlat_tables_defs.h>
 
-#include <arm_def.h>
-
 /*
  * Reserve 4 MiB for binaries of Secure Partitions and Resource Description
  * blobs.
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index 6b355a4..575db04 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -11,8 +11,6 @@
 #include <drivers/arm/gic_common.h>
 #include <drivers/arm/tzc400.h>
 
-#include <arm_def.h>
-
 /*************************************************************************
  * Definitions common to all ARM Compute SubSystems (CSS)
  *************************************************************************/
diff --git a/lib/aarch32/arm32_aeabi_divmod.c b/lib/aarch32/arm32_aeabi_divmod.c
index a8f2e74..0b36cb6 100644
--- a/lib/aarch32/arm32_aeabi_divmod.c
+++ b/lib/aarch32/arm32_aeabi_divmod.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,12 +18,12 @@
  *     unsigned denominator);
  */
 
-/* struct qr - stores qutient/remainder to handle divmod EABI interfaces. */
+/* struct qr - stores quotient/remainder to handle divmod EABI interfaces. */
 struct qr {
 	unsigned int q;		/* computed quotient */
 	unsigned int r;		/* computed remainder */
-	unsigned int q_n;	/* specficies if quotient shall be negative */
-	unsigned int r_n;	/* specficies if remainder shall be negative */
+	unsigned int q_n;	/* specifies if quotient shall be negative */
+	unsigned int r_n;	/* specifies if remainder shall be negative */
 };
 
 static void uint_div_qr(unsigned int numerator, unsigned int denominator,
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 8a5764c..b956491 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -55,7 +55,7 @@
  * The security state to initialize is determined by the SECURE attribute
  * of the entry_point_info.
  *
- * The EE and ST attributes are used to configure the endianess and secure
+ * The EE and ST attributes are used to configure the endianness and secure
  * timer availability for the new execution context.
  *
  * To prepare the register state for entry call cm_prepare_el3_exit() and
@@ -124,7 +124,7 @@
 
 #ifdef IMAGE_BL31
 	/*
-	 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as
+	 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
 	 *  indicated by the interrupt routing model for BL31.
 	 */
 	scr_el3 |= get_scr_el3_from_routing_model(security_state);
@@ -175,7 +175,7 @@
 
 	/*
 	 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
-	 * and other EL2 registers are set up by cm_preapre_ns_entry() as they
+	 * and other EL2 registers are set up by cm_prepare_ns_entry() as they
 	 * are not part of the stored cpu_context.
 	 */
 	write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
@@ -350,7 +350,7 @@
 					| CPTR_EL2_TFP_BIT));
 
 			/*
-			 * Initiliase CNTHCTL_EL2. All fields are
+			 * Initialise CNTHCTL_EL2. All fields are
 			 * architecturally UNKNOWN on reset and are set to zero
 			 * except for field(s) listed below.
 			 *
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index 349b6c4..913c86d 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 #include <platform_def.h>
 
 #include <arch.h>
+#include <arch_features.h>
 #include <arch_helpers.h>
 #include <lib/cassert.h>
 #include <lib/utils_def.h>
@@ -219,13 +220,10 @@
 	/* Set TTBR0 bits as well */
 	ttbr0 = (uint64_t)(uintptr_t) base_table;
 
-#if ARM_ARCH_AT_LEAST(8, 2)
-	/*
-	 * Enable CnP bit so as to share page tables with all PEs. This
-	 * is mandatory for ARMv8.2 implementations.
-	 */
-	ttbr0 |= TTBR_CNP_BIT;
-#endif
+	if (is_armv8_2_ttcnp_present()) {
+		/* Enable CnP bit so as to share page tables with all PEs. */
+		ttbr0 |= TTBR_CNP_BIT;
+	}
 
 	/* Now populate MMU configuration */
 	params[MMU_CFG_MAIR] = mair;
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index a803d83..228f751 100644
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 #include <stdint.h>
 
 #include <arch.h>
+#include <arch_features.h>
 #include <arch_helpers.h>
 #include <lib/cassert.h>
 #include <lib/utils_def.h>
@@ -266,13 +267,10 @@
 	/* Set TTBR bits as well */
 	ttbr0 = (uint64_t) base_table;
 
-#if ARM_ARCH_AT_LEAST(8, 2)
-	/*
-	 * Enable CnP bit so as to share page tables with all PEs. This
-	 * is mandatory for ARMv8.2 implementations.
-	 */
-	ttbr0 |= TTBR_CNP_BIT;
-#endif
+	if (is_armv8_2_ttcnp_present()) {
+		/* Enable CnP bit so as to share page tables with all PEs. */
+		ttbr0 |= TTBR_CNP_BIT;
+	}
 
 	params[MMU_CFG_MAIR] = mair;
 	params[MMU_CFG_TCR] = tcr;
diff --git a/maintainers.rst b/maintainers.rst
index 37766ed..f53dda5 100644
--- a/maintainers.rst
+++ b/maintainers.rst
@@ -144,6 +144,13 @@
 :F: docs/plat/imx8.rst
 :F: plat/imx/
 
+NXP i.MX8M platform port
+------------------------
+:M: Jacky Bai <ping.bai@nxp.com>
+:G: `JackyBai`_
+:F: doc/plat/imx8m.rst
+:F: plat/imx/imx8m/
+
 OP-TEE dispatcher
 -----------------
 :M: Jens Wiklander <jens.wiklander@linaro.org>
@@ -241,6 +248,7 @@
 .. _etienne-lms: https://github.com/etienne-lms
 .. _glneo: https://github.com/glneo
 .. _hzhuang1: https://github.com/hzhuang1
+.. _JackyBai: https://github.com/JackyBai
 .. _jenswi-linaro: https://github.com/jenswi-linaro
 .. _ldts: https://github.com/ldts
 .. _niej: https://github.com/niej
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index d60a5bf..961cabf 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -216,10 +216,11 @@
 $(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
 $(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
 $(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
+$(eval BL_CFLAGS := $(BL$(call uppercase,$(3))_CFLAGS))
 
 $(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
 	$$(ECHO) "  CC      $$<"
-	$$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@
+	$$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@
 
 -include $(DEP)
 
diff --git a/plat/arm/board/common/aarch32/board_arm_helpers.S b/plat/arm/board/common/aarch32/board_arm_helpers.S
index 320bfb3..8c63693 100644
--- a/plat/arm/board/common/aarch32/board_arm_helpers.S
+++ b/plat/arm/board/common/aarch32/board_arm_helpers.S
@@ -6,7 +6,7 @@
 
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <v2m_def.h>
+#include <platform_def.h>
 
 	.globl  plat_report_exception
 
diff --git a/plat/arm/board/common/aarch64/board_arm_helpers.S b/plat/arm/board/common/aarch64/board_arm_helpers.S
index 5a90524..cde6b00 100644
--- a/plat/arm/board/common/aarch64/board_arm_helpers.S
+++ b/plat/arm/board/common/aarch64/board_arm_helpers.S
@@ -6,7 +6,7 @@
 
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <v2m_def.h>
+#include <platform_def.h>
 
 	.globl  plat_report_exception
 
diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c
index 64ca3c3..e3c6805 100644
--- a/plat/arm/board/common/board_arm_trusted_boot.c
+++ b/plat/arm/board/common/board_arm_trusted_boot.c
@@ -11,8 +11,7 @@
 #include <lib/cassert.h>
 #include <plat/common/platform.h>
 #include <tools_share/tbbr_oid.h>
-
-#include <arm_def.h>
+#include <platform_def.h>
 
 /* SHA256 algorithm */
 #define SHA256_BYTES			32
diff --git a/plat/arm/board/fvp/aarch32/fvp_helpers.S b/plat/arm/board/fvp/aarch32/fvp_helpers.S
index 5d88546..f689557 100644
--- a/plat/arm/board/fvp/aarch32/fvp_helpers.S
+++ b/plat/arm/board/fvp/aarch32/fvp_helpers.S
@@ -7,8 +7,8 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <platform_def.h>
+
 #include "../drivers/pwrc/fvp_pwrc.h"
-#include "../fvp_def.h"
 
 	.globl	plat_secondary_cold_boot_setup
 	.globl	plat_get_my_entrypoint
diff --git a/plat/arm/board/fvp/aarch64/fvp_helpers.S b/plat/arm/board/fvp/aarch64/fvp_helpers.S
index 0f90515..02a3c7c 100644
--- a/plat/arm/board/fvp/aarch64/fvp_helpers.S
+++ b/plat/arm/board/fvp/aarch64/fvp_helpers.S
@@ -9,9 +9,8 @@
 #include <drivers/arm/gicv2.h>
 #include <drivers/arm/gicv3.h>
 #include <platform_def.h>
-#include <v2m_def.h>
+
 #include "../drivers/pwrc/fvp_pwrc.h"
-#include "../fvp_def.h"
 
 	.globl	plat_secondary_cold_boot_setup
 	.globl	plat_get_my_entrypoint
diff --git a/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
index c48bb07..cae9827 100644
--- a/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
+++ b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
@@ -6,10 +6,9 @@
 
 #include <lib/bakery_lock.h>
 #include <lib/mmio.h>
+#include <platform_def.h>
 
 #include <plat_arm.h>
-
-#include "../../fvp_def.h"
 #include "../../fvp_private.h"
 #include "fvp_pwrc.h"
 
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index 13e74fd..7aa620b 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -8,10 +8,9 @@
 #include <drivers/generic_delay_timer.h>
 #include <lib/mmio.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
 #include <plat_arm.h>
-#include <v2m_def.h>
-#include "fvp_def.h"
 #include "fvp_private.h"
 
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
diff --git a/plat/arm/board/fvp/fvp_bl2u_setup.c b/plat/arm/board/fvp/fvp_bl2u_setup.c
index c51e287..6367be6 100644
--- a/plat/arm/board/fvp/fvp_bl2u_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2u_setup.c
@@ -5,9 +5,9 @@
  */
 
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
 #include <plat_arm.h>
-#include "fvp_def.h"
 #include "fvp_private.h"
 
 void bl2u_early_platform_setup(struct meminfo *mem_layout, void *plat_info)
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index fa5539d..4da807a 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -13,15 +13,12 @@
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_compat.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 #include <services/secure_partition.h>
 
 #include <arm_config.h>
-#include <arm_def.h>
-#include <arm_spm_def.h>
 #include <plat_arm.h>
-#include <v2m_def.h>
 
-#include "../fvp_def.h"
 #include "fvp_private.h"
 
 /* Defines for GIC Driver build time selection */
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index 7da246b..8ba8281 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -14,14 +14,13 @@
 #include <lib/mmio.h>
 #include <lib/psci/psci.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
 #include <arm_config.h>
 #include <plat_arm.h>
-#include <v2m_def.h>
 
 #include "../../../../drivers/arm/gic/v3/gicv3_private.h"
 #include "drivers/pwrc/fvp_pwrc.h"
-#include "fvp_def.h"
 #include "fvp_private.h"
 
 
diff --git a/plat/arm/board/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_trusted_boot.c
index c18bfb2..0d160cb 100644
--- a/plat/arm/board/fvp/fvp_trusted_boot.c
+++ b/plat/arm/board/fvp/fvp_trusted_boot.c
@@ -9,10 +9,9 @@
 #include <string.h>
 
 #include <plat/common/platform.h>
+#include <platform_def.h>
 #include <tools_share/tbbr_oid.h>
 
-#include "fvp_def.h"
-
 /*
  * Store a new non-volatile counter value. On some FVP versions, the
  * non-volatile counters are RO. On these versions we expect the values in the
diff --git a/plat/arm/board/fvp/include/plat_macros.S b/plat/arm/board/fvp/include/plat_macros.S
index 6be8b09..57f5924 100644
--- a/plat/arm/board/fvp/include/plat_macros.S
+++ b/plat/arm/board/fvp/include/plat_macros.S
@@ -7,8 +7,7 @@
 #define PLAT_MACROS_S
 
 #include <arm_macros.S>
-#include <v2m_def.h>
-#include "../fvp_def.h"
+#include <platform_def.h>
 
 	/* ---------------------------------------------
 	 * The below required platform porting macro
diff --git a/plat/arm/board/juno/aarch32/juno_helpers.S b/plat/arm/board/juno/aarch32/juno_helpers.S
index 080a8dd..8f9561c 100644
--- a/plat/arm/board/juno/aarch32/juno_helpers.S
+++ b/plat/arm/board/juno/aarch32/juno_helpers.S
@@ -11,9 +11,7 @@
 #include <cortex_a57.h>
 #include <cortex_a72.h>
 #include <cpu_macros.S>
-#include <v2m_def.h>
-#include "../juno_def.h"
-
+#include <platform_def.h>
 
 	.globl	plat_reset_handler
 	.globl	plat_arm_calc_core_pos
diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S
index 373f2fc..c94fa3e 100644
--- a/plat/arm/board/juno/aarch64/juno_helpers.S
+++ b/plat/arm/board/juno/aarch64/juno_helpers.S
@@ -11,10 +11,7 @@
 #include <cortex_a57.h>
 #include <cortex_a72.h>
 #include <cpu_macros.S>
-#include <css_def.h>
-#include <v2m_def.h>
-#include "../juno_def.h"
-
+#include <platform_def.h>
 
 	.globl	plat_reset_handler
 	.globl	plat_arm_calc_core_pos
diff --git a/plat/arm/board/juno/juno_bl1_setup.c b/plat/arm/board/juno/juno_bl1_setup.c
index e751ab6..383409d 100644
--- a/plat/arm/board/juno/juno_bl1_setup.c
+++ b/plat/arm/board/juno/juno_bl1_setup.c
@@ -11,10 +11,10 @@
 #include <common/tbbr/tbbr_img_def.h>
 #include <drivers/arm/sp805.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
 #include <plat_arm.h>
 #include <sds.h>
-#include <v2m_def.h>
 
 void juno_reset_to_aarch32_state(void);
 
diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c
index 2e6b011..e134108 100644
--- a/plat/arm/board/juno/juno_common.c
+++ b/plat/arm/board/juno/juno_common.c
@@ -3,7 +3,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#include <arm_def.h>
+
+#include <platform_def.h>
 #include <plat_arm.h>
 
 /*
diff --git a/plat/arm/board/juno/juno_err.c b/plat/arm/board/juno/juno_err.c
index 69daa1a..f80ff24 100644
--- a/plat/arm/board/juno/juno_err.c
+++ b/plat/arm/board/juno/juno_err.c
@@ -8,8 +8,7 @@
 
 #include <arch_helpers.h>
 #include <plat/common/platform.h>
-
-#include <v2m_def.h>
+#include <platform_def.h>
 
 /*
  * Juno error handler
diff --git a/plat/arm/board/juno/juno_pm.c b/plat/arm/board/juno/juno_pm.c
index da2e92b..dbf7b6c 100644
--- a/plat/arm/board/juno/juno_pm.c
+++ b/plat/arm/board/juno/juno_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,5 +9,9 @@
 
 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
 {
+#if CSS_USE_SCMI_SDS_DRIVER
 	return css_scmi_override_pm_ops(ops);
+#else
+	return ops;
+#endif /* CSS_USE_SCMI_SDS_DRIVER */
 }
diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c
index b0df837..51c8669 100644
--- a/plat/arm/board/juno/juno_security.c
+++ b/plat/arm/board/juno/juno_security.c
@@ -7,10 +7,10 @@
 #include <common/debug.h>
 #include <drivers/arm/nic_400.h>
 #include <lib/mmio.h>
+#include <platform_def.h>
 
 #include <plat_arm.h>
 #include <soc_css.h>
-#include "juno_def.h"
 #include "juno_tzmp1_def.h"
 
 #ifdef JUNO_TZMP1
diff --git a/plat/arm/board/juno/juno_stack_protector.c b/plat/arm/board/juno/juno_stack_protector.c
index ff05b5d..236eb5b 100644
--- a/plat/arm/board/juno/juno_stack_protector.c
+++ b/plat/arm/board/juno/juno_stack_protector.c
@@ -7,9 +7,9 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <lib/utils.h>
+#include <platform_def.h>
 
 #include "juno_decl.h"
-#include "juno_def.h"
 
 u_register_t plat_get_stack_protector_canary(void)
 {
diff --git a/plat/arm/board/juno/juno_topology.c b/plat/arm/board/juno/juno_topology.c
index 51b99ac..e70cbdc 100644
--- a/plat/arm/board/juno/juno_topology.c
+++ b/plat/arm/board/juno/juno_topology.c
@@ -5,11 +5,10 @@
  */
 
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
-#include <arm_def.h>
 #include <css_pm.h>
 #include <plat_arm.h>
-#include "juno_def.h"
 #include "../../css/drivers/scmi/scmi.h"
 #include "../../css/drivers/mhu/css_mhu_doorbell.h"
 
diff --git a/plat/arm/board/juno/juno_trng.c b/plat/arm/board/juno/juno_trng.c
index 505fb02..7869d3e 100644
--- a/plat/arm/board/juno/juno_trng.c
+++ b/plat/arm/board/juno/juno_trng.c
@@ -9,9 +9,9 @@
 
 #include <lib/mmio.h>
 #include <lib/utils_def.h>
+#include <platform_def.h>
 
 #include "juno_decl.h"
-#include "juno_def.h"
 
 #define NSAMPLE_CLOCKS	1 /* min 1 cycle, max 231 cycles */
 #define NRETRIES	5
diff --git a/plat/arm/board/juno/juno_tzmp1_def.h b/plat/arm/board/juno/juno_tzmp1_def.h
index 5d0978c..4186d02 100644
--- a/plat/arm/board/juno/juno_tzmp1_def.h
+++ b/plat/arm/board/juno/juno_tzmp1_def.h
@@ -7,8 +7,6 @@
 #ifndef JUNO_TZMP1_DEF_H
 #define JUNO_TZMP1_DEF_H
 
-#include <plat_arm.h>
-
 /*
  * Public memory regions for both protected and non-protected mode
  *
diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
index 1556ac7..68d0f93 100644
--- a/plat/arm/board/n1sdp/include/platform_def.h
+++ b/plat/arm/board/n1sdp/include/platform_def.h
@@ -9,6 +9,7 @@
 
 #include <arm_def.h>
 #include <css_def.h>
+#include <v2m_def.h>
 
 /* UART related constants */
 #define PLAT_ARM_BOOT_UART_BASE			0x2A400000
diff --git a/plat/arm/board/n1sdp/n1sdp_plat.c b/plat/arm/board/n1sdp/n1sdp_plat.c
index 3bf1fe6..87e1511 100644
--- a/plat/arm/board/n1sdp/n1sdp_plat.c
+++ b/plat/arm/board/n1sdp/n1sdp_plat.c
@@ -10,7 +10,6 @@
 #include <common/debug.h>
 #include <plat/common/platform.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 /*
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index e28211c..3a8b5c2 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -16,11 +16,8 @@
 #include <lib/xlat_tables/xlat_tables_compat.h>
 #include <plat/common/platform.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
-#include "../../../bl1/bl1_private.h"
-
 /* Weak definitions may be overridden in specific ARM standard platform */
 #pragma weak bl1_early_platform_setup
 #pragma weak bl1_plat_arch_setup
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c
index 0c1f63e..c38f2ec 100644
--- a/plat/arm/common/arm_bl2_el3_setup.c
+++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -8,8 +8,8 @@
 
 #include <drivers/generic_delay_timer.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 #pragma weak bl2_el3_early_platform_setup
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 9319004..b661eb1 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -20,7 +20,6 @@
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 /* Data structure which holds the extents of the trusted SRAM for BL2 */
diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c
index 0dc66e6..332ed14 100644
--- a/plat/arm/common/arm_bl2u_setup.c
+++ b/plat/arm/common/arm_bl2u_setup.c
@@ -14,7 +14,6 @@
 #include <drivers/generic_delay_timer.h>
 #include <plat/common/platform.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 /* Weak definitions may be overridden in specific ARM standard platform */
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 41151c2..dacefc4 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -16,8 +16,8 @@
 #include <lib/utils.h>
 #include <lib/xlat_tables/xlat_tables_compat.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 /*
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index 0f6690a..e16e13d 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,7 +11,6 @@
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 /******************************************************************************
@@ -152,7 +151,7 @@
 	 * If an ITS is available, save its context before
 	 * the Redistributor using:
 	 * gicv3_its_save_disable(gits_base, &its_ctx[i])
-	 * Additionnaly, an implementation-defined sequence may
+	 * Additionally, an implementation-defined sequence may
 	 * be required to save the whole ITS state.
 	 */
 
diff --git a/plat/arm/common/arm_image_load.c b/plat/arm/common/arm_image_load.c
index 791f05e..bf1fbfd 100644
--- a/plat/arm/common/arm_image_load.c
+++ b/plat/arm/common/arm_image_load.c
@@ -8,7 +8,6 @@
 #include <common/desc_image_load.h>
 #include <plat/common/platform.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 #pragma weak plat_flush_next_bl_params
diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
index acfd908..4ce13aa 100644
--- a/plat/arm/common/arm_pm.c
+++ b/plat/arm/common/arm_pm.c
@@ -13,7 +13,6 @@
 #include <lib/psci/psci.h>
 #include <plat/common/platform.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 /* Allow ARM Standard platforms to override these functions */
diff --git a/plat/arm/common/arm_tzc400.c b/plat/arm/common/arm_tzc400.c
index 0346fa1..322713b 100644
--- a/plat/arm/common/arm_tzc400.c
+++ b/plat/arm/common/arm_tzc400.c
@@ -9,8 +9,6 @@
 #include <common/debug.h>
 #include <drivers/arm/tzc400.h>
 
-#include <arm_def.h>
-#include <arm_spm_def.h>
 #include <plat_arm.h>
 
 /* Weak definitions may be overridden in specific ARM standard platform */
diff --git a/plat/arm/common/arm_tzc_dmc500.c b/plat/arm/common/arm_tzc_dmc500.c
index bea3867..07260a7 100644
--- a/plat/arm/common/arm_tzc_dmc500.c
+++ b/plat/arm/common/arm_tzc_dmc500.c
@@ -11,7 +11,6 @@
 #include <common/debug.h>
 #include <drivers/arm/tzc_dmc500.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 /*******************************************************************************
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index a3d2f71..2937697 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,7 +14,6 @@
 #include <drivers/arm/pl011.h>
 #include <drivers/console.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 
 #define BL32_END (unsigned long)(&__BL32_END__)
@@ -78,7 +77,7 @@
 void tsp_plat_arch_setup(void)
 {
 #if USE_COHERENT_MEM
-	/* Ensure ARM platforms dont use coherent memory in TSP */
+	/* Ensure ARM platforms don't use coherent memory in TSP */
 	assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
 #endif
 
diff --git a/plat/arm/css/common/aarch32/css_helpers.S b/plat/arm/css/common/aarch32/css_helpers.S
index 80aa24c..d47e13d 100644
--- a/plat/arm/css/common/aarch32/css_helpers.S
+++ b/plat/arm/css/common/aarch32/css_helpers.S
@@ -3,10 +3,11 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #include <arch.h>
 #include <asm_macros.S>
 #include <cpu_macros.S>
-#include <css_def.h>
+#include <platform_def.h>
 
 	.weak	plat_secondary_cold_boot_setup
 	.weak	plat_get_my_entrypoint
diff --git a/plat/arm/css/common/aarch64/css_helpers.S b/plat/arm/css/common/aarch64/css_helpers.S
index 5096d8d..01669be 100644
--- a/plat/arm/css/common/aarch64/css_helpers.S
+++ b/plat/arm/css/common/aarch64/css_helpers.S
@@ -3,10 +3,11 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #include <arch.h>
 #include <asm_macros.S>
 #include <cpu_macros.S>
-#include <css_def.h>
+#include <platform_def.h>
 
 	.weak	plat_secondary_cold_boot_setup
 	.weak	plat_get_my_entrypoint
diff --git a/plat/arm/css/common/css_bl2_setup.c b/plat/arm/css/common/css_bl2_setup.c
index c1c7868..6aefe03 100644
--- a/plat/arm/css/common/css_bl2_setup.c
+++ b/plat/arm/css/common/css_bl2_setup.c
@@ -10,8 +10,8 @@
 #include <common/debug.h>
 #include <lib/mmio.h>
 #include <lib/utils.h>
+#include <platform_def.h>
 
-#include <css_def.h>
 #include <plat_arm.h>
 
 #include "../drivers/scp/css_scp.h"
diff --git a/plat/arm/css/drivers/mhu/css_mhu.c b/plat/arm/css/drivers/mhu/css_mhu.c
index e13818f..981df9c 100644
--- a/plat/arm/css/drivers/mhu/css_mhu.c
+++ b/plat/arm/css/drivers/mhu/css_mhu.c
@@ -12,7 +12,6 @@
 #include <lib/bakery_lock.h>
 #include <lib/mmio.h>
 
-#include <css_def.h>
 #include <plat_arm.h>
 
 #include "css_mhu.h"
diff --git a/plat/arm/css/drivers/mhu/css_mhu_doorbell.c b/plat/arm/css/drivers/mhu/css_mhu_doorbell.c
index b3203c2..964428b 100644
--- a/plat/arm/css/drivers/mhu/css_mhu_doorbell.c
+++ b/plat/arm/css/drivers/mhu/css_mhu_doorbell.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -32,7 +32,7 @@
 			plat_info->db_modify_mask,
 			plat_info->db_preserve_mask);
 
-	/* clear the access request for the recevier */
+	/* clear the access request for the receiver */
 	MHU_V2_CLEAR_REQUEST(MHUV2_BASE_ADDR);
 
 	return;
diff --git a/plat/arm/css/drivers/scp/css_bom_bootloader.c b/plat/arm/css/drivers/scp/css_bom_bootloader.c
index 27c9e1d..ca40c30 100644
--- a/plat/arm/css/drivers/scp/css_bom_bootloader.c
+++ b/plat/arm/css/drivers/scp/css_bom_bootloader.c
@@ -10,8 +10,7 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <plat/common/platform.h>
-
-#include <css_def.h>
+#include <platform_def.h>
 
 #include "../mhu/css_mhu.h"
 #include "../scpi/css_scpi.h"
diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c
index bd6b595..fa4dd8a 100644
--- a/plat/arm/css/drivers/scp/css_pm_scmi.c
+++ b/plat/arm/css/drivers/scp/css_pm_scmi.c
@@ -10,8 +10,8 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
-#include <css_def.h>
 #include <css_pm.h>
 #include <plat_arm.h>
 
diff --git a/plat/arm/css/drivers/scp/css_sds.c b/plat/arm/css/drivers/scp/css_sds.c
index c152abc..e3f6102 100644
--- a/plat/arm/css/drivers/scp/css_sds.c
+++ b/plat/arm/css/drivers/scp/css_sds.c
@@ -11,8 +11,7 @@
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
 #include <plat/common/platform.h>
-
-#include <css_def.h>
+#include <platform_def.h>
 
 #include "css_scp.h"
 #include "../sds/sds.h"
diff --git a/plat/arm/css/drivers/scpi/css_scpi.c b/plat/arm/css/drivers/scpi/css_scpi.c
index 42bf3b8..d64bfa2 100644
--- a/plat/arm/css/drivers/scpi/css_scpi.c
+++ b/plat/arm/css/drivers/scpi/css_scpi.c
@@ -11,8 +11,7 @@
 #include <common/debug.h>
 #include <lib/utils.h>
 #include <plat/common/platform.h>
-
-#include <css_def.h>
+#include <platform_def.h>
 
 #include "../mhu/css_mhu.h"
 #include "css_scpi.h"
diff --git a/plat/arm/css/drivers/sds/sds.c b/plat/arm/css/drivers/sds/sds.c
index 3eeb0dc..eb2f48e 100644
--- a/plat/arm/css/drivers/sds/sds.c
+++ b/plat/arm/css/drivers/sds/sds.c
@@ -10,8 +10,8 @@
 
 #include <arch_helpers.h>
 #include <common/debug.h>
+#include <platform_def.h>
 
-#include <css_def.h>
 #include "sds.h"
 #include "sds_private.h"
 
diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c
index 8357794..72cda7f 100644
--- a/plat/arm/css/sgi/sgi_plat.c
+++ b/plat/arm/css/sgi/sgi_plat.c
@@ -14,10 +14,7 @@
 #include <plat/common/platform.h>
 #include <services/secure_partition.h>
 
-#include <arm_def.h>
-#include <arm_spm_def.h>
 #include <plat_arm.h>
-#include "../../../../bl1/bl1_private.h"
 
 #if USE_COHERENT_MEM
 /*
diff --git a/plat/arm/css/sgm/sgm_mmap_config.c b/plat/arm/css/sgm/sgm_mmap_config.c
index a4df9ab..763f36a 100644
--- a/plat/arm/css/sgm/sgm_mmap_config.c
+++ b/plat/arm/css/sgm/sgm_mmap_config.c
@@ -9,7 +9,6 @@
 #include <common/bl_common.h>
 #include <common/debug.h>
 
-#include <arm_def.h>
 #include <plat_arm.h>
 #include <sgm_variant.h>
 
diff --git a/plat/arm/soc/common/soc_css_security.c b/plat/arm/soc/common/soc_css_security.c
index bbc5dcd..b48357a 100644
--- a/plat/arm/soc/common/soc_css_security.c
+++ b/plat/arm/soc/common/soc_css_security.c
@@ -9,9 +9,7 @@
 #include <drivers/arm/nic_400.h>
 #include <lib/mmio.h>
 
-#include <board_css_def.h>
 #include <soc_css.h>
-#include <soc_css_def.h>
 
 void soc_css_init_nic400(void)
 {
diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c
index a08bdfa..a97d763 100644
--- a/plat/hisilicon/hikey/hikey_bl1_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl1_setup.c
@@ -22,7 +22,6 @@
 #include <hikey_def.h>
 #include <hikey_layout.h>
 
-#include "../../../bl1/bl1_private.h"
 #include "hikey_private.h"
 
 /* Data structure which holds the extents of the trusted RAM for BL1 */
diff --git a/plat/hisilicon/hikey960/hikey960_bl1_setup.c b/plat/hisilicon/hikey960/hikey960_bl1_setup.c
index 38bdbe4..4a7036c 100644
--- a/plat/hisilicon/hikey960/hikey960_bl1_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl1_setup.c
@@ -25,7 +25,6 @@
 #include <plat/common/platform.h>
 
 #include <hi3660.h>
-#include "../../../bl1/bl1_private.h"
 #include "hikey960_def.h"
 #include "hikey960_private.h"
 
diff --git a/plat/hisilicon/hikey960/hikey960_def.h b/plat/hisilicon/hikey960/hikey960_def.h
index d977c79..4ea3acd 100644
--- a/plat/hisilicon/hikey960/hikey960_def.h
+++ b/plat/hisilicon/hikey960/hikey960_def.h
@@ -11,7 +11,7 @@
 #include <plat/common/common_def.h>
 
 #define DDR_BASE			0x0
-#define DDR_SIZE			0xC0000000
+#define DDR_SIZE			0xE0000000
 
 #define DEVICE_BASE			0xE0000000
 #define DEVICE_SIZE			0x20000000
diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h
index 3e2d79d..7c3c102 100644
--- a/plat/hisilicon/hikey960/include/platform_def.h
+++ b/plat/hisilicon/hikey960/include/platform_def.h
@@ -122,11 +122,7 @@
 #endif
 
 #ifdef IMAGE_BL2
-#ifdef SPD_opteed
 #define MAX_XLAT_TABLES			4
-#else
-#define MAX_XLAT_TABLES			3
-#endif
 #endif
 
 #define MAX_MMAP_REGIONS		16
diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c
index eb8ffe4..08ad67c 100644
--- a/plat/hisilicon/poplar/bl1_plat_setup.c
+++ b/plat/hisilicon/poplar/bl1_plat_setup.c
@@ -22,7 +22,6 @@
 #include <lib/mmio.h>
 #include <plat/common/platform.h>
 
-#include "../../../bl1/bl1_private.h"
 #include "hi3798cv200.h"
 #include "plat_private.h"
 
diff --git a/plat/imx/common/imx_uart_console.S b/plat/imx/common/imx_uart_console.S
index 7dbde79..03ec313 100644
--- a/plat/imx/common/imx_uart_console.S
+++ b/plat/imx/common/imx_uart_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,10 +16,11 @@
 #define UTS   0xb4 /* UART Test Register (mx31) */
 #define  URXD_RX_DATA    (0xFF)
 
-	.globl	console_uart_register
-	.globl	console_uart_init
-	.globl	console_uart_putc
-	.globl	console_uart_getc
+	.globl	console_imx_uart_register
+	.globl	console_imx_uart_init
+	.globl	console_imx_uart_putc
+	.globl	console_imx_uart_getc
+	.globl	console_imx_uart_flush
 
 func console_imx_uart_register
 	mov	x7, x30
@@ -32,7 +33,7 @@
 
 	mov	x0, x6
 	mov	x30, x7
-	finish_console_register imx_uart putc=1, getc=1
+	finish_console_register imx_uart putc=1, getc=1, flush=1
 
 register_fail:
 	ret	x7
@@ -82,3 +83,8 @@
 	mov	w0, #-1
 	ret
 endfunc console_imx_uart_getc
+
+func console_imx_uart_flush
+	mov	x0, #0
+	ret
+endfunc console_imx_uart_flush
diff --git a/plat/imx/common/include/imx_uart.h b/plat/imx/common/include/imx_uart.h
index a251024..1b52e2f 100644
--- a/plat/imx/common/include/imx_uart.h
+++ b/plat/imx/common/include/imx_uart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,7 @@
 	uintptr_t base;
 } console_uart_t;
 
-int console_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+int console_imx_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
 			   console_uart_t *console);
 #endif /*__ASSEMBLY__*/
 
diff --git a/plat/imx/common/lpuart_console.S b/plat/imx/common/lpuart_console.S
index 668fd62..0162868 100644
--- a/plat/imx/common/lpuart_console.S
+++ b/plat/imx/common/lpuart_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,6 +15,7 @@
 	.globl	console_lpuart_init
 	.globl	console_lpuart_putc
 	.globl	console_lpuart_getc
+	.globl	console_lpuart_flush
 
 func console_lpuart_register
 	mov	x7, x30
@@ -27,7 +28,7 @@
 
 	mov	x0, x6
 	mov	x30, x7
-	finish_console_register lpuart putc=1, getc=1
+	finish_console_register lpuart putc=1, getc=1, flush=1
 
 register_fail:
 	ret	x7
@@ -70,3 +71,8 @@
 	mov	w0, #-1
 	ret
 endfunc console_lpuart_getc
+
+func console_lpuart_flush
+	mov	x0, #0
+	ret
+endfunc console_lpuart_flush
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index f4e6ee7..b18edd9 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -87,7 +87,7 @@
 #if DEBUG_CONSOLE
 	static console_uart_t console;
 
-	console_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
+	console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
 		IMX_CONSOLE_BAUDRATE, &console);
 #endif
 	/*
diff --git a/plat/layerscape/common/ls_bl1_setup.c b/plat/layerscape/common/ls_bl1_setup.c
index fb929fe..163b35c 100644
--- a/plat/layerscape/common/ls_bl1_setup.c
+++ b/plat/layerscape/common/ls_bl1_setup.c
@@ -4,11 +4,11 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <common/bl_common.h>
 #include <common/debug.h>
 
 #include "ls_16550.h"
 #include "plat_ls.h"
-#include "../../../bl1/bl1_private.h"
 
 /* Data structure which holds the extents of the trusted SRAM for BL1*/
 static meminfo_t bl1_tzram_layout;
diff --git a/plat/marvell/common/marvell_bl1_setup.c b/plat/marvell/common/marvell_bl1_setup.c
index 8f72210..7b7cef3 100644
--- a/plat/marvell/common/marvell_bl1_setup.c
+++ b/plat/marvell/common/marvell_bl1_setup.c
@@ -8,7 +8,6 @@
 #include <platform_def.h>
 
 #include <bl1/bl1.h>
-#include <bl1/bl1_private.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <drivers/arm/sp805.h>
diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h
index ab2bf1b..754831a 100644
--- a/plat/qemu/qemu_private.h
+++ b/plat/qemu/qemu_private.h
@@ -9,8 +9,6 @@
 
 #include <stdint.h>
 
-#include "../../bl1/bl1_private.h"
-
 void qemu_configure_mmu_svc_mon(unsigned long total_base,
 			unsigned long total_size,
 			unsigned long code_start, unsigned long code_limit,
diff --git a/plat/renesas/rcar/aarch64/plat_helpers.S b/plat/renesas/rcar/aarch64/plat_helpers.S
index d40f8f2..ae0d675 100644
--- a/plat/renesas/rcar/aarch64/plat_helpers.S
+++ b/plat/renesas/rcar/aarch64/plat_helpers.S
@@ -217,6 +217,8 @@
 	 * ---------------------------------------------
 	 */
 func plat_report_exception
+	/* Switch to SP_EL0 */
+	msr	spsel, #0
 #if IMAGE_BL2
 	mov	w1, #FIQ_SP_EL0
 	cmp	w0, w1
@@ -326,11 +328,11 @@
 	ubfx	w0, w0, 8, 8
 	/* H3? */
 	cmp	w0, #0x4F
-	b.eq	H3
+	b.eq	RCARH3
 	/* set R-Car M3/M3N */
 	mov	x2, #1
 	b	CHK_A5x
-H3:
+RCARH3:
 	/* set R-Car H3 */
 	mov	x2, #0
 	/* --------------------------------------------------------------------
diff --git a/plat/renesas/rcar/aarch64/platform_common.c b/plat/renesas/rcar/aarch64/platform_common.c
index 647a562..b0a88cb 100644
--- a/plat/renesas/rcar/aarch64/platform_common.c
+++ b/plat/renesas/rcar/aarch64/platform_common.c
@@ -102,7 +102,7 @@
 #endif
 
 #if IMAGE_BL2
-const mmap_region_t rcar_mmap[] = {
+static const mmap_region_t rcar_mmap[] = {
 	MAP_FLASH0,	/*   0x08000000 -   0x0BFFFFFF  RPC area            */
 	MAP_DRAM0,	/*   0x40000000 -   0xBFFFFFFF  DRAM area(Legacy)   */
 	MAP_REG0,	/*   0xE6000000 -   0xE62FFFFF  SoC register area   */
@@ -116,7 +116,7 @@
 #endif
 
 #if IMAGE_BL31
-const mmap_region_t rcar_mmap[] = {
+static const mmap_region_t rcar_mmap[] = {
 	MAP_SHARED_RAM,
 	MAP_ATFW_CRASH,
 	MAP_ATFW_LOG,
@@ -129,7 +129,7 @@
 #endif
 
 #if IMAGE_BL32
-const mmap_region_t rcar_mmap[] = {
+static const mmap_region_t rcar_mmap[] = {
 	MAP_DEVICE0,
 	MAP_DEVICE1,
 	{0}
diff --git a/plat/renesas/rcar/bl2_interrupt_error.c b/plat/renesas/rcar/bl2_interrupt_error.c
index 2346017..d9a4b8e 100644
--- a/plat/renesas/rcar/bl2_interrupt_error.c
+++ b/plat/renesas/rcar/bl2_interrupt_error.c
@@ -24,7 +24,7 @@
 	ERROR("\n");
 	if (int_id >= SWDT_ERROR_ID) {
 		ERROR("Unhandled exception occurred.\n");
-		ERROR("     Exception type = FIQ_SP_ELX\n");
+		ERROR("     Exception type = FIQ_SP_EL0\n");
 		panic();
 	}
 
@@ -32,11 +32,11 @@
 	gicv2_end_of_interrupt((uint32_t) int_id);
 	rcar_swdt_release();
 	ERROR("Unhandled exception occurred.\n");
-	ERROR("     Exception type = FIQ_SP_ELX\n");
-	ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
-	ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
-	ERROR("     ESR_EL1  = 0x%x\n", (uint32_t) read_esr_el1());
-	ERROR("     FAR_EL1  = 0x%x\n", (uint32_t) read_far_el1());
+	ERROR("     Exception type = FIQ_SP_EL0\n");
+	ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+	ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
+	ERROR("     ESR_EL3  = 0x%x\n", (uint32_t) read_esr_el3());
+	ERROR("     FAR_EL3  = 0x%x\n", (uint32_t) read_far_el3());
 	ERROR("\n");
 	panic();
 }
@@ -78,27 +78,27 @@
 		 &interrupt_ex[ex_type][0]);
 	ERROR("%s", msg);
 	switch (ex_type) {
-	case SYNC_EXCEPTION_SP_ELX:
-		ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
-		ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
-		ERROR("     ESR_EL1  = 0x%x\n", (uint32_t) read_esr_el1());
-		ERROR("     FAR_EL1  = 0x%x\n", (uint32_t) read_far_el1());
+	case SYNC_EXCEPTION_SP_EL0:
+		ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+		ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
+		ERROR("     ESR_EL3  = 0x%x\n", (uint32_t) read_esr_el3());
+		ERROR("     FAR_EL3  = 0x%x\n", (uint32_t) read_far_el3());
 		break;
-	case IRQ_SP_ELX:
-		ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
-		ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
-		ERROR("     IAR_EL1  = 0x%x\n", gicv2_acknowledge_interrupt());
+	case IRQ_SP_EL0:
+		ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+		ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
+		ERROR("     IAR_EL3  = 0x%x\n", gicv2_acknowledge_interrupt());
 		break;
-	case FIQ_SP_ELX:
-		ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
-		ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
-		ERROR("     IAR_EL1  = 0x%x\n", gicv2_acknowledge_interrupt());
+	case FIQ_SP_EL0:
+		ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+		ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
+		ERROR("     IAR_EL3  = 0x%x\n", gicv2_acknowledge_interrupt());
 		break;
-	case SERROR_SP_ELX:
-		ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
-		ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
-		ERROR("     ESR_EL1  = 0x%x\n", (uint32_t) read_esr_el1());
-		ERROR("     FAR_EL1  = 0x%x\n", (uint32_t) read_far_el1());
+	case SERROR_SP_EL0:
+		ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+		ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
+		ERROR("     ESR_EL3  = 0x%x\n", (uint32_t) read_esr_el3());
+		ERROR("     FAR_EL3  = 0x%x\n", (uint32_t) read_far_el3());
 		break;
 	default:
 		break;
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index 77a5ed1..2debbf9 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -61,6 +61,8 @@
 extern void rcar_pfc_init(void);
 extern void rcar_dma_init(void);
 
+static void bl2_init_generic_timer(void);
+
 /* R-Car Gen3 product check */
 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
 #define TARGET_PRODUCT			RCAR_PRODUCT_H3
@@ -74,6 +76,8 @@
 #elif RCAR_LSI == RCAR_E3
 #define TARGET_PRODUCT			RCAR_PRODUCT_E3
 #define TARGET_NAME			"R-Car E3"
+#elif RCAR_LSI == RCAR_AUTO
+#define TARGET_NAME			"R-Car H3/M3/M3N"
 #endif
 
 #if (RCAR_LSI == RCAR_E3)
@@ -259,8 +263,10 @@
 		   product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) {
 		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
-	} else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
+	} else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) ||
+		   (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) {
 		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
 	}
 
@@ -388,7 +394,7 @@
 	return 0;
 }
 
-meminfo_t *bl2_plat_sec_mem_layout(void)
+struct meminfo *bl2_plat_sec_mem_layout(void)
 {
 	return &bl2_tzram_layout;
 }
@@ -624,6 +630,8 @@
 	int fcnlnode;
 #endif
 
+	bl2_init_generic_timer();
+
 	reg = mmio_read_32(RCAR_MODEMR);
 	boot_dev = reg & MODEMR_BOOT_DEV_MASK;
 	boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
@@ -899,7 +907,7 @@
 #if RCAR_BL2_DCACHE == 1
 	NOTICE("BL2: D-Cache enable\n");
 	rcar_configure_mmu_el3(BL2_BASE,
-			       RCAR_SYSRAM_LIMIT - BL2_BASE,
+			       BL2_END - BL2_BASE,
 			       BL2_RO_BASE, BL2_RO_LIMIT
 #if USE_COHERENT_MEM
 			       , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
@@ -912,3 +920,52 @@
 {
 
 }
+
+static void bl2_init_generic_timer(void)
+{
+#if RCAR_LSI == RCAR_E3
+	uint32_t reg_cntfid = EXTAL_EBISU;
+#else /* RCAR_LSI == RCAR_E3 */
+	uint32_t reg;
+	uint32_t reg_cntfid;
+	uint32_t modemr;
+	uint32_t modemr_pll;
+	uint32_t board_type;
+	uint32_t board_rev;
+	uint32_t pll_table[] = {
+		EXTAL_MD14_MD13_TYPE_0,	/* MD14/MD13 : 0b00 */
+		EXTAL_MD14_MD13_TYPE_1,	/* MD14/MD13 : 0b01 */
+		EXTAL_MD14_MD13_TYPE_2,	/* MD14/MD13 : 0b10 */
+		EXTAL_MD14_MD13_TYPE_3	/* MD14/MD13 : 0b11 */
+	};
+
+	modemr = mmio_read_32(RCAR_MODEMR);
+	modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
+
+	/* Set frequency data in CNTFID0 */
+	reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
+	reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	switch (modemr_pll) {
+	case MD14_MD13_TYPE_0:
+		rcar_get_board_type(&board_type, &board_rev);
+		if (BOARD_SALVATOR_XS == board_type) {
+			reg_cntfid = EXTAL_SALVATOR_XS;
+		}
+		break;
+	case MD14_MD13_TYPE_3:
+		if (RCAR_PRODUCT_H3_CUT10 == reg) {
+			reg_cntfid = reg_cntfid >> 1U;
+		}
+		break;
+	default:
+		/* none */
+		break;
+	}
+#endif /* RCAR_LSI == RCAR_E3 */
+	/* Update memory mapped and register based freqency */
+	write_cntfrq_el0((u_register_t )reg_cntfid);
+	mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
+	/* Enable counter */
+	mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
+			(uint32_t)CNTCR_EN);
+}
diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c
index 6f31417..4e08b5a 100644
--- a/plat/renesas/rcar/bl31_plat_setup.c
+++ b/plat/renesas/rcar/bl31_plat_setup.c
@@ -64,7 +64,7 @@
 	cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
 }
 
-entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
 {
 	bl2_to_bl31_params_mem_t *from_bl2 = (bl2_to_bl31_params_mem_t *)
 					     PARAMS_BASE;
@@ -100,6 +100,7 @@
 			       , BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
 #endif
 	    );
+	rcar_pwrc_code_copy_to_system_ram();
 }
 
 void bl31_platform_setup(void)
diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h
index 20fd712..934b2dc 100644
--- a/plat/renesas/rcar/include/platform_def.h
+++ b/plat/renesas/rcar/include/platform_def.h
@@ -79,7 +79,7 @@
  *          Cortex-A53
  * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
  */
-#define PLATFORM_CACHE_LINE_SIZE	128
+#define PLATFORM_CACHE_LINE_SIZE	64
 #define PLATFORM_CLUSTER_COUNT		U(2)
 #define PLATFORM_CLUSTER0_CORE_COUNT	U(4)
 #define PLATFORM_CLUSTER1_CORE_COUNT	U(4)
@@ -104,16 +104,16 @@
  * size plus a little space for growth. */
 #define RCAR_SYSRAM_BASE		U(0xE6300000)
 #if RCAR_LSI == RCAR_E3
-#define RCAR_SYSRAM_LIMIT		U(0xE6320000)
+#define BL2_LIMIT			U(0xE6320000)
 #else
-#define RCAR_SYSRAM_LIMIT		U(0xE6360000)
+#define BL2_LIMIT			U(0xE6360000)
 #endif
 
 #define BL2_BASE			U(0xE6304000)
 #if RCAR_LSI == RCAR_E3
-#define BL2_LIMIT			U(0xE6318000)
+#define BL2_IMAGE_LIMIT			U(0xE6318000)
 #else
-#define BL2_LIMIT			U(0xE632E800)
+#define BL2_IMAGE_LIMIT			U(0xE632E800)
 #endif
 #define RCAR_SYSRAM_SIZE		(BL2_BASE - RCAR_SYSRAM_BASE)
 
diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h
index 242e007..1829e59 100644
--- a/plat/renesas/rcar/include/rcar_def.h
+++ b/plat/renesas/rcar/include/rcar_def.h
@@ -24,7 +24,7 @@
 #define DEVICE_RCAR_SIZE		U(0x00300000)
 #define DEVICE_RCAR_BASE2		U(0xE6360000)
 #define DEVICE_RCAR_SIZE2		U(0x19CA0000)
-#define DEVICE_SRAM_BASE		U(0xE6310000)
+#define DEVICE_SRAM_BASE		U(0xE6300000)
 #define DEVICE_SRAM_SIZE		U(0x00002000)
 #define DEVICE_SRAM_STACK_BASE		(DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
 #define DEVICE_SRAM_STACK_SIZE		U(0x00001000)
@@ -231,6 +231,8 @@
 #define IPMMUMM_IMSCTLR_ENABLE		(0xC0000000U)
 #define IPMMUMM_IMAUXCTLR_NMERGE40_BIT	(0x01000000U)
 #define IMSCTLR_DISCACHE		(0xE0000000U)
+#define IPMMU_VP0_BASE			(0xFE990000U)
+#define IPMMUVP0_IMSCTLR		(IPMMU_VP0_BASE + 0x0500U)
 #define IPMMU_VI0_BASE			(0xFEBD0000U)
 #define IPMMUVI0_IMSCTLR		(IPMMU_VI0_BASE + 0x0500U)
 #define IPMMU_VI1_BASE			(0xFEBE0000U)
diff --git a/plat/renesas/rcar/include/rcar_version.h b/plat/renesas/rcar/include/rcar_version.h
index 5ab8efc..5c8805c 100644
--- a/plat/renesas/rcar/include/rcar_version.h
+++ b/plat/renesas/rcar/include/rcar_version.h
@@ -9,7 +9,7 @@
 
 #include <arch_helpers.h>
 
-#define VERSION_OF_RENESAS		"1.0.22"
+#define VERSION_OF_RENESAS		"2.0.0"
 #define	VERSION_OF_RENESAS_MAXLEN	(128)
 
 extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/rcar/plat_pm.c
index 7086613..245a45a 100644
--- a/plat/renesas/rcar/plat_pm.c
+++ b/plat/renesas/rcar/plat_pm.c
@@ -22,6 +22,7 @@
 #include "pwrc.h"
 #include "rcar_def.h"
 #include "rcar_private.h"
+#include "ulcb_cpld.h"
 
 #define	DVFS_SET_VID_0V		(0x00)
 #define	P_ALL_OFF		(0x80)
@@ -41,10 +42,6 @@
 extern void plat_rcar_gic_init(void);
 extern u_register_t rcar_boot_mpidr;
 
-#if (RCAR_GEN3_ULCB == 1)
-extern void rcar_cpld_reset_cpu(void);
-#endif
-
 static uintptr_t rcar_sec_entrypoint;
 
 static void rcar_program_mailbox(uint64_t mpidr, uint64_t address)
@@ -155,6 +152,7 @@
 	write_cntfrq_el0(plat_get_syscnt_freq2());
 	mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
 	rcar_pwrc_setup();
+	rcar_pwrc_code_copy_to_system_ram();
 
 #if RCAR_SYSTEM_SUSPEND
 	rcar_pwrc_init_suspend_to_ram();
@@ -167,11 +165,9 @@
 {
 #if PMIC_ROHM_BD9571
 #if PMIC_LEVEL_MODE
-	rcar_pwrc_code_copy_to_system_ram();
 	if (rcar_iic_dvfs_send(PMIC, DVFS_SET_VID, DVFS_SET_VID_0V))
 		ERROR("BL3-1:Failed the SYSTEM-OFF.\n");
 #else
-	rcar_pwrc_code_copy_to_system_ram();
 	if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
 		ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
 #endif
@@ -204,7 +200,6 @@
 	uint8_t mode;
 	int32_t error;
 
-	rcar_pwrc_code_copy_to_system_ram();
 	error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
 	if (error) {
 		ERROR("Failed send KEEP10 magic ret=%d \n", error);
@@ -227,7 +222,6 @@
 	rcar_pwrc_set_suspend_to_ram();
 done:
 #else
-	rcar_pwrc_code_copy_to_system_ram();
 	if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
 		ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
 #endif
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 0cc746d..b9c0802 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -4,13 +4,14 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-PROGRAMMABLE_RESET_ADDRESS	:= 0
+PROGRAMMABLE_RESET_ADDRESS	:= 1
 COLD_BOOT_SINGLE_CPU		:= 1
 ARM_CCI_PRODUCT_ID		:= 500
 TRUSTED_BOARD_BOOT		:= 1
 RESET_TO_BL31			:= 1
 GENERATE_COT			:= 1
 BL2_AT_EL3			:= 1
+ENABLE_SVE_FOR_NS		:= 0
 
 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
 
@@ -310,6 +311,7 @@
 			-Idrivers/staging/renesas/rcar/qos	\
 			-Idrivers/renesas/rcar/iic_dvfs		\
 			-Idrivers/renesas/rcar/board		\
+			-Idrivers/renesas/rcar/cpld/		\
 			-Idrivers/renesas/rcar/avs		\
 			-Idrivers/renesas/rcar/delay		\
 			-Idrivers/renesas/rcar/rom		\
@@ -353,7 +355,7 @@
 			drivers/renesas/rcar/rpc/rpc_driver.c		\
 			drivers/renesas/rcar/dma/dma_driver.c		\
 			drivers/renesas/rcar/avs/avs_driver.c		\
-			drivers/renesas/rcar/delay/micro_delay.S	\
+			drivers/renesas/rcar/delay/micro_delay.c	\
 			drivers/renesas/rcar/emmc/emmc_interrupt.c	\
 			drivers/renesas/rcar/emmc/emmc_utility.c	\
 			drivers/renesas/rcar/emmc/emmc_mount.c		\
@@ -376,6 +378,7 @@
 			plat/renesas/rcar/plat_pm.c			\
 			drivers/renesas/rcar/console/rcar_console.S	\
 			drivers/renesas/rcar/console/rcar_printf.c	\
+			drivers/renesas/rcar/delay/micro_delay.c	\
 			drivers/renesas/rcar/pwrc/call_sram.S		\
 			drivers/renesas/rcar/pwrc/pwrc.c		\
 			drivers/renesas/rcar/common.c			\
@@ -415,7 +418,7 @@
 	rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
 
 .PHONY: rcar_srecord
-rcar_srecord:
+rcar_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC)
 	@echo "generating srec: ${SREC_PATH}/bl2.srec"
 	$(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC}  ${SREC_PATH}/bl2.srec
 	@echo "generating srec: ${SREC_PATH}/bl31.srec"
diff --git a/plat/rpi3/rpi3_bl1_setup.c b/plat/rpi3/rpi3_bl1_setup.c
index ea4215d..b869e9d 100644
--- a/plat/rpi3/rpi3_bl1_setup.c
+++ b/plat/rpi3/rpi3_bl1_setup.c
@@ -13,7 +13,6 @@
 #include <lib/xlat_tables/xlat_mmu_helpers.h>
 #include <lib/xlat_tables/xlat_tables_defs.h>
 
-#include "../../bl1/bl1_private.h"
 #include "rpi3_private.h"
 
 /* Data structure which holds the extents of the trusted SRAM for BL1 */
diff --git a/plat/xilinx/zynqmp/zynqmp_ipi.h b/plat/xilinx/common/include/ipi.h
similarity index 68%
rename from plat/xilinx/zynqmp/zynqmp_ipi.h
rename to plat/xilinx/common/include/ipi.h
index b9b40dd..483902e 100644
--- a/plat/xilinx/zynqmp/zynqmp_ipi.h
+++ b/plat/xilinx/common/include/ipi.h
@@ -1,32 +1,17 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Xilinx, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-/* ZynqMP IPI management enums and defines */
+/* Xilinx IPI management configuration data and macros */
 
-#ifndef ZYNQMP_IPI_H
-#define ZYNQMP_IPI_H
+#ifndef IPI_H
+#define IPI_H
 
 #include <stdint.h>
 
 /*********************************************************************
- * IPI agent IDs macros
- ********************************************************************/
-#define IPI_ID_APU	0U
-#define IPI_ID_RPU0	1U
-#define IPI_ID_RPU1	2U
-#define IPI_ID_PMU0	3U
-#define IPI_ID_PMU1	4U
-#define IPI_ID_PMU2	5U
-#define IPI_ID_PMU3	6U
-#define IPI_ID_PL0	7U
-#define IPI_ID_PL1	8U
-#define IPI_ID_PL2	9U
-#define IPI_ID_PL3	10U
-
-/*********************************************************************
  * IPI mailbox status macros
  ********************************************************************/
 #define IPI_MB_STATUS_IDLE		0
@@ -40,9 +25,31 @@
 #define IPI_MB_CALL_SECURE	1
 
 /*********************************************************************
+ * IPI secure check
+ ********************************************************************/
+#define IPI_SECURE_MASK  0x1U
+#define IPI_IS_SECURE(I) ((ipi_table[(I)].secure_only & \
+			   IPI_SECURE_MASK) ? 1 : 0)
+
+/*********************************************************************
+ * Struct definitions
+ ********************************************************************/
+
+/* structure to maintain IPI configuration information */
+struct ipi_config {
+	unsigned int ipi_bit_mask;
+	unsigned int ipi_reg_base;
+	unsigned char secure_only;
+};
+
+/*********************************************************************
  * IPI APIs declarations
  ********************************************************************/
 
+/* Initialize IPI configuration table */
+void ipi_config_table_init(const struct ipi_config *ipi_table,
+			   uint32_t total_ipi);
+
 /* Validate IPI mailbox access */
 int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure);
 
@@ -67,4 +74,4 @@
 /* Enable IPI mailbox notification interrupt */
 void ipi_mb_enable_irq(uint32_t local, uint32_t remote);
 
-#endif /* ZYNQMP_IPI_H */
+#endif /* IPI_H */
diff --git a/plat/xilinx/zynqmp/pm_service/pm_common.h b/plat/xilinx/common/include/pm_common.h
similarity index 60%
rename from plat/xilinx/zynqmp/pm_service/pm_common.h
rename to plat/xilinx/common/include/pm_common.h
index 94e0568..c0a51f0 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_common.h
+++ b/plat/xilinx/common/include/pm_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,28 +13,17 @@
 #define PM_COMMON_H
 
 #include <stdint.h>
-
-#include <common/debug.h>
-
-#include "pm_defs.h"
-
-#define PAYLOAD_ARG_CNT		6U
-#define PAYLOAD_ARG_SIZE	4U	/* size in bytes */
-
-#define ZYNQMP_TZ_VERSION_MAJOR		1
-#define ZYNQMP_TZ_VERSION_MINOR		0
-#define ZYNQMP_TZ_VERSION		((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
-					ZYNQMP_TZ_VERSION_MINOR)
+#include <plat_pm_common.h>
 
 /**
  * pm_ipi - struct for capturing IPI-channel specific info
- * @apu_ipi_id	APU IPI agent ID
- * @pmu_ipi_id	PMU Agent ID
+ * @local_ipi_id	Local IPI agent ID
+ * @remote_ipi_id	Remote IPI Agent ID
  * @buffer_base	base address for payload buffer
  */
 struct pm_ipi {
-	const uint32_t apu_ipi_id;
-	const uint32_t pmu_ipi_id;
+	const uint32_t local_ipi_id;
+	const uint32_t remote_ipi_id;
 	const uintptr_t buffer_base;
 };
 
@@ -46,12 +35,11 @@
  *		(in APU all processors share one IPI channel)
  */
 struct pm_proc {
-	const enum pm_node_id node_id;
+	const uint32_t node_id;
 	const unsigned int pwrdn_mask;
 	const struct pm_ipi *ipi;
 };
 
 const struct pm_proc *pm_get_proc(unsigned int cpuid);
-const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid);
 
 #endif /* PM_COMMON_H */
diff --git a/plat/xilinx/zynqmp/pm_service/pm_ipi.h b/plat/xilinx/common/include/pm_ipi.h
similarity index 78%
rename from plat/xilinx/zynqmp/pm_service/pm_ipi.h
rename to plat/xilinx/common/include/pm_ipi.h
index 650de52..16db5c5 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_ipi.h
+++ b/plat/xilinx/common/include/pm_ipi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,8 +7,12 @@
 #ifndef PM_IPI_H
 #define PM_IPI_H
 
+#include <plat_ipi.h>
 #include "pm_common.h"
 
+#define IPI_BLOCKING		1
+#define IPI_NON_BLOCKING	0
+
 int pm_ipi_init(const struct pm_proc *proc);
 
 enum pm_ret_status pm_ipi_send(const struct pm_proc *proc,
@@ -21,5 +25,6 @@
 void pm_ipi_buff_read_callb(unsigned int *value, size_t count);
 void pm_ipi_irq_enable(const struct pm_proc *proc);
 void pm_ipi_irq_clear(const struct pm_proc *proc);
+uint32_t pm_ipi_irq_status(const struct pm_proc *proc);
 
 #endif /* PM_IPI_H */
diff --git a/plat/xilinx/common/ipi.c b/plat/xilinx/common/ipi.c
new file mode 100644
index 0000000..0b8020b
--- /dev/null
+++ b/plat/xilinx/common/ipi.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * Xilinx IPI agent registers access management
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+
+#include <ipi.h>
+#include <plat_ipi.h>
+#include <plat_private.h>
+
+/*********************************************************************
+ * Macros definitions
+ ********************************************************************/
+
+/* IPI registers offsets macros */
+#define IPI_TRIG_OFFSET 0x00U
+#define IPI_OBR_OFFSET  0x04U
+#define IPI_ISR_OFFSET  0x10U
+#define IPI_IMR_OFFSET  0x14U
+#define IPI_IER_OFFSET  0x18U
+#define IPI_IDR_OFFSET  0x1CU
+
+/* IPI register start offset */
+#define IPI_REG_BASE(I) (ipi_table[(I)].ipi_reg_base)
+
+/* IPI register bit mask */
+#define IPI_BIT_MASK(I) (ipi_table[(I)].ipi_bit_mask)
+
+/* IPI configuration table */
+const static struct ipi_config *ipi_table;
+
+/* Total number of IPI */
+static uint32_t ipi_total;
+
+/**
+ * ipi_config_init() - Initialize IPI configuration data
+ *
+ * @ipi_config_table  - IPI configuration table
+ * @ipi_total - Total number of IPI available
+ *
+ */
+void ipi_config_table_init(const struct ipi_config *ipi_config_table,
+			   uint32_t total_ipi)
+{
+	ipi_table = ipi_config_table;
+	ipi_total = total_ipi;
+}
+
+/* is_ipi_mb_within_range() - verify if IPI mailbox is within range
+ *
+ * @local  - local IPI ID
+ * @remote - remote IPI ID
+ *
+ * return - 1 if within range, 0 if not
+ */
+static inline int is_ipi_mb_within_range(uint32_t local, uint32_t remote)
+{
+	int ret = 1;
+
+	if (remote >= ipi_total || local >= ipi_total)
+		ret = 0;
+
+	return ret;
+}
+
+/**
+ * ipi_mb_validate() - validate IPI mailbox access
+ *
+ * @local  - local IPI ID
+ * @remote - remote IPI ID
+ * @is_secure - indicate if the requester is from secure software
+ *
+ * return - 0 success, negative value for errors
+ */
+int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
+{
+	int ret = 0;
+
+	if (!is_ipi_mb_within_range(local, remote))
+		ret = -EINVAL;
+	else if (IPI_IS_SECURE(local) && !is_secure)
+		ret = -EPERM;
+	else if (IPI_IS_SECURE(remote) && !is_secure)
+		ret = -EPERM;
+
+	return ret;
+}
+
+/**
+ * ipi_mb_open() - Open IPI mailbox.
+ *
+ * @local  - local IPI ID
+ * @remote - remote IPI ID
+ *
+ */
+void ipi_mb_open(uint32_t local, uint32_t remote)
+{
+	mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
+		      IPI_BIT_MASK(remote));
+	mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
+		      IPI_BIT_MASK(remote));
+}
+
+/**
+ * ipi_mb_release() - Open IPI mailbox.
+ *
+ * @local  - local IPI ID
+ * @remote - remote IPI ID
+ *
+ */
+void ipi_mb_release(uint32_t local, uint32_t remote)
+{
+	mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
+		      IPI_BIT_MASK(remote));
+}
+
+/**
+ * ipi_mb_enquire_status() - Enquire IPI mailbox status
+ *
+ * @local  - local IPI ID
+ * @remote - remote IPI ID
+ *
+ * return - 0 idle, positive value for pending sending or receiving,
+ *          negative value for errors
+ */
+int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
+{
+	int ret = 0;
+	uint32_t status;
+
+	status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
+	if (status & IPI_BIT_MASK(remote))
+		ret |= IPI_MB_STATUS_SEND_PENDING;
+	status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
+	if (status & IPI_BIT_MASK(remote))
+		ret |= IPI_MB_STATUS_RECV_PENDING;
+
+	return ret;
+}
+
+/* ipi_mb_notify() - Trigger IPI mailbox notification
+ *
+ * @local - local IPI ID
+ * @remote - remote IPI ID
+ * @is_blocking - if to trigger the notification in blocking mode or not.
+ *
+ * It sets the remote bit in the IPI agent trigger register.
+ *
+ */
+void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking)
+{
+	uint32_t status;
+
+	mmio_write_32(IPI_REG_BASE(local) + IPI_TRIG_OFFSET,
+		      IPI_BIT_MASK(remote));
+	if (is_blocking) {
+		do {
+			status = mmio_read_32(IPI_REG_BASE(local) +
+					      IPI_OBR_OFFSET);
+		} while (status & IPI_BIT_MASK(remote));
+	}
+}
+
+/* ipi_mb_ack() - Ack IPI mailbox notification from the other end
+ *
+ * @local - local IPI ID
+ * @remote - remote IPI ID
+ *
+ * It will clear the remote bit in the isr register.
+ *
+ */
+void ipi_mb_ack(uint32_t local, uint32_t remote)
+{
+	mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
+		      IPI_BIT_MASK(remote));
+}
+
+/* ipi_mb_disable_irq() - Disable IPI mailbox notification interrupt
+ *
+ * @local - local IPI ID
+ * @remote - remote IPI ID
+ *
+ * It will mask the remote bit in the idr register.
+ *
+ */
+void ipi_mb_disable_irq(uint32_t local, uint32_t remote)
+{
+	mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
+		      IPI_BIT_MASK(remote));
+}
+
+/* ipi_mb_enable_irq() - Enable IPI mailbox notification interrupt
+ *
+ * @local - local IPI ID
+ * @remote - remote IPI ID
+ *
+ * It will mask the remote bit in the idr register.
+ *
+ */
+void ipi_mb_enable_irq(uint32_t local, uint32_t remote)
+{
+	mmio_write_32(IPI_REG_BASE(local) + IPI_IER_OFFSET,
+		      IPI_BIT_MASK(remote));
+}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
similarity index 75%
rename from plat/xilinx/zynqmp/pm_service/pm_ipi.c
rename to plat/xilinx/common/pm_service/pm_ipi.c
index b3d833d..034cd5b 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c
@@ -1,45 +1,28 @@
 /*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+
 #include <arch_helpers.h>
+
 #include <lib/bakery_lock.h>
 #include <lib/mmio.h>
+
+#include <ipi.h>
+#include <plat_ipi.h>
+#include <plat_private.h>
 #include <plat/common/platform.h>
 
-#include "../zynqmp_ipi.h"
-#include "../zynqmp_private.h"
 #include "pm_ipi.h"
 
-/* IPI message buffers */
-#define IPI_BUFFER_BASEADDR	0xFF990000U
-
-#define IPI_BUFFER_APU_BASE	(IPI_BUFFER_BASEADDR + 0x400U)
-#define IPI_BUFFER_PMU_BASE	(IPI_BUFFER_BASEADDR + 0xE00U)
-
-#define IPI_BUFFER_TARGET_APU_OFFSET	0x80U
-#define IPI_BUFFER_TARGET_PMU_OFFSET	0x1C0U
-
-#define IPI_BUFFER_MAX_WORDS	8
-
-#define IPI_BUFFER_REQ_OFFSET	0x0U
-#define IPI_BUFFER_RESP_OFFSET	0x20U
-
-#define IPI_BLOCKING		1
-#define IPI_NON_BLOCKING	0
 
 DEFINE_BAKERY_LOCK(pm_secure_lock);
 
-const struct pm_ipi apu_ipi = {
-	.apu_ipi_id = IPI_ID_APU,
-	.pmu_ipi_id = IPI_ID_PMU0,
-	.buffer_base = IPI_BUFFER_APU_BASE,
-};
-
 /**
- * pm_ipi_init() - Initialize IPI peripheral for communication with PMU
+ * pm_ipi_init() - Initialize IPI peripheral for communication with
+ *		   remote processor
  *
  * @proc	Pointer to the processor who is initiating request
  * @return	On success, the initialization function must return 0.
@@ -51,13 +34,13 @@
 int pm_ipi_init(const struct pm_proc *proc)
 {
 	bakery_lock_init(&pm_secure_lock);
-	ipi_mb_open(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id);
+	ipi_mb_open(proc->ipi->local_ipi_id, proc->ipi->remote_ipi_id);
 
 	return 0;
 }
 
 /**
- * pm_ipi_send_common() - Sends IPI request to the PMU
+ * pm_ipi_send_common() - Sends IPI request to the remote processor
  * @proc	Pointer to the processor who is initiating request
  * @payload	API id and call arguments to be written in IPI buffer
  *
@@ -72,7 +55,7 @@
 {
 	unsigned int offset = 0;
 	uintptr_t buffer_base = proc->ipi->buffer_base +
-					IPI_BUFFER_TARGET_PMU_OFFSET +
+					IPI_BUFFER_TARGET_REMOTE_OFFSET +
 					IPI_BUFFER_REQ_OFFSET;
 
 	/* Write payload into IPI buffer */
@@ -81,16 +64,16 @@
 		offset += PAYLOAD_ARG_SIZE;
 	}
 
-	/* Generate IPI to PMU */
-	ipi_mb_notify(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id,
+	/* Generate IPI to remote processor */
+	ipi_mb_notify(proc->ipi->local_ipi_id, proc->ipi->remote_ipi_id,
 		      is_blocking);
 
 	return PM_RET_SUCCESS;
 }
 
 /**
- * pm_ipi_send_non_blocking() - Sends IPI request to the PMU without blocking
- *			        notification
+ * pm_ipi_send_non_blocking() - Sends IPI request to the remote processor
+ *			        without blocking notification
  * @proc	Pointer to the processor who is initiating request
  * @payload	API id and call arguments to be written in IPI buffer
  *
@@ -113,7 +96,7 @@
 }
 
 /**
- * pm_ipi_send() - Sends IPI request to the PMU
+ * pm_ipi_send() - Sends IPI request to the remote processor
  * @proc	Pointer to the processor who is initiating request
  * @payload	API id and call arguments to be written in IPI buffer
  *
@@ -137,7 +120,8 @@
 
 
 /**
- * pm_ipi_buff_read() - Reads IPI response after PMU has handled interrupt
+ * pm_ipi_buff_read() - Reads IPI response after remote processor has handled
+ *			interrupt
  * @proc	Pointer to the processor who is waiting and reading response
  * @value	Used to return value from IPI buffer element (optional)
  * @count	Number of values to return in @value
@@ -149,7 +133,7 @@
 {
 	size_t i;
 	uintptr_t buffer_base = proc->ipi->buffer_base +
-				IPI_BUFFER_TARGET_PMU_OFFSET +
+				IPI_BUFFER_TARGET_REMOTE_OFFSET +
 				IPI_BUFFER_RESP_OFFSET;
 
 	/*
@@ -168,7 +152,8 @@
 }
 
 /**
- * pm_ipi_buff_read_callb() - Reads IPI response after PMU has handled interrupt
+ * pm_ipi_buff_read_callb() - Reads IPI response after remote processor has
+ *			      handled interrupt
  * @value	Used to return value from IPI buffer element (optional)
  * @count	Number of values to return in @value
  *
@@ -177,8 +162,8 @@
 void pm_ipi_buff_read_callb(unsigned int *value, size_t count)
 {
 	size_t i;
-	uintptr_t buffer_base = IPI_BUFFER_PMU_BASE +
-				IPI_BUFFER_TARGET_APU_OFFSET +
+	uintptr_t buffer_base = IPI_BUFFER_REMOTE_BASE +
+				IPI_BUFFER_TARGET_LOCAL_OFFSET +
 				IPI_BUFFER_REQ_OFFSET;
 
 	if (count > IPI_BUFFER_MAX_WORDS)
@@ -191,7 +176,7 @@
 }
 
 /**
- * pm_ipi_send_sync() - Sends IPI request to the PMU
+ * pm_ipi_send_sync() - Sends IPI request to the remote processor
  * @proc	Pointer to the processor who is initiating request
  * @payload	API id and call arguments to be written in IPI buffer
  * @value	Used to return value from IPI buffer element (optional)
@@ -224,10 +209,22 @@
 
 void pm_ipi_irq_enable(const struct pm_proc *proc)
 {
-	ipi_mb_enable_irq(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id);
+	ipi_mb_enable_irq(proc->ipi->local_ipi_id, proc->ipi->remote_ipi_id);
 }
 
 void pm_ipi_irq_clear(const struct pm_proc *proc)
 {
+	ipi_mb_ack(proc->ipi->local_ipi_id, proc->ipi->remote_ipi_id);
+}
+
+uint32_t pm_ipi_irq_status(const struct pm_proc *proc)
+{
-	ipi_mb_ack(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id);
+	int ret;
+
+	ret = ipi_mb_enquire_status(proc->ipi->local_ipi_id,
+				    proc->ipi->remote_ipi_id);
+	if (ret & IPI_MB_STATUS_RECV_PENDING)
+		return 1;
+	else
+		return 0;
 }
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 23c02e0..8ff6c43 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -11,9 +11,9 @@
 #include <drivers/generic_delay_timer.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables.h>
+#include <plat_private.h>
 #include <plat/common/platform.h>
 
-#include "../zynqmp_private.h"
 #include "pm_api_sys.h"
 
 /*
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 01cd781..8ecd6d7 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -12,10 +12,9 @@
 #include <common/debug.h>
 #include <drivers/console.h>
 #include <plat_arm.h>
+#include <plat_private.h>
 #include <plat/common/platform.h>
 
-#include "zynqmp_private.h"
-
 #define BL31_END (unsigned long)(&__BL31_END__)
 
 static entry_point_info_t bl32_image_ep_info;
diff --git a/plat/xilinx/zynqmp/include/plat_ipi.h b/plat/xilinx/zynqmp/include/plat_ipi.h
new file mode 100644
index 0000000..bccd2f1
--- /dev/null
+++ b/plat/xilinx/zynqmp/include/plat_ipi.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* ZynqMP IPI management enums and defines */
+
+#ifndef PLAT_IPI_H
+#define PLAT_IPI_H
+
+#include <stdint.h>
+#include <ipi.h>
+
+/*********************************************************************
+ * IPI agent IDs macros
+ ********************************************************************/
+#define IPI_ID_APU	0U
+#define IPI_ID_RPU0	1U
+#define IPI_ID_RPU1	2U
+#define IPI_ID_PMU0	3U
+#define IPI_ID_PMU1	4U
+#define IPI_ID_PMU2	5U
+#define IPI_ID_PMU3	6U
+#define IPI_ID_PL0	7U
+#define IPI_ID_PL1	8U
+#define IPI_ID_PL2	9U
+#define IPI_ID_PL3	10U
+
+/*********************************************************************
+ * IPI message buffers
+ ********************************************************************/
+#define IPI_BUFFER_BASEADDR	0xFF990000U
+
+#define IPI_BUFFER_APU_BASE	(IPI_BUFFER_BASEADDR + 0x400U)
+#define IPI_BUFFER_PMU_BASE	(IPI_BUFFER_BASEADDR + 0xE00U)
+
+#define IPI_BUFFER_LOCAL_BASE	IPI_BUFFER_APU_BASE
+#define IPI_BUFFER_REMOTE_BASE	IPI_BUFFER_PMU_BASE
+
+#define IPI_BUFFER_TARGET_LOCAL_OFFSET	0x80U
+#define IPI_BUFFER_TARGET_REMOTE_OFFSET	0x1C0U
+
+#define IPI_BUFFER_MAX_WORDS	8
+
+#define IPI_BUFFER_REQ_OFFSET	0x0U
+#define IPI_BUFFER_RESP_OFFSET	0x20U
+
+/*********************************************************************
+ * Platform specific IPI API declarations
+ ********************************************************************/
+
+/* Configure IPI table for zynqmp */
+void zynqmp_ipi_config_table_init(void);
+
+#endif /* PLAT_IPI_H */
diff --git a/plat/xilinx/zynqmp/include/plat_macros.S b/plat/xilinx/zynqmp/include/plat_macros.S
index e54cfc4..bf1ff82 100644
--- a/plat/xilinx/zynqmp/include/plat_macros.S
+++ b/plat/xilinx/zynqmp/include/plat_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,7 +8,7 @@
 
 #include <arm_macros.S>
 #include <cci_macros.S>
-#include "../zynqmp_def.h"
+#include "zynqmp_def.h"
 
 	/* ---------------------------------------------
 	 * The below required platform porting macro
diff --git a/plat/xilinx/zynqmp/include/plat_pm_common.h b/plat/xilinx/zynqmp/include/plat_pm_common.h
new file mode 100644
index 0000000..1b371cc
--- /dev/null
+++ b/plat/xilinx/zynqmp/include/plat_pm_common.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * Contains platform specific definitions of commonly used macros data types
+ * for PU Power Management. This file should be common for all PU's.
+ */
+
+#ifndef PLAT_PM_COMMON_H
+#define PLAT_PM_COMMON_H
+
+#include <stdint.h>
+#include <common/debug.h>
+#include "pm_defs.h"
+
+#define PAYLOAD_ARG_CNT		6U
+#define PAYLOAD_ARG_SIZE	4U	/* size in bytes */
+
+#define ZYNQMP_TZ_VERSION_MAJOR		1
+#define ZYNQMP_TZ_VERSION_MINOR		0
+#define ZYNQMP_TZ_VERSION		((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
+					ZYNQMP_TZ_VERSION_MINOR)
+#endif /* _PLAT_PM_COMMON_H_ */
diff --git a/plat/xilinx/zynqmp/zynqmp_private.h b/plat/xilinx/zynqmp/include/plat_private.h
similarity index 91%
rename from plat/xilinx/zynqmp/zynqmp_private.h
rename to plat/xilinx/zynqmp/include/plat_private.h
index a8ebceb..99d0bc6 100644
--- a/plat/xilinx/zynqmp/zynqmp_private.h
+++ b/plat/xilinx/zynqmp/include/plat_private.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef ZYNQMP_PRIVATE_H
-#define ZYNQMP_PRIVATE_H
+#ifndef PLAT_PRIVATE_H
+#define PLAT_PRIVATE_H
 
 #include <stdint.h>
 
@@ -39,4 +39,4 @@
 enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32_image_ep_info,
 		       entry_point_info_t *bl33_image_ep_info);
 
-#endif /* ZYNQMP_PRIVATE_H */
+#endif /* PLAT_PRIVATE_H */
diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h
index e3c9fcc..fb10411 100644
--- a/plat/xilinx/zynqmp/include/platform_def.h
+++ b/plat/xilinx/zynqmp/include/platform_def.h
@@ -12,7 +12,7 @@
 #include <drivers/arm/gic_common.h>
 #include <lib/utils_def.h>
 
-#include "../zynqmp_def.h"
+#include "zynqmp_def.h"
 
 /*******************************************************************************
  * Generic platform constants
diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
similarity index 94%
rename from plat/xilinx/zynqmp/zynqmp_def.h
rename to plat/xilinx/zynqmp/include/zynqmp_def.h
index f75530e..8648b9a 100644
--- a/plat/xilinx/zynqmp/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -60,8 +60,10 @@
 #define CRL_APB_BOOT_PIN_MASK		(U(0xf0f) << 0)
 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT	U(9)
 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT	U(1)
-#define CRL_APB_BOOT_ENABLE_PIN_1	(U(0x1) << CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
-#define CRL_APB_BOOT_DRIVE_PIN_1	(U(0x1) << CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
+#define CRL_APB_BOOT_ENABLE_PIN_1	(U(0x1) << \
+					CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
+#define CRL_APB_BOOT_DRIVE_PIN_1	(U(0x1) << \
+					CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
 #define ZYNQMP_BOOTMODE_JTAG		U(0)
 #define ZYNQMP_ULPI_RESET_VAL_HIGH	(CRL_APB_BOOT_ENABLE_PIN_1 | \
 					 CRL_APB_BOOT_DRIVE_PIN_1)
@@ -137,7 +139,7 @@
 #define ZYNQMP_UART0_BASE		0xFF000000
 #define ZYNQMP_UART1_BASE		0xFF010000
 
-#if ZYNQMP_CONSOLE_IS(cadence)
+#if ZYNQMP_CONSOLE_IS(cadence) || ZYNQMP_CONSOLE_IS(dcc)
 # define ZYNQMP_UART_BASE	ZYNQMP_UART0_BASE
 #elif ZYNQMP_CONSOLE_IS(cadence1)
 # define ZYNQMP_UART_BASE	ZYNQMP_UART1_BASE
@@ -167,22 +169,27 @@
 #define ZYNQMP_CSU_IDCODE_OFFSET	0x40
 
 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT	0
-#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK	(0xFFF << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
+#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK	(0xFFF << \
+					ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
 #define ZYNQMP_CSU_IDCODE_XILINX_ID		0x093
 
 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT		12
 #define ZYNQMP_CSU_IDCODE_SVD_MASK		(0x7 << \
 						 ZYNQMP_CSU_IDCODE_SVD_SHIFT)
 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15
-#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xF << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xF << \
+					ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT	19
-#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK	(0x3 << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
+#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK	(0x3 << \
+					ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT		21
-#define ZYNQMP_CSU_IDCODE_FAMILY_MASK		(0x7F << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
+#define ZYNQMP_CSU_IDCODE_FAMILY_MASK		(0x7F << \
+					ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
 #define ZYNQMP_CSU_IDCODE_FAMILY		0x23
 
 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT	28
-#define ZYNQMP_CSU_IDCODE_REVISION_MASK		(0xF << ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
+#define ZYNQMP_CSU_IDCODE_REVISION_MASK		(0xF << \
+					ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
 #define ZYNQMP_CSU_IDCODE_REVISION		0
 
 #define ZYNQMP_CSU_VERSION_OFFSET	0x44
diff --git a/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c
index 11f382a..c499d78 100644
--- a/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c
+++ b/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,9 +16,11 @@
 #include <lib/bakery_lock.h>
 #include <lib/mmio.h>
 
+#include <ipi.h>
+#include <plat_ipi.h>
+#include <plat_private.h>
+
 #include "ipi_mailbox_svc.h"
-#include "../zynqmp_ipi.h"
-#include "../zynqmp_private.h"
 #include "../../../services/spd/trusty/smcall.h"
 
 /*********************************************************************
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index 4183979..8522d3e 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -12,12 +12,12 @@
 #include <drivers/arm/gicv2.h>
 #include <lib/mmio.h>
 #include <lib/psci/psci.h>
+#include <plat_private.h>
 #include <plat/common/platform.h>
 
 #include <plat_arm.h>
 #include "pm_api_sys.h"
 #include "pm_client.h"
-#include "zynqmp_private.h"
 
 uintptr_t zynqmp_sec_entry;
 
diff --git a/plat/xilinx/zynqmp/plat_startup.c b/plat/xilinx/zynqmp/plat_startup.c
index 03f0e3d..cd2c3ba 100644
--- a/plat/xilinx/zynqmp/plat_startup.c
+++ b/plat/xilinx/zynqmp/plat_startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,9 +9,9 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <lib/mmio.h>
+#include <plat_private.h>
 
 #include "zynqmp_def.h"
-#include "zynqmp_private.h"
 
 /*
  * ATFHandoffParams
diff --git a/plat/xilinx/zynqmp/plat_zynqmp.c b/plat/xilinx/zynqmp/plat_zynqmp.c
index ad18aaf..906ce1b 100644
--- a/plat/xilinx/zynqmp/plat_zynqmp.c
+++ b/plat/xilinx/zynqmp/plat_zynqmp.c
@@ -4,10 +4,9 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <plat_private.h>
 #include <plat/common/platform.h>
 
-#include "zynqmp_private.h"
-
 int plat_core_pos_by_mpidr(u_register_t mpidr)
 {
 	if (mpidr & MPIDR_CLUSTER_MASK)
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 35c8983..d147916 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -47,6 +47,7 @@
 
 PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
 				-Iinclude/plat/arm/common/aarch64/		\
+				-Iplat/xilinx/common/include/			\
 				-Iplat/xilinx/zynqmp/include/			\
 				-Iplat/xilinx/zynqmp/pm_service/		\
 				-Iplat/xilinx/zynqmp/ipi_mailbox_service/
@@ -64,6 +65,7 @@
 				plat/arm/common/arm_common.c			\
 				plat/arm/common/arm_gicv2.c			\
 				plat/common/plat_gicv2.c			\
+				plat/xilinx/common/ipi.c			\
 				plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S	\
 				plat/xilinx/zynqmp/aarch64/zynqmp_common.c
 
@@ -71,6 +73,7 @@
 				lib/cpus/aarch64/aem_generic.S			\
 				lib/cpus/aarch64/cortex_a53.S			\
 				plat/common/plat_psci_common.c			\
+				plat/xilinx/common/pm_service/pm_ipi.c		\
 				plat/xilinx/zynqmp/bl31_zynqmp_setup.c		\
 				plat/xilinx/zynqmp/plat_psci.c			\
 				plat/xilinx/zynqmp/plat_zynqmp.c		\
@@ -83,6 +86,5 @@
 				plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c	\
 				plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c	\
 				plat/xilinx/zynqmp/pm_service/pm_api_clock.c	\
-				plat/xilinx/zynqmp/pm_service/pm_ipi.c		\
 				plat/xilinx/zynqmp/pm_service/pm_client.c	\
 				plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index d3f1fbf..44acb4b 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -12,6 +12,7 @@
 #include <drivers/delay_timer.h>
 #include <lib/mmio.h>
 #include <plat/common/platform.h>
+#include <zynqmp_def.h>
 
 #include "pm_api_clock.h"
 #include "pm_api_ioctl.h"
@@ -19,7 +20,6 @@
 #include "pm_client.h"
 #include "pm_common.h"
 #include "pm_ipi.h"
-#include "../zynqmp_def.h"
 
 /**
  * pm_ioctl_get_rpu_oper_mode () - Get current RPU operation mode
diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c
index bebb74c..163e891 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_client.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_client.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,7 +19,8 @@
 #include <lib/mmio.h>
 #include <lib/utils.h>
 
-#include "../zynqmp_def.h"
+#include <plat_ipi.h>
+#include <zynqmp_def.h>
 #include "pm_api_sys.h"
 #include "pm_client.h"
 #include "pm_ipi.h"
@@ -35,6 +36,12 @@
 
 extern const struct pm_ipi apu_ipi;
 
+const struct pm_ipi apu_ipi = {
+	.local_ipi_id = IPI_ID_APU,
+	.remote_ipi_id = IPI_ID_PMU0,
+	.buffer_base = IPI_BUFFER_APU_BASE,
+};
+
 static uint32_t suspend_mode = PM_SUSPEND_MODE_STD;
 
 /* Order in pm_procs_all array must match cpu ids */
diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.h b/plat/xilinx/zynqmp/pm_service/pm_client.h
index 0a34a07..adbb76f 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_client.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_client.h
@@ -21,6 +21,7 @@
 void pm_client_wakeup(const struct pm_proc *proc);
 enum pm_ret_status set_ocm_retention(void);
 enum pm_ret_status pm_set_suspend_mode(uint32_t mode);
+const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid);
 
 /* Global variables to be set in pm_client.c */
 extern const struct pm_proc *primary_proc;
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
index 0b8fc23..faa2827 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -20,7 +20,7 @@
 #include <plat/common/platform.h>
 #endif
 
-#include "../zynqmp_private.h"
+#include <plat_private.h>
 #include "pm_api_sys.h"
 #include "pm_client.h"
 #include "pm_ipi.h"
diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c
index 8d23a01..edb81f5 100644
--- a/plat/xilinx/zynqmp/sip_svc_setup.c
+++ b/plat/xilinx/zynqmp/sip_svc_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,9 +9,9 @@
 #include <common/runtime_svc.h>
 #include <tools_share/uuid.h>
 
+#include <plat_ipi.h>
 #include "ipi_mailbox_svc.h"
 #include "pm_svc_main.h"
-#include "zynqmp_ipi.h"
 
 /* SMC function IDs for SiP Service queries */
 #define ZYNQMP_SIP_SVC_CALL_COUNT	0x8200ff00
@@ -41,6 +41,9 @@
  */
 static int32_t sip_svc_setup(void)
 {
+	/* Configure IPI data for ZynqMP */
+	zynqmp_ipi_config_table_init();
+
 	/* PM implementation as SiP Service */
 	pm_setup();
 
diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index 25359f9..97718d6 100644
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -9,9 +9,9 @@
 #include <drivers/console.h>
 
 #include <plat_arm.h>
+#include <plat_private.h>
 #include <platform_tsp.h>
 
-#include "../zynqmp_private.h"
 
 #define BL32_END (unsigned long)(&__BL32_END__)
 
diff --git a/plat/xilinx/zynqmp/zynqmp_ipi.c b/plat/xilinx/zynqmp/zynqmp_ipi.c
index 54b1838..f57369f 100644
--- a/plat/xilinx/zynqmp/zynqmp_ipi.c
+++ b/plat/xilinx/zynqmp/zynqmp_ipi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,48 +16,12 @@
 #include <lib/bakery_lock.h>
 #include <lib/mmio.h>
 
-#include "zynqmp_ipi.h"
-#include "../zynqmp_private.h"
-
-/*********************************************************************
- * Macros definitions
- ********************************************************************/
-
-/* IPI registers base address */
-#define IPI_REGS_BASE   0xFF300000U
-
-/* IPI registers offsets macros */
-#define IPI_TRIG_OFFSET 0x00U
-#define IPI_OBR_OFFSET  0x04U
-#define IPI_ISR_OFFSET  0x10U
-#define IPI_IMR_OFFSET  0x14U
-#define IPI_IER_OFFSET  0x18U
-#define IPI_IDR_OFFSET  0x1CU
-
-/* IPI register start offset */
-#define IPI_REG_BASE(I) (zynqmp_ipi_table[(I)].ipi_reg_base)
-
-/* IPI register bit mask */
-#define IPI_BIT_MASK(I) (zynqmp_ipi_table[(I)].ipi_bit_mask)
-
-/* IPI secure check */
-#define IPI_SECURE_MASK  0x1U
-#define IPI_IS_SECURE(I) ((zynqmp_ipi_table[(I)].secure_only & \
-			   IPI_SECURE_MASK) ? 1 : 0)
-
-/*********************************************************************
- * Struct definitions
- ********************************************************************/
-
-/* structure to maintain IPI configuration information */
-struct zynqmp_ipi_config {
-	unsigned int ipi_bit_mask;
-	unsigned int ipi_reg_base;
-	unsigned char secure_only;
-};
+#include <ipi.h>
+#include <plat_ipi.h>
+#include <plat_private.h>
 
 /* Zynqmp ipi configuration table */
-const static struct zynqmp_ipi_config zynqmp_ipi_table[] = {
+const static struct ipi_config zynqmp_ipi_table[] = {
 	/* APU IPI */
 	{
 		.ipi_bit_mask = 0x1,
@@ -126,160 +90,11 @@
 	},
 };
 
-/* is_ipi_mb_within_range() - verify if IPI mailbox is within range
- *
- * @local  - local IPI ID
- * @remote - remote IPI ID
- *
- * return - 1 if within range, 0 if not
- */
-static inline int is_ipi_mb_within_range(uint32_t local, uint32_t remote)
-{
-	int ret = 1;
-	uint32_t ipi_total = ARRAY_SIZE(zynqmp_ipi_table);
-
-	if (remote >= ipi_total || local >= ipi_total)
-		ret = 0;
-
-	return ret;
-}
-
-/**
- * ipi_mb_validate() - validate IPI mailbox access
- *
- * @local  - local IPI ID
- * @remote - remote IPI ID
- * @is_secure - indicate if the requester is from secure software
- *
- * return - 0 success, negative value for errors
- */
-int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
-{
-	int ret = 0;
-
-	if (!is_ipi_mb_within_range(local, remote))
-		ret = -EINVAL;
-	else if (IPI_IS_SECURE(local) && !is_secure)
-		ret = -EPERM;
-	else if (IPI_IS_SECURE(remote) && !is_secure)
-		ret = -EPERM;
-
-	return ret;
-}
-
-/**
- * ipi_mb_open() - Open IPI mailbox.
- *
- * @local  - local IPI ID
- * @remote - remote IPI ID
- *
- */
-void ipi_mb_open(uint32_t local, uint32_t remote)
-{
-	mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
-		      IPI_BIT_MASK(remote));
-	mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
-		      IPI_BIT_MASK(remote));
-}
-
-/**
- * ipi_mb_release() - Open IPI mailbox.
- *
- * @local  - local IPI ID
- * @remote - remote IPI ID
- *
- */
-void ipi_mb_release(uint32_t local, uint32_t remote)
-{
-	mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
-		      IPI_BIT_MASK(remote));
-}
-
 /**
- * ipi_mb_enquire_status() - Enquire IPI mailbox status
- *
- * @local  - local IPI ID
- * @remote - remote IPI ID
- *
- * return - 0 idle, positive value for pending sending or receiving,
- *          negative value for errors
- */
-int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
-{
-	int ret = 0;
-	uint32_t status;
-
-	status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
-	if (status & IPI_BIT_MASK(remote))
-		ret |= IPI_MB_STATUS_SEND_PENDING;
-	status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
-	if (status & IPI_BIT_MASK(remote))
-		ret |= IPI_MB_STATUS_RECV_PENDING;
-
-	return ret;
-}
-
-/* ipi_mb_notify() - Trigger IPI mailbox notification
- *
- * @local - local IPI ID
- * @remote - remote IPI ID
- * @is_blocking - if to trigger the notification in blocking mode or not.
- *
- * It sets the remote bit in the IPI agent trigger register.
- *
- */
-void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking)
-{
-	uint32_t status;
-
-	mmio_write_32(IPI_REG_BASE(local) + IPI_TRIG_OFFSET,
-		      IPI_BIT_MASK(remote));
-	if (is_blocking) {
-		do {
-			status = mmio_read_32(IPI_REG_BASE(local) +
-					      IPI_OBR_OFFSET);
-		} while (status & IPI_BIT_MASK(remote));
-	}
-}
-
-/* ipi_mb_ack() - Ack IPI mailbox notification from the other end
- *
- * @local - local IPI ID
- * @remote - remote IPI ID
- *
- * It will clear the remote bit in the isr register.
- *
- */
-void ipi_mb_ack(uint32_t local, uint32_t remote)
-{
-	mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
-		      IPI_BIT_MASK(remote));
-}
-
-/* ipi_mb_disable_irq() - Disable IPI mailbox notification interrupt
- *
- * @local - local IPI ID
- * @remote - remote IPI ID
- *
- * It will mask the remote bit in the idr register.
- *
- */
-void ipi_mb_disable_irq(uint32_t local, uint32_t remote)
-{
-	mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
-		      IPI_BIT_MASK(remote));
-}
-
-/* ipi_mb_enable_irq() - Enable IPI mailbox notification interrupt
- *
- * @local - local IPI ID
- * @remote - remote IPI ID
- *
- * It will mask the remote bit in the idr register.
+ * zynqmp_ipi_config_table_init() - Initialize ZynqMP IPI configuration data
  *
  */
-void ipi_mb_enable_irq(uint32_t local, uint32_t remote)
+void zynqmp_ipi_config_table_init(void)
 {
-	mmio_write_32(IPI_REG_BASE(local) + IPI_IER_OFFSET,
-		      IPI_BIT_MASK(remote));
+	ipi_config_table_init(zynqmp_ipi_table, ARRAY_SIZE(zynqmp_ipi_table));
 }
diff --git a/readme.rst b/readme.rst
index e7fbfb4..1f02bf1 100644
--- a/readme.rst
+++ b/readme.rst
@@ -9,7 +9,7 @@
 -  The `Power State Coordination Interface (PSCI)`_
 -  Trusted Board Boot Requirements (TBBR, Arm DEN0006C-1)
 -  `SMC Calling Convention`_
--  `System Control and Management Interface`_
+-  `System Control and Management Interface (SCMI)`_
 -  `Software Delegated Exception Interface (SDEI)`_
 
 Where possible, the code is designed for reuse or porting to other Armv7-A and
@@ -58,7 +58,7 @@
 
 This release provides a suitable starting point for productization of secure
 world boot and runtime firmware, in either the AArch32 or AArch64 execution
-state.
+states.
 
 Users are encouraged to do their own security validation, including penetration
 testing, on any secure world code derived from TF-A.
@@ -95,13 +95,13 @@
 -  Secure Monitor library code such as world switching, EL1 context management
    and interrupt routing.
    When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
-   AArch64 EL3 Runtime Software must be integrated with a dispatcher component
-   (SPD) to customize the interaction with the SP.
+   AArch64 EL3 Runtime Software must be integrated with a Secure Payload
+   Dispatcher (SPD) component to customize the interaction with the SP.
 
--  A Test SP/SPD to demonstrate AArch64 Secure Monitor functionality and SP
+-  A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
    interaction with PSCI.
 
--  SPDs for the `OP-TEE Secure OS`_, `NVidia Trusted Little Kernel`_
+-  SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
    and `Trusty Secure OS`_.
 
 -  A Trusted Board Boot implementation, conforming to all mandatory TBBR
@@ -136,8 +136,8 @@
 
 -  Support for the GCC, LLVM and Arm Compiler 6 toolchains.
 
--  Support combining several libraries into a self-called "romlib" image, that
-   may be shared across images to reduce memory footprint. The romlib image
+-  Support for combining several libraries into a self-called "romlib" image
+   that may be shared across images to reduce memory footprint. The romlib image
    is stored in ROM but is accessed through a jump-table that may be stored
    in read-write memory, allowing for the library code to be patched.
 
@@ -148,8 +148,8 @@
 Platforms
 ~~~~~~~~~
 
-Various AArch32 and AArch64 builds of this release has been tested on variants
-r0, r1 and r2 of the `Juno Arm Development Platform`_.
+Various AArch32 and AArch64 builds of this release have been tested on r0, r1
+and r2 variants of the `Juno Arm Development Platform`_.
 
 Various AArch64 builds of this release have been tested on the following Arm
 Fixed Virtual Platforms (`FVP`_) without shifted affinities that do not
@@ -229,10 +229,10 @@
 
 Get the TF-A source code from `GitHub`_.
 
-See the `User Guide`_ for instructions on how to install, build and use
-the TF-A with the Arm `FVP`_\ s.
+See the `User Guide`_ for instructions on how to install, build and use TF-A
+with the Arm `FVP`_\ s.
 
-See the `Firmware Design`_ for information on how the TF-A works.
+See the `Firmware Design`_ for information on how TF-A works.
 
 See the `Porting Guide`_ as well for information about how to use this
 software on another Armv7-A or Armv8-A platform.
@@ -267,7 +267,7 @@
 .. _Power State Coordination Interface (PSCI): PSCI_
 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
 .. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
-.. _System Control and Management Interface: SCMI_
+.. _System Control and Management Interface (SCMI): SCMI_
 .. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
 .. _Software Delegated Exception Interface (SDEI): SDEI_
 .. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
@@ -276,7 +276,7 @@
 .. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
 .. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04
 .. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
-.. _NVidia Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
+.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
 .. _Trusty Secure OS: https://source.android.com/security/trusty
 .. _GitHub: https://www.github.com/ARM-software/arm-trusted-firmware
 .. _GitHub issue tracker: https://github.com/ARM-software/tf-issues/issues
diff --git a/services/spd/opteed/teesmc_opteed.h b/services/spd/opteed/teesmc_opteed.h
index 71b8d71..ec821ba 100644
--- a/services/spd/opteed/teesmc_opteed.h
+++ b/services/spd/opteed/teesmc_opteed.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,13 +10,13 @@
 #define TEESMC_OPTEED_H
 
 /*
- * This file specify SMC function IDs used when returning from TEE to the
+ * This file specifies SMC function IDs used when returning from TEE to the
  * secure monitor.
  *
  * All SMC Function IDs indicates SMC32 Calling Convention but will carry
  * full 64 bit values in the argument registers if invoked from Aarch64
  * mode. This violates the SMC Calling Convention, but since this
- * convention only coveres API towards Normwal World it's something that
+ * convention only coveres API towards Normal World it's something that
  * only concerns the OP-TEE Dispatcher in ARM Trusted Firmware and OP-TEE
  * OS at Secure EL1.
  */
diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c
index ffe3319..b1a0477 100644
--- a/services/spd/tlkd/tlkd_main.c
+++ b/services/spd/tlkd/tlkd_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -341,7 +341,7 @@
 
 		/*
 		 * SP has been successfully initialized. Register power
-		 * managemnt hooks with PSCI
+		 * management hooks with PSCI
 		 */
 		psci_register_spd_pm_hook(&tlkd_pm_ops);
 
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index b6ebeeb..c9d73f0 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -100,7 +100,7 @@
 
 	/*
 	 * To avoid the additional overhead in PSCI flow, skip FP context
-	 * saving/restoring in case of CPU suspend and resume, asssuming that
+	 * saving/restoring in case of CPU suspend and resume, assuming that
 	 * when it's needed the PSCI caller has preserved FP context before
 	 * going here.
 	 */
@@ -302,7 +302,7 @@
 
 	/*
 	 * Adjust secondary cpu entry point for 32 bit images to the
-	 * end of exeption vectors
+	 * end of exception vectors
 	 */
 	if ((cpu != 0) && (reg_width == MODE_RW_32)) {
 		INFO("trusty: cpu %d, adjust entry point to 0x%lx\n",
diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c
index d2bd43f..f206724 100644
--- a/services/spd/tspd/tspd_main.c
+++ b/services/spd/tspd/tspd_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -375,7 +375,7 @@
 
 			/*
 			 * TSP has been successfully initialized. Register power
-			 * managemnt hooks with PSCI
+			 * management hooks with PSCI
 			 */
 			psci_register_spd_pm_hook(&tspd_pm);
 
diff --git a/services/std_svc/sdei/sdei_private.h b/services/std_svc/sdei/sdei_private.h
index b945394..1486431 100644
--- a/services/std_svc/sdei/sdei_private.h
+++ b/services/std_svc/sdei/sdei_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -54,7 +54,7 @@
 /*
  * 'info' parameter to SDEI_EVENT_GET_INFO SMC.
  *
- * Note that the SDEI v1.0 speification mistakenly enumerates the
+ * Note that the SDEI v1.0 specification mistakenly enumerates the
  * SDEI_INFO_EV_SIGNALED as SDEI_INFO_SIGNALED. This will be corrected in a
  * future version.
  */