feat(plat/marvell/a3k): add north and south bridge reset registers
These registers make it is possible to do external resets of A3700
peripherals. Most peripherals are reset by clearing a particular bit,
but some need setting the bit. Reflect this via "_N" suffix in macro
names.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iacef5e671746b831b5beea9e4fdcc59d8de84edc
diff --git a/plat/marvell/armada/a3k/common/include/a3700_plat_def.h b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
index 83d9561..4d45e15 100644
--- a/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
+++ b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
@@ -51,6 +51,41 @@
#define MVEBU_CCI_BASE 0xFE000000
/*****************************************************************************
+ * North and south bridge reset registers
+ *****************************************************************************
+ */
+#define MVEBU_NB_RESET_REG (MVEBU_REGS_BASE + 0x12400)
+#define MVEBU_NB_RESET_I2C1_N (1 << 0)
+#define MVEBU_NB_RESET_1WIRE_N (1 << 1)
+#define MVEBU_NB_RESET_SPI_N (1 << 2)
+#define MVEBU_NB_RESET_UART_N (1 << 3)
+#define MVEBU_NB_RESET_XTL_N (1 << 4)
+#define MVEBU_NB_RESET_I2C2_N (1 << 5)
+#define MVEBU_NB_RESET_UART2_N (1 << 6)
+#define MVEBU_NB_RESET_AVS_N (1 << 7)
+#define MVEBU_NB_RESET_DDR_N (1 << 10)
+#define MVEBU_NB_RESET_SETM_N (1 << 11)
+#define MVEBU_NB_RESET_DMA_N (1 << 12)
+#define MVEBU_NB_RESET_TSECM_N (1 << 13)
+#define MVEBU_NB_RESET_SDIO_N (1 << 14)
+#define MVEBU_NB_RESET_SATA_N (1 << 15)
+#define MVEBU_NB_RESET_PWRMGT_N (1 << 16)
+#define MVEBU_NB_RESET_OTP_N (1 << 17)
+#define MVEBU_NB_RESET_EIP_N (1 << 18)
+#define MVEBU_SB_RESET_REG (MVEBU_REGS_BASE + 0x18600)
+#define MVEBU_SB_RESET_MCIPHY (1 << 1)
+#define MVEBU_SB_RESET_SDIO_N (1 << 2)
+#define MVEBU_SB_RESET_PCIE_N (1 << 3)
+#define MVEBU_SB_RESET_GBE1_N (1 << 4)
+#define MVEBU_SB_RESET_GBE0_N (1 << 5)
+#define MVEBU_SB_RESET_USB2PHY (1 << 6)
+#define MVEBU_SB_RESET_USB2HPHY (1 << 7)
+#define MVEBU_SB_RESET_MCI_N (1 << 8)
+#define MVEBU_SB_RESET_PWRMGT_N (1 << 9)
+#define MVEBU_SB_RESET_EBM_N (1 << 10)
+#define MVEBU_SB_RESET_OTP_N (1 << 11)
+
+/*****************************************************************************
* North and south bridge register base
*****************************************************************************
*/