Merge pull request #253 from danh-arm/dh/deps-for-v1.1
Move up dependency versions in user guide
diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md
index b913f5f..2368fd2 100644
--- a/docs/cpu-specific-build-macros.md
+++ b/docs/cpu-specific-build-macros.md
@@ -21,7 +21,7 @@
ARM Trusted Firmware exports a series of build flags which control the
errata workarounds that are applied to each CPU by the reset handler. The
-errata details can be found in the CPU specifc errata documents published
+errata details can be found in the CPU specific errata documents published
by ARM. The errata workarounds are implemented for a particular revision
or a set of processor revisions. This is checked by reset handler at runtime.
Each errata workaround is identified by its `ID` as specified in the processor's
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index acfef4e..f0c2f62 100644
--- a/docs/firmware-design.md
+++ b/docs/firmware-design.md
@@ -425,7 +425,7 @@
PSTATE.EL = 3
PSTATE.RW = 1
PSTATE.DAIF = 0xf
- CTLR_EL3.EE = 0
+ SCTLR_EL3.EE = 0
X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
platform code in BL3-1:
@@ -1060,9 +1060,9 @@
The BL entrypoint code first invokes the `plat_reset_handler()` to allow
the platform to perform any system initialization required and any system
-errata wrokarounds that needs to be applied. The `get_cpu_ops_ptr()` reads
+errata workarounds that needs to be applied. The `get_cpu_ops_ptr()` reads
the current CPU midr, finds the matching `cpu_ops` entry in the `cpu_ops`
-array and returns it. Note that only the part number and implementator fields
+array and returns it. Note that only the part number and implementer fields
in midr are used to find the matching `cpu_ops` entry. The `reset_func()` in
the returned `cpu_ops` is then invoked which executes the required reset
handling for that CPU and also any errata workarounds enabled by the platform.
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 09cd7d5..5a04c54 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -1445,9 +1445,10 @@
It is mandatory to implement at least one storage driver. For the FVP the
Firmware Image Package(FIP) driver is provided as the default means to load data
from storage (see the "Firmware Image Package" section in the [User Guide]).
-The storage layer is described in the header file `include/io_storage.h`. The
-implementation of the common library is in `lib/io_storage.c` and the driver
-files are located in `drivers/io/`.
+The storage layer is described in the header file
+`include/drivers/io/io_storage.h`. The implementation of the common library
+is in `drivers/io/io_storage.c` and the driver files are located in
+`drivers/io/`.
Each IO driver must provide `io_dev_*` structures, as described in
`drivers/io/io_driver.h`. These are returned via a mandatory registration
diff --git a/docs/user-guide.md b/docs/user-guide.md
index ab981fd..ab443ba 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -510,7 +510,7 @@
git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Not all required features are available in the kernel mainline yet. These
- can be obtained from the ARM-software EDK2 repository instead:
+ can be obtained from the ARM-software Linux repository instead:
cd linux
git remote add -f --tags arm-software https://github.com/ARM-software/linux.git
@@ -789,7 +789,6 @@
-C cluster0.NUM_CORES=4 \
-C cluster1.NUM_CORES=4 \
-C cache_state_modelled=1 \
- -C bp.pl011_uart0.untimed_fifos=1 \
-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
@@ -807,7 +806,6 @@
-C bp.secure_memory=1 \
-C bp.tzc_400.diagnostics=1 \
-C cache_state_modelled=1 \
- -C bp.pl011_uart0.untimed_fifos=1 \
-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
@@ -827,7 +825,6 @@
-C cluster0.NUM_CORES=4 \
-C cluster1.NUM_CORES=4 \
-C cache_state_modelled=1 \
- -C bp.pl011_uart0.untimed_fifos=1 \
-C cluster0.cpu0.RVBAR=0x04023000 \
-C cluster0.cpu1.RVBAR=0x04023000 \
-C cluster0.cpu2.RVBAR=0x04023000 \
@@ -854,7 +851,6 @@
-C bp.secure_memory=1 \
-C bp.tzc_400.diagnostics=1 \
-C cache_state_modelled=1 \
- -C bp.pl011_uart0.untimed_fifos=1 \
-C cluster0.cpu0.RVBARADDR=0x04023000 \
-C cluster0.cpu1.RVBARADDR=0x04023000 \
-C cluster0.cpu2.RVBARADDR=0x04023000 \