Tegra: sanity check members of the "from_bl2" struct
This patch checks that the pointers to BL3-3 and BL3-2 ep_info
structs are valid before accessing them. Add some INFO prints
in the BL3-1 setup path for early debugging purposes.
Change-Id: I62b23fa870f1b2fb783c8de69aab819f1749d15a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 0fd7c82..1635bfb 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -37,6 +37,7 @@
#include <cortex_a57.h>
#include <cortex_a53.h>
#include <debug.h>
+#include <denver.h>
#include <errno.h>
#include <memctrl.h>
#include <mmio.h>
@@ -110,7 +111,9 @@
{
plat_params_from_bl2_t *plat_params =
(plat_params_from_bl2_t *)plat_params_from_bl2;
-
+#if DEBUG
+ int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
+#endif
/*
* Configure the UART port to be used as the console
*/
@@ -120,12 +123,18 @@
/* Initialise crash console */
plat_crash_console_init();
+ INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
+ "Denver" : "ARM", read_mpidr());
+
/*
* Copy BL3-3, BL3-2 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
- bl33_image_ep_info = *from_bl2->bl33_ep_info;
- bl32_image_ep_info = *from_bl2->bl32_ep_info;
+ if (from_bl2->bl33_ep_info)
+ bl33_image_ep_info = *from_bl2->bl33_ep_info;
+
+ if (from_bl2->bl32_ep_info)
+ bl32_image_ep_info = *from_bl2->bl32_ep_info;
/*
* Parse platform specific parameters - TZDRAM aperture size
@@ -168,6 +177,8 @@
/* Initialize the gic cpu and distributor interfaces */
tegra_gic_setup();
+
+ INFO("BL3-1: Tegra platform setup complete\n");
}
/*******************************************************************************
@@ -215,6 +226,8 @@
/* enable the MMU */
enable_mmu_el3(0);
+
+ INFO("BL3-1: Tegra: MMU enabled\n");
}
/*******************************************************************************