Merge pull request #1066 from islmit01/im/enable_cnp_bit
Enable CnP bit for ARMv8.2 CPUs
diff --git a/Makefile b/Makefile
index b57b212..0a64514 100644
--- a/Makefile
+++ b/Makefile
@@ -571,10 +571,10 @@
locate-checkpatch:
ifndef CHECKPATCH
- $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl")
+ $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/scripts/checkpatch.pl")
else
ifeq (,$(wildcard ${CHECKPATCH}))
- $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl")
+ $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/scripts/checkpatch.pl")
endif
endif
diff --git a/docs/diagrams/Makefile b/docs/diagrams/Makefile
new file mode 100644
index 0000000..de7d8f3
--- /dev/null
+++ b/docs/diagrams/Makefile
@@ -0,0 +1,74 @@
+#
+# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+# This Makefile generates the image files used in the ARM Trusted Firmware
+# document from the dia file.
+#
+# The PNG files in the present directory have been generated using Dia version
+# 0.97.2, which can be obtained from https://wiki.gnome.org/Apps/Dia/Download
+#
+
+# generate_image use the tool dia generate png from dia file
+# $(1) = layers
+# $(2) = image file name
+# $(3) = image file format
+# $(4) = addition opts
+# $(5) = dia source file
+define generate_image
+ dia --show-layers=$(1) --filter=$(3) --export=$(2) $(4) $(5)
+endef
+
+RESET_DIA = reset_code_flow.dia
+RESET_PNGS = \
+ default_reset_code.png \
+ reset_code_no_cpu_check.png \
+ reset_code_no_boot_type_check.png \
+ reset_code_no_checks.png \
+
+# The $(RESET_DIA) file is organized in several layers.
+# Each image is generated by combining and exporting the appropriate set of
+# layers.
+default_reset_code_layers = "Frontground,Background,cpu_type_check,boot_type_check"
+reset_code_no_cpu_check_layers = "Frontground,Background,no_cpu_type_check,boot_type_check"
+reset_code_no_boot_type_check_layers= "Frontground,Background,cpu_type_check,no_boot_type_check"
+reset_code_no_checks_layers = "Frontground,Background,no_cpu_type_check,no_boot_type_check"
+
+default_reset_code_opts =
+reset_code_no_cpu_check_opts =
+reset_code_no_boot_type_check_opts =
+reset_code_no_checks_opts =
+
+INT_DIA = int_handling.dia
+INT_PNGS = \
+ sec-int-handling.png \
+ non-sec-int-handling.png
+
+# The $(INT_DIA) file is organized in several layers.
+# Each image is generated by combining and exporting the appropriate set of
+# layers.
+non-sec-int-handling_layers = "non_sec_int_bg,legend,non_sec_int_note,non_sec_int_handling"
+sec-int-handling_layers = "sec_int_bg,legend,sec_int_note,sec_int_handling"
+
+non-sec-int-handling_opts = --size=1692x
+sec-int-handling_opts = --size=1570x
+
+XLAT_DIA = xlat_align.dia
+XLAT_PNG = xlat_align.png
+
+xlat_align_layers = "bg,translations"
+xlat_align_opts =
+
+all:$(RESET_PNGS) $(INT_PNGS) $(XLAT_PNG)
+
+$(RESET_PNGS):$(RESET_DIA)
+ $(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<)
+
+$(INT_PNGS):$(INT_DIA)
+ $(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<)
+
+$(XLAT_PNG):$(XLAT_DIA)
+ $(call generate_image,$($(patsubst %.png,%_layers,$@)),$(patsubst %.png,%.svg,$@),svg,$($(patsubst %.png,%_opts,$@)),$<)
+ inkscape -z $(patsubst %.png,%.svg,$@) -e $@ -d 45
diff --git a/docs/diagrams/generate_reset_images.sh b/docs/diagrams/generate_reset_images.sh
deleted file mode 100755
index eef5648..0000000
--- a/docs/diagrams/generate_reset_images.sh
+++ /dev/null
@@ -1,41 +0,0 @@
-#! /bin/bash
-
-#
-# This script generates the image files used in the ARM Trusted Firmware Reset
-# Design document from the 'reset_code_flow.dia' file.
-#
-# The PNG files in the present directory have been generated using Dia version
-# 0.97.2, which can be obtained from https://wiki.gnome.org/Apps/Dia/Download
-#
-
-set -e
-
-# Usage: generate_image <layers> <image_filename>
-function generate_image
-{
- dia \
- --show-layers=$1 \
- --filter=png \
- --export=$2 \
- reset_code_flow.dia
-
-}
-
-# The 'reset_code_flow.dia' file is organized in several layers.
-# Each image is generated by combining and exporting the appropriate set of
-# layers.
-generate_image \
- Frontground,Background,cpu_type_check,boot_type_check \
- default_reset_code.png
-
-generate_image \
- Frontground,Background,no_cpu_type_check,boot_type_check \
- reset_code_no_cpu_check.png
-
-generate_image \
- Frontground,Background,cpu_type_check,no_boot_type_check \
- reset_code_no_boot_type_check.png
-
-generate_image \
- Frontground,Background,no_cpu_type_check,no_boot_type_check \
- reset_code_no_checks.png
diff --git a/docs/diagrams/generate_xlat_images.sh b/docs/diagrams/generate_xlat_images.sh
deleted file mode 100755
index 9daef5f..0000000
--- a/docs/diagrams/generate_xlat_images.sh
+++ /dev/null
@@ -1,26 +0,0 @@
-#! /bin/bash
-
-#
-# This script generates the image file used in the ARM Trusted Firmware
-# Translation Tables Library V2 Design document from the 'xlat_align.dia' file.
-#
-
-set -e
-
-# Usage: generate_image <dia_filename> <layers> <image_filename>
-function generate_image
-{
- dia \
- --show-layers=$2 \
- --filter=svg \
- --export=$3 \
- $1
-
-}
-
-generate_image \
- xlat_align.dia \
- bg,translations \
- xlat_align.svg
-
-inkscape -z xlat_align.svg -e xlat_align.png -d 45
diff --git a/docs/diagrams/int_handling.dia b/docs/diagrams/int_handling.dia
new file mode 100644
index 0000000..12aa186
--- /dev/null
+++ b/docs/diagrams/int_handling.dia
Binary files differ
diff --git a/docs/diagrams/non-sec-int-handling.png b/docs/diagrams/non-sec-int-handling.png
index 1a5f629..64082c9 100644
--- a/docs/diagrams/non-sec-int-handling.png
+++ b/docs/diagrams/non-sec-int-handling.png
Binary files differ
diff --git a/docs/diagrams/sec-int-handling.png b/docs/diagrams/sec-int-handling.png
index 2ebbca4..fa5c340 100644
--- a/docs/diagrams/sec-int-handling.png
+++ b/docs/diagrams/sec-int-handling.png
Binary files differ
diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst
index facf016..997d29b 100644
--- a/docs/firmware-design.rst
+++ b/docs/firmware-design.rst
@@ -1045,8 +1045,8 @@
``bl31_main()`` will set up the return to the normal world firmware BL33 and
continue the boot process in the normal world.
-#. .. rubric:: Crash Reporting in BL31
- :name: crash-reporting-in-bl31
+Crash Reporting in BL31
+-----------------------
BL31 implements a scheme for reporting the processor state when an unhandled
exception is encountered. The reporting mechanism attempts to preserve all the
@@ -1864,7 +1864,7 @@
`offset_address`: The offset address at which the corresponding payload data
can be found. The offset is calculated from the ToC base address.
`size`: The size of the corresponding payload data in bytes.
- `flags`: Flags associated with this entry. Non are yet defined.
+ `flags`: Flags associated with this entry. None are yet defined.
Firmware Image Package creation tool
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -2333,8 +2333,8 @@
#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``.
-#. .. rubric:: ARMv8 Architecture Extensions
- :name: armv8-architecture-extensions
+ARMv8 Architecture Extensions
+-----------------------------
ARM Trusted Firmware makes use of ARMv8 Architecture Extensions where
applicable. This section lists the usage of Architecture Extensions, and build
diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h
index 24a9c6c..8e86df4 100644
--- a/include/lib/cpus/aarch32/cortex_a53.h
+++ b/include/lib/cpus/aarch32/cortex_a53.h
@@ -40,11 +40,11 @@
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A53_ACTLR p15, 0, c15
+#define CORTEX_A53_CPUACTLR p15, 0, c15
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT 44
-#define CORTEX_A53_ACTLR_ENDCCASCI (1 << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
-#define CORTEX_A53_ACTLR_DTAH (1 << 24)
+#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT 44
+#define CORTEX_A53_CPUACTLR_ENDCCASCI (1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
+#define CORTEX_A53_CPUACTLR_DTAH (1 << 24)
/*******************************************************************************
* L2 Auxiliary Control register specific definitions.
@@ -67,4 +67,16 @@
******************************************************************************/
#define CORTEX_A53_L2MERRSR p15, 3, c15
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A53_ACTLR CORTEX_A53_CPUACTLR
+
+#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT
+#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_ENDCCASCI
+#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_DTAH
+#endif /* !ERROR_DEPRECATED */
+
#endif /* __CORTEX_A53_H__ */
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h
index 1486b98..d3ae5b9 100644
--- a/include/lib/cpus/aarch32/cortex_a57.h
+++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -6,6 +6,7 @@
#ifndef __CORTEX_A57_H__
#define __CORTEX_A57_H__
+#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
#define CORTEX_A57_MIDR 0x410FD070
@@ -24,13 +25,13 @@
******************************************************************************/
#define CORTEX_A57_ECTLR p15, 1, c15
-#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6)
-#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
-#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
-#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
+#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
+#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
+#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
+#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0
-#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
+#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
@@ -40,28 +41,28 @@
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A57_ACTLR p15, 0, c15
+#define CORTEX_A57_CPUACTLR p15, 0, c15
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59)
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
-#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52)
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49)
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44)
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38)
-#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27)
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25)
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
+#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
+#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
+#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
+#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
+#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
+#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
+#define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)
+#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25)
+#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
-#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
+#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
-#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
-#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
+#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
+#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
-#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
-#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Extended Control register specific definitions.
@@ -69,11 +70,29 @@
#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0
-#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
+#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CORTEX_A57_L2MERRSR p15, 3, c15
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A57_ACTLR CORTEX_A57_CPUACTLR
+
+#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
+#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
+#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_DIS_OVERREAD
+#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
+#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_DCC_AS_DCCI
+#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
+#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_DIS_STREAMING
+#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_DIS_L1_STREAMING
+#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
+#endif /* !ERROR_DEPRECATED */
+
#endif /* __CORTEX_A57_H__ */
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 59057bc..306253d 100644
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -6,6 +6,7 @@
#ifndef __CORTEX_A72_H__
#define __CORTEX_A72_H__
+#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
#define CORTEX_A72_MIDR 0x410FD080
@@ -13,42 +14,54 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_A72_ECTLR p15, 1, c15
+#define CORTEX_A72_ECTLR p15, 1, c15
-#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
-#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
-#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
-#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
+#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
+#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
+#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
+#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
-#define CORTEX_A72_MERRSR p15, 2, c15
+#define CORTEX_A72_MERRSR p15, 2, c15
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A72_ACTLR p15, 0, c15
+#define CORTEX_A72_CPUACTLR p15, 0, c15
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
+#define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
+#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
+#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
-#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
+#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
-#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
-#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
+#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
+#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
-#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
-#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
-#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
-#define CORTEX_A72_L2MERRSR p15, 3, c15
+#define CORTEX_A72_L2MERRSR p15, 3, c15
+
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR
+
+#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
+#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA
+#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_DCC_AS_DCCI
+#endif /* !ERROR_DEPRECATED */
#endif /* __CORTEX_A72_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 6627dcf..22c6800 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -22,53 +22,70 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
+#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
-#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
+#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
-#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
-#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
+#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
-#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
-#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
+#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
-#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
+#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A53_ACTLR_EL1 S3_1_C15_C2_0
+#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT U(44)
-#define CORTEX_A53_ACTLR_ENDCCASCI (U(1) << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
-#define CORTEX_A53_ACTLR_RADIS_SHIFT U(27)
-#define CORTEX_A53_ACTLR_RADIS (U(3) << CORTEX_A53_ACTLR_RADIS_SHIFT)
-#define CORTEX_A53_ACTLR_L1RADIS_SHIFT U(25)
-#define CORTEX_A53_ACTLR_L1RADIS (U(3) << CORTEX_A53_ACTLR_L1RADIS_SHIFT)
-#define CORTEX_A53_ACTLR_DTAH_SHIFT U(24)
-#define CORTEX_A53_ACTLR_DTAH (U(1) << CORTEX_A53_ACTLR_DTAH_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44)
+#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27)
+#define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25)
+#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24)
+#define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
/*******************************************************************************
* L2 Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
+#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
-#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
-#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
+#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
+#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
/*******************************************************************************
* L2 Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
+#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
-#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
-#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
+#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
+#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
-#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
+#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
+
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions
+ * so as not to break platforms that continue using them.
+ */
+#define CORTEX_A53_ACTLR_EL1 CORTEX_A53_CPUACTLR_EL1
+
+#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT
+#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
+#define CORTEX_A53_ACTLR_RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT
+#define CORTEX_A53_ACTLR_RADIS CORTEX_A53_CPUACTLR_EL1_RADIS
+#define CORTEX_A53_ACTLR_L1RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT
+#define CORTEX_A53_ACTLR_L1RADIS CORTEX_A53_CPUACTLR_EL1_L1RADIS
+#define CORTEX_A53_ACTLR_DTAH_SHIFT CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT
+#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_EL1_DTAH
+#endif /* !ERROR_DEPRECATED */
#endif /* __CORTEX_A53_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 20d11e1..070108d 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -6,6 +6,7 @@
#ifndef __CORTEX_A57_H__
#define __CORTEX_A57_H__
+#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
#define CORTEX_A57_MIDR U(0x410FD070)
@@ -40,30 +41,30 @@
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A57_ACTLR_EL1 S3_1_C15_C2_0
+#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
-#define CORTEX_A57_ACTLR_DIS_OVERREAD (ULL(1) << 52)
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI (ULL(1) << 44)
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
-#define CORTEX_A57_ACTLR_DIS_STREAMING (ULL(3) << 27)
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (ULL(3) << 25)
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
+#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
+#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
+#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
+#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
-#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
+#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
-#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
+#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
-#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
-#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
+#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
+#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
-#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21)
+#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21)
/*******************************************************************************
* L2 Extended Control register specific definitions.
@@ -78,4 +79,22 @@
******************************************************************************/
#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A57_ACTLR_EL1 CORTEX_A57_CPUACTLR_EL1
+
+#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
+#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
+#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
+#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
+#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
+#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
+#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING
+#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING
+#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
+#endif /* !ERROR_DEPRECATED */
+
#endif /* __CORTEX_A57_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index 90f0abd..aed714c 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -6,49 +6,62 @@
#ifndef __CORTEX_A72_H__
#define __CORTEX_A72_H__
+#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
-#define CORTEX_A72_MIDR 0x410FD080
+#define CORTEX_A72_MIDR 0x410FD080
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
+#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
-#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
-#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
-#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
-#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
+#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
+#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
+#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
+#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
-#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
+#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0
+#define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
+#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
+#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
+#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
-#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
+#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
-#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
+#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
-#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
-#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
-#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
-#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
+#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
+
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR_EL1
+
+#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
+#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
+#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
+#endif /* !ERROR_DEPRECATED */
#endif /* __CORTEX_A72_H__ */
diff --git a/include/plat/arm/board/common/drivers/norflash.h b/include/plat/arm/board/common/drivers/norflash.h
index e74635e..5763b36 100644
--- a/include/plat/arm/board/common/drivers/norflash.h
+++ b/include/plat/arm/board/common/drivers/norflash.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,6 +19,7 @@
#define NOR_CMD_WORD_PROGRAM 0x40
#define NOR_CMD_BLOCK_ERASE 0x20
#define NOR_CMD_LOCK_UNLOCK 0x60
+#define NOR_CMD_BLOCK_ERASE_ACK 0xD0
/* Second bus cycle */
#define NOR_LOCK_BLOCK 0x01
@@ -37,8 +38,9 @@
/* Public API */
void nor_send_cmd(uintptr_t base_addr, unsigned long cmd);
int nor_word_program(uintptr_t base_addr, unsigned long data);
-void nor_lock(uintptr_t base_addr);
-void nor_unlock(uintptr_t base_addr);
+int nor_lock(uintptr_t base_addr);
+int nor_unlock(uintptr_t base_addr);
+int nor_erase(uintptr_t base_addr);
#endif /* __NORFLASH_H_ */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 55747bf..106cd74 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -97,16 +97,18 @@
#ifdef SPD_opteed
/*
- * BL2 needs to map 3.5MB from 512KB offset in TZC_DRAM1 in order to
- * load/authenticate the trusted os extra image. The first 512KB of TZC_DRAM1
- * are reserved for trusted os (OPTEE). The extra image loading for OPTEE is
- * paged image which only include the paging part using virtual memory but
- * without "init" data. OPTEE will copy the "init" data (from pager image) to
- * the first 512KB of TZC_DRAM, and then copy the extra image behind the "init"
- * data.
+ * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
+ * load/authenticate the trusted os extra image. The first 512KB of
+ * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
+ * for OPTEE is paged image which only include the paging part using
+ * virtual memory but without "init" data. OPTEE will copy the "init" data
+ * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
+ * extra image behind the "init" data.
*/
-#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + 0x80000)
-#define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x380000
+#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
+ ARM_AP_TZC_DRAM1_SIZE - \
+ ARM_OPTEE_PAGEABLE_LOAD_SIZE)
+#define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000
#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
ARM_OPTEE_PAGEABLE_LOAD_BASE, \
ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 3a73776..f0e9767 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -45,7 +45,7 @@
* Use this macro to instantiate lock before it is used in below
* arm_lock_xxx() macros
*/
-#define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock);
+#define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock)
#define ARM_LOCK_GET_INSTANCE (&arm_lock)
/*
* These are wrapper macros to the Coherent Memory Bakery Lock API.
@@ -59,7 +59,7 @@
/*
* Empty macros for all other BL stages other than BL31 and BL32
*/
-#define ARM_INSTANTIATE_LOCK
+#define ARM_INSTANTIATE_LOCK static int arm_lock __unused
#define ARM_LOCK_GET_INSTANCE 0
#define arm_lock_init()
#define arm_lock_get()
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S
index bc2c762..74cedc3 100644
--- a/lib/cpus/aarch32/cortex_a53.S
+++ b/lib/cpus/aarch32/cortex_a53.S
@@ -84,9 +84,9 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A53_ACTLR
- orr64_imm r0, r1, CORTEX_A53_ACTLR_DTAH
- stcopr16 r0, r1, CORTEX_A53_ACTLR
+ ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A53_CPUACTLR_DTAH
+ stcopr16 r0, r1, CORTEX_A53_CPUACTLR
1:
bx lr
endfunc a53_disable_non_temporal_hint
@@ -118,9 +118,9 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A53_ACTLR
- orr64_imm r0, r1, CORTEX_A53_ACTLR_ENDCCASCI
- stcopr16 r0, r1, CORTEX_A53_ACTLR
+ ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A53_CPUACTLR_ENDCCASCI
+ stcopr16 r0, r1, CORTEX_A53_CPUACTLR
1:
bx lr
endfunc errata_a53_855873_wa
diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S
index a791e4e..e4aad79 100644
--- a/lib/cpus/aarch32/cortex_a57.S
+++ b/lib/cpus/aarch32/cortex_a57.S
@@ -67,9 +67,9 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_806969_wa
@@ -111,9 +111,9 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_DCC_AS_DCCI
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DCC_AS_DCCI
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_813420_wa
@@ -143,9 +143,9 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_OVERREAD
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_OVERREAD
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc a57_disable_ldnp_overread
@@ -172,9 +172,9 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_826974_wa
@@ -201,9 +201,9 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_826977_wa
@@ -230,15 +230,15 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
/*
- * Setting the relevant bits in CORTEX_A57_ACTLR has to be done in 2
+ * Setting the relevant bits in CORTEX_A57_CPUACTLR has to be done in 2
* instructions here because the resulting bitmask doesn't fit in a
* 16-bit value so it cannot be encoded in a single instruction.
*/
- orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
- orr64_imm r0, r1, (CORTEX_A57_ACTLR_DIS_L1_STREAMING | CORTEX_A57_ACTLR_DIS_STREAMING)
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
+ orr64_imm r0, r1, (CORTEX_A57_CPUACTLR_DIS_L1_STREAMING | CORTEX_A57_CPUACTLR_DIS_STREAMING)
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_828024_wa
@@ -265,9 +265,9 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_829520_wa
@@ -294,9 +294,9 @@
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r1, r1, CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_833471_wa
diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S
index cdd83ad..d164cfd 100644
--- a/lib/cpus/aarch32/cortex_a72.S
+++ b/lib/cpus/aarch32/cortex_a72.S
@@ -29,9 +29,9 @@
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
- ldcopr16 r0, r1, CORTEX_A72_ACTLR
- orr64_imm r0, r1, CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
- stcopr16 r0, r1, CORTEX_A72_ACTLR
+ ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
+ stcopr16 r0, r1, CORTEX_A72_CPUACTLR
isb
dsb ish
bx lr
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 7a17f8f..3e480bc 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -93,9 +93,9 @@
mov x17, x30
bl check_errata_disable_non_temporal_hint
cbz x0, 1f
- mrs x1, CORTEX_A53_ACTLR_EL1
- orr x1, x1, #CORTEX_A53_ACTLR_DTAH
- msr CORTEX_A53_ACTLR_EL1, x1
+ mrs x1, CORTEX_A53_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH
+ msr CORTEX_A53_CPUACTLR_EL1, x1
1:
ret x17
endfunc a53_disable_non_temporal_hint
@@ -126,9 +126,9 @@
bl check_errata_855873
cbz x0, 1f
- mrs x1, CORTEX_A53_ACTLR_EL1
- orr x1, x1, #CORTEX_A53_ACTLR_ENDCCASCI
- msr CORTEX_A53_ACTLR_EL1, x1
+ mrs x1, CORTEX_A53_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
+ msr CORTEX_A53_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a53_855873_wa
@@ -300,7 +300,7 @@
mrs x8, CORTEX_A53_ECTLR_EL1
mrs x9, CORTEX_A53_MERRSR_EL1
mrs x10, CORTEX_A53_L2MERRSR_EL1
- mrs x11, CORTEX_A53_ACTLR_EL1
+ mrs x11, CORTEX_A53_CPUACTLR_EL1
ret
endfunc cortex_a53_cpu_reg_dump
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 9e8480a..289d0d4 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -78,9 +78,9 @@
mov x17, x30
bl check_errata_806969
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_806969_wa
@@ -120,9 +120,9 @@
mov x17, x30
bl check_errata_813420
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_DCC_AS_DCCI
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_813420_wa
@@ -150,9 +150,9 @@
mov x17, x30
bl check_errata_disable_ldnp_overread
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_DIS_OVERREAD
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc a57_disable_ldnp_overread
@@ -177,9 +177,9 @@
mov x17, x30
bl check_errata_826974
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_826974_wa
@@ -204,9 +204,9 @@
mov x17, x30
bl check_errata_826977
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_826977_wa
@@ -231,16 +231,16 @@
mov x17, x30
bl check_errata_828024
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
/*
* Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
* instructions here because the resulting bitmask doesn't fit in a
* 16-bit value so it cannot be encoded in a single instruction.
*/
- orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
- orr x1, x1, #(CORTEX_A57_ACTLR_DIS_L1_STREAMING | \
- CORTEX_A57_ACTLR_DIS_STREAMING)
- msr CORTEX_A57_ACTLR_EL1, x1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
+ orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \
+ CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING)
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_828024_wa
@@ -265,9 +265,9 @@
mov x17, x30
bl check_errata_829520
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_829520_wa
@@ -292,9 +292,9 @@
mov x17, x30
bl check_errata_833471
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_833471_wa
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index 0307627..5de2bf0 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,9 +42,9 @@
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
- mrs x0, CORTEX_A72_ACTLR_EL1
- orr x0, x0, #CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
- msr CORTEX_A72_ACTLR_EL1, x0
+ mrs x0, CORTEX_A72_CPUACTLR_EL1
+ orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
+ msr CORTEX_A72_CPUACTLR_EL1, x0
isb
dsb ish
ret
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 5257bf1..3d26056 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -229,7 +229,7 @@
/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx),
CTX_SCTLR_EL1);
- sctlr_elx &= ~SCTLR_EE_BIT;
+ sctlr_elx &= SCTLR_EE_BIT;
sctlr_elx |= SCTLR_EL2_RES1;
write_sctlr_el2(sctlr_elx);
} else if (EL_IMPLEMENTED(2)) {
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index f31b323..4502c24 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -194,8 +194,15 @@
unsigned int cpu_idx,
plat_local_state_t req_pwr_state)
{
+ /*
+ * This should never happen, we have this here to avoid
+ * "array subscript is above array bounds" errors in GCC.
+ */
assert(pwrlvl > PSCI_CPU_PWR_LVL);
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
+#pragma GCC diagnostic pop
}
/******************************************************************************
diff --git a/plat/arm/board/common/drivers/norflash/norflash.c b/plat/arm/board/common/drivers/norflash/norflash.c
index cc63d75..722cf33 100644
--- a/plat/arm/board/common/drivers/norflash/norflash.c
+++ b/plat/arm/board/common/drivers/norflash/norflash.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,8 +8,6 @@
#include <mmio.h>
#include <norflash.h>
-/* Helper macros to access two flash banks in parallel */
-#define NOR_2X16(d) ((d << 16) | (d & 0xffff))
/*
* DWS ready poll retries. The number of retries in this driver have been
@@ -17,84 +15,182 @@
* model
*/
#define DWS_WORD_PROGRAM_RETRIES 1000
+#define DWS_WORD_ERASE_RETRIES 3000000
+#define DWS_WORD_LOCK_RETRIES 1000
+
+/* Helper macro to detect end of command */
+#define NOR_CMD_END (NOR_DWS | NOR_DWS << 16l)
/*
- * Poll Write State Machine. Return values:
+ * This file supplies a low level interface to the vexpress NOR flash
+ * memory of juno and fvp. This memory is organized as an interleaved
+ * memory of two chips with a 16 bit word. It means that every 32 bit
+ * access is going to access to two different chips. This is very
+ * important when we send commands or read status of the chips
+ */
+
+/* Helper macros to access two flash banks in parallel */
+#define NOR_2X16(d) ((d << 16) | (d & 0xffff))
+
+static unsigned int nor_status(uintptr_t base_addr)
+{
+ unsigned long status;
+
+ nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG);
+ status = mmio_read_32(base_addr);
+ status |= status >> 16; /* merge status from both flash banks */
+
+ return status & 0xFFFF;
+}
+
+/*
+ * Poll Write State Machine.
+ * Return values:
* 0 = WSM ready
* -EBUSY = WSM busy after the number of retries
*/
-static int nor_poll_dws(uintptr_t base_addr, unsigned int retries)
+static int nor_poll_dws(uintptr_t base_addr, unsigned long int retries)
{
- uint32_t status;
- int ret;
+ unsigned long status;
- for (;;) {
+ do {
nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG);
status = mmio_read_32(base_addr);
- if ((status & NOR_DWS) &&
- (status & (NOR_DWS << 16))) {
- ret = 0;
- break;
- }
- if (retries-- == 0) {
- ret = -EBUSY;
- break;
- }
- }
+ if ((status & NOR_CMD_END) == NOR_CMD_END)
+ return 0;
+ } while (retries-- > 0);
- return ret;
+ return -EBUSY;
}
+/*
+ * Return values:
+ * 0 = success
+ * -EPERM = Device protected or Block locked
+ * -EIO = General I/O error
+ */
+static int nor_full_status_check(uintptr_t base_addr)
+{
+ unsigned long status;
+
+ /* Full status check */
+ status = nor_status(base_addr);
+
+ if (status & (NOR_PS | NOR_BLS | NOR_ESS | NOR_PSS))
+ return -EPERM;
+ if (status & (NOR_VPPS | NOR_ES))
+ return -EIO;
+ return 0;
+}
+
void nor_send_cmd(uintptr_t base_addr, unsigned long cmd)
{
mmio_write_32(base_addr, NOR_2X16(cmd));
}
/*
+ * This function programs a word in the flash. Be aware that it only
+ * can reset bits that were previously set. It cannot set bits that
+ * were previously reset. The resulting bits = old_bits & new bits.
* Return values:
- * 0 = success
- * -EBUSY = WSM not ready
- * -EPERM = Device protected or Block locked
+ * 0 = success
+ * otherwise it returns a negative value
*/
int nor_word_program(uintptr_t base_addr, unsigned long data)
{
uint32_t status;
int ret;
+ nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG);
+
/* Set the device in write word mode */
nor_send_cmd(base_addr, NOR_CMD_WORD_PROGRAM);
mmio_write_32(base_addr, data);
ret = nor_poll_dws(base_addr, DWS_WORD_PROGRAM_RETRIES);
- if (ret != 0) {
- goto word_program_end;
+ if (ret == 0) {
+ /* Full status check */
+ nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG);
+ status = mmio_read_32(base_addr);
+
+ if (status & (NOR_PS | NOR_BLS)) {
+ nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG);
+ ret = -EPERM;
+ }
}
- /* Full status check */
- nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG);
- status = mmio_read_32(base_addr);
+ if (ret == 0)
+ ret = nor_full_status_check(base_addr);
+ nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
- if (status & (NOR_PS | NOR_BLS)) {
- nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG);
- ret = -EPERM;
- }
+ return ret;
+}
-word_program_end:
+/*
+ * Erase a full 256K block
+ * Return values:
+ * 0 = success
+ * otherwise it returns a negative value
+ */
+int nor_erase(uintptr_t base_addr)
+{
+ int ret;
+
+ nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG);
+
+ nor_send_cmd(base_addr, NOR_CMD_BLOCK_ERASE);
+ nor_send_cmd(base_addr, NOR_CMD_BLOCK_ERASE_ACK);
+
+ ret = nor_poll_dws(base_addr, DWS_WORD_ERASE_RETRIES);
+ if (ret == 0)
+ ret = nor_full_status_check(base_addr);
nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
+
return ret;
}
-void nor_lock(uintptr_t base_addr)
+/*
+ * Lock a full 256 block
+ * Return values:
+ * 0 = success
+ * otherwise it returns a negative value
+ */
+int nor_lock(uintptr_t base_addr)
{
+ int ret;
+
+ nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG);
+
nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK);
- mmio_write_32(base_addr, NOR_2X16(NOR_LOCK_BLOCK));
+ nor_send_cmd(base_addr, NOR_LOCK_BLOCK);
+
+ ret = nor_poll_dws(base_addr, DWS_WORD_LOCK_RETRIES);
+ if (ret == 0)
+ ret = nor_full_status_check(base_addr);
nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
+
+ return ret;
}
-void nor_unlock(uintptr_t base_addr)
+/*
+ * unlock a full 256 block
+ * Return values:
+ * 0 = success
+ * otherwise it returns a negative value
+ */
+int nor_unlock(uintptr_t base_addr)
{
+ int ret;
+
+ nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG);
+
nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK);
- mmio_write_32(base_addr, NOR_2X16(NOR_UNLOCK_BLOCK));
+ nor_send_cmd(base_addr, NOR_UNLOCK_BLOCK);
+
+ ret = nor_poll_dws(base_addr, DWS_WORD_LOCK_RETRIES);
+ if (ret == 0)
+ ret = nor_full_status_check(base_addr);
nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
-}
+ return ret;
+}
diff --git a/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
index 9dad146..5948e14 100644
--- a/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
+++ b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,7 @@
* TODO: Someday there will be a generic power controller api. At the moment
* each platform has its own pwrc so just exporting functions is fine.
*/
-ARM_INSTANTIATE_LOCK
+ARM_INSTANTIATE_LOCK;
unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr)
{
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index c1dcc02..d97a049 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -87,6 +87,9 @@
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
+#ifdef SPD_opteed
+ ARM_OPTEE_PAGEABLE_LOAD_MEM,
+#endif
{0}
};
#endif
@@ -219,8 +222,7 @@
arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
break;
case REV_BASE_FVP_REVC:
- arm_config.flags |= (ARM_CONFIG_FVP_SHIFTED_AFF |
- ARM_CONFIG_FVP_HAS_SMMUV3 |
+ arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
ARM_CONFIG_FVP_HAS_CCI5XX);
break;
default:
@@ -232,6 +234,14 @@
ERROR("Unsupported board HBI number 0x%x\n", hbi);
panic();
}
+
+ /*
+ * We assume that the presence of MT bit, and therefore shifted
+ * affinities, is uniform across the platform: either all CPUs, or no
+ * CPUs implement it.
+ */
+ if (read_mpidr_el1() & MPIDR_MT_MASK)
+ arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
}
diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c
index 1ca70a2..9098d3f 100644
--- a/plat/arm/css/drivers/scp/css_pm_scmi.c
+++ b/plat/arm/css/drivers/scp/css_pm_scmi.c
@@ -76,7 +76,7 @@
/* The SCMI channel global object */
static scmi_channel_t scmi_channel;
-ARM_INSTANTIATE_LOCK
+ARM_INSTANTIATE_LOCK;
/*
* Helper function to suspend a CPU power domain and its parent power domains
diff --git a/plat/arm/css/drivers/scpi/css_mhu.c b/plat/arm/css/drivers/scpi/css_mhu.c
index 509afe8..500b8df 100644
--- a/plat/arm/css/drivers/scpi/css_mhu.c
+++ b/plat/arm/css/drivers/scpi/css_mhu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,7 +23,7 @@
#define CPU_INTR_S_SET 0x308
#define CPU_INTR_S_CLEAR 0x310
-ARM_INSTANTIATE_LOCK
+ARM_INSTANTIATE_LOCK;
/* Weak definition may be overridden in specific CSS based platform */
#pragma weak plat_arm_pwrc_setup
diff --git a/plat/hisilicon/hikey/hisi_pwrc_sram.S b/plat/hisilicon/hikey/hisi_pwrc_sram.S
index f9e1de4..62542f2 100644
--- a/plat/hisilicon/hikey/hisi_pwrc_sram.S
+++ b/plat/hisilicon/hikey/hisi_pwrc_sram.S
@@ -19,11 +19,12 @@
mov x0, 0
msr oslar_el1, x0
- mrs x0, CORTEX_A53_ACTLR_EL1
- bic x0, x0, #(CORTEX_A53_ACTLR_RADIS | CORTEX_A53_ACTLR_L1RADIS)
+ mrs x0, CORTEX_A53_CPUACTLR_EL1
+ bic x0, x0, #(CORTEX_A53_CPUACTLR_EL1_RADIS | \
+ CORTEX_A53_CPUACTLR_EL1_L1RADIS)
orr x0, x0, #0x180000
orr x0, x0, #0xe000
- msr CORTEX_A53_ACTLR_EL1, x0
+ msr CORTEX_A53_CPUACTLR_EL1, x0
mrs x3, actlr_el3
orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index 691b90a..3c490d0 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -316,18 +316,18 @@
* entries from the branch predictor array.
* -------------------------------------------------------
*/
- mrs x0, CORTEX_A57_ACTLR_EL1
+ mrs x0, CORTEX_A57_CPUACTLR_EL1
orr x0, x0, #1
- msr CORTEX_A57_ACTLR_EL1, x0 /* invalidate BTB and I$ together */
+ msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
dsb sy
isb
ic iallu /* actual invalidate */
dsb sy
isb
- mrs x0, CORTEX_A57_ACTLR_EL1
+ mrs x0, CORTEX_A57_CPUACTLR_EL1
bic x0, x0, #1
- msr CORTEX_A57_ACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
+ msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
dsb sy
isb
@@ -351,7 +351,7 @@
msr oslar_el1, x0 /* os lock stays 0 across warm reset */
mov x3, #3
movz x4, #0x8000, lsl #48
- msr CORTEX_A57_ACTLR_EL1, x4 /* turn off RCG */
+ msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */
isb
msr rmr_el3, x3 /* request warm reset */
isb
diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h
index ceb0539..e91a7db 100644
--- a/plat/qemu/include/platform_def.h
+++ b/plat/qemu/include/platform_def.h
@@ -73,6 +73,11 @@
#define SEC_DRAM_BASE 0x0e100000
#define SEC_DRAM_SIZE 0x00f00000
+/* Load pageable part of OP-TEE at end of secure DRAM */
+#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
+ QEMU_OPTEE_PAGEABLE_LOAD_SIZE)
+#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000
+
/*
* ARM-TF lives in SRAM, partition it here
*/
@@ -154,7 +159,8 @@
#define NS_IMAGE_OFFSET 0x60000000
-#define ADDR_SPACE_SIZE (1ull << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
#define MAX_MMAP_REGIONS 8
#define MAX_XLAT_TABLES 6
#define MAX_IO_DEVICES 3
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index dc3b5d9..ed197a1 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -65,6 +65,10 @@
plat/qemu/qemu_image_load.c \
common/desc_image_load.c
endif
+ifeq (${SPD},opteed)
+BL2_SOURCES += lib/optee/optee_utils.c
+endif
+
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
@@ -72,13 +76,23 @@
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/common/gic_common.c \
- plat/common/aarch64/plat_psci_common.c \
+ plat/common/plat_psci_common.c \
plat/qemu/qemu_pm.c \
plat/qemu/topology.c \
plat/qemu/aarch64/plat_helpers.S \
plat/qemu/qemu_bl31_setup.c \
plat/qemu/qemu_gic.c
+
+# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
+# in the FIP if the platform requires.
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call FIP_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call FIP_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
+endif
+
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
diff --git a/plat/qemu/qemu_bl2_mem_params_desc.c b/plat/qemu/qemu_bl2_mem_params_desc.c
index 3396140..47f88ac 100644
--- a/plat/qemu/qemu_bl2_mem_params_desc.c
+++ b/plat/qemu/qemu_bl2_mem_params_desc.c
@@ -72,6 +72,43 @@
.next_handoff_image_id = BL33_IMAGE_ID,
},
+
+ /*
+ * Fill BL32 external 1 related information.
+ * A typical use for extra1 image is with OP-TEE where it is the
+ * pager image.
+ */
+ { .image_id = BL32_EXTRA1_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t, SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+ .image_info.image_base = BL32_BASE,
+ .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+ /*
+ * Fill BL32 external 2 related information.
+ * A typical use for extra2 image is with OP-TEE where it is the
+ * paged image.
+ */
+ { .image_id = BL32_EXTRA2_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t, SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+#ifdef SPD_opteed
+ .image_info.image_base = QEMU_OPTEE_PAGEABLE_LOAD_BASE,
+ .image_info.image_max_size = QEMU_OPTEE_PAGEABLE_LOAD_SIZE,
+#endif
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
# endif /* QEMU_LOAD_BL32 */
/* Fill BL33 related information */
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index 1306f34..60d9623 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -9,6 +9,9 @@
#include <console.h>
#include <debug.h>
#include <desc_image_load.h>
+#ifdef SPD_opteed
+#include <optee_utils.h>
+#endif
#include <libfdt.h>
#include <platform_def.h>
#include <string.h>
@@ -225,12 +228,36 @@
{
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+#ifdef SPD_opteed
+ bl_mem_params_node_t *pager_mem_params = NULL;
+ bl_mem_params_node_t *paged_mem_params = NULL;
+#endif
assert(bl_mem_params);
switch (image_id) {
# ifdef AARCH64
case BL32_IMAGE_ID:
+#ifdef SPD_opteed
+ pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ assert(pager_mem_params);
+
+ paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+ assert(paged_mem_params);
+
+ err = parse_optee_header(&bl_mem_params->ep_info,
+ &pager_mem_params->image_info,
+ &paged_mem_params->image_info);
+ if (err != 0) {
+ WARN("OPTEE header parse error.\n");
+ }
+
+ /*
+ * OP-TEE expect to receive DTB address in x2.
+ * This will be copied into x2 by dispatcher.
+ */
+ bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
+#endif
bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
break;
# endif
diff --git a/plat/qemu/qemu_io_storage.c b/plat/qemu/qemu_io_storage.c
index 19baf21..e0f7e8a 100644
--- a/plat/qemu/qemu_io_storage.c
+++ b/plat/qemu/qemu_io_storage.c
@@ -21,6 +21,8 @@
#define BL2_IMAGE_NAME "bl2.bin"
#define BL31_IMAGE_NAME "bl31.bin"
#define BL32_IMAGE_NAME "bl32.bin"
+#define BL32_EXTRA1_IMAGE_NAME "bl32_extra1.bin"
+#define BL32_EXTRA2_IMAGE_NAME "bl32_extra2.bin"
#define BL33_IMAGE_NAME "bl33.bin"
#if TRUSTED_BOARD_BOOT
@@ -61,6 +63,14 @@
.uuid = UUID_SECURE_PAYLOAD_BL32,
};
+static const io_uuid_spec_t bl32_extra1_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
+};
+
+static const io_uuid_spec_t bl32_extra2_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
+};
+
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
@@ -112,6 +122,14 @@
.path = BL32_IMAGE_NAME,
.mode = FOPEN_MODE_RB
},
+ [BL32_EXTRA1_IMAGE_ID] = {
+ .path = BL32_EXTRA1_IMAGE_NAME,
+ .mode = FOPEN_MODE_RB
+ },
+ [BL32_EXTRA2_IMAGE_ID] = {
+ .path = BL32_EXTRA2_IMAGE_NAME,
+ .mode = FOPEN_MODE_RB
+ },
[BL33_IMAGE_ID] = {
.path = BL33_IMAGE_NAME,
.mode = FOPEN_MODE_RB
@@ -185,6 +203,16 @@
(uintptr_t)&bl32_uuid_spec,
open_fip
},
+ [BL32_EXTRA1_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_extra1_uuid_spec,
+ open_fip
+ },
+ [BL32_EXTRA2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_extra2_uuid_spec,
+ open_fip
+ },
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl33_uuid_spec,
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 290811a..5456773 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -90,6 +90,8 @@
struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
struct apio_info *plat_get_rockchip_suspend_apio(void);
void plat_rockchip_gpio_init(void);
+void plat_rockchip_save_gpio(void);
+void plat_rockchip_restore_gpio(void);
int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint);
int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
index 22bdffc..5a1854b 100644
--- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
+++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
@@ -45,7 +45,7 @@
ddr_resume:
ldr x2, =__bl31_sram_stack_end
mov sp, x2
- bl dmc_restore
+ bl dmc_resume
#endif
bl sram_restore
sys_resume:
diff --git a/plat/rockchip/rk3399/drivers/dram/dram.h b/plat/rockchip/rk3399/drivers/dram/dram.h
index fede7ee..0780fc3 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram.h
+++ b/plat/rockchip/rk3399/drivers/dram/dram.h
@@ -25,10 +25,10 @@
struct rk3399_ddr_publ_regs {
/*
- * PHY registers from 0 to 511.
- * Only registers 0-90 of each 128 register range are used.
+ * PHY registers from 0 to 90 for slice1.
+ * These are used to restore slice1-4 on resume.
*/
- uint32_t phy0[4][91];
+ uint32_t phy0[91];
/*
* PHY registers from 512 to 895.
* Only registers 0-37 of each 128 register range are used.
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c
index 6867744..f66150a 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.c
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.c
@@ -43,6 +43,9 @@
#define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS / 1000000)
+__pmusramdata uint32_t dpll_data[PLL_CON_COUNT];
+__pmusramdata uint32_t cru_clksel_con6;
+
/*
* Copy @num registers from @src to @dst
*/
@@ -528,7 +531,7 @@
for (i = 0; i < 4; i++)
sram_regcpy(PHY_REG(ch, 128 * i),
- (uintptr_t)&phy_regs->phy0[i][0], 91);
+ (uintptr_t)&phy_regs->phy0[0], 91);
for (i = 0; i < 3; i++)
sram_regcpy(PHY_REG(ch, 512 + 128 * i),
@@ -636,24 +639,45 @@
return 0;
}
+__pmusramfunc static void pmusram_restore_pll(int pll_id, uint32_t *src)
+{
+ mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
+
+ mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK);
+ mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK);
+ mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]);
+ mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK);
+ mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK);
+
+ mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
+
+ while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
+ (1 << 31)) == 0x0)
+ ;
+}
+
-void dmc_save(void)
+void dmc_suspend(void)
{
struct rk3399_sdram_params *sdram_params = &sdram_config;
struct rk3399_ddr_publ_regs *phy_regs;
uint32_t *params_ctl;
uint32_t *params_pi;
uint32_t refdiv, postdiv2, postdiv1, fbdiv;
- uint32_t tmp, ch, byte, i;
+ uint32_t ch, byte, i;
phy_regs = &sdram_params->phy_regs;
params_ctl = sdram_params->pctl_regs.denali_ctl;
params_pi = sdram_params->pi_regs.denali_pi;
+ /* save dpll register and ddr clock register value to pmusram */
+ cru_clksel_con6 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON6);
+ for (i = 0; i < PLL_CON_COUNT; i++)
+ dpll_data[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, i));
+
- fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff;
- tmp = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1));
- postdiv2 = POSTDIV2_DEC(tmp);
- postdiv1 = POSTDIV1_DEC(tmp);
- refdiv = REFDIV_DEC(tmp);
+ fbdiv = dpll_data[0] & 0xfff;
+ postdiv2 = POSTDIV2_DEC(dpll_data[1]);
+ postdiv1 = POSTDIV1_DEC(dpll_data[1]);
+ refdiv = REFDIV_DEC(dpll_data[1]);
sdram_params->ddr_freq = ((fbdiv * 24) /
(refdiv * postdiv1 * postdiv2)) * MHz;
@@ -674,9 +698,8 @@
/* mask DENALI_PI_00_DATA.START, only copy here, will trigger later*/
params_pi[0] &= ~(0x1 << 0);
- for (i = 0; i < 4; i++)
- dram_regcpy((uintptr_t)&phy_regs->phy0[i][0],
- PHY_REG(0, 128 * i), 91);
+ dram_regcpy((uintptr_t)&phy_regs->phy0[0],
+ PHY_REG(0, 0), 91);
for (i = 0; i < 3; i++)
dram_regcpy((uintptr_t)&phy_regs->phy512[i][0],
@@ -697,12 +720,22 @@
phy_regs->phy896[0] &= ~(0x3 << 8);
}
-__pmusramfunc void dmc_restore(void)
+__pmusramfunc void dmc_resume(void)
{
struct rk3399_sdram_params *sdram_params = &sdram_config;
uint32_t channel_mask = 0;
uint32_t channel;
+ sram_secure_timer_init();
+
+ /*
+ * we switch ddr clock to abpll when suspend,
+ * we set back to dpll here
+ */
+ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON6,
+ cru_clksel_con6 | REG_SOC_WMSK);
+ pmusram_restore_pll(DPLL_ID, dpll_data);
+
configure_sgrf();
retry:
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.h b/plat/rockchip/rk3399/drivers/dram/suspend.h
index 77f9c31..a8a8641 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.h
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.h
@@ -19,7 +19,7 @@
#define PI_WDQ_LEVELING (1 << 4)
#define PI_FULL_TRAINING (0xff)
-void dmc_save(void);
-__pmusramfunc void dmc_restore(void);
+void dmc_suspend(void);
+__pmusramfunc void dmc_resume(void);
#endif /* __DRAM_H__ */
diff --git a/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c b/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c
index d5a2660..e74c4d9 100644
--- a/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c
+++ b/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c
@@ -22,10 +22,29 @@
GPIO4_BASE,
};
+struct {
+ uint32_t swporta_dr;
+ uint32_t swporta_ddr;
+ uint32_t inten;
+ uint32_t intmask;
+ uint32_t inttype_level;
+ uint32_t int_polarity;
+ uint32_t debounce;
+ uint32_t ls_sync;
+} store_gpio[3];
+
+static uint32_t store_grf_gpio[(GRF_GPIO2D_HE - GRF_GPIO2A_IOMUX) / 4 + 1];
+
#define SWPORTA_DR 0x00
#define SWPORTA_DDR 0x04
-#define EXT_PORTA 0x50
+#define INTEN 0x30
+#define INTMASK 0x34
+#define INTTYPE_LEVEL 0x38
+#define INT_POLARITY 0x3c
+#define DEBOUNCE 0x48
+#define LS_SYNC 0x60
+#define EXT_PORTA 0x50
#define PMU_GPIO_PORT0 0
#define PMU_GPIO_PORT1 1
#define GPIO_PORT2 2
@@ -290,6 +309,99 @@
gpio_put_clock(gpio, clock_state);
}
+void plat_rockchip_save_gpio(void)
+{
+ int i;
+ uint32_t cru_gate_save;
+
+ cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31));
+
+ /*
+ * when shutdown logic, we need to save gpio2 ~ gpio4 register,
+ * we need to enable gpio2 ~ gpio4 clock here, since it may be gating,
+ * and we do not care gpio0 and gpio1 clock gate, since we never
+ * gating them
+ */
+ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
+ BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
+
+ /*
+ * since gpio0, gpio1 are pmugpio, they will keep ther value
+ * when shutdown logic power rail, so only need to save gpio2 ~ gpio4
+ * register value
+ */
+ for (i = 2; i < 5; i++) {
+ store_gpio[i - 2].swporta_dr =
+ mmio_read_32(gpio_port[i] + SWPORTA_DR);
+ store_gpio[i - 2].swporta_ddr =
+ mmio_read_32(gpio_port[i] + SWPORTA_DDR);
+ store_gpio[i - 2].inten =
+ mmio_read_32(gpio_port[i] + INTEN);
+ store_gpio[i - 2].intmask =
+ mmio_read_32(gpio_port[i] + INTMASK);
+ store_gpio[i - 2].inttype_level =
+ mmio_read_32(gpio_port[i] + INTTYPE_LEVEL);
+ store_gpio[i - 2].int_polarity =
+ mmio_read_32(gpio_port[i] + INT_POLARITY);
+ store_gpio[i - 2].debounce =
+ mmio_read_32(gpio_port[i] + DEBOUNCE);
+ store_gpio[i - 2].ls_sync =
+ mmio_read_32(gpio_port[i] + LS_SYNC);
+ }
+ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
+ cru_gate_save | REG_SOC_WMSK);
+
+ /*
+ * gpio0, gpio1 in pmuiomux, they will keep ther value
+ * when shutdown logic power rail, so only need to save gpio2 ~ gpio4
+ * iomux register value
+ */
+ for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++)
+ store_grf_gpio[i] =
+ mmio_read_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4);
+}
+
+void plat_rockchip_restore_gpio(void)
+{
+ int i;
+ uint32_t cru_gate_save;
+
+ for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++)
+ mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4,
+ REG_SOC_WMSK | store_grf_gpio[i]);
+
+ cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31));
+
+ /*
+ * when shutdown logic, we need to save gpio2 ~ gpio4 register,
+ * we need to enable gpio2 ~ gpio4 clock here, since it may be gating,
+ * and we do not care gpio0 and gpio1 clock gate, since we never
+ * gating them
+ */
+ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
+ BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
+
+ for (i = 2; i < 5; i++) {
+ mmio_write_32(gpio_port[i] + SWPORTA_DR,
+ store_gpio[i - 2].swporta_dr);
+ mmio_write_32(gpio_port[i] + SWPORTA_DDR,
+ store_gpio[i - 2].swporta_ddr);
+ mmio_write_32(gpio_port[i] + INTEN, store_gpio[i - 2].inten);
+ mmio_write_32(gpio_port[i] + INTMASK,
+ store_gpio[i - 2].intmask);
+ mmio_write_32(gpio_port[i] + INTTYPE_LEVEL,
+ store_gpio[i - 2].inttype_level);
+ mmio_write_32(gpio_port[i] + INT_POLARITY,
+ store_gpio[i - 2].int_polarity);
+ mmio_write_32(gpio_port[i] + DEBOUNCE,
+ store_gpio[i - 2].debounce);
+ mmio_write_32(gpio_port[i] + LS_SYNC,
+ store_gpio[i - 2].ls_sync);
+ }
+ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
+ cru_gate_save | REG_SOC_WMSK);
+}
+
const gpio_ops_t rk3399_gpio_ops = {
.get_direction = get_direction,
.set_direction = set_direction,
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index 6b420c2..c666c3c 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -32,6 +32,19 @@
static uint32_t cpu_warm_boot_addr;
static char store_sram[SRAM_BIN_LIMIT + SRAM_TEXT_LIMIT + SRAM_DATA_LIMIT];
+static uint32_t store_cru[CRU_SDIO0_CON1 / 4];
+static uint32_t store_usbphy0[7];
+static uint32_t store_usbphy1[7];
+static uint32_t store_grf_io_vsel;
+static uint32_t store_grf_soc_con0;
+static uint32_t store_grf_soc_con1;
+static uint32_t store_grf_soc_con2;
+static uint32_t store_grf_soc_con3;
+static uint32_t store_grf_soc_con4;
+static uint32_t store_grf_soc_con7;
+static uint32_t store_grf_ddrc_con[4];
+static uint32_t store_wdt0[2];
+static uint32_t store_wdt1[2];
/*
* There are two ways to powering on or off on core.
@@ -323,6 +336,11 @@
pmu_set_power_domain(PD_RGA, pmu_pd_off);
pmu_set_power_domain(PD_VCODEC, pmu_pd_off);
pmu_set_power_domain(PD_VDU, pmu_pd_off);
+ pmu_set_power_domain(PD_USB3, pmu_pd_off);
+ pmu_set_power_domain(PD_EMMC, pmu_pd_off);
+ pmu_set_power_domain(PD_VIO, pmu_pd_off);
+ pmu_set_power_domain(PD_SD, pmu_pd_off);
+ pmu_set_power_domain(PD_PERIHP, pmu_pd_off);
clk_gate_con_restore();
}
@@ -358,6 +376,16 @@
pmu_set_power_domain(PD_TCPD0, pmu_pd_on);
if (!(pmu_powerdomain_state & BIT(PD_GPU)))
pmu_set_power_domain(PD_GPU, pmu_pd_on);
+ if (!(pmu_powerdomain_state & BIT(PD_USB3)))
+ pmu_set_power_domain(PD_USB3, pmu_pd_on);
+ if (!(pmu_powerdomain_state & BIT(PD_EMMC)))
+ pmu_set_power_domain(PD_EMMC, pmu_pd_on);
+ if (!(pmu_powerdomain_state & BIT(PD_VIO)))
+ pmu_set_power_domain(PD_VIO, pmu_pd_on);
+ if (!(pmu_powerdomain_state & BIT(PD_SD)))
+ pmu_set_power_domain(PD_SD, pmu_pd_on);
+ if (!(pmu_powerdomain_state & BIT(PD_PERIHP)))
+ pmu_set_power_domain(PD_PERIHP, pmu_pd_on);
qos_restore();
clk_gate_con_restore();
}
@@ -815,6 +843,7 @@
BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW));
slp_mode_cfg = BIT(PMU_PWR_MODE_EN) |
+ BIT(PMU_INPUT_CLAMP_EN) |
BIT(PMU_POWER_OFF_REQ_CFG) |
BIT(PMU_CPU0_PD_EN) |
BIT(PMU_L2_FLUSH_EN) |
@@ -828,7 +857,9 @@
BIT(PMU_DDRC0_GATING_EN) |
BIT(PMU_DDRC1_GATING_EN) |
BIT(PMU_DDRIO0_RET_EN) |
+ BIT(PMU_DDRIO0_RET_DE_REQ) |
BIT(PMU_DDRIO1_RET_EN) |
+ BIT(PMU_DDRIO1_RET_DE_REQ) |
BIT(PMU_DDRIO_RET_HW_DE_REQ) |
BIT(PMU_CENTER_PD_EN) |
BIT(PMU_PERILP_PD_EN) |
@@ -1076,15 +1107,229 @@
incbin_size);
}
+struct uart_debug {
+ uint32_t uart_dll;
+ uint32_t uart_dlh;
+ uint32_t uart_ier;
+ uint32_t uart_fcr;
+ uint32_t uart_mcr;
+ uint32_t uart_lcr;
+};
+
+#define UART_DLL 0x00
+#define UART_DLH 0x04
+#define UART_IER 0x04
+#define UART_FCR 0x08
+#define UART_LCR 0x0c
+#define UART_MCR 0x10
+#define UARTSRR 0x88
+
+#define UART_RESET BIT(0)
+#define UARTFCR_FIFOEN BIT(0)
+#define RCVR_FIFO_RESET BIT(1)
+#define XMIT_FIFO_RESET BIT(2)
+#define DIAGNOSTIC_MODE BIT(4)
+#define UARTLCR_DLAB BIT(7)
+
+static struct uart_debug uart_save;
+
+void suspend_uart(void)
+{
+ uart_save.uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
+ uart_save.uart_ier = mmio_read_32(PLAT_RK_UART_BASE + UART_IER);
+ uart_save.uart_mcr = mmio_read_32(PLAT_RK_UART_BASE + UART_MCR);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_LCR,
+ uart_save.uart_lcr | UARTLCR_DLAB);
+ uart_save.uart_dll = mmio_read_32(PLAT_RK_UART_BASE + UART_DLL);
+ uart_save.uart_dlh = mmio_read_32(PLAT_RK_UART_BASE + UART_DLH);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
+}
+
+void resume_uart(void)
+{
+ uint32_t uart_lcr;
+
+ mmio_write_32(PLAT_RK_UART_BASE + UARTSRR,
+ XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET);
+
+ uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, DIAGNOSTIC_MODE);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_lcr | UARTLCR_DLAB);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_DLL, uart_save.uart_dll);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_DLH, uart_save.uart_dlh);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_IER, uart_save.uart_ier);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_FCR, UARTFCR_FIFOEN);
+ mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, uart_save.uart_mcr);
+}
+
+void save_usbphy(void)
+{
+ store_usbphy0[0] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL0);
+ store_usbphy0[1] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL2);
+ store_usbphy0[2] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL3);
+ store_usbphy0[3] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL12);
+ store_usbphy0[4] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL13);
+ store_usbphy0[5] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL15);
+ store_usbphy0[6] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL16);
+
+ store_usbphy1[0] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL0);
+ store_usbphy1[1] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL2);
+ store_usbphy1[2] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL3);
+ store_usbphy1[3] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL12);
+ store_usbphy1[4] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL13);
+ store_usbphy1[5] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL15);
+ store_usbphy1[6] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL16);
+}
+
+void restore_usbphy(void)
+{
+ mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL0,
+ REG_SOC_WMSK | store_usbphy0[0]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL2,
+ REG_SOC_WMSK | store_usbphy0[1]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL3,
+ REG_SOC_WMSK | store_usbphy0[2]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL12,
+ REG_SOC_WMSK | store_usbphy0[3]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL13,
+ REG_SOC_WMSK | store_usbphy0[4]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL15,
+ REG_SOC_WMSK | store_usbphy0[5]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL16,
+ REG_SOC_WMSK | store_usbphy0[6]);
+
+ mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL0,
+ REG_SOC_WMSK | store_usbphy1[0]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL2,
+ REG_SOC_WMSK | store_usbphy1[1]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL3,
+ REG_SOC_WMSK | store_usbphy1[2]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL12,
+ REG_SOC_WMSK | store_usbphy1[3]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL13,
+ REG_SOC_WMSK | store_usbphy1[4]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL15,
+ REG_SOC_WMSK | store_usbphy1[5]);
+ mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL16,
+ REG_SOC_WMSK | store_usbphy1[6]);
+}
+
+void grf_register_save(void)
+{
+ int i;
+
+ store_grf_soc_con0 = mmio_read_32(GRF_BASE + GRF_SOC_CON(0));
+ store_grf_soc_con1 = mmio_read_32(GRF_BASE + GRF_SOC_CON(1));
+ store_grf_soc_con2 = mmio_read_32(GRF_BASE + GRF_SOC_CON(2));
+ store_grf_soc_con3 = mmio_read_32(GRF_BASE + GRF_SOC_CON(3));
+ store_grf_soc_con4 = mmio_read_32(GRF_BASE + GRF_SOC_CON(4));
+ store_grf_soc_con7 = mmio_read_32(GRF_BASE + GRF_SOC_CON(7));
+
+ for (i = 0; i < 4; i++)
+ store_grf_ddrc_con[i] =
+ mmio_read_32(GRF_BASE + GRF_DDRC0_CON0 + i * 4);
+
+ store_grf_io_vsel = mmio_read_32(GRF_BASE + GRF_IO_VSEL);
+}
+
+void grf_register_restore(void)
+{
+ int i;
+
+ mmio_write_32(GRF_BASE + GRF_SOC_CON(0),
+ REG_SOC_WMSK | store_grf_soc_con0);
+ mmio_write_32(GRF_BASE + GRF_SOC_CON(1),
+ REG_SOC_WMSK | store_grf_soc_con1);
+ mmio_write_32(GRF_BASE + GRF_SOC_CON(2),
+ REG_SOC_WMSK | store_grf_soc_con2);
+ mmio_write_32(GRF_BASE + GRF_SOC_CON(3),
+ REG_SOC_WMSK | store_grf_soc_con3);
+ mmio_write_32(GRF_BASE + GRF_SOC_CON(4),
+ REG_SOC_WMSK | store_grf_soc_con4);
+ mmio_write_32(GRF_BASE + GRF_SOC_CON(7),
+ REG_SOC_WMSK | store_grf_soc_con7);
+
+ for (i = 0; i < 4; i++)
+ mmio_write_32(GRF_BASE + GRF_DDRC0_CON0 + i * 4,
+ REG_SOC_WMSK | store_grf_ddrc_con[i]);
+
+ mmio_write_32(GRF_BASE + GRF_IO_VSEL, REG_SOC_WMSK | store_grf_io_vsel);
+}
+
+void cru_register_save(void)
+{
+ int i;
+
+ for (i = 0; i <= CRU_SDIO0_CON1; i = i + 4)
+ store_cru[i / 4] = mmio_read_32(CRU_BASE + i);
+}
+
+void cru_register_restore(void)
+{
+ int i;
+
+ for (i = 0; i <= CRU_SDIO0_CON1; i = i + 4) {
+
+ /*
+ * since DPLL, CRU_CLKSEL_CON6 have been restore in
+ * dmc_resume, ABPLL will resote later, so skip them
+ */
+ if ((i == CRU_CLKSEL_CON6) ||
+ (i >= CRU_PLL_CON(ABPLL_ID, 0) &&
+ i <= CRU_PLL_CON(DPLL_ID, 5)))
+ continue;
+
+ if ((i == CRU_PLL_CON(ALPLL_ID, 2)) ||
+ (i == CRU_PLL_CON(CPLL_ID, 2)) ||
+ (i == CRU_PLL_CON(GPLL_ID, 2)) ||
+ (i == CRU_PLL_CON(NPLL_ID, 2)) ||
+ (i == CRU_PLL_CON(VPLL_ID, 2)))
+ mmio_write_32(CRU_BASE + i, store_cru[i / 4]);
+ /*
+ * CRU_GLB_CNT_TH and CRU_CLKSEL_CON97~CRU_CLKSEL_CON107
+ * not need do high 16bit mask
+ */
+ else if ((i > 0x27c && i < 0x2b0) || (i == 0x508))
+ mmio_write_32(CRU_BASE + i, store_cru[i / 4]);
+ else
+ mmio_write_32(CRU_BASE + i,
+ REG_SOC_WMSK | store_cru[i / 4]);
+ }
+}
+
+void wdt_register_save(void)
+{
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ store_wdt0[i] = mmio_read_32(WDT0_BASE + i * 4);
+ store_wdt1[i] = mmio_read_32(WDT1_BASE + i * 4);
+ }
+}
+
+void wdt_register_restore(void)
+{
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]);
+ mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]);
+ }
+}
+
int rockchip_soc_sys_pwr_dm_suspend(void)
{
uint32_t wait_cnt = 0;
uint32_t status = 0;
ddr_prepare_for_sys_suspend();
- dmc_save();
+ dmc_suspend();
pmu_scu_b_pwrdn();
+ /* need to save usbphy before shutdown PERIHP PD */
+ save_usbphy();
+
pmu_power_domains_suspend();
set_hw_idle(BIT(PMU_CLR_CENTER1) |
BIT(PMU_CLR_ALIVE) |
@@ -1096,7 +1341,7 @@
BIT(PMU_CLR_PERILP) |
BIT(PMU_CLR_PERILPM0) |
BIT(PMU_CLR_GIC));
-
+ set_pmu_rsthold();
sys_slp_config();
m0_configure_suspend();
@@ -1139,8 +1384,13 @@
suspend_apio();
suspend_gpio();
-
+ suspend_uart();
+ grf_register_save();
+ cru_register_save();
+ wdt_register_save();
sram_save();
+ plat_rockchip_save_gpio();
+
return 0;
}
@@ -1149,6 +1399,11 @@
uint32_t wait_cnt = 0;
uint32_t status = 0;
+ plat_rockchip_restore_gpio();
+ wdt_register_restore();
+ cru_register_restore();
+ grf_register_restore();
+ resume_uart();
resume_apio();
resume_gpio();
enable_nodvfs_plls();
@@ -1158,6 +1413,8 @@
enable_dvfs_plls();
secure_watchdog_enable();
+ secure_sgrf_init();
+ secure_sgrf_ddr_rgn_init();
/* restore clk_ddrc_bpll_src_en gate */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
@@ -1211,10 +1468,8 @@
pmu_scu_b_pwrup();
pmu_power_domains_resume();
- restore_dpll();
- sram_func_set_ddrctl_pll(DPLL_ID);
restore_abpll();
-
+ restore_pmu_rsthold();
clr_hw_idle(BIT(PMU_CLR_CENTER1) |
BIT(PMU_CLR_ALIVE) |
BIT(PMU_CLR_MSCH0) |
@@ -1229,6 +1484,8 @@
plat_rockchip_gic_cpuif_enable();
m0_stop();
+ restore_usbphy();
+
ddr_prepare_for_sys_resume();
return 0;
diff --git a/plat/rockchip/rk3399/drivers/secure/secure.c b/plat/rockchip/rk3399/drivers/secure/secure.c
index 6b4f3b8..589d833 100644
--- a/plat/rockchip/rk3399/drivers/secure/secure.c
+++ b/plat/rockchip/rk3399/drivers/secure/secure.c
@@ -101,6 +101,19 @@
WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
}
+__pmusramfunc void sram_secure_timer_init(void)
+{
+ mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
+ mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
+
+ mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
+ mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
+
+ /* auto reload & enable the timer */
+ mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
+ TIMER_EN | TIMER_FMODE);
+}
+
void secure_timer_init(void)
{
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
diff --git a/plat/rockchip/rk3399/drivers/secure/secure.h b/plat/rockchip/rk3399/drivers/secure/secure.h
index 7784ae7..334805d 100644
--- a/plat/rockchip/rk3399/drivers/secure/secure.h
+++ b/plat/rockchip/rk3399/drivers/secure/secure.h
@@ -100,5 +100,6 @@
void secure_timer_init(void);
void secure_sgrf_init(void);
void secure_sgrf_ddr_rgn_init(void);
+__pmusramfunc void sram_secure_timer_init(void);
#endif /* __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ */
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index 993b80a..7dd0b72 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -171,11 +171,6 @@
restore_pll(ABPLL_ID, slp_data.plls_con[ABPLL_ID]);
}
-void restore_dpll(void)
-{
- restore_pll(DPLL_ID, slp_data.plls_con[DPLL_ID]);
-}
-
void clk_gate_con_save(void)
{
uint32_t i = 0;
@@ -229,6 +224,47 @@
set_pll_normal_mode(pll_id);
}
+void set_pmu_rsthold(void)
+{
+ uint32_t rstnhold_cofig0;
+ uint32_t rstnhold_cofig1;
+
+ slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE +
+ PMUCRU_RSTNHOLD_CON0);
+ slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE +
+ PMUCRU_RSTNHOLD_CON1);
+ rstnhold_cofig0 = BIT_WITH_WMSK(PRESETN_NOC_PMU_HOLD) |
+ BIT_WITH_WMSK(PRESETN_INTMEM_PMU_HOLD) |
+ BIT_WITH_WMSK(HRESETN_CM0S_PMU_HOLD) |
+ BIT_WITH_WMSK(HRESETN_CM0S_NOC_PMU_HOLD) |
+ BIT_WITH_WMSK(DRESETN_CM0S_PMU_HOLD) |
+ BIT_WITH_WMSK(POESETN_CM0S_PMU_HOLD) |
+ BIT_WITH_WMSK(PRESETN_TIMER_PMU_0_1_HOLD) |
+ BIT_WITH_WMSK(RESETN_TIMER_PMU_0_HOLD) |
+ BIT_WITH_WMSK(RESETN_TIMER_PMU_1_HOLD) |
+ BIT_WITH_WMSK(PRESETN_UART_M0_PMU_HOLD) |
+ BIT_WITH_WMSK(RESETN_UART_M0_PMU_HOLD) |
+ BIT_WITH_WMSK(PRESETN_WDT_PMU_HOLD);
+ rstnhold_cofig1 = BIT_WITH_WMSK(PRESETN_RKPWM_PMU_HOLD) |
+ BIT_WITH_WMSK(PRESETN_PMUGRF_HOLD) |
+ BIT_WITH_WMSK(PRESETN_SGRF_HOLD) |
+ BIT_WITH_WMSK(PRESETN_GPIO0_HOLD) |
+ BIT_WITH_WMSK(PRESETN_GPIO1_HOLD) |
+ BIT_WITH_WMSK(PRESETN_CRU_PMU_HOLD) |
+ BIT_WITH_WMSK(PRESETN_PVTM_PMU_HOLD);
+
+ mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0, rstnhold_cofig0);
+ mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1, rstnhold_cofig1);
+}
+
+void restore_pmu_rsthold(void)
+{
+ mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0,
+ slp_data.pmucru_rstnhold_con0 | REG_SOC_WMSK);
+ mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1,
+ slp_data.pmucru_rstnhold_con1 | REG_SOC_WMSK);
+}
+
/**
* enable_dvfs_plls - To resume the specific PLLs
*
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.h b/plat/rockchip/rk3399/drivers/soc/soc.h
index 8d1fd13..6100d95 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.h
+++ b/plat/rockchip/rk3399/drivers/soc/soc.h
@@ -56,6 +56,43 @@
#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
#define CRU_GATE_CON(n) (0x300 + (n) * 4)
+#define PMUCRU_RSTNHOLD_CON0 0x120
+enum {
+ PRESETN_NOC_PMU_HOLD = 1,
+ PRESETN_INTMEM_PMU_HOLD,
+ HRESETN_CM0S_PMU_HOLD,
+ HRESETN_CM0S_NOC_PMU_HOLD,
+ DRESETN_CM0S_PMU_HOLD,
+ POESETN_CM0S_PMU_HOLD,
+ PRESETN_SPI3_HOLD,
+ RESETN_SPI3_HOLD,
+ PRESETN_TIMER_PMU_0_1_HOLD,
+ RESETN_TIMER_PMU_0_HOLD,
+ RESETN_TIMER_PMU_1_HOLD,
+ PRESETN_UART_M0_PMU_HOLD,
+ RESETN_UART_M0_PMU_HOLD,
+ PRESETN_WDT_PMU_HOLD
+};
+
+#define PMUCRU_RSTNHOLD_CON1 0x124
+enum {
+ PRESETN_I2C0_HOLD,
+ PRESETN_I2C4_HOLD,
+ PRESETN_I2C8_HOLD,
+ PRESETN_MAILBOX_PMU_HOLD,
+ PRESETN_RKPWM_PMU_HOLD,
+ PRESETN_PMUGRF_HOLD,
+ PRESETN_SGRF_HOLD,
+ PRESETN_GPIO0_HOLD,
+ PRESETN_GPIO1_HOLD,
+ PRESETN_CRU_PMU_HOLD,
+ PRESETN_INTR_ARB_HOLD,
+ PRESETN_PVTM_PMU_HOLD,
+ RESETN_I2C0_HOLD,
+ RESETN_I2C4_HOLD,
+ RESETN_I2C8_HOLD
+};
+
enum plls_id {
ALPLL_ID = 0,
ABPLL_ID,
@@ -97,6 +134,8 @@
uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
uint32_t cru_gate_con[CRU_GATE_COUNT];
uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
+ uint32_t pmucru_rstnhold_con0;
+ uint32_t pmucru_rstnhold_con1;
};
/**************************************************
@@ -189,13 +228,35 @@
#define PWM_ENABLE (1 << 0)
/* grf reg offset */
+#define GRF_USBPHY0_CTRL0 0x4480
+#define GRF_USBPHY0_CTRL2 0x4488
+#define GRF_USBPHY0_CTRL3 0x448c
+#define GRF_USBPHY0_CTRL12 0x44b0
+#define GRF_USBPHY0_CTRL13 0x44b4
+#define GRF_USBPHY0_CTRL15 0x44bc
+#define GRF_USBPHY0_CTRL16 0x44c0
+
+#define GRF_USBPHY1_CTRL0 0x4500
+#define GRF_USBPHY1_CTRL2 0x4508
+#define GRF_USBPHY1_CTRL3 0x450c
+#define GRF_USBPHY1_CTRL12 0x4530
+#define GRF_USBPHY1_CTRL13 0x4534
+#define GRF_USBPHY1_CTRL15 0x453c
+#define GRF_USBPHY1_CTRL16 0x4540
+
+#define GRF_GPIO2A_IOMUX 0xe000
+#define GRF_GPIO2D_HE 0xe18c
#define GRF_DDRC0_CON0 0xe380
#define GRF_DDRC0_CON1 0xe384
#define GRF_DDRC1_CON0 0xe388
#define GRF_DDRC1_CON1 0xe38c
#define GRF_SOC_CON_BASE 0xe200
#define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4)
+#define GRF_IO_VSEL 0xe640
+#define CRU_CLKSEL_CON0 0x0100
+#define CRU_CLKSEL_CON6 0x0118
+#define CRU_SDIO0_CON1 0x058c
#define PMUCRU_CLKSEL_CON0 0x0080
#define PMUCRU_CLKGATE_CON2 0x0108
#define PMUCRU_SOFTRST_CON0 0x0110
@@ -231,9 +292,9 @@
void enable_nodvfs_plls(void);
void prepare_abpll_for_ddrctrl(void);
void restore_abpll(void);
-void restore_dpll(void);
void clk_gate_con_save(void);
void clk_gate_con_disable(void);
void clk_gate_con_restore(void);
-
+void set_pmu_rsthold(void);
+void restore_pmu_rsthold(void);
#endif /* __SOC_H__ */
diff --git a/plat/rockchip/rk3399/include/shared/addressmap_shared.h b/plat/rockchip/rk3399/include/shared/addressmap_shared.h
index fe23e56..dc5c8d5 100644
--- a/plat/rockchip/rk3399/include/shared/addressmap_shared.h
+++ b/plat/rockchip/rk3399/include/shared/addressmap_shared.h
@@ -40,6 +40,9 @@
#define GPIO2_BASE (MMIO_BASE + 0x07780000)
#define GPIO3_BASE (MMIO_BASE + 0x07788000)
#define GPIO4_BASE (MMIO_BASE + 0x07790000)
+#define WDT1_BASE (MMIO_BASE + 0x07840000)
+#define WDT0_BASE (MMIO_BASE + 0x07848000)
+#define TIMER_BASE (MMIO_BASE + 0x07850000)
#define STIME_BASE (MMIO_BASE + 0x07860000)
#define SRAM_BASE (MMIO_BASE + 0x078C0000)
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000)
diff --git a/services/spd/opteed/opteed_common.c b/services/spd/opteed/opteed_common.c
index a0cd86c..2693e7d 100644
--- a/services/spd/opteed/opteed_common.c
+++ b/services/spd/opteed/opteed_common.c
@@ -20,7 +20,7 @@
void opteed_init_optee_ep_state(struct entry_point_info *optee_entry_point,
uint32_t rw, uint64_t pc,
uint64_t pageable_part, uint64_t mem_limit,
- optee_context_t *optee_ctx)
+ uint64_t dt_addr, optee_context_t *optee_ctx)
{
uint32_t ep_attr;
@@ -54,6 +54,7 @@
zeromem(&optee_entry_point->args, sizeof(optee_entry_point->args));
optee_entry_point->args.arg0 = pageable_part;
optee_entry_point->args.arg1 = mem_limit;
+ optee_entry_point->args.arg2 = dt_addr;
}
/*******************************************************************************
diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c
index b3031e4..13a307a 100644
--- a/services/spd/opteed/opteed_main.c
+++ b/services/spd/opteed/opteed_main.c
@@ -96,6 +96,7 @@
uint32_t linear_id;
uint64_t opteed_pageable_part;
uint64_t opteed_mem_limit;
+ uint64_t dt_addr;
linear_id = plat_my_core_pos();
@@ -120,19 +121,17 @@
if (!optee_ep_info->pc)
return 1;
- /*
- * We could inspect the SP image and determine it's execution
- * state i.e whether AArch32 or AArch64.
- */
opteed_rw = optee_ep_info->args.arg0;
opteed_pageable_part = optee_ep_info->args.arg1;
opteed_mem_limit = optee_ep_info->args.arg2;
+ dt_addr = optee_ep_info->args.arg3;
opteed_init_optee_ep_state(optee_ep_info,
opteed_rw,
optee_ep_info->pc,
opteed_pageable_part,
opteed_mem_limit,
+ dt_addr,
&opteed_sp_context[linear_id]);
/*
diff --git a/services/spd/opteed/opteed_pm.c b/services/spd/opteed/opteed_pm.c
index 5a1dd4f..2420b1e 100644
--- a/services/spd/opteed/opteed_pm.c
+++ b/services/spd/opteed/opteed_pm.c
@@ -99,7 +99,7 @@
opteed_init_optee_ep_state(&optee_on_entrypoint, opteed_rw,
(uint64_t)&optee_vectors->cpu_on_entry,
- 0, 0, optee_ctx);
+ 0, 0, 0, optee_ctx);
/* Initialise this cpu's secure context */
cm_init_my_context(&optee_on_entrypoint);
diff --git a/services/spd/opteed/opteed_private.h b/services/spd/opteed/opteed_private.h
index 11c1a1f..6cda2c8 100644
--- a/services/spd/opteed/opteed_private.h
+++ b/services/spd/opteed/opteed_private.h
@@ -149,6 +149,7 @@
uint64_t pc,
uint64_t pageable_part,
uint64_t mem_limit,
+ uint64_t dt_addr,
optee_context_t *optee_ctx);
extern optee_context_t opteed_sp_context[OPTEED_CORE_COUNT];
