commit bacbdeee3fcda49c1e9d9b605ff6872ab290c6a0
author Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Fri Aug 20 00:27:03 2021 -0700
committer Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Tue Nov 30 02:00:01 2021 -0800
tree c081dcb60947928cf3d7baae21928213270477be
parent f435a141da0acedd30a388554e3d27ce953e5c93

fix(plat/xilinx/versal): resolve misra R14.4

MISRA Violation: MISRA-C:2012 R.14.4
- The controlling expression of an if statement and the controlling
  expression of an iteration-statement shall have essentially Boolean type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I8cf821a42015858200cc0c514600012c8f61061f

plat/xilinx/versal/bl31_versal_setup.c

diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 4d7caf1..c82e8a6 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -127,7 +127,7 @@
 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
 {
 	/* Validate 'handler'*/
-	if (!handler) {
+	if (handler == NULL) {
 		return -EINVAL;
 	}
 
@@ -150,7 +150,7 @@
 	}
 
 	handler = type_el3_interrupt_handler;
-	if (handler) {
+	if (handler != NULL) {
 		return handler(intr_id, flags, handle, cookie);
 	}
 
@@ -171,7 +171,7 @@
 	set_interrupt_rm_flag(flags, NON_SECURE);
 	rc = register_interrupt_type_handler(INTR_TYPE_EL3,
 					     rdo_el3_interrupt_handler, flags);
-	if (rc) {
+	if (rc != 0) {
 		panic();
 	}
 }

plat/xilinx/versal/plat_psci.c

diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 30742f7..eb05e58 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -205,7 +205,7 @@
 	}
 
 	/* We expect the 'state id' to be zero */
-	if (psci_get_pstate_id(power_state)) {
+	if (psci_get_pstate_id(power_state) != 0U) {
 		return PSCI_E_INVALID_PARAMS;
 	}
 

plat/xilinx/versal/plat_versal.c

diff --git a/plat/xilinx/versal/plat_versal.c b/plat/xilinx/versal/plat_versal.c
index 15b89bf..54c35b6 100644
--- a/plat/xilinx/versal/plat_versal.c
+++ b/plat/xilinx/versal/plat_versal.c
@@ -9,7 +9,7 @@
 
 int plat_core_pos_by_mpidr(u_register_t mpidr)
 {
-	if (mpidr & MPIDR_CLUSTER_MASK) {
+	if ((mpidr & MPIDR_CLUSTER_MASK) != 0U) {
 		return -1;
 	}