diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h
index 202ef5c..117826d 100644
--- a/include/lib/cpus/aarch64/neoverse_poseidon.h
+++ b/include/lib/cpus/aarch64/neoverse_poseidon.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,7 +8,8 @@
 #define NEOVERSE_POSEIDON_H
 
 
-#define NEOVERSE_POSEIDON_MIDR                      		U(0x410FD830)
+#define NEOVERSE_POSEIDON_VNAE_MIDR				U(0x410FD830)
+#define NEOVERSE_POSEIDON_V_MIDR				U(0x410FD840)
 
 /* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
 #define NEOVERSE_POSEIDON_BHB_LOOP_COUNT			U(132)
diff --git a/include/plat/arm/board/common/rotpk/rotpk_def.h b/include/plat/arm/board/common/rotpk/rotpk_def.h
new file mode 100644
index 0000000..685c21a
--- /dev/null
+++ b/include/plat/arm/board/common/rotpk/rotpk_def.h
@@ -0,0 +1,24 @@
+
+/*
+ * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ROTPK_DEF_H
+#define ROTPK_DEF_H
+
+/*
+ * Definitions related to ROTPK
+ */
+
+/*
+ * Root of trust key lengths
+ */
+#ifndef ARM_ROTPK_HEADER_LEN
+#define ARM_ROTPK_HEADER_LEN		19
+#endif
+#ifndef ARM_ROTPK_HASH_LEN
+#define ARM_ROTPK_HASH_LEN		32
+#endif
+#endif /* ROTPK_DEF_H */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index e098c10..54b184d 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,6 +12,7 @@
 #include <drivers/arm/gic_common.h>
 #include <lib/utils_def.h>
 #include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/rotpk/rotpk_def.h>
 #include <plat/arm/common/smccc_def.h>
 #include <plat/common/common_def.h>
 
@@ -19,11 +20,6 @@
  * Definitions common to all ARM standard platforms
  *****************************************************************************/
 
-/*
- * Root of trust key lengths
- */
-#define ARM_ROTPK_HEADER_LEN		19
-#define ARM_ROTPK_HASH_LEN		32
 
 /* Special value used to verify platform parameters from BL2 to BL31 */
 #define ARM_BL31_PLAT_PARAM_VAL		ULL(0x0f1e2d3c4b5a6978)
diff --git a/lib/cpus/aarch64/neoverse_poseidon.S b/lib/cpus/aarch64/neoverse_poseidon.S
index 3b3245d..54c2ff9 100644
--- a/lib/cpus/aarch64/neoverse_poseidon.S
+++ b/lib/cpus/aarch64/neoverse_poseidon.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -81,6 +81,10 @@
 	ret
 endfunc neoverse_poseidon_cpu_reg_dump
 
-declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \
+declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_VNAE_MIDR, \
+	neoverse_poseidon_reset_func, \
+	neoverse_poseidon_core_pwr_dwn
+
+declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_V_MIDR, \
 	neoverse_poseidon_reset_func, \
 	neoverse_poseidon_core_pwr_dwn
diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
index a7fadf6..22ae9d3 100644
--- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S
+++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
@@ -1,17 +1,10 @@
 /*
- * Copyright (c) 2021-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-/* corstone1000 platform provides custom values for the macros defined in
- * arm_def.h , so only platform_def.h needs to be included
- */
-#if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)
-#include "plat/arm/common/arm_def.h"
-#else
-#include <platform_def.h>
-#endif
+#include <plat/arm/board/common/rotpk/rotpk_def.h>
 
 	.global arm_rotpk_header
 	.section .rodata.arm_rotpk_hash, "a"
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
index 442d187..6953b89 100644
--- a/plat/arm/board/corstone1000/common/include/platform_def.h
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,15 +10,13 @@
 #include <common/tbbr/tbbr_img_def.h>
 #include <lib/utils_def.h>
 #include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/rotpk/rotpk_def.h>
 #include <plat/arm/board/common/v2m_def.h>
 #include <plat/arm/common/arm_spm_def.h>
 #include <plat/arm/common/smccc_def.h>
 #include <plat/common/common_def.h>
 #include <plat/arm/soc/common/soc_css_def.h>
 
-#define ARM_ROTPK_HEADER_LEN		19
-#define ARM_ROTPK_HASH_LEN		32
-
 /* Special value used to verify platform parameters from BL2 to BL31 */
 #define ARM_BL31_PLAT_PARAM_VAL		ULL(0x0f1e2d3c4b5a6978)
 
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index 65749f3..349233a 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -60,7 +60,9 @@
 #define BL31_LIMIT			(BL31_BASE + BL31_SIZE)
 
 /* non-secure uboot base */
+#ifndef PLAT_NS_IMAGE_OFFSET
 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
+#endif
 #define PLAT_NS_IMAGE_SIZE		U(0x00200000)
 
 #define BL32_FDT_OVERLAY_ADDR		(PLAT_NS_IMAGE_OFFSET + 0x3000000)
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 97f4f24..6136820 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -153,6 +153,10 @@
 ERRATA_A53_843419	:=	1
 ERRATA_A53_855873	:=	1
 
+ifneq (${PRELOADED_BL33_BASE},)
+$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
+endif
+
 BL32_BASE		?=	0xbe000000
 $(eval $(call add_define,BL32_BASE))
 
diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h
index d5176dd..8e7be98 100644
--- a/plat/imx/imx8m/imx8mn/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mn/include/platform_def.h
@@ -45,7 +45,9 @@
 #define BL31_LIMIT			(BL31_BASE + BL31_SIZE)
 
 /* non-secure uboot base */
+#ifndef PLAT_NS_IMAGE_OFFSET
 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
+#endif
 
 #define BL32_FDT_OVERLAY_ADDR		(PLAT_NS_IMAGE_OFFSET + 0x3000000)
 
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index e0826e2..6036b6a 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -59,6 +59,10 @@
 ERRATA_A53_843419	:=	1
 ERRATA_A53_855873	:=	1
 
+ifneq (${PRELOADED_BL33_BASE},)
+$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
+endif
+
 BL32_BASE		?=	0xbe000000
 $(eval $(call add_define,BL32_BASE))
 
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index 1281270..4a03830 100644
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -62,7 +62,9 @@
 #define PLAT_SDEI_SGI_PRIVATE		U(9)
 
 /* non-secure uboot base */
+#ifndef PLAT_NS_IMAGE_OFFSET
 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
+#endif
 #define PLAT_NS_IMAGE_SIZE		U(0x00200000)
 
 #define BL32_FDT_OVERLAY_ADDR		(PLAT_NS_IMAGE_OFFSET + 0x3000000)
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index ce69071..40764b1 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -150,6 +150,10 @@
 ERRATA_A53_843419	:=	1
 ERRATA_A53_855873	:=	1
 
+ifneq (${PRELOADED_BL33_BASE},)
+$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
+endif
+
 BL32_BASE		?=	0x56000000
 $(eval $(call add_define,BL32_BASE))
 
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 2526a02..b04f391 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -38,7 +38,9 @@
 #define BL31_LIMIT			(BL31_BASE + BL31_SIZE)
 
 /* non-secure uboot base */
+#ifndef PLAT_NS_IMAGE_OFFSET
 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
+#endif
 #define BL32_FDT_OVERLAY_ADDR		(PLAT_NS_IMAGE_OFFSET + 0x3000000)
 
 /* GICv3 base address */
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index b1c189f..2356cbd 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -55,6 +55,10 @@
 ERRATA_A53_843419	:=	1
 ERRATA_A53_855873	:=	1
 
+ifneq (${PRELOADED_BL33_BASE},)
+$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
+endif
+
 BL32_BASE		?=	0xfe000000
 $(eval $(call add_define,BL32_BASE))
 
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 0895bf9..9ef7598 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -9,6 +9,7 @@
 #define PLAT_SOCFPGA_DEF_H
 
 #include "agilex_system_manager.h"
+#include <lib/utils_def.h>
 #include <platform_def.h>
 
 /* Platform Setting */
@@ -90,8 +91,8 @@
 #define PLAT_GICD_BASE				(PLAT_GIC_BASE + 0x1000)
 #define PLAT_GICR_BASE				0
 
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
-#define PLAT_HZ_CONVERT_TO_MHZ	(1000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS		(400000000)
+#define PLAT_HZ_CONVERT_TO_MHZ		(1000000)
 
 /*******************************************************************************
  * SDMMC related pointer function
@@ -106,6 +107,6 @@
 #define L2_RESET_DONE_REG			0xFFD12218
 
 /* Platform specific system counter */
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ	get_mpu_periph_clk()
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ		U(400)
 
 #endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index 5c92f72..f81480d 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -53,6 +53,7 @@
 		plat/intel/soc/common/soc/socfpga_handoff.c		\
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
 		plat/intel/soc/common/soc/socfpga_reset_manager.c	\
+		plat/intel/soc/common/drivers/ddr/ddr.c	\
 		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
 		plat/intel/soc/common/drivers/wdt/watchdog.c
 
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index f865124..391eac6 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -398,12 +398,21 @@
 	return mpu_clk;
 }
 
+uint32_t get_l4_clk(void)
+{
+	uint32_t l4_clk;
+
+	l4_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1,
+				CLKMGR_PERPLL_PLLC1);
+	return l4_clk;
+}
+
 /* Get cpu freq clock */
 uint32_t get_cpu_clk(void)
 {
 	uint32_t cpu_clk;
 
-	cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
+	cpu_clk = get_l4_clk()/PLAT_HZ_CONVERT_TO_MHZ;
 
 	return cpu_clk;
 }
diff --git a/plat/intel/soc/common/drivers/ddr/ddr.c b/plat/intel/soc/common/drivers/ddr/ddr.c
index 188302f..62f03ef 100644
--- a/plat/intel/soc/common/drivers/ddr/ddr.c
+++ b/plat/intel/soc/common/drivers/ddr/ddr.c
@@ -7,6 +7,7 @@
 #include <assert.h>
 #include <errno.h>
 #include <common/debug.h>
+#include <drivers/delay_timer.h>
 #include "ddr.h"
 #include <lib/mmio.h>
 #include "socfpga_handoff.h"
@@ -340,3 +341,143 @@
 	NOTICE("DDR init successfully\n");
 	return status;
 }
+
+int ddr_config_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type)
+{
+	uint32_t temp[9] = {0};
+	int ret = 0;
+
+	/* Write default value to prevent scrubber stop due to lower power */
+	mmio_write_32(0, umctl2_base + DDR4_PWRCTL_OFFSET);
+
+	/* To backup user configurations in temp array */
+	temp[0] = mmio_read_32(umctl2_base + DDR4_SBRCTL_OFFSET);
+	temp[1] = mmio_read_32(umctl2_base + DDR4_SBRWDATA0_OFFSET);
+	temp[2] = mmio_read_32(umctl2_base + DDR4_SBRSTART0_OFFSET);
+	if (umctl2_type == DDR_TYPE_DDR4) {
+		temp[3] = mmio_read_32(umctl2_base + DDR4_SBRWDATA1_OFFSET);
+		temp[4] = mmio_read_32(umctl2_base + DDR4_SBRSTART1_OFFSET);
+	}
+	temp[5] = mmio_read_32(umctl2_base + DDR4_SBRRANGE0_OFFSET);
+	temp[6] = mmio_read_32(umctl2_base + DDR4_SBRRANGE1_OFFSET);
+	temp[7] = mmio_read_32(umctl2_base + DDR4_ECCCFG0_OFFSET);
+	temp[8] = mmio_read_32(umctl2_base + DDR4_ECCCFG1_OFFSET);
+
+	if (umctl2_type != DDR_TYPE_DDR4) {
+		/* Lock ECC region, ensure this regions is not being accessed */
+		mmio_setbits_32(umctl2_base + DDR4_ECCCFG1_OFFSET,
+			     LPDDR4_ECCCFG1_ECC_REGIONS_PARITY_LOCK);
+	}
+	/* Disable input traffic per port */
+	mmio_clrbits_32(umctl2_base + DDR4_PCTRL0_OFFSET, DDR4_PCTRL0_PORT_EN);
+	/* Disables scrubber */
+	mmio_clrbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
+	/* Polling all scrub writes data have been sent */
+	ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),
+			       DDR4_SBRSTAT_SCRUB_BUSY, true, 5000);
+
+	if (ret) {
+		INFO("%s: Timeout while waiting for", __func__);
+		INFO(" sending all scrub data\n");
+		return ret;
+	}
+
+	/* LPDDR4 supports inline ECC only */
+	if (umctl2_type != DDR_TYPE_DDR4) {
+		/*
+		 * Setting all regions for protected, this is required for
+		 * srubber to init whole LPDDR4 expect ECC region
+		 */
+		mmio_write_32(((ONE_EIGHT <<
+		       LPDDR4_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT) |
+		       (ALL_PROTECTED << LPDDR4_ECCCFG0_ECC_REGION_MAP_SHIFT)),
+		       umctl2_base + DDR4_ECCCFG0_OFFSET);
+	}
+
+	/* Scrub_burst = 1, scrub_mode = 1(performs writes) */
+	mmio_write_32(DDR4_SBRCTL_SCRUB_BURST_1 | DDR4_SBRCTL_SCRUB_WRITE,
+	       umctl2_base + DDR4_SBRCTL_OFFSET);
+
+	/* Wipe DDR content after calibration */
+	ret = ddr_zerofill_scrubber(umctl2_base, umctl2_type);
+	if (ret) {
+		ERROR("Failed to clear DDR content\n");
+	}
+
+	/* Polling all scrub writes data have been sent */
+	ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),
+			       DDR4_SBRSTAT_SCRUB_BUSY, true, 5000);
+	if (ret) {
+		INFO("%s: Timeout while waiting for", __func__);
+		INFO(" sending all scrub data\n");
+		return ret;
+	}
+
+	/* Disables scrubber */
+	mmio_clrbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
+
+	/* Restore user configurations */
+	mmio_write_32(temp[0], umctl2_base + DDR4_SBRCTL_OFFSET);
+	mmio_write_32(temp[1], umctl2_base + DDR4_SBRWDATA0_OFFSET);
+	mmio_write_32(temp[2], umctl2_base + DDR4_SBRSTART0_OFFSET);
+	if (umctl2_type == DDR_TYPE_DDR4) {
+		mmio_write_32(temp[3], umctl2_base + DDR4_SBRWDATA1_OFFSET);
+		mmio_write_32(temp[4], umctl2_base + DDR4_SBRSTART1_OFFSET);
+	}
+	mmio_write_32(temp[5], umctl2_base + DDR4_SBRRANGE0_OFFSET);
+	mmio_write_32(temp[6], umctl2_base + DDR4_SBRRANGE1_OFFSET);
+	mmio_write_32(temp[7], umctl2_base + DDR4_ECCCFG0_OFFSET);
+	mmio_write_32(temp[8], umctl2_base + DDR4_ECCCFG1_OFFSET);
+
+	/* Enables ECC scrub on scrubber */
+	if (!(mmio_read_32(umctl2_base + DDR4_SBRCTL_OFFSET) & DDR4_SBRCTL_SCRUB_WRITE)) {
+		/* Enables scrubber */
+		mmio_setbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
+	}
+
+	return 0;
+}
+
+int ddr_zerofill_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type)
+{
+	int ret = 0;
+
+	/* Zeroing whole DDR */
+	mmio_write_32(0, umctl2_base + DDR4_SBRWDATA0_OFFSET);
+	mmio_write_32(0, umctl2_base + DDR4_SBRSTART0_OFFSET);
+	if (umctl2_type == DDR_TYPE_DDR4) {
+		mmio_write_32(0, umctl2_base + DDR4_SBRWDATA1_OFFSET);
+		mmio_write_32(0, umctl2_base + DDR4_SBRSTART1_OFFSET);
+	}
+	mmio_write_32(0, umctl2_base + DDR4_SBRRANGE0_OFFSET);
+	mmio_write_32(0, umctl2_base + DDR4_SBRRANGE1_OFFSET);
+
+	NOTICE("Enabling scrubber (zeroing whole DDR) ...\n");
+
+	/* Enables scrubber */
+	mmio_setbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
+	/* Polling all scrub writes commands have been sent */
+	ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),
+			       DDR4_SBRSTAT_SCRUB_DONE, true, 5000);
+	if (ret) {
+		INFO("%s: Timeout while waiting for", __func__);
+		INFO(" sending all scrub commands\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
+{
+	int time_out = delay_ms;
+
+	while (time_out-- > 0) {
+
+		if ((mmio_read_32(addr) & mask) == match) {
+			return 0;
+		}
+		udelay(1000);
+	}
+	return -ETIMEDOUT;
+}
diff --git a/plat/intel/soc/common/drivers/ddr/ddr.h b/plat/intel/soc/common/drivers/ddr/ddr.h
index 416b64e..e50cda8 100644
--- a/plat/intel/soc/common/drivers/ddr/ddr.h
+++ b/plat/intel/soc/common/drivers/ddr/ddr.h
@@ -10,6 +10,28 @@
 #include <lib/mmio.h>
 #include "socfpga_handoff.h"
 
+enum ddr_type {
+	DDR_TYPE_LPDDR4_0,
+	DDR_TYPE_LPDDR4_1,
+	DDR_TYPE_DDR4,
+	DDR_TYPE_LPDDR5_0,
+	DDR_TYPE_LPDDR5_1,
+	DDR_TYPE_DDR5,
+	DDR_TYPE_UNKNOWN
+};
+
+/* Region size for ECCCFG0.ecc_region_map */
+enum region_size {
+	ONE_EIGHT,
+	ONE_SIXTEENTH,
+	ONE_THIRTY_SECOND,
+	ONE_SIXTY_FOURTH
+};
+
+/* DATATYPE DEFINATION */
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+
 /* MACRO DEFINATION */
 #define IO96B_0_REG_BASE				0x18400000
 #define IO96B_1_REG_BASE				0x18800000
@@ -86,6 +108,34 @@
 
 #define IOSSM_MB_WRITE(addr, data)			mmio_write_32(addr, data)
 
+/* DDR4 Register */
+#define DDR4_PWRCTL_OFFSET				0x30
+#define DDR4_SBRCTL_OFFSET				0x0F24
+#define DDR4_SBRSTAT_OFFSET				0x0F28
+#define DDR4_SBRWDATA0_OFFSET				0x0F2C
+#define DDR4_SBRSTART0_OFFSET				0x0F38
+#define DDR4_SBRWDATA1_OFFSET				0x0F30
+#define DDR4_SBRSTART1_OFFSET				0x0F3C
+#define DDR4_SBRRANGE0_OFFSET				0x0F40
+#define DDR4_SBRRANGE1_OFFSET				0x0F44
+#define DDR4_ECCCFG0_OFFSET				0x70
+#define DDR4_ECCCFG1_OFFSET				0x74
+#define DDR4_PCTRL0_OFFSET				0x0490
+
+#define LPDDR4_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT	30
+#define ALL_PROTECTED					0x7F
+#define LPDDR4_ECCCFG0_ECC_REGION_MAP_SHIFT		8
+
+
+
+#define LPDDR4_ECCCFG1_ECC_REGIONS_PARITY_LOCK		BIT(4)
+#define DDR4_PCTRL0_PORT_EN				BIT(0)
+#define DDR4_SBRCTL_SCRUB_EN				BIT(0)
+#define DDR4_SBRSTAT_SCRUB_BUSY				BIT(0)
+#define DDR4_SBRCTL_SCRUB_BURST_1			BIT(4)
+#define DDR4_SBRCTL_SCRUB_WRITE				BIT(2)
+#define DDR4_SBRSTAT_SCRUB_DONE				BIT(1)
+
 /* FUNCTION DEFINATION */
 int ddr_calibration_check(void);
 
@@ -109,4 +159,10 @@
 
 bool is_ddr_init_in_progress(void);
 
+int ddr_zerofill_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type);
+
+int ddr_config_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type);
+
+int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms);
+
 #endif
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index 843ec69..adeb069 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -2175,14 +2175,28 @@
 
 	param_addr_ptr = (uint64_t *) param_addr;
 
+	/* Check if mbox_error is not NULL or 0xF or 0x3FF */
+	if (mbox_error == NULL || *mbox_error > 0xF ||
+		(*mbox_error != 0 && *mbox_error != 0x3FF)) {
+		return INTEL_SIP_SMC_STATUS_REJECTED;
+	}
+
+	/* Check if param_addr is not 0 or larger that 0xFFFFFFFFFF */
+	if (param_addr == 0 || param_addr > 0xFFFFFFFFFF) {
+		return INTEL_SIP_SMC_STATUS_REJECTED;
+	}
+
 	/*
-	 * Since crypto param size vary between mode.
-	 * Check ECB here and limit to size 12 bytes
+	 * Check if not ECB, CBC and CTR mode, addr ptr is NULL.
+	 * Return "Reject" status
 	 */
-	if (((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_ECB_MODE) &&
-		(param_size > FCS_CRYPTO_ECB_BUFFER_SIZE)) {
+	if ((param_addr_ptr == NULL) ||
+		(((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_ECB_MODE) &&
+		((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CBC_MODE) &&
+		((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CTR_MODE))) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
+
 	/*
 	 * Since crypto param size vary between mode.
 	 * Check CBC/CTR here and limit to size 28 bytes
@@ -2193,7 +2207,12 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
-	if (mbox_error == NULL) {
+	/*
+	 * Since crypto param size vary between mode.
+	 * Check ECB here and limit to size 12 bytes
+	 */
+	if (((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_ECB_MODE) &&
+		(param_size > FCS_CRYPTO_ECB_BUFFER_SIZE)) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 7aa6b70..5204146 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -431,7 +431,7 @@
 		 * To request handshake
 		 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 1
 		 */
-		INFO("Set S2F hdskreq ...\n");
+		VERBOSE("Set S2F hdskreq ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_SOC2FPGAREQ);
 
@@ -451,7 +451,7 @@
 		 * To clear idle request
 		 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
 		 */
-		INFO("Clear S2F hdskreq ...\n");
+		VERBOSE("Clear S2F hdskreq ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_SOC2FPGAREQ);
 
@@ -459,7 +459,7 @@
 		 * To assert reset
 		 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
 		 */
-		INFO("Assert S2F ...\n");
+		VERBOSE("Assert S2F ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
 			RSTMGR_BRGMODRST_SOC2FPGA);
 
@@ -472,7 +472,7 @@
 		 * To deassert reset
 		 * Write Reset Manager brgmodrst[soc2fpga] = 0
 		 */
-		INFO("Deassert S2F ...\n");
+		VERBOSE("Deassert S2F ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
 			RSTMGR_BRGMODRST_SOC2FPGA);
 	}
@@ -483,7 +483,7 @@
 		 * To request handshake
 		 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 1
 		 */
-		INFO("Set LWS2F hdskreq ...\n");
+		VERBOSE("Set LWS2F hdskreq ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
 
@@ -503,7 +503,7 @@
 		 * To clear idle request
 		 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
 		 */
-		INFO("Clear LWS2F hdskreq ...\n");
+		VERBOSE("Clear LWS2F hdskreq ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
 
@@ -511,7 +511,7 @@
 		 * To assert reset
 		 * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
 		 */
-		INFO("Assert LWS2F ...\n");
+		VERBOSE("Assert LWS2F ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
 			RSTMGR_BRGMODRST_LWHPS2FPGA);
 
@@ -524,7 +524,7 @@
 		 * To deassert reset
 		 * Write Reset Manager brgmodrst[lwsoc2fpga] = 0
 		 */
-		INFO("Deassert LWS2F ...\n");
+		VERBOSE("Deassert LWS2F ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
 			RSTMGR_BRGMODRST_LWHPS2FPGA);
 	}
@@ -557,21 +557,21 @@
 		 * To request handshake
 		 * Write Reset Manager hdsken[fpgahsen] = 1
 		 */
-		INFO("Set FPGA hdsken(fpgahsen) ...\n");
+		VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
 
 		/*
 		 * To request handshake
 		 * Write Reset Manager hdskreq[fpgahsreq] = 1
 		 */
-		INFO("Set FPGA hdskreq(fpgahsreq) ...\n");
+		VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
 
 		/*
 		 * To poll idle status
 		 * Read Reset Manager hdskack[fpgahsack] = 1
 		 */
-		INFO("Get FPGA hdskack(fpgahsack) ...\n");
+		VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
 			300);
@@ -584,7 +584,7 @@
 		 * To fence and drain traffic
 		 * Write Reset Manager hdskreq[f2s_flush_req] = 1
 		 */
-		INFO("Set F2S hdskreq(f2s_flush_req) ...\n");
+		VERBOSE("Set F2S hdskreq(f2s_flush_req) ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_FPGA2SOCREQ);
 
@@ -592,7 +592,7 @@
 		 * To poll idle status
 		 * Read Reset Manager hdskack[f2s_flush_ack] = 1
 		 */
-		INFO("Get F2S hdskack(f2s_flush_ack) ...\n");
+		VERBOSE("Get F2S hdskack(f2s_flush_ack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK,
 			300);
@@ -605,14 +605,14 @@
 		 * To clear idle request
 		 * Write Reset Manager hdskreq[fpgahsreq] = 1
 		 */
-		INFO("Clear FPGA hdskreq(fpgahsreq) ...\n");
+		VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
 
 		/*
 		 * To clear idle request
 		 * Write Reset Manager hdskreq[f2s_flush_req] = 1
 		 */
-		INFO("Clear F2S hdskreq(f2s_flush_req) ...\n");
+		VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_FPGA2SOCREQ);
 
@@ -620,7 +620,7 @@
 		 * To poll idle status
 		 * Read Reset Manager hdskack[f2s_flush_ack] = 0
 		 */
-		INFO("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
+		VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
 			300);
@@ -633,7 +633,7 @@
 		 * To poll idle status
 		 * Read Reset Manager hdskack[fpgahsack] = 0
 		 */
-		INFO("Get FPGA hdskack(fpgahsack) ...\n");
+		VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
 			300);
@@ -646,7 +646,7 @@
 		 * To assert reset
 		 * Write Reset Manager brgmodrst[fpga2soc] = 1
 		 */
-		INFO("Assert F2S ...\n");
+		VERBOSE("Assert F2S ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
 
 		/* ToDo: Shall use udelay for product release */
@@ -658,11 +658,11 @@
 		 * To deassert reset
 		 * Write Reset Manager brgmodrst[fpga2soc] = 0
 		 */
-		INFO("Deassert F2S ...\n");
+		VERBOSE("Deassert F2S ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
 
 		/* Write System Manager f2s bridge control register[f2soc_enable] = 1 */
-		INFO("Deassert F2S f2soc_enable ...\n");
+		VERBOSE("Deassert F2S f2soc_enable ...\n");
 		mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
 			SYSMGR_F2S_BRIDGE_CTRL_EN);
 	}
@@ -673,21 +673,21 @@
 		 * To request handshake
 		 * Write Reset Manager hdsken[fpgahsen] = 1
 		 */
-		INFO("Set F2SDRAM hdsken(fpgahsen) ...\n");
+		VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
 
 		/*
 		 * To request handshake
 		 * Write Reset Manager hdskreq[fpgahsreq] = 1
 		 */
-		INFO("Set F2SDRAM hdskreq(fpgahsreq) ...\n");
+		VERBOSE("Set F2SDRAM hdskreq(fpgahsreq) ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
 
 		/*
 		 * To poll idle status
 		 * Read Reset Manager hdskack[fpgahsack] = 1
 		 */
-		INFO("Get F2SDRAM hdskack(fpgahsack) ...\n");
+		VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
 			300);
@@ -700,7 +700,7 @@
 		 * To fence and drain traffic
 		 * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
 		 */
-		INFO("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
+		VERBOSE("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_F2SDRAM0REQ);
 
@@ -708,7 +708,7 @@
 		 * To poll idle status
 		 * Read Reset Manager hdskack[f2sdram_flush_ack] = 1
 		 */
-		INFO("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
+		VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK,
 			300);
@@ -721,21 +721,21 @@
 		 * To clear idle request
 		 * Write Reset Manager hdskreq[fpgahsreq] = 1
 		 */
-		INFO("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
+		VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
 
 		/*
 		 * To clear idle request
 		 * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
 		 */
-		INFO("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
+		VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
 
 		/*
 		 * To poll idle status
 		 * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
 		 */
-		INFO("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
+		VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
 			300);
@@ -748,7 +748,7 @@
 		 * To poll idle status
 		 * Read Reset Manager hdskack[fpgahsack] = 0
 		 */
-		INFO("Get F2SDRAM hdskack(fpgahsack) ...\n");
+		VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
 			300);
@@ -761,7 +761,7 @@
 		 * To assert reset
 		 * Write Reset Manager brgmodrst[fpga2sdram] = 1
 		 */
-		INFO("Assert F2SDRAM ...\n");
+		VERBOSE("Assert F2SDRAM ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
 			RSTMGR_BRGMODRST_F2SSDRAM0);
 
@@ -774,7 +774,7 @@
 		 * To deassert reset
 		 * Write Reset Manager brgmodrst[fpga2sdram] = 0
 		 */
-		INFO("Deassert F2SDRAM ...\n");
+		VERBOSE("Deassert F2SDRAM ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
 			RSTMGR_BRGMODRST_F2SSDRAM0);
 
@@ -782,7 +782,7 @@
 		 * Clear fpga2sdram_manager_main_SidebandManager_FlagOutClr0
 		 * f2s_ready_latency_enable
 		 */
-		INFO("Clear F2SDRAM f2s_ready_latency_enable ...\n");
+		VERBOSE("Clear F2SDRAM f2s_ready_latency_enable ...\n");
 		mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
 			FLAGOUTCLR0_F2SDRAM0_ENABLE);
 	}
@@ -885,7 +885,7 @@
 		 * To clear handshake
 		 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
 		 */
-		INFO("Set S2F hdskreq ...\n");
+		VERBOSE("Set S2F hdskreq ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_SOC2FPGAREQ);
 
@@ -905,7 +905,7 @@
 		 * To assert reset
 		 * Write Reset Manager brgmodrst[soc2fpga] = 1
 		 */
-		INFO("Assert S2F ...\n");
+		VERBOSE("Assert S2F ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
 			RSTMGR_BRGMODRST_SOC2FPGA);
 
@@ -921,7 +921,7 @@
 		 * To clear handshake
 		 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
 		 */
-		INFO("Set LWS2F hdskreq ...\n");
+		VERBOSE("Set LWS2F hdskreq ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
 
@@ -941,7 +941,7 @@
 		 * To assert reset
 		 * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
 		 */
-		INFO("Assert LWS2F ...\n");
+		VERBOSE("Assert LWS2F ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
 			RSTMGR_BRGMODRST_LWHPS2FPGA);
 
@@ -986,21 +986,21 @@
 		 * To request handshake
 		 * Write Reset Manager hdsken[fpgahsen] = 1
 		 */
-		INFO("Set FPGA hdsken(fpgahsen) ...\n");
+		VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
 
 		/*
 		 * To clear handshake request
 		 * Write Reset Manager hdskreq[fpgahsreq] = 0
 		 */
-		INFO("Clear FPGA hdskreq(fpgahsreq) ...\n");
+		VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
 
 		/*
 		 * To clear handshake request
 		 * Write Reset Manager hdskreq[f2s_flush_req] = 0
 		 */
-		INFO("Clear F2S hdskreq(f2s_flush_req) ...\n");
+		VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
 			RSTMGR_HDSKREQ_FPGA2SOCREQ);
 
@@ -1008,7 +1008,7 @@
 		 * To poll idle status
 		 * Read Reset Manager hdskack[f2s_flush_ack] = 0
 		 */
-		INFO("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
+		VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
 			300);
@@ -1021,7 +1021,7 @@
 		 * To poll idle status
 		 * Read Reset Manager hdskack[fpgahsack] = 0
 		 */
-		INFO("Get FPGA hdskack(fpgahsack) ...\n");
+		VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
 			300);
@@ -1034,7 +1034,7 @@
 		 * To assert reset
 		 * Write Reset Manager brgmodrst[fpga2soc] = 1
 		 */
-		INFO("Assert F2S ...\n");
+		VERBOSE("Assert F2S ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
 
 		/* ToDo: Shall use udelay for product release */
@@ -1043,7 +1043,7 @@
 		}
 
 		/* Write System Manager f2s bridge control register[f2soc_enable] = 0 */
-		INFO("Assert F2S f2soc_enable ...\n");
+		VERBOSE("Assert F2S f2soc_enable ...\n");
 		mmio_clrbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
 			SYSMGR_F2S_BRIDGE_CTRL_EN);
 	}
@@ -1054,28 +1054,28 @@
 		 * To request handshake
 		 * Write Reset Manager hdsken[fpgahsen] = 1
 		 */
-		INFO("Set F2SDRAM hdsken(fpgahsen) ...\n");
+		VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
 
 		/*
 		 * To clear handshake request
 		 * Write Reset Manager hdskreq[fpgahsreq] = 0
 		 */
-		INFO("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
+		VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
 
 		/*
 		 * To clear handshake request
 		 * Write Reset Manager hdskreq[f2sdram_flush_req] = 0
 		 */
-		INFO("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
+		VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
 
 		/*
 		 * To poll idle status
 		 * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
 		 */
-		INFO("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
+		VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
 			300);
@@ -1088,7 +1088,7 @@
 		 * To poll idle status
 		 * Read Reset Manager hdskack[fpgahsack] = 0
 		 */
-		INFO("Get F2SDRAM hdskack(fpgahsack) ...\n");
+		VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
 		ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
 			RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
 			300);
@@ -1101,7 +1101,7 @@
 		 * To assert reset
 		 * Write Reset Manager brgmodrst[fpga2sdram] = 1
 		 */
-		INFO("Assert F2SDRAM ...\n");
+		VERBOSE("Assert F2SDRAM ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
 			RSTMGR_BRGMODRST_F2SSDRAM0);
 
@@ -1114,7 +1114,7 @@
 		 * Assert fpga2sdram_manager_main_SidebandManager_FlagOutClr0
 		 * f2s_ready_latency_enable
 		 */
-		INFO("Assert F2SDRAM f2s_ready_latency_enable ...\n");
+		VERBOSE("Assert F2SDRAM f2s_ready_latency_enable ...\n");
 		mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
 			FLAGOUTCLR0_F2SDRAM0_ENABLE);
 	}
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index 3568e3b..1eafeef 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -9,14 +9,15 @@
 #define PLAT_SOCFPGA_DEF_H
 
 #include <platform_def.h>
+#include <lib/utils_def.h>
 #include "n5x_system_manager.h"
 
 /* Platform Setting */
-#define PLATFORM_MODEL						PLAT_SOCFPGA_N5X
-#define BOOT_SOURCE							BOOT_SOURCE_SDMMC
-#define PLAT_PRIMARY_CPU					0
+#define PLATFORM_MODEL				PLAT_SOCFPGA_N5X
+#define BOOT_SOURCE				BOOT_SOURCE_SDMMC
+#define PLAT_PRIMARY_CPU			0
 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT		MPIDR_AFF1_SHIFT
-#define PLAT_CPU_ID_MPIDR_AFF_SHIFT			MPIDR_AFF0_SHIFT
+#define PLAT_CPU_ID_MPIDR_AFF_SHIFT		MPIDR_AFF0_SHIFT
 
 /* FPGA config helpers */
 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR		0x400000
@@ -34,10 +35,10 @@
 #define SOCFPGA_SYSMGR_REG_BASE			U(0xffd12000)
 #define SOCFPGA_ECC_QSPI_REG_BASE				U(0xffa22000)
 
-#define SOCFPGA_L4_PER_SCR_REG_BASE			U(0xffd21000)
-#define SOCFPGA_L4_SYS_SCR_REG_BASE			U(0xffd21100)
-#define SOCFPGA_SOC2FPGA_SCR_REG_BASE			U(0xffd21200)
-#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE			U(0xffd21300)
+#define SOCFPGA_L4_PER_SCR_REG_BASE		U(0xffd21000)
+#define SOCFPGA_L4_SYS_SCR_REG_BASE		U(0xffd21100)
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE		U(0xffd21200)
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE		U(0xffd21300)
 
 
 /*******************************************************************************
@@ -64,17 +65,17 @@
 #define DEVICE4_BASE				(0x2000000000)
 #define DEVICE4_SIZE				(0x0100000000)
 
-#define BL2_BASE		(0xffe00000)
-#define BL2_LIMIT		(0xffe1b000)
+#define BL2_BASE				(0xffe00000)
+#define BL2_LIMIT				(0xffe1b000)
 
-#define BL31_BASE		(0x1000)
-#define BL31_LIMIT		(0x81000)
+#define BL31_BASE				(0x1000)
+#define BL31_LIMIT				(0x81000)
 
 /*******************************************************************************
  * UART related constants
  ******************************************************************************/
-#define PLAT_UART0_BASE		(0xFFC02000)
-#define PLAT_UART1_BASE		(0xFFC02100)
+#define PLAT_UART0_BASE				(0xFFC02000)
+#define PLAT_UART1_BASE				(0xFFC02100)
 
 /*******************************************************************************
  * WDT related constants
@@ -84,19 +85,19 @@
 /*******************************************************************************
  * GIC related constants
  ******************************************************************************/
-#define PLAT_GIC_BASE			(0xFFFC0000)
-#define PLAT_GICC_BASE			(PLAT_GIC_BASE + 0x2000)
-#define PLAT_GICD_BASE			(PLAT_GIC_BASE + 0x1000)
-#define PLAT_GICR_BASE			0
+#define PLAT_GIC_BASE				(0xFFFC0000)
+#define PLAT_GICC_BASE				(PLAT_GIC_BASE + 0x2000)
+#define PLAT_GICD_BASE				(PLAT_GIC_BASE + 0x1000)
+#define PLAT_GICR_BASE				0
 
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
-#define PLAT_HZ_CONVERT_TO_MHZ	(1000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS		(400000000)
+#define PLAT_HZ_CONVERT_TO_MHZ		(1000000)
 
 /*******************************************************************************
  * SDMMC related pointer function
  ******************************************************************************/
-#define SDMMC_READ_BLOCKS	mmc_read_blocks
-#define SDMMC_WRITE_BLOCKS	mmc_write_blocks
+#define SDMMC_READ_BLOCKS			mmc_read_blocks
+#define SDMMC_WRITE_BLOCKS			mmc_write_blocks
 
 /*******************************************************************************
  * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
@@ -105,6 +106,6 @@
 #define L2_RESET_DONE_REG			0xFFD12218
 
 /* Platform specific system counter */
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ	get_mpu_periph_clk()
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ		U(400)
 
 #endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/n5x/soc/n5x_clock_manager.c b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
index 2e3acc9..c33140d 100644
--- a/plat/intel/soc/n5x/soc/n5x_clock_manager.c
+++ b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
@@ -150,7 +150,7 @@
 {
 	uint32_t cpu_clk = 0;
 
-	cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
+	cpu_clk = get_l4_clk()/PLAT_HZ_CONVERT_TO_MHZ;
 
 	return cpu_clk;
 }
diff --git a/plat/intel/soc/stratix10/include/s10_clock_manager.h b/plat/intel/soc/stratix10/include/s10_clock_manager.h
index 790dbc1..c7632be 100644
--- a/plat/intel/soc/stratix10/include/s10_clock_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_clock_manager.h
@@ -95,6 +95,7 @@
 uint32_t get_uart_clk(void);
 uint32_t get_mmc_clk(void);
 uint32_t get_l3_clk(uint32_t ref_clk);
+uint32_t get_cpu_clk(void);
 uint32_t get_ref_clk(uint32_t pllglob);
 uint32_t get_mpu_periph_clk(void);
 
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index 84b7eec..7f452bd 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -8,14 +8,15 @@
 #define PLAT_SOCFPGA_DEF_H
 
 #include <platform_def.h>
+#include <lib/utils_def.h>
 #include "s10_system_manager.h"
 
 /* Platform Setting */
-#define PLATFORM_MODEL						PLAT_SOCFPGA_STRATIX10
-#define BOOT_SOURCE							BOOT_SOURCE_SDMMC
-#define PLAT_PRIMARY_CPU					0
+#define PLATFORM_MODEL				PLAT_SOCFPGA_STRATIX10
+#define BOOT_SOURCE				BOOT_SOURCE_SDMMC
+#define PLAT_PRIMARY_CPU			0
 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT		MPIDR_AFF1_SHIFT
-#define PLAT_CPU_ID_MPIDR_AFF_SHIFT			MPIDR_AFF0_SHIFT
+#define PLAT_CPU_ID_MPIDR_AFF_SHIFT		MPIDR_AFF0_SHIFT
 
 /* FPGA config helpers */
 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR		0x400000
@@ -64,17 +65,17 @@
 #define DEVICE4_BASE				(0x2000000000)
 #define DEVICE4_SIZE				(0x0100000000)
 
-#define BL2_BASE		(0xffe00000)
-#define BL2_LIMIT		(0xffe2b000)
+#define BL2_BASE				(0xffe00000)
+#define BL2_LIMIT				(0xffe2b000)
 
-#define BL31_BASE		(0x1000)
-#define BL31_LIMIT		(0x81000)
+#define BL31_BASE				(0x1000)
+#define BL31_LIMIT				(0x81000)
 
 /*******************************************************************************
  * UART related constants
  ******************************************************************************/
-#define PLAT_UART0_BASE		(0xFFC02000)
-#define PLAT_UART1_BASE		(0xFFC02100)
+#define PLAT_UART0_BASE				(0xFFC02000)
+#define PLAT_UART1_BASE				(0xFFC02100)
 
 /*******************************************************************************
  * WDT related constants
@@ -84,19 +85,19 @@
 /*******************************************************************************
  * GIC related constants
  ******************************************************************************/
-#define PLAT_GIC_BASE			(0xFFFC0000)
-#define PLAT_GICC_BASE			(PLAT_GIC_BASE + 0x2000)
-#define PLAT_GICD_BASE			(PLAT_GIC_BASE + 0x1000)
-#define PLAT_GICR_BASE			0
+#define PLAT_GIC_BASE				(0xFFFC0000)
+#define PLAT_GICC_BASE				(PLAT_GIC_BASE + 0x2000)
+#define PLAT_GICD_BASE				(PLAT_GIC_BASE + 0x1000)
+#define PLAT_GICR_BASE				0
 
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
-#define PLAT_HZ_CONVERT_TO_MHZ	(1000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS		(400000000)
+#define PLAT_HZ_CONVERT_TO_MHZ		(1000000)
 
 /*******************************************************************************
  * SDMMC related pointer function
  ******************************************************************************/
-#define SDMMC_READ_BLOCKS	mmc_read_blocks
-#define SDMMC_WRITE_BLOCKS	mmc_write_blocks
+#define SDMMC_READ_BLOCKS			mmc_read_blocks
+#define SDMMC_WRITE_BLOCKS			mmc_write_blocks
 
 /*******************************************************************************
  * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
@@ -105,7 +106,7 @@
 #define L2_RESET_DONE_REG			0xFFD12218
 
 /* Platform specific system counter */
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ	get_mpu_periph_clk()
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ		U(400)
 
 #endif /* PLATSOCFPGA_DEF_H */
 
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 6bc96fb..9567c45 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -53,6 +53,7 @@
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
 		plat/intel/soc/common/soc/socfpga_reset_manager.c	\
 		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
+		plat/intel/soc/common/drivers/ddr/ddr.c	\
 		plat/intel/soc/common/drivers/wdt/watchdog.c
 
 include lib/zlib/zlib.mk
diff --git a/services/std_svc/rmmd/rmmd.mk b/services/std_svc/rmmd/rmmd.mk
index bcf54e1..eae5031 100644
--- a/services/std_svc/rmmd/rmmd.mk
+++ b/services/std_svc/rmmd/rmmd.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -8,7 +8,10 @@
         $(error "Error: RMMD is only supported on aarch64.")
 endif
 
-include services/std_svc/rmmd/trp/trp.mk
+# Include TRP makefile only if RMM is not defined.
+ifeq ($(RMM),)
+        include services/std_svc/rmmd/trp/trp.mk
+endif
 
 RMMD_SOURCES	+=	$(addprefix services/std_svc/rmmd/,	\
 			${ARCH}/rmmd_helpers.S			\