diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 18f3368..5986416 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -679,13 +679,6 @@
 		tegra_mc_write_32(index, 0);
 
 	/*
-	 * Allow CPU read/write access to the aperture
-	 */
-	tegra_mc_write_32(MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1,
-		TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT |
-		TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT);
-
-	/*
 	 * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
 	 */
 	assert(!(phys_base & 0xFFF));
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index f919ac3..8a1dd3f 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -182,8 +182,6 @@
 #define  TZRAM_ENABLE_TZ_LOCK_BIT		(1 << 0)
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0	0x21A0
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1	0x21A4
-#define  TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT	(1 << 25)
-#define  TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT	(1 << 7)
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2	0x21A8
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3	0x21AC
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4	0x21B0