Merge "feat(tc): add default SLC policy for the gpu" into integration
diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index 07916fd..494c825 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -278,37 +278,35 @@
#size-cells = <1>;
ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>;
- cpu_scp_scmi_mem: scp-shmem@0 {
+ cpu_scp_scmi_a2p: scp-shmem@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x80>;
};
};
mbox_db_rx: mhu@MHU_RX_ADDR {
- compatible = "arm,mhuv2-rx","arm,primecell";
- reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>;
+ compatible = MHU_RX_COMPAT;
+ reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
- #mbox-cells = <2>;
- interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mhu_rx";
+ #mbox-cells = <MHU_MBOX_CELLS>;
+ interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = MHU_RX_INT_NAME;
};
mbox_db_tx: mhu@MHU_TX_ADDR {
- compatible = "arm,mhuv2-tx","arm,primecell";
- reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>;
+ compatible = MHU_TX_COMPAT;
+ reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
- #mbox-cells = <2>;
- interrupt-names = "mhu_tx";
+ #mbox-cells = <MHU_MBOX_CELLS>;
+ interrupt-names = MHU_TX_INT_NAME;
};
firmware {
scmi {
compatible = "arm,scmi";
mbox-names = "tx", "rx";
- mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
- shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/fdts/tc-fvp.dtsi b/fdts/tc-fvp.dtsi
index 46b0e81..9f3a9ac 100644
--- a/fdts/tc-fvp.dtsi
+++ b/fdts/tc-fvp.dtsi
@@ -7,6 +7,23 @@
#define GIC_CTRL_ADDR 2c010000
#define GIC_GICR_OFFSET 0x200000
#define UART_OFFSET 0x1000
+
+#ifdef TC_RESOLUTION_1920X1080P60
+
+#define VENCODER_TIMING_CLK 148500000
+#define VENCODER_TIMING \
+ clock-frequency = <VENCODER_TIMING_CLK>; \
+ hactive = <1920>; \
+ vactive = <1080>; \
+ hfront-porch = <88>; \
+ hback-porch = <148>; \
+ hsync-len = <44>; \
+ vfront-porch = <4>; \
+ vback-porch = <36>; \
+ vsync-len = <5>
+
+#else /* TC_RESOLUTION_640X480P60 */
+
#define VENCODER_TIMING_CLK 25175000
#define VENCODER_TIMING \
clock-frequency = <VENCODER_TIMING_CLK>; \
@@ -19,6 +36,8 @@
vback-porch = <33>; \
vsync-len = <2>
+#endif
+
/ {
chosen {
stdout-path = "serial0:115200n8";
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
index 288b40f..69c6886 100644
--- a/fdts/tc2.dts
+++ b/fdts/tc2.dts
@@ -20,9 +20,17 @@
#endif /* TARGET_FLAVOUR_FPGA */
#define BIG_CAPACITY 1024
-#define INT_MBOX_RX 317
#define MHU_TX_ADDR 45000000 /* hex */
+#define MHU_TX_COMPAT "arm,mhuv2-tx","arm,primecell"
+#define MHU_TX_INT_NAME "mhu_tx"
+
#define MHU_RX_ADDR 45010000 /* hex */
+#define MHU_RX_COMPAT "arm,mhuv2-rx","arm,primecell"
+#define MHU_OFFSET 0x1000
+#define MHU_MBOX_CELLS 2
+#define MHU_RX_INT_NUM 317
+#define MHU_RX_INT_NAME "mhu_rx"
+
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ 5000000
@@ -211,6 +219,24 @@
arm,mhuv2-protocols = <0 1>;
};
+ firmware {
+ /*
+ * TC2 does not have a P2A channel, but wiring one was needed to make Linux work
+ * (by chance). At the time the SCMI driver did not support bidirectional
+ * mailboxes so as a workaround, the A2P channel was wired for TX communication
+ * and the synchronous replies would be read asyncrhonously as if coming from
+ * the P2A channel, while being the actual A2P channel.
+ *
+ * This will not work with kernels > 5.15, but keep it around to keep TC2
+ * working with its target kernel. Newer kernels will still work, but SCMI
+ * won't as they check that the two regions are distinct.
+ */
+ scmi {
+ mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0>;
+ shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_a2p>;
+ };
+ };
+
dp0: display@DPU_ADDR {
#if TC_SCMI_PD_CTRL_EN
power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index 52b0856..fe6a695 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -14,9 +14,17 @@
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024
-#define INT_MBOX_RX 300
#define MHU_TX_ADDR 46040000 /* hex */
+#define MHU_TX_COMPAT "arm,mhuv3"
+#define MHU_TX_INT_NAME ""
+
#define MHU_RX_ADDR 46140000 /* hex */
+#define MHU_RX_COMPAT "arm,mhuv3"
+#define MHU_OFFSET 0x10000
+#define MHU_MBOX_CELLS 3
+#define MHU_RX_INT_NUM 300
+#define MHU_RX_INT_NAME "combined-mbx"
+
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
@@ -63,4 +71,18 @@
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
+
+ sram: sram@6000000 {
+ cpu_scp_scmi_p2a: scp-shmem@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+ };
+
+ firmware {
+ scmi {
+ mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
+ shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
+ };
+ };
};
diff --git a/include/drivers/arm/css/css_mhu_doorbell.h b/include/drivers/arm/css/css_mhu_doorbell.h
index 88302fd..d6c1a2a 100644
--- a/include/drivers/arm/css/css_mhu_doorbell.h
+++ b/include/drivers/arm/css/css_mhu_doorbell.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,10 @@
#define SENDER_REG_STAT(_channel) (0x20 * (_channel))
#define SENDER_REG_SET(_channel) ((0x20 * (_channel)) + 0xC)
+#define MHU_V3_PBX_PDBCW_PAGE_OFFSET UL(0x1000)
+#define MHU_V3_SENDER_REG_SET(_channel) (MHU_V3_PBX_PDBCW_PAGE_OFFSET + \
+ SENDER_REG_SET(_channel))
+
/* Helper macro to ring doorbell */
#define MHU_RING_DOORBELL(addr, modify_mask, preserve_mask) do { \
uint32_t db = mmio_read_32(addr) & (preserve_mask); \
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index dcae95f..0cf7500 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -298,9 +298,14 @@
#endif /* TARGET_PLATFORM == 3 */
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-/* TC2: AP<->RSE MHUs */
+/* AP<->RSS MHUs */
+#if TARGET_PLATFORM <= 2
#define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000)
#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000)
+#elif TARGET_PLATFORM == 3
+#define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000)
+#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000)
+#endif
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 3d10b7e..cd5abd0 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -44,6 +44,18 @@
CTX_INCLUDE_PAUTH_REGS := 1
endif
+# TC RESOLUTION - LIST OF VALID OPTIONS (this impacts only FVP)
+TC_RESOLUTION_OPTIONS := 640x480p60 \
+ 1920x1080p60
+# Set default to the 640x480p60 resolution mode
+TC_RESOLUTION ?= $(firstword $(TC_RESOLUTION_OPTIONS))
+
+# Check resolution option for FVP
+ifneq ($(filter ${TARGET_FLAVOUR}, fvp),)
+ifeq ($(filter ${TC_RESOLUTION}, ${TC_RESOLUTION_OPTIONS}),)
+ $(error TC_RESOLUTION is ${TC_RESOLUTION}, it must be: ${TC_RESOLUTION_OPTIONS})
+endif
+endif
ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
$(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
@@ -61,6 +73,7 @@
$(eval $(call add_defines, \
TARGET_PLATFORM \
TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \
+ TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \
TC_DPU_USE_SCMI_CLK \
TC_SCMI_PD_CTRL_EN \
TC_IOMMU_EN \
@@ -71,6 +84,13 @@
# Save DSU PMU registers on cluster off and restore them on cluster on
PRESERVE_DSU_PMU_REGS := 1
+# Specify MHU type based on platform
+ifneq ($(filter ${TARGET_PLATFORM}, 2),)
+ PLAT_MHU_VERSION := 2
+else
+ PLAT_MHU_VERSION := 3
+endif
+
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 5742d07..d6b0311 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -50,25 +50,33 @@
}
#endif /* PLATFORM_TEST_TFM_TESTSUITE */
-static scmi_channel_plat_info_t tc_scmi_plat_info[] = {
- {
- .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
- .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
- .db_preserve_mask = 0xfffffffe,
- .db_modify_mask = 0x1,
- .ring_doorbell = &mhuv2_ring_doorbell,
- }
+#if TARGET_PLATFORM <= 2
+static scmi_channel_plat_info_t tc_scmi_plat_info = {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
+ .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhuv2_ring_doorbell,
};
+#elif TARGET_PLATFORM == 3
+static scmi_channel_plat_info_t tc_scmi_plat_info = {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
+ .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+};
+#endif
void bl31_platform_setup(void)
{
tc_bl31_common_platform_setup();
}
-scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused)
{
- return &tc_scmi_plat_info[channel_id];
+ return &tc_scmi_plat_info;
}
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index 2d59fc9..61e1076 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -45,7 +45,7 @@
};
struct em_cpu_list{
- unsigned long cpu_partnumber; /* cpu specific part number defined in midr reg */
+ unsigned long cpu_midr; /* cpu specific part number is bit[15:4] of midr value */
struct em_cpu cpu_errata_list[MAX_PLAT_CPU_ERRATA_ENTRIES];
};
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 0a1d4f3..0d0ecc3 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -23,7 +23,7 @@
struct em_cpu_list cpu_list[] = {
#if CORTEX_A78_H_INC
{
- .cpu_partnumber = CORTEX_A78_MIDR,
+ .cpu_midr = CORTEX_A78_MIDR,
.cpu_errata_list = {
[0] = {2712571, 0x00, 0x12},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -33,7 +33,7 @@
#if CORTEX_A78_AE_H_INC
{
- .cpu_partnumber = CORTEX_A78_AE_MIDR,
+ .cpu_midr = CORTEX_A78_AE_MIDR,
.cpu_errata_list = {
[0] = {2712574, 0x00, 0x02},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -43,7 +43,7 @@
#if CORTEX_A78C_H_INC
{
- .cpu_partnumber = CORTEX_A78C_MIDR,
+ .cpu_midr = CORTEX_A78C_MIDR,
.cpu_errata_list = {
[0] = {2712575, 0x01, 0x02},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -53,7 +53,7 @@
#if NEOVERSE_V1_H_INC
{
- .cpu_partnumber = NEOVERSE_V1_MIDR,
+ .cpu_midr = NEOVERSE_V1_MIDR,
.cpu_errata_list = {
[0] = {2701953, 0x00, 0x11},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -63,7 +63,7 @@
#if CORTEX_A710_H_INC
{
- .cpu_partnumber = CORTEX_A710_MIDR,
+ .cpu_midr = CORTEX_A710_MIDR,
.cpu_errata_list = {
[0] = {2701952, 0x00, 0x21},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -73,7 +73,7 @@
#if NEOVERSE_N2_H_INC
{
- .cpu_partnumber = NEOVERSE_N2_MIDR,
+ .cpu_midr = NEOVERSE_N2_MIDR,
.cpu_errata_list = {
[0] = {2728475, 0x00, 0x02},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -83,7 +83,7 @@
#if CORTEX_X2_H_INC
{
- .cpu_partnumber = CORTEX_X2_MIDR,
+ .cpu_midr = CORTEX_X2_MIDR,
.cpu_errata_list = {
[0] = {2701952, 0x00, 0x21},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -93,7 +93,7 @@
#if NEOVERSE_V2_H_INC
{
- .cpu_partnumber = NEOVERSE_V2_MIDR,
+ .cpu_midr = NEOVERSE_V2_MIDR,
.cpu_errata_list = {
[0] = {2719103, 0x00, 0x01},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -103,7 +103,7 @@
#if CORTEX_X3_H_INC
{
- .cpu_partnumber = CORTEX_X3_MIDR,
+ .cpu_midr = CORTEX_X3_MIDR,
.cpu_errata_list = {
[0] = {2701951, 0x00, 0x11},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -113,7 +113,7 @@
#if CORTEX_X4_H_INC
{
- .cpu_partnumber = CORTEX_X4_MIDR,
+ .cpu_midr = CORTEX_X4_MIDR,
.cpu_errata_list = {
[0] = {2701112, 0x00, 0x00},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
@@ -142,7 +142,7 @@
* If the cpu partnumber in the cpu list, matches the midr
* part number, check to see if the errata ID matches
*/
- if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(cpu_ptr->cpu_partnumber)) {
+ if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(cpu_ptr->cpu_midr)) {
struct em_cpu *ptr = NULL;