Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration
* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): set DRAM information in Boot Manifest platform data
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 2a3d838..e70eb55 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -93,15 +93,6 @@
/* Perform late platform-specific setup */
bl31_plat_arch_setup();
-#if ENABLE_FEAT_HCX
- /*
- * Assert that FEAT_HCX is supported on this system, without this check
- * an exception would occur during context save/restore if enabled but
- * not supported.
- */
- assert(is_feat_hcx_present());
-#endif /* ENABLE_FEAT_HCX */
-
#if CTX_INCLUDE_PAUTH_REGS
/*
* Assert that the ARMv8.3-PAuth registers are present or an access
diff --git a/changelog.yaml b/changelog.yaml
index 1e1f0a1..e100f82 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -101,6 +101,9 @@
- title: Extended Cache Index (FEAT_CCIDX)
scope: ccidx
+ - title: CPU feature / ID register handling in general
+ scope: cpufeat
+
- title: Support for the `HCRX_EL2` register (FEAT_HCX)
scope: hcx
diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c
index 1b065b1..783b660 100644
--- a/common/fdt_wrappers.c
+++ b/common/fdt_wrappers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -206,9 +206,9 @@
assert(cells <= 2U);
if (cells == 2U)
- *(uint64_t *)value = cpu_to_fdt64(*(uint64_t *)value);
+ *(fdt64_t *)value = cpu_to_fdt64(*(uint64_t *)value);
else
- *(uint32_t *)value = cpu_to_fdt32(*(uint32_t *)value);
+ *(fdt32_t *)value = cpu_to_fdt32(*(uint32_t *)value);
len = (int)cells * 4;
@@ -392,7 +392,7 @@
* to a global address with help of various helper functions.
******************************************************************************/
-static bool fdtw_xlat_hit(const uint32_t *value, int child_addr_size,
+static bool fdtw_xlat_hit(const fdt32_t *value, int child_addr_size,
int parent_addr_size, int range_size, uint64_t base_address,
uint64_t *translated_addr)
{
@@ -427,7 +427,7 @@
int local_bus, uint64_t base_address)
{
uint64_t translated_addr;
- const uint32_t *next_entry;
+ const fdt32_t *next_entry;
int parent_bus_node, nxlat_entries, length;
int self_addr_cells, parent_addr_cells, self_size_cells, ncells_xlat;
@@ -460,7 +460,7 @@
assert(nxlat_entries > 0);
- next_entry = (const uint32_t *)ranges_prop->data;
+ next_entry = (const fdt32_t *)ranges_prop->data;
/* Iterate over the entries in the "ranges" */
for (int i = 0; i < nxlat_entries; i++) {
diff --git a/common/feat_detect.c b/common/feat_detect.c
index ee34588..a8c40f7 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -4,24 +4,59 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <arch_features.h>
+#include <common/debug.h>
#include <common/feat_detect.h>
+static bool tainted;
+
/*******************************************************************************
* This section lists the wrapper modules for each feature to evaluate the
- * feature states (FEAT_STATE_1 and FEAT_STATE_2) and perform necessary action
- * as below:
+ * feature states (FEAT_STATE_ALWAYS and FEAT_STATE_CHECK) and perform
+ * necessary action as below:
*
* It verifies whether the FEAT_XXX (eg: FEAT_SB) is supported by the PE or not.
* Without this check an exception would occur during context save/restore
* routines, if the feature is enabled but not supported by PE.
******************************************************************************/
+
+#define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b))
+
+/*******************************************************************************
+ * Function : feature_panic
+ * Customised panic function with error logging mechanism to list the feature
+ * not supported by the PE.
+ ******************************************************************************/
+static inline void feature_panic(char *feat_name)
+{
+ ERROR("FEAT_%s not supported by the PE\n", feat_name);
+ panic();
+}
+
+/*******************************************************************************
+ * Function : check_feature
+ * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and
+ * feature availability on the hardware.
+ * Panics if a feature is forcefully enabled, but not available on the PE.
+ *
+ * We force inlining here to let the compiler optimise away the whole check
+ * if the feature is disabled at build time (FEAT_STATE_DISABLED).
+ ******************************************************************************/
+static inline void __attribute((__always_inline__))
+check_feature(int state, unsigned long field, const char *feat_name)
+{
+ if (state == FEAT_STATE_ALWAYS && field == 0U) {
+ ERROR("FEAT_%s not supported by the PE\n", feat_name);
+ tainted = true;
+ }
+}
/******************************************
* Feature : FEAT_SB (Speculation Barrier)
*****************************************/
static void read_feat_sb(void)
{
-#if (ENABLE_FEAT_SB == FEAT_STATE_1)
+#if (ENABLE_FEAT_SB == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_0_feat_sb_present(), "SB");
#endif
}
@@ -31,7 +66,7 @@
*****************************************************/
static void read_feat_csv2_2(void)
{
-#if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_1)
+#if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_0_feat_csv2_2_present(), "CSV2_2");
#endif
}
@@ -41,7 +76,7 @@
**********************************************/
static void read_feat_pan(void)
{
-#if (ENABLE_FEAT_PAN == FEAT_STATE_1)
+#if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_1_pan_present(), "PAN");
#endif
}
@@ -51,7 +86,7 @@
*****************************************************/
static void read_feat_vhe(void)
{
-#if (ENABLE_FEAT_VHE == FEAT_STATE_1)
+#if (ENABLE_FEAT_VHE == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_1_vhe_present(), "VHE");
#endif
}
@@ -61,7 +96,7 @@
******************************************************************************/
static void read_feat_ras(void)
{
-#if (RAS_EXTENSION == FEAT_STATE_1)
+#if (RAS_EXTENSION == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_2_feat_ras_present(), "RAS");
#endif
}
@@ -71,7 +106,7 @@
***********************************************/
static void read_feat_pauth(void)
{
-#if (ENABLE_PAUTH == FEAT_STATE_1) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_1)
+#if (ENABLE_PAUTH == FEAT_STATE_ALWAYS) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_3_pauth_present(), "PAUTH");
#endif
}
@@ -81,27 +116,17 @@
***********************************************************/
static void read_feat_dit(void)
{
-#if (ENABLE_FEAT_DIT == FEAT_STATE_1)
+#if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_4_feat_dit_present(), "DIT");
#endif
}
-/*********************************************************
- * Feature : FEAT_AMUv1 (Activity Monitors Extensions v1)
- ********************************************************/
-static void read_feat_amuv1(void)
-{
-#if (ENABLE_FEAT_AMUv1 == FEAT_STATE_1)
- feat_detect_panic(is_armv8_4_feat_amuv1_present(), "AMUv1");
-#endif
-}
-
/****************************************************************************
* Feature : FEAT_MPAM (Memory Partitioning and Monitoring (MPAM) Extension)
***************************************************************************/
static void read_feat_mpam(void)
{
-#if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_1)
+#if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_ALWAYS)
feat_detect_panic(get_mpam_version() != 0U, "MPAM");
#endif
}
@@ -111,7 +136,7 @@
*************************************************************/
static void read_feat_nv2(void)
{
-#if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_1)
+#if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS)
unsigned int nv = get_armv8_4_feat_nv_support();
feat_detect_panic((nv == ID_AA64MMFR2_EL1_NV2_SUPPORTED), "NV2");
@@ -123,7 +148,7 @@
**********************************/
static void read_feat_sel2(void)
{
-#if (ENABLE_FEAT_SEL2 == FEAT_STATE_1)
+#if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_4_sel2_present(), "SEL2");
#endif
}
@@ -133,7 +158,7 @@
***************************************************/
static void read_feat_trf(void)
{
-#if (ENABLE_TRF_FOR_NS == FEAT_STATE_1)
+#if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_arm8_4_feat_trf_present(), "TRF");
#endif
}
@@ -143,7 +168,7 @@
***********************************************/
static void read_feat_mte(void)
{
-#if (CTX_INCLUDE_MTE_REGS == FEAT_STATE_1)
+#if (CTX_INCLUDE_MTE_REGS == FEAT_STATE_ALWAYS)
unsigned int mte = get_armv8_5_mte_support();
feat_detect_panic((mte != MTE_UNIMPLEMENTED), "MTE");
@@ -155,7 +180,7 @@
**********************************************/
static void read_feat_rng(void)
{
-#if (ENABLE_FEAT_RNG == FEAT_STATE_1)
+#if (ENABLE_FEAT_RNG == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_5_rng_present(), "RNG");
#endif
}
@@ -165,27 +190,17 @@
***************************************************/
static void read_feat_bti(void)
{
-#if (ENABLE_BTI == FEAT_STATE_1)
+#if (ENABLE_BTI == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_5_bti_present(), "BTI");
#endif
}
-/****************************************
- * Feature : FEAT_FGT (Fine Grain Traps)
- ***************************************/
-static void read_feat_fgt(void)
-{
-#if (ENABLE_FEAT_FGT == FEAT_STATE_1)
- feat_detect_panic(is_armv8_6_fgt_present(), "FGT");
-#endif
-}
-
/***********************************************
* Feature : FEAT_AMUv1p1 (AMU Extensions v1.1)
**********************************************/
static void read_feat_amuv1p1(void)
{
-#if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_1)
+#if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_6_feat_amuv1p1_present(), "AMUv1p1");
#endif
}
@@ -195,7 +210,7 @@
******************************************************/
static void read_feat_ecv(void)
{
-#if (ENABLE_FEAT_ECV == FEAT_STATE_1)
+#if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS)
unsigned int ecv = get_armv8_6_ecv_support();
feat_detect_panic(((ecv == ID_AA64MMFR0_EL1_ECV_SUPPORTED) ||
@@ -208,27 +223,17 @@
**********************************************************/
static void read_feat_twed(void)
{
-#if (ENABLE_FEAT_TWED == FEAT_STATE_1)
+#if (ENABLE_FEAT_TWED == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_6_twed_present(), "TWED");
#endif
}
-/******************************************************************
- * Feature : FEAT_HCX (Extended Hypervisor Configuration Register)
- *****************************************************************/
-static void read_feat_hcx(void)
-{
-#if (ENABLE_FEAT_HCX == FEAT_STATE_1)
- feat_detect_panic(is_feat_hcx_present(), "HCX");
-#endif
-}
-
/**************************************************
* Feature : FEAT_RME (Realm Management Extension)
*************************************************/
static void read_feat_rme(void)
{
-#if (ENABLE_RME == FEAT_STATE_1)
+#if (ENABLE_RME == FEAT_STATE_ALWAYS)
feat_detect_panic((get_armv9_2_feat_rme_support() !=
ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED), "RME");
#endif
@@ -239,7 +244,7 @@
*****************************************************/
static void read_feat_brbe(void)
{
-#if (ENABLE_BRBE_FOR_NS == FEAT_STATE_1)
+#if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_feat_brbe_present(), "BRBE");
#endif
}
@@ -249,7 +254,7 @@
*****************************************************/
static void read_feat_trbe(void)
{
-#if (ENABLE_TRBE_FOR_NS == FEAT_STATE_1)
+#if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_feat_trbe_present(), "TRBE");
#endif
}
@@ -259,7 +264,7 @@
*****************************************************************/
static void read_feat_rng_trap(void)
{
-#if (ENABLE_FEAT_RNG_TRAP == FEAT_STATE_1)
+#if (ENABLE_FEAT_RNG_TRAP == FEAT_STATE_ALWAYS)
feat_detect_panic(is_feat_rng_trap_present(), "RNG_TRAP");
#endif
}
@@ -283,11 +288,14 @@
* ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime
* depending on hardware capability.
*
- * For better readability, state values are defined with macros namely:
- * { FEAT_STATE_0, FEAT_STATE_1, FEAT_STATE_2 } taking values as their naming.
+ * For better readability, state values are defined with macros, namely:
+ * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values
+ * { 0, 1, 2 }, respectively, as their naming.
**********************************************************************************/
void detect_arch_features(void)
{
+ tainted = false;
+
/* v8.0 features */
read_feat_sb();
read_feat_csv2_2();
@@ -304,7 +312,7 @@
/* v8.4 features */
read_feat_dit();
- read_feat_amuv1();
+ check_feature(ENABLE_FEAT_AMUv1, read_feat_amu_id_field(), "AMUv1");
read_feat_mpam();
read_feat_nv2();
read_feat_sel2();
@@ -318,12 +326,12 @@
/* v8.6 features */
read_feat_amuv1p1();
- read_feat_fgt();
+ check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT");
read_feat_ecv();
read_feat_twed();
/* v8.7 features */
- read_feat_hcx();
+ check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX");
/* v9.0 features */
read_feat_brbe();
@@ -331,4 +339,8 @@
/* v9.2 features */
read_feat_rme();
+
+ if (tainted) {
+ panic();
+ }
}
diff --git a/docs/components/realm-management-extension.rst b/docs/components/realm-management-extension.rst
index 2ea8012..919eea5 100644
--- a/docs/components/realm-management-extension.rst
+++ b/docs/components/realm-management-extension.rst
@@ -13,7 +13,7 @@
The following diagram shows an Arm CCA software architecture with TF-A as the
EL3 firmware. In the Arm CCA architecture there are two additional security
states and address spaces: ``Root`` and ``Realm``. TF-A firmware runs in the
-Root world. In the realm world, a Realm Management Monitor firmware (RMM)
+Root world. In the realm world, a Realm Management Monitor firmware (`RMM`_)
manages the execution of Realm VMs and their interaction with the hypervisor.
.. image:: ../resources/diagrams/arm-cca-software-arch.png
@@ -44,7 +44,7 @@
In a typical TF-A boot flow, BL2 runs at Secure-EL1. However when RME is
enabled, TF-A runs in the Root world at EL3. Therefore, the boot flow is
modified to run BL2 at EL3 when RME is enabled. In addition to this, a
-Realm-world firmware (RMM) is loaded by BL2 in the Realm physical address
+Realm-world firmware (`RMM`_) is loaded by BL2 in the Realm physical address
space.
The boot flow when RME is enabled looks like the following:
@@ -70,57 +70,85 @@
RMM Dispatcher (RMMD)
************************
RMMD is a new standard runtime service that handles the switch to the Realm
-world. It initializes the RMM and handles Realm Management Interface (RMI)
-SMC calls from Non-secure and Realm worlds.
+world. It initializes the `RMM`_ and handles Realm Management Interface (RMI)
+SMC calls from Non-secure.
-There is a contract between RMM and RMMD that defines the arguments that the
+There is a contract between `RMM`_ and RMMD that defines the arguments that the
former needs to take in order to initialize and also the possible return values.
-This contract is defined in the RMM Boot Interface, which can be found at
+This contract is defined in the `RMM`_ Boot Interface, which can be found at
:ref:`rmm_el3_boot_interface`.
There is also a specification of the runtime services provided by TF-A
-to RMM. This can be found at :ref:`runtime_services_and_interface`.
+to `RMM`_. This can be found at :ref:`runtime_services_and_interface`.
Test Realm Payload (TRP)
*************************
TRP is a small test payload that runs at R-EL2 and implements a subset of
the Realm Management Interface (RMI) commands to primarily test EL3 firmware
and the interface between R-EL2 and EL3. When building TF-A with RME enabled,
-if a path to an RMM image is not provided, TF-A builds the TRP by default
-and uses it as RMM image.
+if the path to an RMM image is not provided, TF-A builds the TRP by default
+and uses it as the R-EL2 payload.
Building and running TF-A with RME
-------------------------------------
+----------------------------------
This section describes how you can build and run TF-A with RME enabled.
-We assume you have all the :ref:`Prerequisites` to build TF-A.
+We assume you have read the :ref:`Prerequisites` to build TF-A.
The following instructions show you how to build and run TF-A with RME
-for two scenarios:
+on FVP for two scenarios:
-- Three-world execution: TF-A with TF-A Tests or Linux.
+- Three-world execution: This is the configuration to use if Secure
+ world functionality is not needed. TF-A is tested with the following
+ software entities in each world as listed below:
- - NS (TF-A Test or Linux),
+ - NS Host (RME capable Linux or TF-A Tests),
- Root (TF-A)
- - Realm (RMM or TRP)
+ - R-EL2 (`RMM`_ or TRP)
-- Four-world execution: TF-A, Hafnium and TF-A Tests or Linux.
+- Four-world execution: This is the configuration to use if both Secure
+ and Realm world functionality is needed. TF-A is tested with the following
+ software entities in each world as listed below:
- - NS (TF-A Test or Linux),
+ - NS Host (RME capable Linux or TF-A Tests),
- Root (TF-A)
- - Realm (RMM or TRP)
- - SPM (Hafnium)
+ - R-EL2 (`RMM`_ or TRP)
+ - S-EL2 (Hafnium SPM)
To run the tests, you need an FVP model. Please use the :ref:`latest version
-<Arm Fixed Virtual Platforms (FVP)>` of *FVP_Base_RevC-2xAEMvA* model.
+<Arm Fixed Virtual Platforms (FVP)>` of *FVP_Base_RevC-2xAEMvA* model. If NS
+Host is Linux, then the below instructions assume that a suitable RME enabled
+kernel image and associated root filesystem are available.
-Three World Testing with TF-A Tests
-*************************************
+Three-world execution
+*********************
-**1. Obtain and build TF-A Tests with Realm Payload**
+**1. Clone and build RMM Image**
-The full set of instructions to setup build host and build options for
-TF-A-Tests can be found in the `TFTF Getting Started`_.
+Please refer to the `RMM Getting Started`_ on how to setup
+Host Environment and build `RMM`_. The build commands assume that
+an AArch64 toolchain and CMake executable are available in the
+shell PATH variable and CROSS_COMPILE variable has been setup
+appropriately.
+
+To clone `RMM`_ and build using the default build options for FVP:
+
+.. code:: shell
+
+ git clone --recursive https://git.trustedfirmware.org/TF-RMM/tf-rmm.git
+ cd tf-rmm
+ cmake -DRMM_CONFIG=fvp_defcfg -S . -B build
+ cmake --build build
+
+This will generate **rmm.img** in **build/Release** folder.
+
+**2. Clone and build TF-A Tests with Realm Payload**
+
+This step is only needed if NS Host is TF-A Tests. The full set
+of instructions to setup build host and build options for
+TF-A-Tests can be found in the `TFTF Getting Started`_. TF-A Tests
+can test Realm world with either `RMM`_ or TRP in R-EL2. In the TRP case,
+some tests which are not applicable will be skipped.
Use the following instructions to build TF-A with `TF-A Tests`_ as the
non-secure payload (BL33).
@@ -134,37 +162,23 @@
This produces a TF-A Tests binary (**tftf.bin**) with Realm payload packaged
and **sp_layout.json** in the **build/fvp/debug** directory.
-**2. Obtain and build RMM Image**
-
-Please refer to the `RMM Getting Started`_ on how to setup
-Host Environment and build RMM.
-
-The below command shows how to build RMM using the default build options for FVP.
-
-.. code:: shell
-
- git clone --recursive https://git.trustedfirmware.org/TF-RMM/tf-rmm.git
- cd tf-rmm
- cmake -DRMM_CONFIG=fvp_defcfg -S . -B build
- cmake --build build
-
-This will generate **rmm.img** in **build** folder.
-**3. Build TF-A**
+**3. Build RME Enabled TF-A**
The `TF-A Getting Started`_ has the necessary instructions to setup Host
machine and build TF-A.
To build for RME, set ``ENABLE_RME`` build option to 1 and provide the path to
-the RMM binary using the ``RMM`` build option.
-Currently, this feature is only supported for the FVP platform.
+the `RMM`_ binary ``rmm.img`` using ``RMM`` build option.
.. note::
ENABLE_RME build option is currently experimental.
+.. note::
+
-If the ``RMM`` option is not used, then the Test Realm Payload (TRP) in TF-A
-will be built and used as the RMM.
+ If the ``RMM`` option is not specified, TF-A builds the TRP to load and
+ run at R-EL2.
.. code:: shell
@@ -176,16 +190,42 @@
RMM=<path/to/rmm.img> \
FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts \
DEBUG=1 \
- BL33=<path/to/tftf.bin> \
+ BL33=<path/to/bl33> \
+ all fip
+
+``BL33`` can point to a Non Secure Bootloader like UEFI/U-Boot or
+the TF-A Tests binary(**tftf.bin**) from the previous step.
+
+This produces **bl1.bin** and **fip.bin** binaries in the **build/fvp/debug**
+directory.
+
+TF-A can also directly boot Linux kernel on the FVP. The kernel needs to be
+`preloaded` to a suitable memory location and this needs to be specified via
+``PRELOADED_BL33_BASE`` build option. Also TF-A should implement the Linux
+kernel register conventions for boot and this can be set using the
+``ARM_LINUX_KERNEL_AS_BL33`` option.
+
+.. code-block:: shell
+
+ cd trusted-firmware-a
+ make CROSS_COMPILE=aarch64-none-elf- \
+ PLAT=fvp \
+ ENABLE_RME=1 \
+ RMM=<path/to/rmm.img> \
+ FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts \
+ DEBUG=1 \
+ ARM_LINUX_KERNEL_AS_BL33=1 \
+ PRELOADED_BL33_BASE=0x84000000 \
all fip
+The above command assumes that the Linux kernel will be placed in FVP
+memory at 0x84000000 via suitable FVP option (see the next step).
+
-This produces **bl1.bin** and **fip.bin** binaries in the **build/fvp/debug** directory.
+.. _fvp_3_world_cmd:
-Running the tests for a 3 world FVP setup
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+**4. Running FVP for 3 world setup**
-Use the following command to run the tests on FVP. TF-A Tests should boot
-and run the default tests including Realm world tests.
+Use the following command to run the tests on FVP.
.. code:: shell
@@ -239,12 +279,33 @@
-C cluster1.restriction_on_speculative_execution_aarch32=2 \
-C pctl.startup=0.0.0.0 \
-C bp.smsc_91c111.enabled=1 \
- -C bp.hostbridge.userNetworking=1
+ -C bp.hostbridge.userNetworking=1 \
+ -C bp.virtioblockdevice.image_path=<path/to/rootfs.ext4>
-The bottom of the output from *uart0* should look something like the following.
+The ``bp.virtioblockdevice.image_path`` option presents the rootfs as a
+virtio block device to Linux kernel. It can be ignored if NS Host is
+TF-A-Tests or rootfs is accessed by some other mechanism.
+
+If TF-A was built to expect a preloaded Linux kernel, then use the following
+FVP argument to load the kernel image at the expected address.
.. code-block:: shell
+ --data cluster0.cpu0=<path_to_kernel_Image>@0x84000000 \
+
+
+.. tip::
+ Tips to boot and run Linux faster on the FVP :
+ 1. Set the FVP option ``cache_state_modelled`` to 0.
+ 2. Disable the CPU Idle driver in Linux either by setting the kernel command line
+ parameter "cpuidle.off=1" or by disabling the ``CONFIG_CPU_IDLE`` kernel config.
+
+If the NS Host is TF-A-Tests, then the default test suite in TFTF
+will execute on the FVP and this includes Realm world tests. The
+tail of the output from *uart0* should look something like the following.
+
+.. code-block:: shell
+
...
> Test suite 'FF-A Interrupt'
@@ -263,52 +324,19 @@
Passed
...
-Building TF-A with RME enabled Linux Kernel
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-If an RME enabled Linux kernel and filesystem is available for testing,
-and a suitable NS boot loader is not available, then this option can be used to
-launch kernel directly after BL31:
-
-.. code-block:: shell
-
- cd trusted-firmware-a
- make CROSS_COMPILE=aarch64-none-elf- \
- PLAT=fvp \
- ENABLE_RME=1 \
- RMM=<path/to/rmm.img> \
- FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts \
- DEBUG=1 \
- ARM_LINUX_KERNEL_AS_BL33=1 \
- PRELOADED_BL33_BASE=0x84000000 \
- all fip
-
-Boot and run the RME enabled Linux Kernel
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Use the following additional arguments to boot the kernel on FVP.
-
-.. code-block:: shell
-
- --data cluster0.cpu0=<path_to_kernel_Image>@0x84000000 \
- -C bp.virtioblockdevice.image_path=<path_to_rootfs.ext4>
-
-.. tip::
-
- Set the FVP option `cache_state_modelled=0` to run Linux based tests much faster.
-
-Four-world execution with Hafnium and TF-A Tests
-*************************************************
+Four-world execution
+********************
Four-world execution involves software components in each security state: root,
secure, realm and non-secure. This section describes how to build TF-A
with four-world support.
-We use TF-A as the root firmware, `Hafnium SPM`_ is the reference Secure world component
-and the software components for the other 2 worlds (Realm and Non-Secure)
-are as described in the previous section.
+We use TF-A as the root firmware, `Hafnium SPM`_ is the reference Secure world
+component running at S-EL2. `RMM`_ can be built as described in previous
+section. The examples below assume TF-A-Tests as the NS Host and utilize SPs
+from TF-A-Tests.
-**1. Obtain and build Hafnium**
+**1. Obtain and build Hafnium SPM**
.. code:: shell
@@ -342,11 +370,12 @@
The Hafnium binary should be located at
*out/reference/secure_aem_v8a_fvp_clang/hafnium.bin*
-**2. Build TF-A**
+**2. Build RME enabled TF-A with SPM**
Build TF-A with RME as well as SPM enabled.
-Use sp_layout.json previously generated in tf-a-test build.
+Use the ``sp_layout.json`` previously generated in TF-A Tests
+build to run SP tests.
.. code:: shell
@@ -355,7 +384,6 @@
ENABLE_RME=1 \
FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts \
SPD=spmd \
- SPMD_SPM_AT_SEL2=1 \
BRANCH_PROTECTION=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
DEBUG=1 \
@@ -365,11 +393,11 @@
RMM=<path/to/rmm.img> \
all fip
-Running the tests for a 4 world FVP setup
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+**3. Running the FVP for a 4 world setup**
-Use the following arguments in addition to
-`Running the tests for a 3 world FVP setup`_ to run tests for 4 world setup.
+Use the following arguments in addition to the FVP options mentioned in
+:ref:`4. Running FVP for 3 world setup <fvp_3_world_cmd>` to run tests for
+4 world setup.
.. code:: shell
@@ -388,4 +416,5 @@
.. _TF-A Tests: https://trustedfirmware-a-tests.readthedocs.io/en/latest
.. _TFTF Getting Started: https://trustedfirmware-a-tests.readthedocs.io/en/latest/getting_started/index.html
.. _Hafnium SPM: https://www.trustedfirmware.org/projects/hafnium
-.. _RMM Getting Started: https://git.trustedfirmware.org/TF-RMM/tf-rmm.git/tree/docs/getting_started/index.rst
+.. _RMM Getting Started: https://tf-rmm.readthedocs.io/en/latest/getting_started/index.html
+.. _RMM: https://www.trustedfirmware.org/projects/tf-rmm/
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 8a8445d..9db29e6 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -321,6 +321,10 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
it is still open.
+- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
+ it is still open.
+
For Cortex-A78 AE, the following errata build flags are defined :
- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
@@ -357,6 +361,10 @@
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
erratum is still open.
+- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to
+ Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
+ This erratum is still open.
+
For Cortex-X1 CPU, the following errata build flags are defined:
- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1
@@ -468,6 +476,10 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
CPU. It is still open.
+- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
+ CPU. It is still open.
+
For Cortex-A710, the following errata build flags are defined :
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
@@ -661,7 +673,7 @@
Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
r0p3 and r1p0, it is fixed in r1p1.
-- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to
+- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to
Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
r0p3, r1p0 and r1p1. It is fixed in r1p2.
@@ -673,6 +685,10 @@
Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
r0p3, r1p0, r1p1. It is fixed in r1p2.
+- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to
+ Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
+ r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3.
+
DSU Errata Workarounds
----------------------
diff --git a/docs/design_documents/measured_boot_poc.rst b/docs/design_documents/measured_boot_poc.rst
index 3ae539b..2e25057 100644
--- a/docs/design_documents/measured_boot_poc.rst
+++ b/docs/design_documents/measured_boot_poc.rst
@@ -6,7 +6,7 @@
security state can be attested later.
The current implementation of the driver included in Trusted Firmware-A
-(TF-A) stores the measurements into a `TGC event log`_ in secure
+(TF-A) stores the measurements into a `TCG event log`_ in secure
memory. No other means of recording measurements (such as a discrete TPM) is
supported right now.
@@ -24,7 +24,7 @@
platforms might have different needs and configurations (e.g. different
SHA algorithms) and they might also use different types of TPM services
(or even a different type of service to provide the attestation)
- and therefore the instuctions given here might not apply in such scenarios.
+ and therefore the instructions given here might not apply in such scenarios.
Components
~~~~~~~~~~
@@ -497,11 +497,11 @@
--------------
-*Copyright (c) 2021, Arm Limited. All rights reserved.*
+*Copyright (c) 2021-2023, Arm Limited. All rights reserved.*
.. _OP-TEE Toolkit: https://github.com/OP-TEE/build
.. _ms-tpm-20-ref: https://github.com/microsoft/ms-tpm-20-ref
.. _Get and build the solution: https://optee.readthedocs.io/en/latest/building/gits/build.html#get-and-build-the-solution
.. _Armv8-A Foundation Platform (For Linux Hosts Only): https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models
.. _tpm2-tools: https://github.com/tpm2-software/tpm2-tools
-.. _TGC event log: https://trustedcomputinggroup.org/resource/tcg-efi-platform-specification/
+.. _TCG event log: https://trustedcomputinggroup.org/resource/tcg-efi-platform-specification/
diff --git a/docs/process/security.rst b/docs/process/security.rst
index e15783b..f1e7a9d 100644
--- a/docs/process/security.rst
+++ b/docs/process/security.rst
@@ -9,10 +9,8 @@
vulnerabilities and inform users as best we can about all possible issues.
We disclose TF-A vulnerabilities as Security Advisories, all of which are listed
-at the bottom of this page. Any new ones will, additionally, be announced as
-issues in the project's `issue tracker`_ with the ``security-advisory`` tag. You
-can receive notification emails for these by watching the "Trusted Firmware-A"
-project at https://developer.trustedfirmware.org/.
+at the bottom of this page. Any new ones will, additionally, be announced on the
+TF-A project's `mailing list`_.
Found a Security Issue?
-----------------------
@@ -86,4 +84,4 @@
--------------
-*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
diff --git a/drivers/auth/mbedtls/mbedtls_x509_parser.c b/drivers/auth/mbedtls/mbedtls_x509_parser.c
index bef2f3d..bbabd9b 100644
--- a/drivers/auth/mbedtls/mbedtls_x509_parser.c
+++ b/drivers/auth/mbedtls/mbedtls_x509_parser.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -484,7 +484,7 @@
rc = get_ext(type_desc->cookie, param, param_len);
break;
case AUTH_PARAM_PUB_KEY:
- if (type_desc->cookie != 0) {
+ if (type_desc->cookie != NULL) {
/* Get public key from extension */
rc = get_ext(type_desc->cookie, param, param_len);
} else {
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index e3fb749..93c38d8 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,7 +11,7 @@
#include <drivers/console.h>
console_t *console_list;
-uint8_t console_state = CONSOLE_FLAG_BOOT;
+static uint8_t console_state = CONSOLE_FLAG_BOOT;
IMPORT_SYM(console_t *, __STACKS_START__, stacks_start)
IMPORT_SYM(console_t *, __STACKS_END__, stacks_end)
diff --git a/drivers/io/io_block.c b/drivers/io/io_block.c
index 5d45c2f..b5e0e5f 100644
--- a/drivers/io/io_block.c
+++ b/drivers/io/io_block.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -271,7 +271,7 @@
block_size = cur->dev_spec->block_size;
assert((length <= cur->size) &&
(length > 0U) &&
- (ops->read != 0));
+ (ops->read != NULL));
/*
* We don't know the number of bytes that we are going
@@ -383,8 +383,8 @@
block_size = cur->dev_spec->block_size;
assert((length <= cur->size) &&
(length > 0U) &&
- (ops->read != 0) &&
- (ops->write != 0));
+ (ops->read != NULL) &&
+ (ops->write != NULL));
/*
* We don't know the number of bytes that we are going
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 8e83464..2b727d4 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -69,8 +69,7 @@
int i;
for (i = 0; i < 4; i++) {
- *r_data = cmd.resp_data[i];
- r_data++;
+ r_data[i] = cmd.resp_data[i];
}
}
@@ -112,7 +111,7 @@
return MMC_GET_STATE(resp_data[0]);
}
-static int mmc_send_part_switch_cmd(unsigned int part_config)
+static int mmc_send_part_switch_cmd(unsigned char part_config)
{
int ret;
unsigned int part_time = 0;
@@ -760,9 +759,9 @@
return size;
}
-static int mmc_part_switch(unsigned int part_type)
+static int mmc_part_switch(unsigned char part_type)
{
- uint8_t part_config = mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG];
+ unsigned char part_config = mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG];
part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK;
part_config |= part_type;
@@ -780,8 +779,7 @@
unsigned char current_boot_part = mmc_current_boot_part();
int ret;
- if (current_boot_part != 1U &&
- current_boot_part != 2U) {
+ if ((current_boot_part != 1U) && (current_boot_part != 2U)) {
ERROR("Got unexpected value for active boot partition, %u\n", current_boot_part);
return -EIO;
}
diff --git a/drivers/partition/gpt.c b/drivers/partition/gpt.c
index 4fe8322..8b1046d 100644
--- a/drivers/partition/gpt.c
+++ b/drivers/partition/gpt.c
@@ -26,14 +26,16 @@
/* check whether the unicode string is valid */
for (i = 1; i < (EFI_NAMELEN << 1); i += 2) {
- if (name[i] != '\0')
+ if (name[i] != '\0') {
return -EINVAL;
+ }
}
/* convert the unicode string to ascii string */
for (i = 0; i < (EFI_NAMELEN << 1); i += 2) {
str_out[i >> 1] = name[i];
- if (name[i] == '\0')
+ if (name[i] == '\0') {
break;
+ }
}
return 0;
}
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
index a938edc..869b912 100644
--- a/fdts/stm32mp151.dtsi
+++ b/fdts/stm32mp151.dtsi
@@ -127,8 +127,8 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40013000 0x400>;
interrupt-names = "event", "error";
- interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C2_K>;
resets = <&rcc I2C2_R>;
#address-cells = <1>;
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index d928563..63753bd 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -169,23 +169,12 @@
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
- };
+ };
- vbus_sw: pwr_sw2 {
+ vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
+ };
};
};
};
diff --git a/fdts/tc.dts b/fdts/tc.dts
index 192f407..c10b7f8 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -519,6 +519,15 @@
};
};
+ /*
+ * L3 cache in the DSU is the Memory System Component (MSC)
+ * The MPAM registers are accessed through utility bus in the DSU
+ */
+ msc0 {
+ compatible = "arm,mpam-msc";
+ reg = <0x1 0x00010000 0x0 0x2000>;
+ };
+
ete0 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU0>;
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 932e885..2b801ac 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -10,6 +10,7 @@
#include <stdbool.h>
#include <arch_helpers.h>
+#include <common/feat_detect.h>
static inline bool is_armv7_gentimer_present(void)
{
@@ -97,12 +98,25 @@
ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED);
}
-static inline bool is_armv8_6_fgt_present(void)
+static unsigned int read_feat_fgt_id_field(void)
{
- return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
- ID_AA64MMFR0_EL1_FGT_MASK) != 0U;
+ return (read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
+ ID_AA64MMFR0_EL1_FGT_MASK;
}
+static inline bool is_feat_fgt_supported(void)
+{
+ if (ENABLE_FEAT_FGT == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_FGT == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_fgt_id_field() != 0U;
+}
+
static inline unsigned long int get_armv8_6_ecv_support(void)
{
return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) &
@@ -115,10 +129,31 @@
ID_AA64ISAR0_RNDR_MASK);
}
+/*******************************************************************************
+ * Functions to identify the presence of the Activity Monitors Extension
+ ******************************************************************************/
+static unsigned int read_feat_amu_id_field(void)
+{
+ return (read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
+ ID_AA64PFR0_AMU_MASK;
+}
+
+static inline bool is_feat_amu_supported(void)
+{
+ if (ENABLE_FEAT_AMUv1 == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_AMUv1 == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1;
+}
+
static inline bool is_armv8_6_feat_amuv1p1_present(void)
{
- return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
- ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1P1);
+ return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1;
}
/*
@@ -138,10 +173,23 @@
ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
}
+static inline unsigned int read_feat_hcx_id_field(void)
+{
+ return (read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_HCX_SHIFT) &
+ ID_AA64MMFR1_EL1_HCX_MASK;
+}
+
-static inline bool is_feat_hcx_present(void)
+static inline bool is_feat_hcx_supported(void)
{
- return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_HCX_SHIFT) &
- ID_AA64MMFR1_EL1_HCX_MASK) == ID_AA64MMFR1_EL1_HCX_SUPPORTED);
+ if (ENABLE_FEAT_HCX == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_HCX == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_hcx_id_field() != 0U;
}
static inline bool is_feat_rng_trap_present(void)
@@ -226,16 +274,6 @@
ID_AA64DFR0_TRACEFILT_MASK) == ID_AA64DFR0_TRACEFILT_SUPPORTED);
}
-/*******************************************************************************
- * Function to identify the presence of FEAT_AMUv1 (Activity Monitors-
- * Extension v1)
- ******************************************************************************/
-static inline bool is_armv8_4_feat_amuv1_present(void)
-{
- return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
- ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1);
-}
-
/********************************************************************************
* Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization
* Support)
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index fe9b5a5..86c1dbe 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -27,6 +27,14 @@
return v; \
}
+#define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \
+static inline u_register_t read_ ## _name(void) \
+{ \
+ u_register_t v; \
+ __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \
+ return v; \
+}
+
#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
static inline void write_ ## _name(u_register_t v) \
{ \
@@ -58,6 +66,14 @@
#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
_DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
+/* Define read function for ID register (w/o volatile qualifier) */
+#define DEFINE_IDREG_READ_FUNC(_name) \
+ _DEFINE_SYSREG_READ_FUNC_NV(_name, _name)
+
+/* Define read function for renamed ID register (w/o volatile qualifier) */
+#define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \
+ _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name)
+
/**********************************************************************
* Macros to create inline functions for system instructions
*********************************************************************/
@@ -247,14 +263,14 @@
#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
DEFINE_SYSREG_RW_FUNCS(par_el1)
-DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
-DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1)
-DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
-DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
+DEFINE_IDREG_READ_FUNC(id_pfr1_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1)
+DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1)
+DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1)
+DEFINE_IDREG_READ_FUNC(id_afr0_el1)
DEFINE_SYSREG_READ_FUNC(CurrentEl)
DEFINE_SYSREG_READ_FUNC(ctr_el0)
DEFINE_SYSREG_RW_FUNCS(daif)
@@ -367,10 +383,10 @@
/*******************************************************************************
* System register accessor prototypes
******************************************************************************/
-DEFINE_SYSREG_READ_FUNC(midr_el1)
+DEFINE_IDREG_READ_FUNC(midr_el1)
DEFINE_SYSREG_READ_FUNC(mpidr_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1)
DEFINE_SYSREG_RW_FUNCS(scr_el3)
DEFINE_SYSREG_RW_FUNCS(hcr_el2)
@@ -516,7 +532,7 @@
DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
-DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
+DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3)
DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
@@ -530,7 +546,7 @@
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
/* Armv8.2 Registers */
-DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
+DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
/* Armv8.3 Pointer Authentication Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
@@ -549,6 +565,14 @@
DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS)
+/* Armv8.6 FEAT_FGT Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2)
+
/* FEAT_HCX Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
diff --git a/include/common/feat_detect.h b/include/common/feat_detect.h
index 0f0f105..788dfb3 100644
--- a/include/common/feat_detect.h
+++ b/include/common/feat_detect.h
@@ -7,26 +7,12 @@
#ifndef FEAT_DETECT_H
#define FEAT_DETECT_H
-#include <arch_features.h>
-#include <common/debug.h>
-
/* Function Prototypes */
void detect_arch_features(void);
/* Macro Definitions */
-#define FEAT_STATE_1 1
-#define FEAT_STATE_2 2
-#define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b))
-
-/*******************************************************************************
- * Function : feature_panic
- * Customised panic module with error logging mechanism to list the feature
- * not supported by the PE.
- ******************************************************************************/
-static inline void feature_panic(char *feat_name)
-{
- ERROR("FEAT_%s not supported by the PE\n", feat_name);
- panic();
-}
+#define FEAT_STATE_DISABLED 0
+#define FEAT_STATE_ALWAYS 1
+#define FEAT_STATE_CHECK 2
#endif /* FEAT_DETECT_H */
diff --git a/include/drivers/console.h b/include/drivers/console.h
index 99bf960..f499571 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -48,6 +48,8 @@
/* Additional private driver data may follow here. */
} console_t;
+extern console_t *console_list;
+
/* offset macro assertions for console_t */
#include <drivers/console_assertions.h>
diff --git a/include/drivers/partition/efi.h b/include/drivers/partition/efi.h
index e463f96..96c2857 100644
--- a/include/drivers/partition/efi.h
+++ b/include/drivers/partition/efi.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2021, Linaro Limited
+ * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -25,13 +26,13 @@
}
#define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
- { (a) & 0xffffffff, \
- (b) & 0xffff, \
- (c) & 0xffff, \
+ { (a) & 0xffffffffU, \
+ (b) & 0xffffU, \
+ (c) & 0xffffU, \
{ (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }
#define NULL_GUID \
- EFI_GUID(0x00000000, 0x0000, 0x0000, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
+ EFI_GUID(0x00000000U, 0x0000U, 0x0000U, 0x00U, 0x00U, \
+ 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U)
#endif /* DRIVERS_PARTITION_EFI_H */
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 31da99e..fb325b6 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -40,6 +40,8 @@
#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
+#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2
+
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
******************************************************************************/
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 9c7e967..4c10484 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -41,4 +41,6 @@
#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
+#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
+
#endif /* NEOVERSE_V1_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 6c13166..6986e0e 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -523,10 +523,6 @@
void el2_sysregs_context_save_mpam(el2_sysregs_t *regs);
void el2_sysregs_context_restore_mpam(el2_sysregs_t *regs);
#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
-#if ENABLE_FEAT_FGT
-void el2_sysregs_context_save_fgt(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_fgt(el2_sysregs_t *regs);
-#endif /* ENABLE_FEAT_FGT */
#if ENABLE_FEAT_ECV
void el2_sysregs_context_save_ecv(el2_sysregs_t *regs);
void el2_sysregs_context_restore_ecv(el2_sysregs_t *regs);
@@ -551,10 +547,6 @@
void el2_sysregs_context_save_csv2(el2_sysregs_t *regs);
void el2_sysregs_context_restore_csv2(el2_sysregs_t *regs);
#endif /* ENABLE_FEAT_CSV2_2 */
-#if ENABLE_FEAT_HCX
-void el2_sysregs_context_save_hcx(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_hcx(el2_sysregs_t *regs);
-#endif /* ENABLE_FEAT_HCX */
#endif /* CTX_INCLUDE_EL2_REGS */
#if CTX_INCLUDE_FPREGS
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 198b890..63eda63 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -68,14 +68,14 @@
__typeof__(x) _x = (x); \
__typeof__(y) _y = (y); \
(void)(&_x == &_y); \
- _x < _y ? _x : _y; \
+ (_x < _y) ? _x : _y; \
})
#define MAX(x, y) __extension__ ({ \
__typeof__(x) _x = (x); \
__typeof__(y) _y = (y); \
(void)(&_x == &_y); \
- _x > _y ? _x : _y; \
+ (_x > _y) ? _x : _y; \
})
#define CLAMP(x, min, max) __extension__ ({ \
@@ -84,7 +84,7 @@
__typeof__(max) _max = (max); \
(void)(&_x == &_min); \
(void)(&_x == &_max); \
- (_x > _max ? _max : (_x < _min ? _min : _x)); \
+ ((_x > _max) ? _max : ((_x < _min) ? _min : _x)); \
})
/*
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index f7f8027..886e1f3 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -361,6 +361,45 @@
b cpu_rev_var_ls
endfunc check_errata_2666669
+/* ------------------------------------------------------
+ * Errata Workaround for Cortex-A510 Erratum 2684597.
+ * This erratum applies to revision r0p0, r0p1, r0p2,
+ * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
+ * is fixed in r1p3.
+ * Shall clobber: x0-x17
+ * ------------------------------------------------------
+ */
+ .globl errata_cortex_a510_2684597_wa
+func errata_cortex_a510_2684597_wa
+ mov x17, x30
+ /* Ensure this errata is only applied to Cortex-A510 cores */
+ jump_if_cpu_midr CORTEX_A510_MIDR, 1f
+ b 2f
+
+1:
+ /* Check workaround compatibility. */
+ mov x0, x18
+ bl check_errata_2684597
+ cbz x0, 2f
+
+ tsb csync
+2:
+ ret x17
+endfunc errata_cortex_a510_2684597_wa
+/* ------------------------------------------------------
+ * Errata Workaround for Cortex-A510 Erratum 2684597.
+ * This erratum applies to revision r0p0, r0p1, r0p2,
+ * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
+ * is fixed in r1p3.
+ * Shall clobber: x0-x17
+ * ------------------------------------------------------
+ */
+func check_errata_2684597
+ /* Applies to revision < r1p3 */
+ mov x1, #0x12
+ b cpu_rev_var_ls
+endfunc check_errata_2684597
+
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
@@ -401,6 +440,7 @@
report_errata ERRATA_A510_2347730, cortex_a510, 2347730
report_errata ERRATA_A510_2371937, cortex_a510, 2371937
report_errata ERRATA_A510_2666669, cortex_a510, 2666669
+ report_errata ERRATA_A510_2684597, cortex_a510, 2684597
report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941
ldp x8, x30, [sp], #16
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 38f58bb..a3932e8 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -351,6 +351,35 @@
b cpu_rev_var_ls
endfunc check_errata_2772019
+/* ----------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata 2779479.
+ * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
+ * It is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * ----------------------------------------------------
+ */
+func errata_a78_2779479_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_2779479
+ cbz x0, 1f
+
+ /* Apply the workaround */
+ mrs x1, CORTEX_A78_ACTLR3_EL1
+ orr x1, x1, #BIT(47)
+ msr CORTEX_A78_ACTLR3_EL1, x1
+
+1:
+ ret x17
+endfunc errata_a78_2779479_wa
+
+func check_errata_2779479
+ /* Applies to r0p0, r1p0, r1p1, r1p2 */
+ mov x1, #CPU_REV(1, 2)
+ b cpu_rev_var_ls
+endfunc check_errata_2779479
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@@ -414,6 +443,11 @@
bl errata_a78_2395406_wa
#endif
+#if ERRATA_A78_2779479
+ mov x0, x18
+ bl errata_a78_2779479_wa
+#endif
+
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@@ -493,6 +527,7 @@
report_errata ERRATA_A78_2376745, cortex_a78, 2376745
report_errata ERRATA_A78_2395406, cortex_a78, 2395406
report_errata ERRATA_A78_2772019, cortex_a78, 2772019
+ report_errata ERRATA_A78_2779479, cortex_a78, 2779479
report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
ldp x8, x30, [sp], #16
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 49cebfe..5cdce89 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -117,13 +117,13 @@
b cpu_rev_var_range
endfunc check_errata_2132064
-/* --------------------------------------------------------------------
+/* ----------------------------------------------------------
* Errata Workaround for A78C Erratum 2242638.
* This applies to revisions r0p1 and r0p2 of the Cortex A78C
* processor and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
- * --------------------------------------------------------------------
+ * ----------------------------------------------------------
*/
func errata_a78c_2242638_wa
/* Compare x0 against revisions r0p1 - r0p2 */
@@ -152,6 +152,31 @@
b cpu_rev_var_range
endfunc check_errata_2242638
+/* ----------------------------------------------------------------
+ * Errata Workaround for A78C Erratum 2772121.
+ * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C
+ * processor and is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ----------------------------------------------------------------
+ */
+func errata_a78c_2772121_wa
+ mov x17, x30
+ bl check_errata_2772121
+ cbz x0, 1f
+
+ /* dsb before isb of power down sequence */
+ dsb sy
+1:
+ ret x17
+endfunc errata_a78c_2772121_wa
+
+func check_errata_2772121
+ /* Applies to all revisions <= r0p2 */
+ mov x1, #0x02
+ b cpu_rev_var_ls
+endfunc check_errata_2772121
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@@ -215,6 +240,12 @@
mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
+#if ERRATA_A78C_2772121
+ mov x15, x30
+ bl cpu_get_rev_var
+ bl errata_a78c_2772121_wa
+ mov x30, x15
+#endif /* ERRATA_A78C_2772121 */
isb
ret
endfunc cortex_a78c_core_pwr_dwn
@@ -237,6 +268,7 @@
report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
+ report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121
report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
ldp x8, x30, [sp], #16
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index c3a70ca..f9a5789 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -486,6 +486,35 @@
b cpu_rev_var_ls
endfunc check_errata_2743093
+ /* ----------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #2779461.
+ * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
+ * It is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * ----------------------------------------------------
+ */
+func errata_neoverse_v1_2779461_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_2779461
+ cbz x0, 1f
+
+ /* Apply the workaround */
+ mrs x1, NEOVERSE_V1_ACTLR3_EL1
+ orr x1, x1, #BIT(47)
+ msr NEOVERSE_V1_ACTLR3_EL1, x1
+
+1:
+ ret x17
+endfunc errata_neoverse_v1_2779461_wa
+
+func check_errata_2779461
+ /* Applies to r0p0, r1p0, r1p1, r1p2 */
+ mov x1, #CPU_REV(1, 2)
+ b cpu_rev_var_ls
+endfunc check_errata_2779461
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@@ -544,6 +573,7 @@
report_errata ERRATA_V1_2294912, neoverse_v1, 2294912
report_errata ERRATA_V1_2372203, neoverse_v1, 2372203
report_errata ERRATA_V1_2743093, neoverse_v1, 2743093
+ report_errata ERRATA_V1_2779461, neoverse_v1, 2779461
report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960
ldp x8, x30, [sp], #16
@@ -622,6 +652,11 @@
bl errata_neoverse_v1_2372203_wa
#endif
+#if ERRATA_V1_2779461
+ mov x0, x18
+ bl errata_neoverse_v1_2779461_wa
+#endif
+
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Neoverse-V1 generic vectors are overridden to apply errata
diff --git a/lib/cpus/aarch64/runtime_errata.S b/lib/cpus/aarch64/runtime_errata.S
new file mode 100644
index 0000000..8d46691
--- /dev/null
+++ b/lib/cpus/aarch64/runtime_errata.S
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <cortex_a510.h>
+#include <cpu_macros.S>
+
+/*
+ * void apply_cpu_pwr_dwn_errata(void);
+ *
+ * This function applies various CPU errata during power down.
+ */
+ .globl apply_cpu_pwr_dwn_errata
+func apply_cpu_pwr_dwn_errata
+ mov x19, x30
+ bl cpu_get_rev_var
+ mov x18, x0
+
+#if ERRATA_A510_2684597
+ bl errata_cortex_a510_2684597_wa
+#endif
+
+ ret x19
+endfunc apply_cpu_pwr_dwn_errata
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index c9b4447..4582f28 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -362,6 +362,10 @@
# open.
ERRATA_A78_2772019 ?=0
+# Flag to apply erratum 2779479 workaround during reset. This erratum applies
+# to revision r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still open.
+ERRATA_A78_2779479 ?=0
+
# Flag to apply erratum 1941500 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
ERRATA_A78_AE_1941500 ?=0
@@ -394,6 +398,10 @@
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
ERRATA_A78C_2395411 ?=0
+# Flag to apply erratum 2772121 workaround during powerdown. This erratum
+# applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open.
+ERRATA_A78C_2772121 ?=0
+
# Flag to apply erratum 1821534 workaround during reset. This erratum applies
# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1.
ERRATA_X1_1821534 ?=0
@@ -522,6 +530,11 @@
# still open.
ERRATA_V1_2743093 ?=0
+# Flag to apply erratum 2779461 workaround during powerdown. This erratum
+# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the Neoverse V1 cpu and is
+# still open.
+ERRATA_V1_2779461 ?=0
+
# Flag to apply erratum 1987031 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
ERRATA_A710_1987031 ?=0
@@ -736,6 +749,11 @@
# to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is fixed in r1p2.
ERRATA_A510_2666669 ?=0
+# Flag to apply erratum 2684597 workaround during powerdown. This erratum
+# applies to revision r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2 of the
+# Cortex-A510 cpu and is fixed in r1p3.
+ERRATA_A510_2684597 ?=0
+
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
ERRATA_DSU_798953 ?=0
@@ -1030,6 +1048,10 @@
$(eval $(call assert_boolean,ERRATA_A78_2772019))
$(eval $(call add_define,ERRATA_A78_2772019))
+# Process ERRATA_A78_2779479 flag
+$(eval $(call assert_boolean,ERRATA_A78_2779479))
+$(eval $(call add_define,ERRATA_A78_2779479))
+
# Process ERRATA_A78_AE_1941500 flag
$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
$(eval $(call add_define,ERRATA_A78_AE_1941500))
@@ -1062,6 +1084,10 @@
$(eval $(call assert_boolean,ERRATA_A78C_2395411))
$(eval $(call add_define,ERRATA_A78C_2395411))
+# Process ERRATA_A78C_2772121 flag
+$(eval $(call assert_boolean,ERRATA_A78C_2772121))
+$(eval $(call add_define,ERRATA_A78C_2772121))
+
# Process ERRATA_X1_1821534 flag
$(eval $(call assert_boolean,ERRATA_X1_1821534))
$(eval $(call add_define,ERRATA_X1_1821534))
@@ -1186,6 +1212,10 @@
$(eval $(call assert_boolean,ERRATA_V1_2743093))
$(eval $(call add_define,ERRATA_V1_2743093))
+# Process ERRATA_V1_2779461 flag
+$(eval $(call assert_boolean,ERRATA_V1_2779461))
+$(eval $(call add_define,ERRATA_V1_2779461))
+
# Process ERRATA_A710_1987031 flag
$(eval $(call assert_boolean,ERRATA_A710_1987031))
$(eval $(call add_define,ERRATA_A710_1987031))
@@ -1390,6 +1420,10 @@
$(eval $(call assert_boolean,ERRATA_A510_2666669))
$(eval $(call add_define,ERRATA_A510_2666669))
+# Process ERRATA_A510_2684597 flag
+$(eval $(call assert_boolean,ERRATA_A510_2684597))
+$(eval $(call add_define,ERRATA_A510_2684597))
+
#Process ERRATA_DSU_798953 flag
$(eval $(call assert_boolean,ERRATA_DSU_798953))
$(eval $(call add_define,ERRATA_DSU_798953))
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index aa0327b..b5d61ff 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -25,10 +25,6 @@
.global el2_sysregs_context_save_mpam
.global el2_sysregs_context_restore_mpam
#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
-#if ENABLE_FEAT_FGT
- .global el2_sysregs_context_save_fgt
- .global el2_sysregs_context_restore_fgt
-#endif /* ENABLE_FEAT_FGT */
#if ENABLE_FEAT_ECV
.global el2_sysregs_context_save_ecv
.global el2_sysregs_context_restore_ecv
@@ -53,10 +49,6 @@
.global el2_sysregs_context_save_csv2
.global el2_sysregs_context_restore_csv2
#endif /* ENABLE_FEAT_CSV2_2 */
-#if ENABLE_FEAT_HCX
- .global el2_sysregs_context_save_hcx
- .global el2_sysregs_context_restore_hcx
-#endif /* ENABLE_FEAT_HCX */
#endif /* CTX_INCLUDE_EL2_REGS */
.global el1_sysregs_context_save
@@ -314,45 +306,6 @@
endfunc el2_sysregs_context_restore_mpam
#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
-#if ENABLE_FEAT_FGT
-func el2_sysregs_context_save_fgt
- mrs x13, HDFGRTR_EL2
-#if ENABLE_FEAT_AMUv1
- mrs x14, HAFGRTR_EL2
- stp x13, x14, [x0, #CTX_HDFGRTR_EL2]
-#else
- str x13, [x0, #CTX_HDFGRTR_EL2]
-#endif /* ENABLE_FEAT_AMUv1 */
- mrs x15, HDFGWTR_EL2
- mrs x16, HFGITR_EL2
- stp x15, x16, [x0, #CTX_HDFGWTR_EL2]
-
- mrs x9, HFGRTR_EL2
- mrs x10, HFGWTR_EL2
- stp x9, x10, [x0, #CTX_HFGRTR_EL2]
- ret
-endfunc el2_sysregs_context_save_fgt
-
-func el2_sysregs_context_restore_fgt
- #if ENABLE_FEAT_AMUv1
- ldp x13, x14, [x0, #CTX_HDFGRTR_EL2]
- msr HAFGRTR_EL2, x14
-#else
- ldr x13, [x0, #CTX_HDFGRTR_EL2]
-#endif /* ENABLE_FEAT_AMUv1 */
- msr HDFGRTR_EL2, x13
-
- ldp x15, x16, [x0, #CTX_HDFGWTR_EL2]
- msr HDFGWTR_EL2, x15
- msr HFGITR_EL2, x16
-
- ldp x9, x10, [x0, #CTX_HFGRTR_EL2]
- msr HFGRTR_EL2, x9
- msr HFGWTR_EL2, x10
- ret
-endfunc el2_sysregs_context_restore_fgt
-#endif /* ENABLE_FEAT_FGT */
-
#if ENABLE_FEAT_ECV
func el2_sysregs_context_save_ecv
mrs x11, CNTPOFF_EL2
@@ -475,19 +428,6 @@
endfunc el2_sysregs_context_restore_csv2
#endif /* ENABLE_FEAT_CSV2_2 */
-#if ENABLE_FEAT_HCX
-func el2_sysregs_context_save_hcx
- mrs x14, hcrx_el2
- str x14, [x0, #CTX_HCRX_EL2]
- ret
-endfunc el2_sysregs_context_save_hcx
-
-func el2_sysregs_context_restore_hcx
- ldr x14, [x0, #CTX_HCRX_EL2]
- msr hcrx_el2, x14
- ret
-endfunc el2_sysregs_context_restore_hcx
-#endif /* ENABLE_FEAT_HCX */
#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 866ac41..3bcefdb 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -320,9 +320,9 @@
* If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
* SCR_EL3.HXEn.
*/
-#if ENABLE_FEAT_HCX
- scr_el3 |= SCR_HXEn_BIT;
-#endif
+ if (is_feat_hcx_supported()) {
+ scr_el3 |= SCR_HXEn_BIT;
+ }
/*
* If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS
@@ -359,7 +359,7 @@
&& (GET_M32(ep->spsr) == MODE32_hyp))) {
scr_el3 |= SCR_HCE_BIT;
- if (is_armv8_6_fgt_present()) {
+ if (is_feat_fgt_supported()) {
scr_el3 |= SCR_FGTEN_BIT;
}
@@ -792,6 +792,35 @@
}
#if CTX_INCLUDE_EL2_REGS
+
+static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx)
+{
+ if (is_feat_fgt_supported()) {
+ write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2());
+ if (is_feat_amu_supported()) {
+ write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2());
+ }
+ write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2());
+ write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2());
+ write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2());
+ write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2());
+ }
+}
+
+static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
+{
+ if (is_feat_fgt_supported()) {
+ write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2));
+ if (is_feat_amu_supported()) {
+ write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2));
+ }
+ write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2));
+ write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2));
+ write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2));
+ write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2));
+ }
+}
+
/*******************************************************************************
* Save EL2 sysreg context
******************************************************************************/
@@ -823,9 +852,9 @@
#if ENABLE_MPAM_FOR_LOWER_ELS
el2_sysregs_context_save_mpam(el2_sysregs_ctx);
#endif
-#if ENABLE_FEAT_FGT
+
el2_sysregs_context_save_fgt(el2_sysregs_ctx);
-#endif
+
#if ENABLE_FEAT_ECV
el2_sysregs_context_save_ecv(el2_sysregs_ctx);
#endif
@@ -844,9 +873,9 @@
#if ENABLE_FEAT_CSV2_2
el2_sysregs_context_save_csv2(el2_sysregs_ctx);
#endif
-#if ENABLE_FEAT_HCX
- el2_sysregs_context_save_hcx(el2_sysregs_ctx);
-#endif
+ if (is_feat_hcx_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2());
+ }
}
}
@@ -881,9 +910,9 @@
#if ENABLE_MPAM_FOR_LOWER_ELS
el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
#endif
-#if ENABLE_FEAT_FGT
+
el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
-#endif
+
#if ENABLE_FEAT_ECV
el2_sysregs_context_restore_ecv(el2_sysregs_ctx);
#endif
@@ -902,9 +931,9 @@
#if ENABLE_FEAT_CSV2_2
el2_sysregs_context_restore_csv2(el2_sysregs_ctx);
#endif
-#if ENABLE_FEAT_HCX
- el2_sysregs_context_restore_hcx(el2_sysregs_ctx);
-#endif
+ if (is_feat_hcx_supported()) {
+ write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2));
+ }
}
}
#endif /* CTX_INCLUDE_EL2_REGS */
diff --git a/lib/libc/putchar.c b/lib/libc/putchar.c
index 3472b24..340bdd8 100644
--- a/lib/libc/putchar.c
+++ b/lib/libc/putchar.c
@@ -1,14 +1,13 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdio.h>
-int __putchar(int c)
+#pragma weak putchar
+int putchar(int c)
{
return c;
}
-
-int putchar(int c) __attribute__((weak,alias("__putchar")));
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S
index 5cc192e..d28d469 100644
--- a/lib/psci/aarch32/psci_helpers.S
+++ b/lib/psci/aarch32/psci_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -143,6 +143,7 @@
*/
func psci_power_down_wfi
dsb sy // ensure write buffer empty
+1:
wfi
- no_ret plat_panic_handler
+ b 1b
endfunc psci_power_down_wfi
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index add968a..61f31e5 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -124,7 +124,11 @@
* -----------------------------------------------------------------------
*/
func psci_power_down_wfi
+#if ERRATA_A510_2684597
+ bl apply_cpu_pwr_dwn_errata
+#endif
dsb sy // ensure write buffer empty
+1:
wfi
- no_ret plat_panic_handler
+ b 1b
endfunc psci_power_down_wfi
diff --git a/lib/psci/psci_lib.mk b/lib/psci/psci_lib.mk
index 1d4aac4..6864202 100644
--- a/lib/psci/psci_lib.mk
+++ b/lib/psci/psci_lib.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -21,7 +21,8 @@
lib/psci/${ARCH}/psci_helpers.S
ifeq (${ARCH}, aarch64)
-PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S
+PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S \
+ lib/cpus/aarch64/runtime_errata.S
endif
ifeq (${USE_COHERENT_MEM}, 1)
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index 1901c17..6ca9ef6 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -304,6 +304,9 @@
*/
void prepare_cpu_pwr_dwn(unsigned int power_level);
+/* This function applies various CPU errata during power down. */
+void apply_cpu_pwr_dwn_errata(void);
+
/* Private exported functions from psci_on.c */
int psci_cpu_on_start(u_register_t target_cpu,
const entry_point_info_t *ep);
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index f28a6ff..efbf68f 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -463,6 +463,10 @@
# enable trace filter control registers access to NS by default
ENABLE_TRF_FOR_NS := 1
+# Linux relies on EL3 enablement if those features are present
+ENABLE_FEAT_FGT := 2
+ENABLE_FEAT_HCX := 2
+
ifeq (${SPMC_AT_EL3}, 1)
PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c
endif
diff --git a/plat/arm/board/morello/fdts/morello_fw_config.dts b/plat/arm/board/morello/fdts/morello_fw_config.dts
index c47bae5..a63d7eb 100644
--- a/plat/arm/board/morello/fdts/morello_fw_config.dts
+++ b/plat/arm/board/morello/fdts/morello_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,8 +19,14 @@
nt_fw-config {
load-address = <0x0 0xFEF00000>;
- max-size = <0x0100000>;
+ max-size = <0xF8000>;
id = <NT_FW_CONFIG_ID>;
};
+
+ hw-config {
+ load-address = <0x0 0xFEFF8000>;
+ max-size = <0x8000>;
+ id = <HW_CONFIG_ID>;
+ };
};
};
diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk
index 156b7ea..0f0cabb 100644
--- a/plat/arm/board/morello/platform.mk
+++ b/plat/arm/board/morello/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -59,11 +59,14 @@
${MORELLO_BASE}/fdts/morello_nt_fw_config.dts
FW_CONFIG := ${BUILD_PLAT}/fdts/morello_fw_config.dtb
+HW_CONFIG := ${BUILD_PLAT}/fdts/morello-${TARGET_PLATFORM}.dtb
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_tb_fw_config.dtb
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_nt_fw_config.dtb
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
diff --git a/plat/arm/board/tc/plat_def_fip_uuid.h b/plat/arm/board/tc/plat_def_fip_uuid.h
new file mode 100644
index 0000000..631f7c9
--- /dev/null
+++ b/plat/arm/board/tc/plat_def_fip_uuid.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __PLAT_DEF_FIP_UUID__
+#define __PLAT_DEF_FIP_UUID__
+
+#include "uuid.h"
+
+#define UUID_RSS_FIRMWARE_BL1_2 \
+ {{0x0a, 0xa5, 0xb1, 0xbe}, {0xe7, 0x84}, {0x41, 0xc5}, 0x81, 0xb8, {0x4a, 0x41, 0xcb, 0x4a, 0xd2, 0xdf}}
+
+#define UUID_RSS_FIRMWARE_BL2 \
+ {{0xa3, 0xb3, 0xb3, 0x0d}, {0xeb, 0xc9}, {0x40, 0x48}, 0xb4, 0x80, {0x15, 0x53, 0x61, 0xc1, 0x70, 0x48}}
+
+#define UUID_RSS_FIRMWARE_SCP_BL1 \
+ {{0xbf, 0xd5, 0x09, 0x8d}, {0xa7, 0x07}, {0x4f, 0x15}, 0x89, 0x1c, {0x37, 0x22, 0x10, 0xcb, 0x51, 0xe2}}
+
+#define UUID_RSS_FIRMWARE_AP_BL1 \
+ {{0x12, 0x4c, 0x50, 0xe0}, {0xf2, 0xda}, {0x45, 0xe9}, 0x85, 0xc8, {0xda, 0xd9, 0x60, 0x9b, 0x7a, 0x11}}
+
+#define UUID_RSS_FIRMWARE_NS \
+ {{0x8d, 0x95, 0x9f, 0x72}, {0xb8, 0xb1}, {0x42, 0x11}, 0x9a, 0xe6, {0x4b, 0x80, 0x97, 0x47, 0x5a, 0xd9}}
+
+#define UUID_RSS_FIRMWARE_S \
+ {{0x22, 0xea, 0x33, 0x85}, {0xf8, 0x6e}, {0x47, 0x93}, 0x96, 0x8a, {0x2f, 0xe3, 0xdd, 0x50, 0x33, 0xcc}}
+
+#define UUID_RSS_SIC_TABLES_NS \
+ {{0xd9, 0x10, 0x00, 0x72}, {0x6a, 0x28}, {0x4b, 0xec}, 0xb0, 0xd6, {0x8c, 0xed, 0xc4, 0x15, 0x7c, 0xe0}}
+
+#define UUID_RSS_SIC_TABLES_S \
+ {{0xc7, 0x38, 0xd0, 0xde}, {0x8c, 0x26}, {0x48, 0x51}, 0x93, 0x36, {0xf3, 0xdb, 0xe2, 0x96, 0x65, 0x18}}
+
+#endif /* __PLAT_DEF_FIP_UUID__ */
diff --git a/plat/arm/board/tc/plat_def_uuid_config.c b/plat/arm/board/tc/plat_def_uuid_config.c
new file mode 100644
index 0000000..903310b
--- /dev/null
+++ b/plat/arm/board/tc/plat_def_uuid_config.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stddef.h>
+
+#include <firmware_image_package.h>
+
+#include "tbbr_config.h"
+
+toc_entry_t plat_def_toc_entries[] = {
+ {
+ .name = "RSS Firmware BL1_2 image",
+ .uuid = UUID_RSS_FIRMWARE_BL1_2,
+ .cmdline_name = "rss-bl1_2"
+ },
+ {
+ .name = "RSS Firmware BL2 image",
+ .uuid = UUID_RSS_FIRMWARE_BL2,
+ .cmdline_name = "rss-bl2"
+ },
+ {
+ .name = "RSS Firmware SCP BL1 image",
+ .uuid = UUID_RSS_FIRMWARE_SCP_BL1,
+ .cmdline_name = "rss-scp-bl1"
+ },
+ {
+ .name = "RSS Firmware AP BL1 image",
+ .uuid = UUID_RSS_FIRMWARE_AP_BL1,
+ .cmdline_name = "rss-ap-bl1"
+ },
+ {
+ .name = "RSS Firmware non-secure image",
+ .uuid = UUID_RSS_FIRMWARE_NS,
+ .cmdline_name = "rss-ns"
+ },
+ {
+ .name = "RSS Firmware secure image",
+ .uuid = UUID_RSS_FIRMWARE_S,
+ .cmdline_name = "rss-s"
+ },
+ {
+ .name = "RSS Firmware non-secure SIC tables",
+ .uuid = UUID_RSS_SIC_TABLES_NS,
+ .cmdline_name = "rss-sic-tables-ns"
+ },
+ {
+ .name = "RSS Firmware secure SIC tables",
+ .uuid = UUID_RSS_SIC_TABLES_S,
+ .cmdline_name = "rss-sic-tables-s"
+ },
+
+ {
+ .name = NULL,
+ .uuid = { {0} },
+ .cmdline_name = NULL,
+ }
+};
diff --git a/plat/arm/board/tc/plat_fiptool.mk b/plat/arm/board/tc/plat_fiptool.mk
new file mode 100644
index 0000000..0e13556
--- /dev/null
+++ b/plat/arm/board/tc/plat_fiptool.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2021, NXP. All rights reserved.
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Name of the platform defined source file name,
+# which contains platform defined UUID entries populated
+# in the plat_def_toc_entries[].
+PLAT_DEF_UUID_CONFIG_FILE_NAME := plat_def_uuid_config
+
+PLAT_DEF_UUID_CONFIG_FILE_PATH := ../../plat/arm/board/tc
+
+PLAT_DEF_UUID := yes
+PLAT_DEF_UUID_OID_CONFIG_PATH := ../../plat/arm/board/tc
+
+
+INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_CONFIG_PATH} \
+ -I./
+# Clean the stale object file.
+$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o)
+
+ifeq (${PLAT_DEF_OID},yes)
+HOSTCCFLAGS += -DPLAT_DEF_OID
+endif
+
+ifeq (${PLAT_DEF_UUID},yes)
+HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
+PLAT_OBJECTS += ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o
+endif
+
+OBJECTS += ${PLAT_OBJECTS}
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 74c0f17..2182477 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -53,6 +53,9 @@
# enable trace filter control registers access to NS by default
ENABLE_TRF_FOR_NS := 1
+# Enable RSS-required FIP UUIDs
+$(shell cp plat/arm/board/tc/plat_fiptool.mk ${PLAT_DIR})
+
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index 9b2639c..3222226 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -130,9 +130,6 @@
/* Prevent interrupts from spuriously waking up this cpu */
plat_arm_gic_cpuif_disable();
- /* Turn redistributor off */
- plat_arm_gic_redistif_off();
-
/* Cluster is to be turned off, so disable coherency */
if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
plat_arm_interconnect_exit_coherency();
diff --git a/plat/imx/common/imx_uart_console.S b/plat/imx/common/imx_uart_console.S
index ceeb3a7..4d17288 100644
--- a/plat/imx/common/imx_uart_console.S
+++ b/plat/imx/common/imx_uart_console.S
@@ -12,6 +12,7 @@
#define URXD 0x0 /* Receiver Register */
#define UTXD 0x40 /* Transmitter Register */
+#define USR2 0x98 /* UART Status Register 2 */
#define UTS 0xb4 /* UART Test Register (mx31) */
#define URXD_RX_DATA (0xFF)
@@ -53,13 +54,13 @@
1:
/* Check if the transmit FIFO is full */
ldr w2, [x1, #UTS]
- tbz w2, #6, 1b
+ tbnz w2, #4, 1b
mov w2, #0xD
str w2, [x1, #UTXD]
2:
/* Check if the transmit FIFO is full */
ldr w2, [x1, #UTS]
- tbz w2, #6, 2b
+ tbnz w2, #4, 2b
str w0, [x1, #UTXD]
ret
putc_error:
@@ -84,5 +85,13 @@
endfunc console_imx_uart_getc
func console_imx_uart_flush
+ ldr x0, [x0, #CONSOLE_T_BASE]
+ cbz x0, flush_exit
+1:
+ /* Wait for the transmit complete bit */
+ ldr w1, [x0, #USR2]
+ tbz w1, #3, 1b
+
+flush_exit:
ret
endfunc console_imx_uart_flush
diff --git a/plat/mediatek/build_helpers/options.mk b/plat/mediatek/build_helpers/options.mk
index 0279648..128b14f 100644
--- a/plat/mediatek/build_helpers/options.mk
+++ b/plat/mediatek/build_helpers/options.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -23,3 +23,4 @@
$(eval $(call add_defined_option,CONFIG_MTK_CPU_SUSPEND_EN))
$(eval $(call add_defined_option,CONFIG_MTK_PM_ARCH))
$(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_ARCH))
+$(eval $(call add_defined_option,CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND))
diff --git a/plat/mediatek/common/lpm/mt_lp_api.c b/plat/mediatek/common/lpm/mt_lp_api.c
new file mode 100644
index 0000000..2a1da6a
--- /dev/null
+++ b/plat/mediatek/common/lpm/mt_lp_api.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lpm/mt_lp_api.h>
+
+int mt_audio_update(int type)
+{
+ int ret, val;
+
+ switch (type) {
+ case AUDIO_AFE_ENTER:
+ case AUDIO_AFE_LEAVE:
+ val = (type == AUDIO_AFE_ENTER) ? 1 : 0;
+ ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_FMAUDIO, &val);
+ break;
+ case AUDIO_DSP_ENTER:
+ case AUDIO_DSP_LEAVE:
+ val = (type == AUDIO_DSP_ENTER) ? 1 : 0;
+ ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_ADSP, &val);
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+int mtk_usb_update(int type)
+{
+ int ret, val;
+
+ switch (type) {
+ case LPM_USB_ENTER:
+ case LPM_USB_LEAVE:
+ val = (type == LPM_USB_ENTER) ? 1 : 0;
+ ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_USB_INFRA, &val);
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
diff --git a/plat/mediatek/common/lpm/mt_lp_rm.c b/plat/mediatek/common/lpm/mt_lp_rm.c
index 0bafc66..9f07968 100644
--- a/plat/mediatek/common/lpm/mt_lp_rm.c
+++ b/plat/mediatek/common/lpm/mt_lp_rm.c
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <mt_lp_rm.h>
#include <stddef.h>
+#include <lpm/mt_lp_rm.h>
struct platform_mt_resource_manager {
unsigned int count;
@@ -36,12 +36,11 @@
return MT_RM_STATUS_OK;
}
-int mt_lp_rm_reset_constraint(int idx, unsigned int cpuid, int stateid)
+int mt_lp_rm_reset_constraint(unsigned int idx, unsigned int cpuid, int stateid)
{
struct mt_resource_constraint const *rc = NULL;
- if ((plat_mt_rm.plat_rm == NULL) || (idx < 0) ||
- (idx >= plat_mt_rm.count)) {
+ if ((plat_mt_rm.plat_rm == NULL) || (idx >= plat_mt_rm.count)) {
return MT_RM_STATUS_BAD;
}
@@ -54,39 +53,92 @@
return rc->reset(cpuid, stateid);
}
-int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
- int stateid, void *priv)
+int mt_lp_rm_get_status(unsigned int type, void *priv)
+{
+ int res = 0;
+ struct mt_resource_constraint *const *con;
+ struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
+
+ if ((rm == NULL) || (type >= PLAT_RC_MAX)) {
+ return -1;
+ }
+
+ for (con = rm->consts; *con != NULL; con++) {
+ if ((*con)->get_status == NULL) {
+ continue;
+ }
+ res = (*con)->get_status(type, priv);
+ if (res == MT_RM_STATUS_STOP) {
+ break;
+ }
+ }
+
+ return res;
+}
+
+int mt_lp_rm_do_constraint(unsigned int constraint_id, unsigned int cpuid, int stateid)
+{
+ int res = MT_RM_STATUS_BAD;
+ struct mt_resource_constraint const *rc;
+ struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
+
+ if ((rm == NULL) || (constraint_id >= plat_mt_rm.count)) {
+ return res;
+ }
+
+ rc = rm->consts[constraint_id];
+ if ((rc != NULL) && (rc->run != NULL)) {
+ res = rc->run(cpuid, stateid);
+ }
+
+ return res;
+}
+
+int mt_lp_rm_find_constraint(unsigned int idx, unsigned int cpuid,
+ int stateid, void *priv)
{
- int i, res = MT_RM_STATUS_BAD;
+ unsigned int i;
+ int res = MT_RM_STATUS_BAD;
struct mt_resource_constraint *const *rc;
struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
- if ((rm == NULL) || (idx < 0) || (idx >= plat_mt_rm.count)) {
+ if ((rm == NULL) || (idx >= plat_mt_rm.count)) {
return res;
}
/* If subsys clk/mtcmos is on, add block-resource-off flag */
if (rm->update != NULL) {
- res = rm->update(rm->consts, stateid, priv);
+ res = rm->update(rm->consts, plat_mt_rm.count, stateid, priv);
if (res != 0) {
- return res;
+ return MT_RM_STATUS_BAD;
}
}
+ res = MT_RM_STATUS_BAD;
for (i = idx, rc = (rm->consts + idx); *rc != NULL; i++, rc++) {
if (((*rc)->is_valid != NULL) &&
((*rc)->is_valid(cpuid, stateid))) {
- if (((*rc)->run != NULL) &&
- ((*rc)->run(cpuid, stateid) == 0)) {
- res = i;
- break;
- }
+ res = i;
+ break;
}
}
return res;
}
+int mt_lp_rm_find_and_run_constraint(unsigned int idx, unsigned int cpuid,
+ int stateid, void *priv)
+{
+ int res = MT_RM_STATUS_BAD;
+
+ res = mt_lp_rm_find_constraint(idx, cpuid, stateid, priv);
+ if (res != MT_RM_STATUS_BAD) {
+ mt_lp_rm_do_constraint(res, cpuid, stateid);
+ }
+
+ return res;
+}
+
int mt_lp_rm_do_update(int stateid, int type, void const *p)
{
int res = MT_RM_STATUS_BAD;
diff --git a/plat/mediatek/common/lpm/mt_lp_rm.h b/plat/mediatek/common/lpm/mt_lp_rm.h
deleted file mode 100644
index e93dac3..0000000
--- a/plat/mediatek/common/lpm/mt_lp_rm.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef MT_LP_RM_H
-#define MT_LP_RM_H
-
-#include <stdbool.h>
-
-#define MT_RM_STATUS_OK 0
-#define MT_RM_STATUS_BAD -1
-
-enum PLAT_MT_LPM_RC_TYPE {
- PLAT_RC_UPDATE_CONDITION,
- PLAT_RC_UPDATE_REMAIN_IRQS
-};
-
-struct mt_resource_constraint {
- int level;
- int (*init)(void);
- bool (*is_valid)(unsigned int cpu, int stateid);
- int (*update)(int stateid, int type, const void *p);
- int (*run)(unsigned int cpu, int stateid);
- int (*reset)(unsigned int cpu, int stateid);
- unsigned int (*allow)(int stateid);
-};
-
-struct mt_resource_manager {
- int (*update)(struct mt_resource_constraint **con,
- int stateid, void *priv);
- struct mt_resource_constraint **consts;
-};
-
-extern int mt_lp_rm_register(struct mt_resource_manager *rm);
-extern int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
- int stateid, void *priv);
-extern int mt_lp_rm_reset_constraint(int constraint_id, unsigned int cpuid,
- int stateid);
-extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
-#endif /* MT_LP_RM_H */
diff --git a/plat/mediatek/common/lpm/mt_lp_rq.c b/plat/mediatek/common/lpm/mt_lp_rq.c
new file mode 100644
index 0000000..7b83fed
--- /dev/null
+++ b/plat/mediatek/common/lpm/mt_lp_rq.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/spinlock.h>
+#include <lpm/mt_lp_rqm.h>
+
+struct mt_lp_res_req_m {
+ unsigned int uname[MT_LP_RQ_USER_MAX];
+ unsigned int user_num;
+ unsigned int user_valid;
+ unsigned int resource_num;
+ unsigned int generic_resource_req;
+ unsigned int flag;
+ struct mt_resource_req_manager *plat_rqm;
+};
+
+static struct mt_lp_res_req_m plat_mt_rqm;
+static spinlock_t mt_lp_rq_lock;
+
+static int mt_lp_resource_request(struct mt_lp_resource_user *this, unsigned int resource)
+{
+ int i;
+ struct mt_lp_res_req *const *rs;
+
+ if ((this == NULL) || (resource == 0) || (resource > MT_LP_RQ_ALL)) {
+ ERROR("invalid request(%x)\n", resource);
+ return MT_LP_RQ_STA_BAD;
+ }
+
+ spin_lock(&mt_lp_rq_lock);
+
+ rs = (plat_mt_rqm.plat_rqm)->res;
+ for (i = 0; i < plat_mt_rqm.resource_num; i++) {
+ if ((resource & rs[i]->res_id) != 0) {
+ rs[i]->res_usage |= this->umask;
+ }
+ }
+
+ plat_mt_rqm.flag = MT_LP_RQ_FLAG_NEED_UPDATE;
+ spin_unlock(&mt_lp_rq_lock);
+
+ return MT_LP_RQ_STA_OK;
+}
+
+static int mt_lp_resource_release(struct mt_lp_resource_user *this)
+{
+ int i;
+ struct mt_lp_res_req *const *rs;
+
+ if (this == NULL) {
+ return MT_LP_RQ_STA_BAD;
+ }
+
+ spin_lock(&mt_lp_rq_lock);
+
+ rs = (plat_mt_rqm.plat_rqm)->res;
+ for (i = 0; i < plat_mt_rqm.resource_num; i++) {
+ rs[i]->res_usage &= ~(this->umask);
+ }
+
+ plat_mt_rqm.flag = MT_LP_RQ_FLAG_NEED_UPDATE;
+ spin_unlock(&mt_lp_rq_lock);
+
+ return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_resource_request_manager_register(struct mt_resource_req_manager *rqm)
+{
+ unsigned int count;
+ struct mt_lp_res_req *const *rs;
+
+ if ((rqm == NULL) || (rqm->res == NULL) || (plat_mt_rqm.plat_rqm != NULL)) {
+ return MT_LP_RQ_STA_BAD;
+ }
+
+ rs = rqm->res;
+ count = 0;
+ while (*rs != NULL) {
+ count++;
+ rs++;
+ }
+
+ plat_mt_rqm.plat_rqm = rqm;
+ plat_mt_rqm.resource_num = count;
+
+ return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_resource_user_register(char *user, struct mt_lp_resource_user *ru)
+{
+ int i, len;
+ unsigned int uname;
+
+ if ((plat_mt_rqm.plat_rqm == NULL) || (plat_mt_rqm.user_num >= MT_LP_RQ_USER_MAX) ||
+ (user == NULL)) {
+ ru->uid = MT_LP_RQ_USER_INVALID;
+ ru->umask = 0;
+ ru->request = NULL;
+ ru->release = NULL;
+ ERROR("rqm register user invalid\n");
+ return MT_LP_RQ_STA_BAD;
+ }
+
+ len = strnlen(user, MT_LP_RQ_USER_NAME_LEN);
+
+ uname = 0;
+ for (i = 0; i < len; i++) {
+ uname |= (user[i] << (MT_LP_RQ_USER_CHAR_U * i));
+ }
+
+ spin_lock(&mt_lp_rq_lock);
+ i = plat_mt_rqm.user_num;
+ plat_mt_rqm.user_num += 1;
+ plat_mt_rqm.uname[i] = uname;
+ plat_mt_rqm.user_valid |= BIT(i);
+ spin_unlock(&mt_lp_rq_lock);
+
+ ru->umask = BIT(i);
+ ru->uid = i;
+ ru->request = mt_lp_resource_request;
+ ru->release = mt_lp_resource_release;
+ INFO("%s register by %s, uid = %d\n", __func__, user, ru->uid);
+
+ return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_rq_get_status(int type, void *p)
+{
+ int i;
+ unsigned int update_sta;
+ struct mt_lp_res_req *const *rs;
+ struct resource_req_status *rq_sta = (struct resource_req_status *)p;
+
+ if (plat_mt_rqm.flag != 0) {
+ spin_lock(&mt_lp_rq_lock);
+
+ update_sta = 0;
+ rs = (plat_mt_rqm.plat_rqm)->res;
+ for (i = 0; i < plat_mt_rqm.resource_num; i++) {
+ update_sta |= ((rs[i]->res_usage & plat_mt_rqm.user_valid) != 0) ?
+ rs[i]->res_rq : 0;
+ }
+
+ plat_mt_rqm.generic_resource_req = update_sta;
+ plat_mt_rqm.flag = MT_LP_RQ_FLAG_DONE;
+ spin_unlock(&mt_lp_rq_lock);
+ }
+
+ switch (type) {
+ case PLAT_RQ_REQ_USAGE:
+ rs = (plat_mt_rqm.plat_rqm)->res;
+ rq_sta->val = (rq_sta->id < plat_mt_rqm.resource_num) ?
+ rs[rq_sta->id]->res_usage : plat_mt_rqm.generic_resource_req;
+ break;
+ case PLAT_RQ_USER_NUM:
+ rq_sta->val = plat_mt_rqm.user_num;
+ break;
+ case PLAT_RQ_USER_VALID:
+ rq_sta->val = plat_mt_rqm.user_valid;
+ break;
+ case PLAT_RQ_PER_USER_NAME:
+ rq_sta->val = (rq_sta->id < plat_mt_rqm.user_num) ?
+ plat_mt_rqm.uname[rq_sta->id] : 0;
+ break;
+ case PLAT_RQ_REQ_NUM:
+ rq_sta->val = plat_mt_rqm.resource_num;
+ break;
+ default:
+ break;
+ }
+
+ return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_rq_update_status(int type, void *p)
+{
+ unsigned int user_mask;
+ struct resource_req_status *rq_sta = (struct resource_req_status *)p;
+
+ switch (type) {
+ case PLAT_RQ_USER_VALID:
+ if (rq_sta->id < plat_mt_rqm.user_num) {
+ user_mask = BIT(rq_sta->id);
+ spin_lock(&mt_lp_rq_lock);
+ plat_mt_rqm.user_valid = (rq_sta->val == 0) ?
+ (plat_mt_rqm.user_valid & ~(user_mask)) :
+ (plat_mt_rqm.user_valid | user_mask);
+ plat_mt_rqm.flag = MT_LP_RQ_FLAG_NEED_UPDATE;
+ spin_unlock(&mt_lp_rq_lock);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return MT_LP_RQ_STA_OK;
+}
diff --git a/plat/mediatek/common/lpm/rules.mk b/plat/mediatek/common/lpm/rules.mk
index 87a212a..eb68e03 100644
--- a/plat/mediatek/common/lpm/rules.mk
+++ b/plat/mediatek/common/lpm/rules.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,7 +7,10 @@
LOCAL_DIR := $(call GET_LOCAL_DIR)
MODULE := lpm
-LOCAL_SRCS-y := $(LOCAL_DIR)/mt_lp_rm.c
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/mt_lp_api.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/mt_lp_rm.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/mt_lp_rq.c
PLAT_INCLUDES += -I${LOCAL_DIR}
diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c
index 313ad47..6281cc0 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c
+++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,10 +11,10 @@
#include <lib/mtk_init/mtk_init.h>
#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
#include "mt_cpu_pm.h"
#include "mt_cpu_pm_cpc.h"
#include "mt_cpu_pm_mbox.h"
-#include <mt_lp_rm.h>
#include "mt_smp.h"
#include <mtk_mmap_pool.h>
#include <platform_def.h>
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c
new file mode 100644
index 0000000..257caa3
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lpm/mt_lpm_smc.h>
+#include <mt_spm.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+
+int spm_rc_condition_modifier(unsigned int id, unsigned int act,
+ const void *val,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct mt_spm_cond_tables * const tlb)
+{
+ unsigned int rc_id, cond_id, cond;
+ int res = 0;
+
+ spin_lock(&spm_lock);
+ rc_id = SPM_RC_UPDATE_COND_RC_ID_GET(id);
+ cond_id = SPM_RC_UPDATE_COND_ID_GET(id);
+
+ do {
+ if ((dest_rc_id != rc_id) || (val == NULL) || (tlb == NULL)) {
+ res = -1;
+ break;
+ }
+
+ cond = *((unsigned int *)val);
+
+ if (cond_id < PLAT_SPM_COND_MAX) {
+ if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+ SPM_RC_BITS_SET(tlb->table_cg[cond_id], cond);
+ } else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(tlb->table_cg[cond_id], cond);
+ } else {
+ res = -1;
+ }
+ } else if ((cond_id - PLAT_SPM_COND_MAX) < PLAT_SPM_COND_PLL_MAX) {
+ unsigned int pll_idx = cond_id - PLAT_SPM_COND_MAX;
+
+ cond = !!cond;
+ if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+ SPM_RC_BITS_SET(tlb->table_pll, (cond << pll_idx));
+ } else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(tlb->table_pll, (cond << pll_idx));
+ } else {
+ res = -1;
+ }
+ } else {
+ res = -1;
+ }
+ } while (0);
+
+ spin_unlock(&spm_lock);
+
+ return res;
+}
+
+int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL) ||
+ (src == NULL)) {
+ return -1;
+ }
+ spin_lock(&spm_lock);
+
+ switch (type) {
+ case CONSTRAINT_GET_ENTER_CNT:
+ if (id == MT_RM_CONSTRAINT_ID_ALL) {
+ dest->enter_cnt += src->enter_cnt;
+ } else {
+ dest->enter_cnt = src->enter_cnt;
+ }
+ break;
+ case CONSTRAINT_GET_VALID:
+ dest->is_valid = src->is_valid;
+ break;
+ case CONSTRAINT_COND_BLOCK:
+ dest->is_cond_block = src->is_cond_block;
+ dest->all_pll_dump = src->all_pll_dump;
+ break;
+ case CONSTRAINT_GET_COND_BLOCK_DETAIL:
+ dest->cond_res = src->cond_res;
+ break;
+ case CONSTRAINT_GET_RESIDNECY:
+ dest->residency = src->residency;
+ if (act & MT_LPM_SMC_ACT_CLR) {
+ src->residency = 0;
+ }
+ break;
+ default:
+ break;
+ }
+
+ spin_unlock(&spm_lock);
+ return 0;
+}
+
+int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+
+ switch (type) {
+ case CONSTRAINT_UPDATE_VALID:
+ if (src != NULL) {
+ if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+ SPM_RC_BITS_SET(dest->is_valid, src->is_valid);
+ } else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(dest->is_valid, src->is_valid);
+ }
+ }
+ break;
+ case CONSTRAINT_RESIDNECY:
+ if (act & MT_LPM_SMC_ACT_CLR) {
+ dest->residency = 0;
+ }
+ break;
+ default:
+ break;
+ }
+
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
+
+int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+ SPM_RC_BITS_SET(dest->is_valid, valid);
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
+
+int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+ SPM_RC_BITS_CLR(dest->is_valid, valid);
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h
new file mode 100644
index 0000000..0736ca3
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_API_H
+#define MT_SPM_RC_API_H
+
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_internal.h>
+
+#define SPM_RC_BITS_SET(dest, src) ({ (dest) |= (src); })
+#define SPM_RC_BITS_CLR(dest, src) ({ (dest) &= (~src); })
+
+int spm_rc_condition_modifier(unsigned int id, unsigned int act,
+ const void *val,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct mt_spm_cond_tables * const tlb);
+
+int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest);
+
+int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest);
+
+int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest);
+
+int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
new file mode 100644
index 0000000..0b792ab
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#ifndef MTK_PLAT_CIRQ_UNSUPPORT
+#include <mtk_cirq.h>
+#endif
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_BUS26M_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
+ MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
+ MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
+#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
+#define CONSTRAINT_BUS26M_RESOURCE_REQ (MT_SPM_26M)
+#else
+#define CONSTRAINT_BUS26M_RESOURCE_REQ (0)
+#endif
+
+static unsigned int bus26m_ext_opand;
+static unsigned int bus26m_ext_opand2;
+
+static struct mt_irqremain *refer2remain_irq;
+
+static struct mt_spm_cond_tables cond_bus26m = {
+ .table_cg = {
+ 0xFF5DD002, /* MTCMOS1 */
+ 0x0000003C, /* MTCMOS2 */
+ 0x27AF8000, /* INFRA0 */
+ 0x22010876, /* INFRA1 */
+ 0x86000650, /* INFRA2 */
+ 0x30008020, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x01002A3B, /* PERI0 */
+ 0x00090000, /* VPPSYS0_0 */
+ 0x38FF3E69, /* VPPSYS0_1 */
+ 0xF0081450, /* VPPSYS1_0 */
+ 0x00003000, /* VPPSYS1_1 */
+ 0x00000000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x000001FF, /* VDOSYS1_0 */
+ 0x000001E0, /* VDOSYS1_1 */
+ 0x00FB0007, /* VDOSYS1_2 */
+ },
+ .table_pll = (PLL_BIT_UNIVPLL |
+ PLL_BIT_MFGPLL |
+ PLL_BIT_MSDCPLL |
+ PLL_BIT_TVDPLL1 |
+ PLL_BIT_TVDPLL2 |
+ PLL_BIT_MMPLL |
+ PLL_BIT_ETHPLL |
+ PLL_BIT_IMGPLL |
+ PLL_BIT_APLL1 |
+ PLL_BIT_APLL2 |
+ PLL_BIT_APLL3 |
+ PLL_BIT_APLL4 |
+ PLL_BIT_APLL5),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_BUS26M,
+ .is_valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_CHECK |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_TRACE_TIME),
+ .is_cond_block = 0U,
+ .enter_cnt = 0U,
+ .all_pll_dump = 0U,
+ .cond_res = &cond_bus26m_res,
+ .residency = 0ULL,
+};
+
+#ifdef MTK_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+ unsigned int irq_index,
+ struct wake_status *wakeup)
+{
+ if ((irqs == NULL) || (wakeup == NULL)) {
+ return;
+ }
+
+ INFO("[SPM] r12=0x%08x(0x%08x), flag=0x%08x 0x%08x 0x%08x, irq:%u(0x%08x) set pending\n",
+ wakeup->tr.comm.r12,
+ wakeup->md32pcm_wakeup_sta,
+ wakeup->tr.comm.debug_flag,
+ wakeup->tr.comm.b_sw_flag0,
+ wakeup->tr.comm.b_sw_flag1,
+ irqs->wakeupsrc[irq_index],
+ irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+ unsigned int idx;
+ struct wake_status *wakeup = NULL;
+ struct mt_irqremain *irqs = refer2remain_irq;
+
+ if (irqs == NULL) {
+ return;
+ }
+
+ if (spm_conservation_get_result(&wakeup) == 0) {
+ if (wakeup != NULL) {
+ for (idx = 0; idx < irqs->count; idx++) {
+ if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+ ((wakeup->tr.comm.raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+ if ((irqs->wakeupsrc_cat[idx] &
+ MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+ mt_spm_irq_remain_dump(irqs, idx, wakeup);
+ }
+ mt_irq_set_pending(irqs->irqs[idx]);
+ }
+ }
+ }
+ }
+}
+#endif
+
+int spm_bus26m_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_BUS26M_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+ return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
+ IS_MT_RM_RC_READY(status.is_valid) &&
+ (IS_PLAT_SUSPEND_ID(state_id) || (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+ const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
+ const struct mt_spm_cond_tables *tlb_check =
+ (const struct mt_spm_cond_tables *)&cond_bus26m;
+
+ if (tlb == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_bus26m_res : NULL);
+ status.all_pll_dump = mt_spm_dump_all_pll(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_bus26m_res : NULL);
+ return MT_RM_STATUS_OK;
+}
+
+static void update_rc_remain_irqs(const void *val)
+{
+ refer2remain_irq = (struct mt_irqremain *)val;
+}
+
+static void update_rc_fmaudio_adsp(int type, const void *val)
+{
+ int *flag = (int *)val;
+ unsigned int ext_op = (type == PLAT_RC_IS_ADSP) ?
+ (MT_SPM_EX_OP_SET_IS_ADSP | MT_SPM_EX_OP_SET_SUSPEND_MODE) :
+ MT_SPM_EX_OP_SET_SUSPEND_MODE;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(bus26m_ext_opand, ext_op);
+ } else {
+ SPM_RC_BITS_CLR(bus26m_ext_opand, ext_op);
+ }
+}
+
+static void update_rc_usb_peri(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ } else {
+ SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ }
+}
+
+static void update_rc_usb_infra(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ } else {
+ SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ }
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st;
+
+ st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+ struct mt_spm_cond_tables * const tlb = &cond_bus26m;
+
+ spm_rc_condition_modifier(st->id, st->act, st->value,
+ MT_RM_CONSTRAINT_ID_BUS26M, tlb);
+ } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+ (st->type == CONSTRAINT_RESIDNECY)) {
+ spm_rc_constraint_status_set(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_BUS26M,
+ (struct constraint_status * const)st->value,
+ (struct constraint_status * const)&status);
+ } else {
+ INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+ }
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ switch (type) {
+ case PLAT_RC_UPDATE_CONDITION:
+ res = update_rc_condition(val);
+ break;
+ case PLAT_RC_UPDATE_REMAIN_IRQS:
+ update_rc_remain_irqs(val);
+ break;
+ case PLAT_RC_IS_FMAUDIO:
+ case PLAT_RC_IS_ADSP:
+ update_rc_fmaudio_adsp(type, val);
+ break;
+ case PLAT_RC_IS_USB_PERI:
+ update_rc_usb_peri(val);
+ break;
+ case PLAT_RC_IS_USB_INFRA:
+ update_rc_usb_infra(val);
+ break;
+ case PLAT_RC_STATUS:
+ update_rc_status(val);
+ break;
+ default:
+ INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+ break;
+ }
+ return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+ return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
+#endif
+ if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT |
+ bus26m_ext_opand |
+ bus26m_ext_opand2),
+ CONSTRAINT_BUS26M_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_bus26m_conduct);
+ }
+ return MT_RM_STATUS_OK;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0);
+#endif
+ if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (bus26m_ext_opand | bus26m_ext_opand2 |
+ MT_SPM_EX_OP_SET_WDT | ext_op),
+ NULL);
+ bus26m_ext_opand = 0;
+ } else {
+ struct wake_status *waken = NULL;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+ ext_op |= MT_SPM_EX_OP_TRACE_LP;
+ }
+
+ mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+ status.enter_cnt++;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+ status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+ }
+ }
+
+ do_irqs_delivery();
+
+ return MT_RM_STATUS_OK;
+}
+
+int spm_get_status_rc_bus26m(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type == PLAT_RC_STATUS) {
+ int res = 0;
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ res = spm_rc_constraint_status_get(st->id, st->type,
+ st->act, MT_RM_CONSTRAINT_ID_BUS26M,
+ (struct constraint_status * const)&status,
+ (struct constraint_status * const)st->value);
+ if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c
new file mode 100644
index 0000000..1bcd509
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lpm_smc.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 (0)
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ (MT_SPM_DRAM_S1 | \
+ MT_SPM_DRAM_S0 | \
+ MT_SPM_SYSPLL | \
+ MT_SPM_INFRA | \
+ MT_SPM_26M | \
+ MT_SPM_XO_FPM)
+
+static unsigned int cpubuckldo_status = (MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_TRACE_TIME);
+static unsigned int cpubuckldo_enter_cnt;
+
+int spm_cpu_bcuk_ldo_conduct(int state_id,
+ struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if ((st->type == CONSTRAINT_UPDATE_VALID) && st->value) {
+ if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
+ (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
+ struct constraint_status *con = (struct constraint_status *)st->value;
+
+ if ((st->act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(cpubuckldo_status, con->is_valid);
+ } else {
+ SPM_RC_BITS_SET(cpubuckldo_status, con->is_valid);
+ }
+ }
+ }
+}
+
+int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val)
+{
+ if (type == PLAT_RC_STATUS) {
+ update_rc_status(val);
+ }
+ return MT_RM_STATUS_OK;
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+ return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ unsigned int ext_op = 0U;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : (0U)));
+#endif
+ if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_SET_WDT),
+ CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_cpu_bcuk_ldo_conduct);
+ }
+
+ cpubuckldo_enter_cnt++;
+
+ return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ unsigned int ext_op = 0U;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+ if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+ } else {
+ mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+ }
+
+ return 0;
+}
+
+int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type != PLAT_RC_STATUS) {
+ return ret;
+ }
+
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
+ (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
+ struct constraint_status *dest;
+
+ dest = (struct constraint_status *)st->value;
+ do {
+ if (dest == NULL) {
+ break;
+ }
+ if (st->type == CONSTRAINT_GET_VALID) {
+ dest->is_valid = cpubuckldo_status;
+ } else if (st->type == CONSTRAINT_COND_BLOCK) {
+ dest->is_cond_block = 0;
+ } else if (st->type == CONSTRAINT_GET_ENTER_CNT) {
+ if (st->id == MT_RM_CONSTRAINT_ID_ALL) {
+ dest->enter_cnt += cpubuckldo_enter_cnt;
+ } else {
+ dest->enter_cnt = cpubuckldo_enter_cnt;
+ }
+ } else {
+ break;
+ }
+ if (st->id != MT_RM_CONSTRAINT_ID_ALL) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ } while (0);
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
new file mode 100644
index 0000000..d1a2435
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_DRAM_ALLOW (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1 (0)
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ (MT_SPM_SYSPLL | MT_SPM_INFRA | MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+ .table_cg = {
+ 0xFF5DD002, /* MTCMOS1 */
+ 0x0000003C, /* MTCMOS2 */
+ 0x27AF8000, /* INFRA0 */
+ 0x20010876, /* INFRA1 */
+ 0x86000640, /* INFRA2 */
+ 0x00000000, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x01002A00, /* PERI0 */
+ 0x00080000, /* VPPSYS0_0 */
+ 0x38803000, /* VPPSYS0_1 */
+ 0x00081450, /* VPPSYS1_0 */
+ 0x00003000, /* VPPSYS1_1 */
+ 0x00000000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x000001F8, /* VDOSYS1_0 */
+ 0x000001E0, /* VDOSYS1_1 */
+ 0x00FB0007, /* VDOSYS1_2 */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_DRAM,
+ .is_valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_CHECK |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM |
+ MT_SPM_RC_VALID_TRACE_TIME),
+ .is_cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_dram_res,
+ .residency = 0ULL,
+};
+
+static unsigned short ext_status_dram;
+
+int spm_dram_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_DRAM_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+ return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK)) &&
+ IS_MT_RM_RC_READY(status.is_valid) &&
+ (IS_PLAT_SUSPEND_ID(state_id) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_MEM) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+ const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
+ const struct mt_spm_cond_tables *tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+
+ if (tlb == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_dram_res : NULL);
+ return MT_RM_STATUS_OK;
+}
+
+static void update_rc_clkbuf_status(const void *val)
+{
+ unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
+
+ if (is_flight != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_ufs_status(const void *val)
+{
+ unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
+
+ if (is_ufs_h8 != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st;
+
+ st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+ struct mt_spm_cond_tables * const tlb = &cond_dram;
+
+ spm_rc_condition_modifier(st->id, st->act, st->value,
+ MT_RM_CONSTRAINT_ID_DRAM, tlb);
+ } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+ (st->type == CONSTRAINT_RESIDNECY)) {
+ spm_rc_constraint_status_set(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ (struct constraint_status * const)st->value,
+ (struct constraint_status * const)&status);
+ } else {
+ INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+ }
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ switch (type) {
+ case PLAT_RC_UPDATE_CONDITION:
+ res = update_rc_condition(val);
+ break;
+ case PLAT_RC_CLKBUF_STATUS:
+ update_rc_clkbuf_status(val);
+ break;
+ case PLAT_RC_UFS_STATUS:
+ update_rc_ufs_status(val);
+ break;
+ case PLAT_RC_STATUS:
+ update_rc_status(val);
+ break;
+ default:
+ INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+ break;
+ }
+
+ return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+ return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ ext_status_dram = status.is_valid;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+ (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#else
+ (void)allows;
+#endif
+
+ if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_HW_S1_DETECT),
+ CONSTRAINT_DRAM_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+
+ if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ struct wake_status *waken = NULL;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+ ext_op |= MT_SPM_EX_OP_TRACE_LP;
+ }
+ mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+ status.enter_cnt++;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+ status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+ }
+ }
+
+ return 0;
+}
+
+int spm_get_status_rc_dram(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type == PLAT_RC_STATUS) {
+ int res = 0;
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ res = spm_rc_constraint_status_get(st->id, st->type,
+ st->act, MT_RM_CONSTRAINT_ID_DRAM,
+ (struct constraint_status * const)&status,
+ (struct constraint_status * const)st->value);
+ if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h
new file mode 100644
index 0000000..7763152
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#ifdef MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT
+#define SPM_FLAG_SRAM_SLEEP_CTRL (SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+#define SPM_SRAM_SLEEP_RC_RES_RESTRICT (0)
+#else
+#define SPM_FLAG_SRAM_SLEEP_CTRL (0)
+#define SPM_SRAM_SLEEP_RC_RES_RESTRICT (0)
+#endif
+
+#define SPM_RC_UPDATE_COND_ID_MASK (0xffff)
+#define SPM_RC_UPDATE_COND_RC_ID_MASK (0xffff)
+#define SPM_RC_UPDATE_COND_RC_ID_SHIFT (16)
+
+#define SPM_RC_UPDATE_COND_RC_ID_GET(val) \
+ ((val >> SPM_RC_UPDATE_COND_RC_ID_SHIFT) & SPM_RC_UPDATE_COND_RC_ID_MASK)
+
+#define SPM_RC_UPDATE_COND_ID_GET(val) (val & SPM_RC_UPDATE_COND_ID_MASK)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+int spm_get_status_rc_dram(unsigned int type, void *priv);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+int spm_get_status_rc_syspll(unsigned int type, void *priv);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+int spm_get_status_rc_bus26m(unsigned int type, void *priv);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
new file mode 100644
index 0000000..700f500
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_ENABLE_6315_CTRL | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1 (0)
+
+/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
+#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
+#else
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
+#endif
+
+static unsigned int syspll_ext_opand2;
+static unsigned short ext_status_syspll;
+
+static struct mt_spm_cond_tables cond_syspll = {
+ .table_cg = {
+ 0xFF5DD002, /* MTCMOS1 */
+ 0x0000003C, /* MTCMOS2 */
+ 0x27AF8000, /* INFRA0 */
+ 0x20010876, /* INFRA1 */
+ 0x86000640, /* INFRA2 */
+ 0x30008020, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x01002A0B, /* PERI0 */
+ 0x00090000, /* VPPSYS0_0 */
+ 0x38FF3E69, /* VPPSYS0_1 */
+ 0xF0081450, /* VPPSYS1_0 */
+ 0x00003000, /* VPPSYS1_1 */
+ 0x00000000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x000001FF, /* VDOSYS1_0 */
+ 0x008001E0, /* VDOSYS1_1 */
+ 0x00FB0007, /* VDOSYS1_2 */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_SYSPLL,
+ .is_valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_CHECK |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM |
+ MT_SPM_RC_VALID_TRACE_TIME),
+ .is_cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_syspll_res,
+ .residency = 0ULL,
+};
+
+int spm_syspll_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_SYSPLL_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+ return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
+ IS_MT_RM_RC_READY(status.is_valid) &&
+ (IS_PLAT_SUSPEND_ID(state_id) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ const struct mt_spm_cond_tables * const tlb =
+ (const struct mt_spm_cond_tables * const)val;
+ const struct mt_spm_cond_tables *tlb_check =
+ (const struct mt_spm_cond_tables *)&cond_syspll;
+
+ if (tlb == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_syspll_res : NULL);
+ return res;
+}
+
+static void update_rc_clkbuf_status(const void *val)
+{
+ unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
+
+ if (is_flight != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_ufs_status(const void *val)
+{
+ unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
+
+ if (is_ufs_h8 != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_usb_peri(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ } else {
+ SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ }
+}
+
+static void update_rc_usb_infra(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ } else {
+ SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ }
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st;
+
+ st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+ struct mt_spm_cond_tables * const tlb = &cond_syspll;
+
+ spm_rc_condition_modifier(st->id, st->act, st->value,
+ MT_RM_CONSTRAINT_ID_SYSPLL, tlb);
+ } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+ (st->type == CONSTRAINT_RESIDNECY)) {
+ spm_rc_constraint_status_set(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ (struct constraint_status * const)st->value,
+ (struct constraint_status * const)&status);
+ } else {
+ INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+ }
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ switch (type) {
+ case PLAT_RC_UPDATE_CONDITION:
+ res = update_rc_condition(val);
+ break;
+ case PLAT_RC_CLKBUF_STATUS:
+ update_rc_clkbuf_status(val);
+ break;
+ case PLAT_RC_UFS_STATUS:
+ update_rc_ufs_status(val);
+ break;
+ case PLAT_RC_IS_USB_PERI:
+ update_rc_usb_peri(val);
+ break;
+ case PLAT_RC_IS_USB_INFRA:
+ update_rc_usb_infra(val);
+ break;
+ case PLAT_RC_STATUS:
+ update_rc_status(val);
+ break;
+ default:
+ INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+ break;
+ }
+ return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+ return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ ext_status_syspll = status.is_valid;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
+#else
+ (void)allows;
+#endif
+ if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (syspll_ext_opand2 | MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE),
+ CONSTRAINT_SYSPLL_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+ if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (syspll_ext_opand2 | MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ struct wake_status *waken = NULL;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+ ext_op |= MT_SPM_EX_OP_TRACE_LP;
+ }
+
+ mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+ status.enter_cnt++;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+ status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+ }
+ }
+
+ return 0;
+}
+
+int spm_get_status_rc_syspll(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type == PLAT_RC_STATUS) {
+ int res = 0;
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ res = spm_rc_constraint_status_get(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ (struct constraint_status * const)&status,
+ (struct constraint_status * const)st->value);
+ if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm.c b/plat/mediatek/drivers/spm/mt8188/mt_spm.c
new file mode 100644
index 0000000..6c4e681
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <arch.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include "constraints/mt_spm_rc_internal.h"
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
+#include <lpm/mt_lp_rqm.h>
+#include <lpm/mt_lpm_smc.h>
+#include "mt_spm.h"
+#include "mt_spm_cond.h"
+#include "mt_spm_conservation.h"
+#include "mt_spm_constraint.h"
+#include "mt_spm_idle.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_pmic_wrap.h"
+#include "mt_spm_reg.h"
+#include "mt_spm_suspend.h"
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+#include "sleep_def.h"
+
+/*
+ * System Power Manager (SPM) is a hardware module which provides CPU idle
+ * and system suspend features.
+ */
+
+spinlock_t spm_lock;
+
+#ifdef MTK_PLAT_SPM_UNSUPPORT
+struct mt_resource_manager plat_mt8188_rm = {
+};
+#else
+struct mt_lp_res_req rq_xo_fpm = {
+ .res_id = MT_LP_RQ_XO_FPM,
+ .res_rq = MT_SPM_XO_FPM,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_26m = {
+ .res_id = MT_LP_RQ_26M,
+ .res_rq = MT_SPM_26M,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_infra = {
+ .res_id = MT_LP_RQ_INFRA,
+ .res_rq = MT_SPM_INFRA,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_syspll = {
+ .res_id = MT_LP_RQ_SYSPLL,
+ .res_rq = MT_SPM_SYSPLL,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_dram_s0 = {
+ .res_id = MT_LP_RQ_DRAM,
+ .res_rq = MT_SPM_DRAM_S0,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_dram_s1 = {
+ .res_id = MT_LP_RQ_DRAM,
+ .res_rq = MT_SPM_DRAM_S1,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req *spm_resources[] = {
+ &rq_xo_fpm,
+ &rq_26m,
+ &rq_infra,
+ &rq_syspll,
+ &rq_dram_s0,
+ &rq_dram_s1,
+ NULL,
+};
+
+struct mt_resource_req_manager plat_mt8188_rq = {
+ .res = spm_resources,
+};
+
+struct mt_resource_constraint plat_constraint_bus26m = {
+ .is_valid = spm_is_valid_rc_bus26m,
+ .update = spm_update_rc_bus26m,
+ .allow = spm_allow_rc_bus26m,
+ .run = spm_run_rc_bus26m,
+ .reset = spm_reset_rc_bus26m,
+ .get_status = spm_get_status_rc_bus26m,
+};
+
+struct mt_resource_constraint plat_constraint_syspll = {
+ .is_valid = spm_is_valid_rc_syspll,
+ .update = spm_update_rc_syspll,
+ .allow = spm_allow_rc_syspll,
+ .run = spm_run_rc_syspll,
+ .reset = spm_reset_rc_syspll,
+ .get_status = spm_get_status_rc_syspll,
+};
+
+struct mt_resource_constraint plat_constraint_dram = {
+ .is_valid = spm_is_valid_rc_dram,
+ .update = spm_update_rc_dram,
+ .allow = spm_allow_rc_dram,
+ .run = spm_run_rc_dram,
+ .reset = spm_reset_rc_dram,
+ .get_status = spm_get_status_rc_dram,
+};
+
+struct mt_resource_constraint plat_constraint_cpu = {
+ .is_valid = spm_is_valid_rc_cpu_buck_ldo,
+ .update = spm_update_rc_cpu_buck_ldo,
+ .allow = spm_allow_rc_cpu_buck_ldo,
+ .run = spm_run_rc_cpu_buck_ldo,
+ .reset = spm_reset_rc_cpu_buck_ldo,
+ .get_status = spm_get_status_rc_cpu_buck_ldo,
+};
+
+struct mt_resource_constraint *plat_constraints[] = {
+ &plat_constraint_bus26m,
+ &plat_constraint_syspll,
+ &plat_constraint_dram,
+ &plat_constraint_cpu,
+ NULL,
+};
+
+struct mt_resource_manager plat_mt8188_rm = {
+ .update = mt_spm_cond_update,
+ .consts = plat_constraints,
+};
+#endif
+
+/* Determine for SPM software resource user */
+static struct mt_lp_resource_user spm_res_user;
+
+struct mt_lp_resource_user *get_spm_res_user(void)
+{
+ return &spm_res_user;
+}
+
+int spm_boot_init(void)
+{
+ mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+ mt_lp_rm_register(&plat_mt8188_rm);
+
+ /* SPM service won't run when SPM not ready */
+#ifndef MTK_PLAT_SPM_UNSUPPORT
+ mt_lp_resource_request_manager_register(&plat_mt8188_rq);
+ mt_lp_resource_user_register("SPM", &spm_res_user);
+#endif
+
+ return 0;
+}
+MTK_ARCH_INIT(spm_boot_init);
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm.h b/plat/mediatek/drivers/spm/mt8188/mt_spm.h
new file mode 100644
index 0000000..0688b71
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_H
+#define MT_SPM_H
+
+#include <stdint.h>
+#include <stdio.h>
+#include <lib/spinlock.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rq.h>
+
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. Therefore, there is no doubt to use the spin_lock here.
+ */
+extern spinlock_t spm_lock;
+
+#ifdef __GNUC__
+#define spm_likely(x) __builtin_expect(!!(x), 1)
+#define spm_unlikely(x) __builtin_expect(!!(x), 0)
+#else
+#define spm_likely(x) (x)
+#define spm_unlikely(x) (x)
+#endif
+
+#define MT_SPM_USING_SRCLKEN_RC
+/* spm extern operand definition */
+#define MT_SPM_EX_OP_CLR_26M_RECORD BIT(0)
+#define MT_SPM_EX_OP_SET_WDT BIT(1)
+#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ BIT(2)
+#define MT_SPM_EX_OP_SET_SUSPEND_MODE BIT(3)
+#define MT_SPM_EX_OP_SET_IS_ADSP BIT(4)
+#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM BIT(5)
+#define MT_SPM_EX_OP_HW_S1_DETECT BIT(6)
+#define MT_SPM_EX_OP_TRACE_LP BIT(7)
+#define MT_SPM_EX_OP_TRACE_SUSPEND BIT(8)
+#define MT_SPM_EX_OP_TRACE_TIMESTAMP_EN BIT(9)
+#define MT_SPM_EX_OP_TIME_CHECK BIT(10)
+#define MT_SPM_EX_OP_TIME_OBS BIT(11)
+#define MT_SPM_EX_OP_PERI_ON BIT(12)
+#define MT_SPM_EX_OP_INFRA_ON BIT(13)
+
+typedef enum {
+ WR_NONE = 0,
+ WR_UART_BUSY = 1,
+ WR_ABORT = 2,
+ WR_PCM_TIMER = 3,
+ WR_WAKE_SRC = 4,
+ WR_DVFSRC = 5,
+ WR_TWAM = 6,
+ WR_PMSR = 7,
+ WR_SPM_ACK_CHK = 8,
+ WR_UNKNOWN = 9,
+} wake_reason_t;
+
+struct mt_lp_resource_user *get_spm_res_user(void);
+int spm_boot_init(void);
+
+#endif /* MT_SPM_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
new file mode 100644
index 0000000..fe6e598
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <lib/mmio.h>
+#include <lib/pm/mtk_pm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <platform_def.h>
+
+#define TOPCKGEB_BASE (IO_PHYS)
+
+#define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
+
+#define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
+#define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEB_BASE + ofs)
+#define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs)
+
+#define MT_LP_TZ_VPPSYS0_REG(ofs) (VPPSYS0_BASE + ofs)
+#define MT_LP_TZ_VPPSYS1_REG(ofs) (VPPSYS1_BASE + ofs)
+#define MT_LP_TZ_VDOSYS0_REG(ofs) (VDOSYS0_BASE + ofs)
+#define MT_LP_TZ_VDOSYS1_REG(ofs) (VDOSYS1_BASE + ofs)
+
+#define MT_LP_TZ_PERI_AO_REG(ofs) (PERICFG_AO_BASE + ofs)
+
+#undef SPM_PWR_STATUS
+#define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C)
+#define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170)
+#define SPM_CPU_PWR_STATUS MT_LP_TZ_SPM_REG(0x0174)
+#define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0090)
+#define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0094)
+#define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC)
+#define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8)
+#define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00E8)
+#define TOP_SW_I2C_CG MT_LP_TZ_TOPCK_REG(0x00A4)
+#define PERI_SW_CG0 MT_LP_TZ_PERI_AO_REG(0x0018)
+#define VPPSYS0_SW_CG0 MT_LP_TZ_VPPSYS0_REG(0x0020)
+#define VPPSYS0_SW_CG1 MT_LP_TZ_VPPSYS0_REG(0x002C)
+#define VPPSYS0_SW_CG2 MT_LP_TZ_VPPSYS0_REG(0x0038)
+#define VPPSYS1_SW_CG0 MT_LP_TZ_VPPSYS1_REG(0x0100)
+#define VPPSYS1_SW_CG1 MT_LP_TZ_VPPSYS1_REG(0x0110)
+#define VDOSYS0_SW_CG0 MT_LP_TZ_VDOSYS0_REG(0x0100)
+#define VDOSYS0_SW_CG1 MT_LP_TZ_VDOSYS0_REG(0x0110)
+#define VDOSYS1_SW_CG0 MT_LP_TZ_VDOSYS1_REG(0x0100)
+#define VDOSYS1_SW_CG1 MT_LP_TZ_VDOSYS1_REG(0x0120)
+#define VDOSYS1_SW_CG2 MT_LP_TZ_VDOSYS1_REG(0x0130)
+
+#define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x2c + id * 0xc)
+
+enum {
+ /* CLK_CFG_0 1000_002c */
+ CLKMUX_VPP = 0,
+ NF_CLKMUX,
+};
+
+#define CLK_CHECK BIT(31)
+
+static bool check_clkmux_pdn(unsigned int clkmux_id)
+{
+ unsigned int reg, val, idx;
+ bool ret = false;
+
+ if ((clkmux_id & CLK_CHECK) != 0U) {
+ clkmux_id = (clkmux_id & ~CLK_CHECK);
+ reg = clkmux_id / 4U;
+ val = mmio_read_32(CLK_CFG(reg));
+ idx = clkmux_id % 4U;
+ ret = (((val >> (idx * 8U)) & 0x80) != 0U);
+ }
+
+ return ret;
+}
+
+static struct mt_spm_cond_tables spm_cond_t;
+
+/* local definitions */
+struct idle_cond_info {
+ /* check SPM_PWR_STATUS for bit definition */
+ unsigned int subsys_mask;
+ /* cg address */
+ uintptr_t addr;
+ /* bitflip value from *addr ? */
+ bool bBitflip;
+ /* check clkmux if bit 31 = 1, id is bit[30:0] */
+ unsigned int clkmux_id;
+};
+
+#define IDLE_CG(mask, addr, bitflip, clkmux) {mask, (uintptr_t)addr, bitflip, clkmux}
+
+static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
+ IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0),
+ IDLE_CG(0xffffffff, SPM_CPU_PWR_STATUS, false, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0),
+ IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0),
+ IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00000800, VPPSYS0_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00001000, VPPSYS1_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00001000, VPPSYS1_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00002000, VDOSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00002000, VDOSYS0_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00004000, VDOSYS1_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00004000, VDOSYS1_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00004000, VDOSYS1_SW_CG2, true, (CLK_CHECK | CLKMUX_VPP)),
+};
+
+/* check pll idle condition */
+#define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x340)
+#define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x544)
+#define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x504)
+#define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x514)
+#define PLL_TVDPLL1 MT_LP_TZ_APMIXEDSYS(0x524)
+#define PLL_TVDPLL2 MT_LP_TZ_APMIXEDSYS(0x534)
+#define PLL_ETHPLL MT_LP_TZ_APMIXEDSYS(0x44c)
+#define PLL_IMGPLL MT_LP_TZ_APMIXEDSYS(0x554)
+#define PLL_APLL1 MT_LP_TZ_APMIXEDSYS(0x304)
+#define PLL_APLL2 MT_LP_TZ_APMIXEDSYS(0x318)
+#define PLL_APLL3 MT_LP_TZ_APMIXEDSYS(0x32c)
+#define PLL_APLL4 MT_LP_TZ_APMIXEDSYS(0x404)
+#define PLL_APLL5 MT_LP_TZ_APMIXEDSYS(0x418)
+
+unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res)
+{
+ unsigned int b_res = 0U;
+ unsigned int i;
+
+ if ((src == NULL) || (dest == NULL)) {
+ return SPM_COND_CHECK_FAIL;
+ }
+
+ for (i = 0; i < PLAT_SPM_COND_MAX; i++) {
+ if (res != NULL) {
+ res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]);
+
+ if ((res->table_cg[i]) != 0U) {
+ b_res |= BIT(i);
+ }
+ } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
+ b_res |= BIT(i);
+ break;
+ }
+ }
+
+ if (res != NULL) {
+ res->table_pll = (src->table_pll & dest->table_pll);
+
+ if ((res->table_pll) != 0U) {
+ b_res |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
+ SPM_COND_CHECK_BLOCKED_PLL;
+ }
+ } else if ((src->table_pll & dest->table_pll) != 0U) {
+ b_res |= SPM_COND_CHECK_BLOCKED_PLL;
+ }
+
+ return b_res;
+}
+
+unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res)
+{
+ unsigned int b_res = 0U;
+
+ if (res != NULL) {
+ res->table_all_pll = src->table_all_pll;
+ if ((res->table_all_pll) != 0U) {
+ b_res |= (res->table_all_pll << SPM_COND_BLOCKED_PLL_IDX) |
+ SPM_COND_CHECK_BLOCKED_PLL;
+ }
+ } else if ((src->table_pll & dest->table_pll) != 0U) {
+ b_res |= SPM_COND_CHECK_BLOCKED_PLL;
+ }
+
+ return b_res;
+}
+
+#define IS_MT_SPM_PWR_OFF(mask) \
+ (!(mmio_read_32(SPM_PWR_STATUS) & mask) && \
+ !(mmio_read_32(SPM_PWR_STATUS_2ND) & mask))
+
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
+ int stateid, void *priv)
+{
+ static const struct {
+ uintptr_t en_reg;
+ uint32_t pll_b;
+ } plls[] = {
+ { PLL_MFGPLL, PLL_BIT_MFGPLL },
+ { PLL_MMPLL, PLL_BIT_MMPLL },
+ { PLL_UNIVPLL, PLL_BIT_UNIVPLL },
+ { PLL_MSDCPLL, PLL_BIT_MSDCPLL },
+ { PLL_TVDPLL1, PLL_BIT_TVDPLL1 },
+ { PLL_TVDPLL2, PLL_BIT_TVDPLL2 },
+ { PLL_ETHPLL, PLL_BIT_ETHPLL },
+ { PLL_IMGPLL, PLL_BIT_IMGPLL },
+ { PLL_APLL1, PLL_BIT_APLL1 },
+ { PLL_APLL2, PLL_BIT_APLL2 },
+ { PLL_APLL3, PLL_BIT_APLL3 },
+ { PLL_APLL4, PLL_BIT_APLL4 },
+ { PLL_APLL5, PLL_BIT_APLL5 },
+ };
+
+ int res;
+ unsigned int i;
+ struct mt_resource_constraint *const *_con;
+
+ /* read all cg state */
+ for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+ spm_cond_t.table_cg[i] = 0U;
+
+ /* check mtcmos, if off set idle_value and clk to 0 disable */
+ if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
+ continue;
+ }
+ /* check clkmux */
+ if (check_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
+ continue;
+ }
+ spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
+ ~mmio_read_32(idle_cg_info[i].addr) :
+ mmio_read_32(idle_cg_info[i].addr);
+ }
+
+ spm_cond_t.table_pll = 0U;
+ for (i = 0U; i < ARRAY_SIZE(plls); i++) {
+ if ((mmio_read_32(plls[i].en_reg) & BIT(9)) != 0U) {
+ spm_cond_t.table_pll |= plls[i].pll_b;
+ }
+ }
+
+ spm_cond_t.priv = priv;
+ for (i = 0U, _con = con; (*_con != NULL) && (i < num); _con++, i++) {
+ if ((*_con)->update == NULL) {
+ continue;
+ }
+ res = (*_con)->update(stateid, PLAT_RC_UPDATE_CONDITION,
+ (void const *)&spm_cond_t);
+ if (res != MT_RM_STATUS_OK) {
+ break;
+ }
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
new file mode 100644
index 0000000..793d5e8
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_COND_H
+#define MT_SPM_COND_H
+
+#include <lpm/mt_lp_rm.h>
+
+enum plat_spm_cond {
+ PLAT_SPM_COND_MTCMOS1 = 0,
+ PLAT_SPM_COND_MTCMOS2,
+ PLAT_SPM_COND_CG_INFRA_0,
+ PLAT_SPM_COND_CG_INFRA_1,
+ PLAT_SPM_COND_CG_INFRA_2,
+ PLAT_SPM_COND_CG_INFRA_3,
+ PLAT_SPM_COND_CG_INFRA_4,
+ PLAT_SPM_COND_CG_PERI_0,
+ PLAT_SPM_COND_CG_VPPSYS0_0,
+ PLAT_SPM_COND_CG_VPPSYS0_1,
+ PLAT_SPM_COND_CG_VPPSYS1_0,
+ PLAT_SPM_COND_CG_VPPSYS1_1,
+ PLAT_SPM_COND_CG_VDOSYS0_0,
+ PLAT_SPM_COND_CG_VDOSYS0_1,
+ PLAT_SPM_COND_CG_VDOSYS1_0,
+ PLAT_SPM_COND_CG_VDOSYS1_1,
+ PLAT_SPM_COND_CG_VDOSYS1_2,
+ PLAT_SPM_COND_MAX,
+};
+
+/* For PLL id >= PLAT_SPM_COND_PLL_MAX is not checked in idle condition */
+enum plat_spm_cond_pll {
+ PLAT_SPM_COND_PLL_UNIVPLL = 0,
+ PLAT_SPM_COND_PLL_MFGPLL,
+ PLAT_SPM_COND_PLL_MSDCPLL,
+ PLAT_SPM_COND_PLL_TVDPLL1,
+ PLAT_SPM_COND_PLL_TVDPLL2,
+ PLAT_SPM_COND_PLL_MMPLL,
+ PLAT_SPM_COND_PLL_ETHPLL,
+ PLAT_SPM_COND_PLL_IMGPLL,
+ PLAT_SPM_COND_PLL_APLL1,
+ PLAT_SPM_COND_PLL_APLL2,
+ PLAT_SPM_COND_PLL_APLL3,
+ PLAT_SPM_COND_PLL_APLL4,
+ PLAT_SPM_COND_PLL_APLL5,
+ PLAT_SPM_COND_PLL_MAX,
+};
+
+#define PLL_BIT_MFGPLL BIT(PLAT_SPM_COND_PLL_MFGPLL)
+#define PLL_BIT_MMPLL BIT(PLAT_SPM_COND_PLL_MMPLL)
+#define PLL_BIT_UNIVPLL BIT(PLAT_SPM_COND_PLL_UNIVPLL)
+#define PLL_BIT_MSDCPLL BIT(PLAT_SPM_COND_PLL_MSDCPLL)
+#define PLL_BIT_TVDPLL1 BIT(PLAT_SPM_COND_PLL_TVDPLL1)
+#define PLL_BIT_TVDPLL2 BIT(PLAT_SPM_COND_PLL_TVDPLL2)
+#define PLL_BIT_ETHPLL BIT(PLAT_SPM_COND_PLL_ETHPLL)
+#define PLL_BIT_IMGPLL BIT(PLAT_SPM_COND_PLL_IMGPLL)
+#define PLL_BIT_APLL1 BIT(PLAT_SPM_COND_PLL_APLL1)
+#define PLL_BIT_APLL2 BIT(PLAT_SPM_COND_PLL_APLL2)
+#define PLL_BIT_APLL3 BIT(PLAT_SPM_COND_PLL_APLL3)
+#define PLL_BIT_APLL4 BIT(PLAT_SPM_COND_PLL_APLL4)
+#define PLL_BIT_APLL5 BIT(PLAT_SPM_COND_PLL_APLL5)
+
+/*
+ * Definition about SPM_COND_CHECK_BLOCKED
+ * bit[00:16]: cg blocking index
+ * bit[17:29]: pll blocking index
+ * bit[30]: pll blocking information
+ * bit[31]: idle condition check fail
+ */
+#define SPM_COND_BLOCKED_CG_IDX (0)
+#define SPM_COND_BLOCKED_PLL_IDX (17)
+#define SPM_COND_CHECK_BLOCKED_PLL BIT(30)
+#define SPM_COND_CHECK_FAIL BIT(31)
+
+struct mt_spm_cond_tables {
+ unsigned int table_cg[PLAT_SPM_COND_MAX];
+ unsigned int table_pll;
+ unsigned int table_all_pll;
+ void *priv;
+};
+
+unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res);
+unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res);
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
+ int stateid, void *priv);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
new file mode 100644
index 0000000..bcb2df6
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rqm.h>
+#include "mt_spm.h"
+#include "mt_spm_conservation.h"
+#include "mt_spm_reg.h"
+#include <platform_def.h>
+
+#define INFRA_EMI_DCM_CFG0 U(0x10002028)
+
+static struct wake_status spm_wakesta; /* record last wakesta */
+static wake_reason_t spm_wake_reason = WR_NONE;
+static unsigned int emi_bak;
+
+static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req)
+{
+ int ret = 0;
+ struct pwr_ctrl *pwrctrl;
+ unsigned int cpu = plat_my_core_pos();
+
+ pwrctrl = spm_lp->pwrctrl;
+
+ /* EMI workaround */
+ emi_bak = mmio_read_32(INFRA_EMI_DCM_CFG0) & BIT(22);
+ mmio_setbits_32(INFRA_EMI_DCM_CFG0, BIT(22));
+
+ __spm_set_cpu_status(cpu);
+ __spm_set_power_control(pwrctrl);
+ __spm_set_wakeup_event(pwrctrl);
+
+ __spm_set_pcm_flags(pwrctrl);
+
+ __spm_src_req_update(pwrctrl, resource_req);
+
+ if ((ext_opand & MT_SPM_EX_OP_CLR_26M_RECORD) != 0U) {
+ __spm_clean_before_wfi();
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+ __spm_set_pcm_wdt(1);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+ spm_hw_s1_state_monitor_resume();
+ }
+
+ __spm_send_cpu_wakeup_event();
+
+ return ret;
+}
+
+static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status)
+{
+ unsigned int ext_status = 0U;
+
+ if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+ __spm_set_pcm_wdt(0);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+ spm_hw_s1_state_monitor_pause(&ext_status);
+ }
+
+ __spm_ext_int_wakeup_req_clr();
+
+ __spm_get_wakeup_status(&spm_wakesta, ext_status);
+
+ if (status != NULL) {
+ *status = &spm_wakesta;
+ }
+
+ __spm_clean_after_wakeup();
+ spm_wake_reason = __spm_output_wake_reason(&spm_wakesta);
+
+ /* EMI workaround */
+ if (emi_bak == 0U) {
+ mmio_clrbits_32(INFRA_EMI_DCM_CFG0, BIT(22));
+ }
+}
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req)
+{
+ unsigned int rc_state = resource_req;
+
+ if (spm_lp == NULL) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+ go_to_spm_before_wfi(state_id, ext_opand, spm_lp, rc_state);
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
+
+void spm_conservation_finish(int state_id, unsigned int ext_opand, struct spm_lp_scen *spm_lp,
+ struct wake_status **status)
+{
+ spin_lock(&spm_lock);
+ go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
+ spin_unlock(&spm_lock);
+}
+
+int spm_conservation_get_result(struct wake_status **res)
+{
+ if (res == NULL) {
+ return -1;
+ }
+ *res = &spm_wakesta;
+ return 0;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.h
new file mode 100644
index 0000000..4be8567
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSERVATION_H
+#define MT_SPM_CONSERVATION_H
+
+#include "mt_spm_internal.h"
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req);
+void spm_conservation_finish(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status);
+int spm_conservation_get_result(struct wake_status **res);
+
+#endif /* MT_SPM_CONSERVATION_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_constraint.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_constraint.h
new file mode 100644
index 0000000..43bb76b
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_constraint.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSTRAINT_H
+#define MT_SPM_CONSTRAINT_H
+
+#include <lpm/mt_lp_rm.h>
+
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF BIT(0)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 BIT(1)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 BIT(2)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP BIT(3)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN BIT(4)
+#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF BIT(5)
+#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND BIT(6)
+#define MT_RM_CONSTRAINT_ALLOW_BBLPM BIT(7)
+#define MT_RM_CONSTRAINT_ALLOW_XO_UFS BIT(8)
+#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE BIT(9)
+#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE BIT(10)
+
+enum mt_spm_rm_rc_type {
+ MT_RM_CONSTRAINT_ID_BUS26M,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
+ MT_RM_CONSTRAINT_ID_ALL,
+};
+
+#define MT_SPM_RC_INVALID (0x0)
+#define MT_SPM_RC_VALID_SW BIT(0)
+#define MT_SPM_RC_VALID_FW BIT(1)
+#define MT_SPM_RC_VALID_RESIDNECY BIT(2)
+#define MT_SPM_RC_VALID_COND_CHECK BIT(3)
+#define MT_SPM_RC_VALID_COND_LATCH BIT(4)
+#define MT_SPM_RC_VALID_UFS_H8 BIT(5)
+#define MT_SPM_RC_VALID_FLIGHTMODE BIT(6)
+#define MT_SPM_RC_VALID_XSOC_BBLPM BIT(7)
+#define MT_SPM_RC_VALID_TRACE_EVENT BIT(8)
+#define MT_SPM_RC_VALID_TRACE_TIME BIT(9)
+
+/* MT_RM_CONSTRAINT_SW_VALID | MT_RM_CONSTRAINT_FW_VALID */
+#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW)
+
+#define IS_MT_RM_RC_READY(status) ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
+
+struct constraint_status {
+ uint16_t id;
+ uint16_t is_valid;
+ uint32_t is_cond_block;
+ uint32_t enter_cnt;
+ uint32_t all_pll_dump;
+ uint64_t residency;
+ struct mt_spm_cond_tables *cond_res;
+};
+
+enum constraint_status_update_type {
+ CONSTRAINT_UPDATE_VALID,
+ CONSTRAINT_UPDATE_COND_CHECK,
+ CONSTRAINT_RESIDNECY,
+};
+
+enum constraint_status_get_type {
+ CONSTRAINT_GET_VALID = 0xD0000000,
+ CONSTRAINT_GET_ENTER_CNT,
+ CONSTRAINT_GET_RESIDENCY,
+ CONSTRAINT_GET_COND_EN,
+ CONSTRAINT_COND_BLOCK,
+ CONSTRAINT_GET_COND_BLOCK_LATCH,
+ CONSTRAINT_GET_COND_BLOCK_DETAIL,
+ CONSTRAINT_GET_RESIDNECY,
+};
+
+struct rc_common_state {
+ unsigned int id;
+ unsigned int act;
+ unsigned int type;
+ void *value;
+};
+
+#define MT_SPM_RC_BBLPM_MODE (MT_SPM_RC_VALID_UFS_H8 | \
+ MT_SPM_RC_VALID_FLIGHTMODE | \
+ MT_SPM_RC_VALID_XSOC_BBLPM)
+
+#define IS_MT_SPM_RC_BBLPM_MODE(st) ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
+
+#endif /* MT_SPM_CONSTRAINT_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.c
new file mode 100644
index 0000000..b4dc3f9
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+
+#define SPM_BYPASS_SYSPWREQ_GENERIC (1)
+
+#define __WAKE_SRC_FOR_IDLE_COMMON__ ( \
+ (R12_PCM_TIMER) | \
+ (R12_KP_IRQ_B) | \
+ (R12_APWDT_EVENT_B) | \
+ (R12_APXGPT1_EVENT_B) | \
+ (R12_MSDC_WAKEUP_B) | \
+ (R12_EINT_EVENT_B) | \
+ (R12_SBD_INTR_WAKEUP_B) | \
+ (R12_SSPM2SPM_WAKEUP_B) | \
+ (R12_SCP2SPM_WAKEUP_B) | \
+ (R12_ADSP2SPM_WAKEUP_B) | \
+ (R12_USBX_CDSC_B) | \
+ (R12_USBX_POWERDWN_B) | \
+ (R12_SYS_TIMER_EVENT_B) | \
+ (R12_EINT_EVENT_SECURE_B) | \
+ (R12_ECE_INT_HDMI_B) | \
+ (R12_AFE_IRQ_MCU_B) | \
+ (R12_SYS_CIRQ_IRQ_B) | \
+ (R12_PCIE_WAKEUPEVENT_B) | \
+ (R12_SPM_CPU_WAKEUPEVENT_B) | \
+ (R12_APUSYS_WAKE_HOST_B))
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
+#else
+#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__ | R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl idle_spm_pwr = {
+ .wake_src = WAKE_SRC_FOR_IDLE,
+
+ /* SPM_AP_STANDBY_CON */
+ /* [0] */
+ .reg_wfi_op = 0,
+ /* [1] */
+ .reg_wfi_type = 0,
+ /* [2] */
+ .reg_mp0_cputop_idle_mask = 0,
+ /* [3] */
+ .reg_mp1_cputop_idle_mask = 0,
+ /* [4] */
+ .reg_mcusys_idle_mask = 0,
+ /* [25] */
+ .reg_md_apsrc_1_sel = 0,
+ /* [26] */
+ .reg_md_apsrc_0_sel = 0,
+ /* [29] */
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC_REQ */
+ /* [0] */
+ .reg_spm_apsrc_req = 0,
+ /* [1] */
+ .reg_spm_f26m_req = 0,
+ /* [3] */
+ .reg_spm_infra_req = 0,
+ /* [4] */
+ .reg_spm_vrf18_req = 0,
+ /* [7] */
+ .reg_spm_ddr_en_req = 0,
+ /* [8] */
+ .reg_spm_dvfs_req = 0,
+ /* [9] */
+ .reg_spm_sw_mailbox_req = 0,
+ /* [10] */
+ .reg_spm_sspm_mailbox_req = 0,
+ /* [11] */
+ .reg_spm_adsp_mailbox_req = 0,
+ /* [12] */
+ .reg_spm_scp_mailbox_req = 0,
+
+ /* SPM_SRC_MASK */
+ /* [0] */
+ .reg_sspm_srcclkena_0_mask_b = 1,
+ /* [1] */
+ .reg_sspm_infra_req_0_mask_b = 1,
+ /* [2] */
+ .reg_sspm_apsrc_req_0_mask_b = 1,
+ /* [3] */
+ .reg_sspm_vrf18_req_0_mask_b = 1,
+ /* [4] */
+ .reg_sspm_ddr_en_0_mask_b = 1,
+ /* [5] */
+ .reg_scp_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_scp_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_scp_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_scp_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_scp_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_apu_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_apu_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_apu_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_apu_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_apu_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_cpueb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_cpueb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_cpueb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_cpueb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_cpueb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ /* [26] */
+ .reg_bak_psri_infra_req_mask_b = 0,
+ /* [27] */
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ /* [28] */
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ /* [29] */
+ .reg_bak_psri_ddr_en_mask_b = 0,
+ /* [30] */
+ .reg_cam_ddren_req_mask_b = 1,
+ /* [31] */
+ .reg_img_ddren_req_mask_b = 1,
+
+ /* SPM_SRC2_MASK */
+ /* [0] */
+ .reg_msdc0_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_msdc0_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_msdc0_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_msdc1_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_msdc1_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_msdc1_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_msdc2_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_msdc2_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_msdc2_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_ufs_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_ufs_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_ufs_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_ufs_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_ufs_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_usb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_usb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_usb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_usb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_usb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_pextp_p0_srcclkena_mask_b = 1,
+ /* [26] */
+ .reg_pextp_p0_infra_req_mask_b = 1,
+ /* [27] */
+ .reg_pextp_p0_apsrc_req_mask_b = 1,
+ /* [28] */
+ .reg_pextp_p0_vrf18_req_mask_b = 1,
+ /* [29] */
+ .reg_pextp_p0_ddr_en_mask_b = 1,
+
+ /* SPM_SRC3_MASK */
+ /* [0] */
+ .reg_pextp_p1_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_pextp_p1_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_pextp_p1_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_pextp_p1_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_pextp_p1_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_gce0_infra_req_mask_b = 1,
+ /* [6] */
+ .reg_gce0_apsrc_req_mask_b = 1,
+ /* [7] */
+ .reg_gce0_vrf18_req_mask_b = 1,
+ /* [8] */
+ .reg_gce0_ddr_en_mask_b = 1,
+ /* [9] */
+ .reg_gce1_infra_req_mask_b = 1,
+ /* [10] */
+ .reg_gce1_apsrc_req_mask_b = 1,
+ /* [11] */
+ .reg_gce1_vrf18_req_mask_b = 1,
+ /* [12] */
+ .reg_gce1_ddr_en_mask_b = 1,
+ /* [13] */
+ .reg_spm_srcclkena_reserved_mask_b = 1,
+ /* [14] */
+ .reg_spm_infra_req_reserved_mask_b = 1,
+ /* [15] */
+ .reg_spm_apsrc_req_reserved_mask_b = 1,
+ /* [16] */
+ .reg_spm_vrf18_req_reserved_mask_b = 1,
+ /* [17] */
+ .reg_spm_ddr_en_reserved_mask_b = 1,
+ /* [18] */
+ .reg_disp0_apsrc_req_mask_b = 1,
+ /* [19] */
+ .reg_disp0_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_disp1_apsrc_req_mask_b = 1,
+ /* [21] */
+ .reg_disp1_ddr_en_mask_b = 1,
+ /* [22] */
+ .reg_disp2_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_disp2_ddr_en_mask_b = 1,
+ /* [24] */
+ .reg_disp3_apsrc_req_mask_b = 1,
+ /* [25] */
+ .reg_disp3_ddr_en_mask_b = 1,
+ /* [26] */
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ /* [27] */
+ .reg_infrasys_ddr_en_mask_b = 1,
+
+ /* [28] */
+ .reg_cg_check_srcclkena_mask_b = 1,
+ /* [29] */
+ .reg_cg_check_apsrc_req_mask_b = 1,
+ /* [30] */
+ .reg_cg_check_vrf18_req_mask_b = 1,
+ /* [31] */
+ .reg_cg_check_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ /* [8:0] */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0,
+ /* [17:9] */
+ .reg_mcusys_merge_ddr_en_mask_b = 0,
+ /* [19:18] */
+ .reg_dramc_md32_infra_req_mask_b = 3,
+ /* [21:20] */
+ .reg_dramc_md32_vrf18_req_mask_b = 3,
+ /* [23:22] */
+ .reg_dramc_md32_ddr_en_mask_b = 0,
+ /* [24] */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ /* [3:0] */
+ .reg_sc_sw2spm_wakeup_mask_b = 0,
+ /* [4] */
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ /* [8:5] */
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ /* [9] */
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ /* [10] */
+ .reg_csyspwrup_ack_mask = 0,
+ /* [11] */
+ .reg_csyspwrup_req_mask = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ /* [31:0] */
+ .reg_wakeup_event_mask = 0xC1282203,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ /* [31:0] */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+};
+
+struct spm_lp_scen idle_spm_lp = {
+ .pwrctrl = &idle_spm_pwr,
+};
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn)
+{
+ int ret = 0;
+ unsigned int src_req = 0U;
+
+ if (fn != NULL) {
+ fn(state_id, &idle_spm_lp, &src_req);
+ }
+
+ ret = spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
+
+ if (ret == 0) {
+ struct mt_lp_publish_event event = {
+ .id = MT_LPM_PUBEVENTS_SYS_POWER_OFF,
+ .val.u32 = 0U,
+ };
+
+ MT_LP_PUBLISH_EVENT(&event);
+ }
+ return ret;
+}
+
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status,
+ spm_idle_conduct_restore fn)
+{
+ struct mt_lp_publish_event event = {
+ .id = MT_LPM_PUBEVENTS_SYS_POWER_ON,
+ .val.u32 = 0U,
+ };
+
+ ext_opand |= (MT_SPM_EX_OP_TIME_CHECK | MT_SPM_EX_OP_TIME_OBS);
+ spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
+
+ if (spm_unlikely(fn)) {
+ fn(state_id, &idle_spm_lp, *status);
+ }
+ MT_LP_PUBLISH_EVENT(&event);
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.h
new file mode 100644
index 0000000..4d78a28
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_IDLE_H
+#define MT_SPM_IDLE_H
+
+#include "mt_spm_internal.h"
+
+typedef int (*spm_idle_conduct)(int state_id,
+ struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req);
+typedef int (*spm_idle_conduct_restore)(int state_id,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status *status);
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn);
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status,
+ spm_idle_conduct_restore fn);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
new file mode 100644
index 0000000..b38a6d0
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <drivers/spm/mt_spm_resource_req.h>
+#include "mt_spm.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_pmic_wrap.h"
+#include "mt_spm_reg.h"
+#include <platform_def.h>
+
+#define SPM_INIT_DONE_US (20) /* Simulation result */
+
+wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta)
+{
+ wake_reason_t wr = WR_UNKNOWN;
+
+ if (wakesta == NULL) {
+ return wr;
+ }
+
+ if (wakesta->is_abort != 0U) {
+ VERBOSE("SPM EARLY WAKE r12 = 0x%x, debug_flag = 0x%x 0x%x\n",
+ wakesta->tr.comm.r12,
+ wakesta->tr.comm.debug_flag, wakesta->tr.comm.debug_flag1);
+ VERBOSE("SPM EARLY WAKE sw_flag = 0x%x 0x%x b_sw_flag = 0x%x 0x%x\n",
+ wakesta->sw_flag0, wakesta->sw_flag1,
+ wakesta->tr.comm.b_sw_flag0, wakesta->tr.comm.b_sw_flag1);
+ }
+
+ if ((wakesta->tr.comm.r12 & R12_PCM_TIMER) != 0U) {
+
+ if ((wakesta->wake_misc & WAKE_MISC_PCM_TIMER_EVENT) != 0U) {
+ wr = WR_PCM_TIMER;
+ }
+ }
+
+ return wr;
+}
+
+void __spm_set_cpu_status(unsigned int cpu)
+{
+ if (cpu >= 8) {
+ ERROR("%s: error cpu number %d\n", __func__, cpu);
+ return;
+ }
+ mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu));
+ mmio_write_32(ROOT_CORE_ADDR, SPM_CPU0_PWR_CON + (cpu * 0x4) + 0x20000000);
+ /* Notify MCUPM to wake the target CPU up */
+ mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
+}
+
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, unsigned int resource_usage)
+{
+
+ uint8_t reg_spm_apsrc_req = (resource_usage & MT_SPM_DRAM_S0) ?
+ 1 : pwrctrl->reg_spm_apsrc_req;
+ uint8_t reg_spm_ddr_en_req = (resource_usage & MT_SPM_DRAM_S1) ?
+ 1 : pwrctrl->reg_spm_ddr_en_req;
+ uint8_t reg_spm_vrf18_req = (resource_usage & MT_SPM_SYSPLL) ?
+ 1 : pwrctrl->reg_spm_vrf18_req;
+ uint8_t reg_spm_infra_req = (resource_usage & MT_SPM_INFRA) ?
+ 1 : pwrctrl->reg_spm_infra_req;
+ uint8_t reg_spm_f26m_req = (resource_usage & (MT_SPM_26M | MT_SPM_XO_FPM)) ?
+ 1 : pwrctrl->reg_spm_f26m_req;
+
+ /* SPM_SRC_REQ */
+ mmio_write_32(SPM_SRC_REQ,
+ ((reg_spm_apsrc_req & 0x1) << 0) |
+ ((reg_spm_f26m_req & 0x1) << 1) |
+ ((reg_spm_infra_req & 0x1) << 3) |
+ ((reg_spm_vrf18_req & 0x1) << 4) |
+ ((reg_spm_ddr_en_req & 0x1) << 7) |
+ ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+ ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+ ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+ ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+ ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+}
+
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+ /* SPM_AP_STANDBY_CON */
+ mmio_write_32(SPM_AP_STANDBY_CON,
+ ((pwrctrl->reg_wfi_op & 0x1) << 0) |
+ ((pwrctrl->reg_wfi_type & 0x1) << 1) |
+ ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+ ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+ ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+ ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+ ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+ ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+ /* SPM_SRC_REQ */
+ mmio_write_32(SPM_SRC_REQ,
+ ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+ ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+ ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+ ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+ ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
+ ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+ ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+ ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+ ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+ ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+ /* SPM_SRC_MASK */
+ mmio_write_32(SPM_SRC_MASK,
+ ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29) |
+ ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 30) |
+ ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 31));
+
+ /* SPM_SRC2_MASK */
+ mmio_write_32(SPM_SRC2_MASK,
+ ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
+
+ /* SPM_SRC3_MASK */
+ mmio_write_32(SPM_SRC3_MASK,
+ ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
+
+ /* SPM_SRC4_MASK */
+ mmio_write_32(SPM_SRC4_MASK,
+ ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
+ ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
+ ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 18) |
+ ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 20) |
+ ((pwrctrl->reg_dramc_md32_ddr_en_mask_b & 0x3) << 22) |
+ ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 24));
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK,
+ ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
+ ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+}
+
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+ unsigned int val, mask;
+
+ /* toggle event counter clear */
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+ /* toggle for reset SYS TIMER start point */
+ mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+
+ if (pwrctrl->timer_val_cust == 0U) {
+ val = (pwrctrl->timer_val != 0U) ? pwrctrl->timer_val : PCM_TIMER_MAX;
+ } else {
+ val = pwrctrl->timer_val_cust;
+ }
+
+ mmio_write_32(PCM_TIMER_VAL, val);
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
+
+ /* unmask AP wakeup source */
+ if (pwrctrl->wake_src_cust == 0U) {
+ mask = pwrctrl->wake_src;
+ } else {
+ mask = pwrctrl->wake_src_cust;
+ }
+
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
+
+ /* unmask SPM ISR (keep TWAM setting) */
+ mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
+
+ /* toggle event counter clear */
+ mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
+ /* toggle for reset SYS TIMER start point */
+ mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+}
+
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
+{
+ /* set PCM flags and data */
+ if (pwrctrl->pcm_flags_cust_clr != 0U) {
+ pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+ }
+ if (pwrctrl->pcm_flags_cust_set != 0U) {
+ pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
+ }
+ if (pwrctrl->pcm_flags1_cust_clr != 0U) {
+ pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+ }
+ if (pwrctrl->pcm_flags1_cust_set != 0U) {
+ pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+ }
+
+ mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
+
+ mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
+
+ mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
+
+ mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
+}
+
+void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_status)
+{
+ /* get wakeup event */
+ wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); /* backup of PCM_REG12_DATA */
+ wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_EXT_STA);
+ wakesta->tr.comm.raw_sta = mmio_read_32(SPM_WAKEUP_STA);
+ wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
+ wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
+ wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
+ wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC); /* backup of SPM_WAKEUP_MISC */
+
+ /* get sleep time */
+ wakesta->tr.comm.timer_out =
+ mmio_read_32(SPM_BK_PCM_TIMER); /* backup of PCM_TIMER_OUT */
+
+ /* get other SYS and co-clock status */
+ wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
+ wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
+ wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+ wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+ wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+ wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+ wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+ /* get debug flag for PCM execution check */
+ wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+ wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+ if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
+ wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
+ SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
+ mmio_write_32(PCM_WDT_LATCH_SPARE_0, wakesta->tr.comm.debug_flag);
+ }
+
+ /* get backup SW flag status */
+ wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); /* SPM_SW_RSV_7 */
+ wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); /* SPM_SW_RSV_8 */
+
+ /* get ISR status */
+ wakesta->isr = mmio_read_32(SPM_IRQ_STA);
+
+ /* get SW flag status */
+ wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
+ wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+
+ /* check abort */
+ wakesta->is_abort = wakesta->tr.comm.debug_flag & DEBUG_ABORT_MASK;
+ wakesta->is_abort |= wakesta->tr.comm.debug_flag1 & DEBUG_ABORT_MASK_1;
+}
+
+void __spm_clean_after_wakeup(void)
+{
+ /*
+ * Copy SPM_WAKEUP_STA to SPM_BK_WAKE_EVENT before clear SPM_WAKEUP_STA
+ *
+ * CPU dormant driver @kernel will copy edge-trig IRQ pending
+ * (recorded @SPM_BK_WAKE_EVENT) to GIC
+ */
+ mmio_write_32(SPM_BK_WAKE_EVENT, mmio_read_32(SPM_WAKEUP_STA) |
+ mmio_read_32(SPM_BK_WAKE_EVENT));
+
+ /* clean CPU wakeup event */
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0U);
+
+ /* clean wakeup event raw status (for edge trigger event) */
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, 0xefffffff); /* bit[28] for cpu wake up event */
+
+ /* clean ISR status (except TWAM) */
+ mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
+ mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
+ mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
+}
+
+void __spm_set_pcm_wdt(int en)
+{
+ /* enable PCM WDT (normal mode) to start count if needed */
+ if (en != 0) {
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, SPM_REGWR_CFG_KEY);
+
+ if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
+ mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
+ }
+ mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
+ } else {
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, SPM_REGWR_CFG_KEY);
+ }
+}
+
+void __spm_send_cpu_wakeup_event(void)
+{
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
+ /* SPM will clear SPM_CPU_WAKEUP_EVENT */
+}
+
+void __spm_ext_int_wakeup_req_clr(void)
+{
+ mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
+
+ /* clear spm2mcupm wakeup interrupt status */
+ mmio_write_32(SPM2CPUEB_CON, 0);
+}
+
+void __spm_clean_before_wfi(void)
+{
+}
+
+void __spm_hw_s1_state_monitor(int en, unsigned int *status)
+{
+ unsigned int reg;
+
+ if (en != 0) {
+ mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_CLR_ALL,
+ SPM_ACK_CHK_3_CON_EN);
+ } else {
+ reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+
+ if ((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) {
+ if (status != NULL) {
+ *status |= SPM_INTERNAL_STATUS_HW_S1;
+ }
+ }
+
+ mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
+ (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL));
+ }
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
new file mode 100644
index 0000000..c719caf
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
@@ -0,0 +1,668 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_INTERNAL_H
+#define MT_SPM_INTERNAL_H
+
+#include <mt_spm.h>
+
+/* PCM_WDT_VAL */
+#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
+/* PCM_TIMER_VAL */
+#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
+
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0 BIT(0)
+#define PCM_PWRIO_EN_R7 BIT(7)
+#define PCM_RF_SYNC_R0 BIT(16)
+#define PCM_RF_SYNC_R6 BIT(22)
+#define PCM_RF_SYNC_R7 BIT(23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0 BIT(0)
+#define PCM_SW_INT1 BIT(1)
+#define PCM_SW_INT2 BIT(2)
+#define PCM_SW_INT3 BIT(3)
+#define PCM_SW_INT4 BIT(4)
+#define PCM_SW_INT5 BIT(5)
+#define PCM_SW_INT6 BIT(6)
+#define PCM_SW_INT7 BIT(7)
+#define PCM_SW_INT8 BIT(8)
+#define PCM_SW_INT9 BIT(9)
+#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+ PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+ PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+ PCM_SW_INT0)
+
+/* SPM_AP_STANDBY_CON */
+#define WFI_OP_AND (1U)
+#define WFI_OP_OR (0U)
+
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM BIT(2)
+#define ISRM_PCM_RETURN BIT(3)
+#define ISRM_RET_IRQ0 BIT(8)
+#define ISRM_RET_IRQ1 BIT(9)
+#define ISRM_RET_IRQ2 BIT(10)
+#define ISRM_RET_IRQ3 BIT(11)
+#define ISRM_RET_IRQ4 BIT(12)
+#define ISRM_RET_IRQ5 BIT(13)
+#define ISRM_RET_IRQ6 BIT(14)
+#define ISRM_RET_IRQ7 BIT(15)
+#define ISRM_RET_IRQ8 BIT(16)
+#define ISRM_RET_IRQ9 BIT(17)
+#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
+ (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
+ (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
+ (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
+ (ISRM_RET_IRQ1))
+#define ISRM_ALL_EXC_TWAM ISRM_RET_IRQ_AUX
+#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM BIT(2)
+#define ISRS_PCM_RETURN BIT(3)
+#define ISRC_TWAM ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
+#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP (0x3FF)
+#define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB
+#define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
+#define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB
+#define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
+#define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB
+#define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB
+
+/* MD32PCM ADDR for SPM code fetch */
+#define MD32PCM_BASE (SPM_BASE + 0x0A00)
+#define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000)
+#define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200)
+#define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204)
+#define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208)
+#define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C)
+#define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210)
+#define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214)
+#define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218)
+#define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224)
+#define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C)
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
+ SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
+ SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
+ SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
+ SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+#define MCUPM_MBOX_WAKEUP_CPU (0x0C55FD10)
+
+struct pcm_desc {
+ const char *version; /* PCM code version */
+ uint32_t *base; /* binary array base */
+ uintptr_t base_dma; /* dma addr of base */
+ uint32_t pmem_words;
+ uint32_t total_words;
+ uint32_t pmem_start;
+ uint32_t dmem_start;
+};
+
+struct pwr_ctrl {
+ /* for SPM */
+ uint32_t pcm_flags;
+ /* can override pcm_flags */
+ uint32_t pcm_flags_cust;
+ /* set bit of pcm_flags, after pcm_flags_cust */
+ uint32_t pcm_flags_cust_set;
+ /* clr bit of pcm_flags, after pcm_flags_cust */
+ uint32_t pcm_flags_cust_clr;
+ uint32_t pcm_flags1;
+ /* can override pcm_flags1 */
+ uint32_t pcm_flags1_cust;
+ /* set bit of pcm_flags1, after pcm_flags1_cust */
+ uint32_t pcm_flags1_cust_set;
+ /* clr bit of pcm_flags1, after pcm_flags1_cust */
+ uint32_t pcm_flags1_cust_clr;
+ /* @ 1T 32K */
+ uint32_t timer_val;
+ /* @ 1T 32K, can override timer_val */
+ uint32_t timer_val_cust;
+ /* stress for dpidle */
+ uint32_t timer_val_ramp_en;
+ /* stress for suspend */
+ uint32_t timer_val_ramp_en_sec;
+ uint32_t wake_src;
+ /* can override wake_src */
+ uint32_t wake_src_cust;
+ /* disable wdt in suspend */
+ uint8_t wdt_disable;
+
+ /* SPM_AP_STANDBY_CON */
+ /* [0] */
+ uint8_t reg_wfi_op;
+ /* [1] */
+ uint8_t reg_wfi_type;
+ /* [2] */
+ uint8_t reg_mp0_cputop_idle_mask;
+ /* [3] */
+ uint8_t reg_mp1_cputop_idle_mask;
+ /* [4] */
+ uint8_t reg_mcusys_idle_mask;
+ /* [25] */
+ uint8_t reg_md_apsrc_1_sel;
+ /* [26] */
+ uint8_t reg_md_apsrc_0_sel;
+ /* [29] */
+ uint8_t reg_conn_apsrc_sel;
+
+ /* SPM_SRC_REQ */
+ /* [0] */
+ uint8_t reg_spm_apsrc_req;
+ /* [1] */
+ uint8_t reg_spm_f26m_req;
+ /* [3] */
+ uint8_t reg_spm_infra_req;
+ /* [4] */
+ uint8_t reg_spm_vrf18_req;
+ /* [7] */
+ uint8_t reg_spm_ddr_en_req;
+ /* [8] */
+ uint8_t reg_spm_dvfs_req;
+ /* [9] */
+ uint8_t reg_spm_sw_mailbox_req;
+ /* [10] */
+ uint8_t reg_spm_sspm_mailbox_req;
+ /* [11] */
+ uint8_t reg_spm_adsp_mailbox_req;
+ /* [12] */
+ uint8_t reg_spm_scp_mailbox_req;
+
+ /* SPM_SRC_MASK */
+ /* [0] */
+ uint8_t reg_sspm_srcclkena_0_mask_b;
+ /* [1] */
+ uint8_t reg_sspm_infra_req_0_mask_b;
+ /* [2] */
+ uint8_t reg_sspm_apsrc_req_0_mask_b;
+ /* [3] */
+ uint8_t reg_sspm_vrf18_req_0_mask_b;
+ /* [4] */
+ uint8_t reg_sspm_ddr_en_0_mask_b;
+ /* [5] */
+ uint8_t reg_scp_srcclkena_mask_b;
+ /* [6] */
+ uint8_t reg_scp_infra_req_mask_b;
+ /* [7] */
+ uint8_t reg_scp_apsrc_req_mask_b;
+ /* [8] */
+ uint8_t reg_scp_vrf18_req_mask_b;
+ /* [9] */
+ uint8_t reg_scp_ddr_en_mask_b;
+ /* [10] */
+ uint8_t reg_audio_dsp_srcclkena_mask_b;
+ /* [11] */
+ uint8_t reg_audio_dsp_infra_req_mask_b;
+ /* [12] */
+ uint8_t reg_audio_dsp_apsrc_req_mask_b;
+ /* [13] */
+ uint8_t reg_audio_dsp_vrf18_req_mask_b;
+ /* [14] */
+ uint8_t reg_audio_dsp_ddr_en_mask_b;
+ /* [15] */
+ uint8_t reg_apu_srcclkena_mask_b;
+ /* [16] */
+ uint8_t reg_apu_infra_req_mask_b;
+ /* [17] */
+ uint8_t reg_apu_apsrc_req_mask_b;
+ /* [18] */
+ uint8_t reg_apu_vrf18_req_mask_b;
+ /* [19] */
+ uint8_t reg_apu_ddr_en_mask_b;
+ /* [20] */
+ uint8_t reg_cpueb_srcclkena_mask_b;
+ /* [21] */
+ uint8_t reg_cpueb_infra_req_mask_b;
+ /* [22] */
+ uint8_t reg_cpueb_apsrc_req_mask_b;
+ /* [23] */
+ uint8_t reg_cpueb_vrf18_req_mask_b;
+ /* [24] */
+ uint8_t reg_cpueb_ddr_en_mask_b;
+ /* [25] */
+ uint8_t reg_bak_psri_srcclkena_mask_b;
+ /* [26] */
+ uint8_t reg_bak_psri_infra_req_mask_b;
+ /* [27] */
+ uint8_t reg_bak_psri_apsrc_req_mask_b;
+ /* [28] */
+ uint8_t reg_bak_psri_vrf18_req_mask_b;
+ /* [29] */
+ uint8_t reg_bak_psri_ddr_en_mask_b;
+ /* [30] */
+ uint8_t reg_cam_ddren_req_mask_b;
+ /* [31] */
+ uint8_t reg_img_ddren_req_mask_b;
+
+ /* SPM_SRC2_MASK */
+ /* [0] */
+ uint8_t reg_msdc0_srcclkena_mask_b;
+ /* [1] */
+ uint8_t reg_msdc0_infra_req_mask_b;
+ /* [2] */
+ uint8_t reg_msdc0_apsrc_req_mask_b;
+ /* [3] */
+ uint8_t reg_msdc0_vrf18_req_mask_b;
+ /* [4] */
+ uint8_t reg_msdc0_ddr_en_mask_b;
+ /* [5] */
+ uint8_t reg_msdc1_srcclkena_mask_b;
+ /* [6] */
+ uint8_t reg_msdc1_infra_req_mask_b;
+ /* [7] */
+ uint8_t reg_msdc1_apsrc_req_mask_b;
+ /* [8] */
+ uint8_t reg_msdc1_vrf18_req_mask_b;
+ /* [9] */
+ uint8_t reg_msdc1_ddr_en_mask_b;
+ /* [10] */
+ uint8_t reg_msdc2_srcclkena_mask_b;
+ /* [11] */
+ uint8_t reg_msdc2_infra_req_mask_b;
+ /* [12] */
+ uint8_t reg_msdc2_apsrc_req_mask_b;
+ /* [13] */
+ uint8_t reg_msdc2_vrf18_req_mask_b;
+ /* [14] */
+ uint8_t reg_msdc2_ddr_en_mask_b;
+ /* [15] */
+ uint8_t reg_ufs_srcclkena_mask_b;
+ /* [16] */
+ uint8_t reg_ufs_infra_req_mask_b;
+ /* [17] */
+ uint8_t reg_ufs_apsrc_req_mask_b;
+ /* [18] */
+ uint8_t reg_ufs_vrf18_req_mask_b;
+ /* [19] */
+ uint8_t reg_ufs_ddr_en_mask_b;
+ /* [20] */
+ uint8_t reg_usb_srcclkena_mask_b;
+ /* [21] */
+ uint8_t reg_usb_infra_req_mask_b;
+ /* [22] */
+ uint8_t reg_usb_apsrc_req_mask_b;
+ /* [23] */
+ uint8_t reg_usb_vrf18_req_mask_b;
+ /* [24] */
+ uint8_t reg_usb_ddr_en_mask_b;
+ /* [25] */
+ uint8_t reg_pextp_p0_srcclkena_mask_b;
+ /* [26] */
+ uint8_t reg_pextp_p0_infra_req_mask_b;
+ /* [27] */
+ uint8_t reg_pextp_p0_apsrc_req_mask_b;
+ /* [28] */
+ uint8_t reg_pextp_p0_vrf18_req_mask_b;
+ /* [29] */
+ uint8_t reg_pextp_p0_ddr_en_mask_b;
+
+ /* SPM_SRC3_MASK */
+ /* [0] */
+ uint8_t reg_pextp_p1_srcclkena_mask_b;
+ /* [1] */
+ uint8_t reg_pextp_p1_infra_req_mask_b;
+ /* [2] */
+ uint8_t reg_pextp_p1_apsrc_req_mask_b;
+ /* [3] */
+ uint8_t reg_pextp_p1_vrf18_req_mask_b;
+ /* [4] */
+ uint8_t reg_pextp_p1_ddr_en_mask_b;
+ /* [5] */
+ uint8_t reg_gce0_infra_req_mask_b;
+ /* [6] */
+ uint8_t reg_gce0_apsrc_req_mask_b;
+ /* [7] */
+ uint8_t reg_gce0_vrf18_req_mask_b;
+ /* [8] */
+ uint8_t reg_gce0_ddr_en_mask_b;
+ /* [9] */
+ uint8_t reg_gce1_infra_req_mask_b;
+ /* [10] */
+ uint8_t reg_gce1_apsrc_req_mask_b;
+ /* [11] */
+ uint8_t reg_gce1_vrf18_req_mask_b;
+ /* [12] */
+ uint8_t reg_gce1_ddr_en_mask_b;
+ /* [13] */
+ uint8_t reg_spm_srcclkena_reserved_mask_b;
+ /* [14] */
+ uint8_t reg_spm_infra_req_reserved_mask_b;
+ /* [15] */
+ uint8_t reg_spm_apsrc_req_reserved_mask_b;
+ /* [16] */
+ uint8_t reg_spm_vrf18_req_reserved_mask_b;
+ /* [17] */
+ uint8_t reg_spm_ddr_en_reserved_mask_b;
+ /* [18] */
+ uint8_t reg_disp0_apsrc_req_mask_b;
+ /* [19] */
+ uint8_t reg_disp0_ddr_en_mask_b;
+ /* [20] */
+ uint8_t reg_disp1_apsrc_req_mask_b;
+ /* [21] */
+ uint8_t reg_disp1_ddr_en_mask_b;
+ /* [22] */
+ uint8_t reg_disp2_apsrc_req_mask_b;
+ /* [23] */
+ uint8_t reg_disp2_ddr_en_mask_b;
+ /* [24] */
+ uint8_t reg_disp3_apsrc_req_mask_b;
+ /* [25] */
+ uint8_t reg_disp3_ddr_en_mask_b;
+ /* [26] */
+ uint8_t reg_infrasys_apsrc_req_mask_b;
+ /* [27] */
+ uint8_t reg_infrasys_ddr_en_mask_b;
+ /* [28] */
+ uint8_t reg_cg_check_srcclkena_mask_b;
+ /* [29] */
+ uint8_t reg_cg_check_apsrc_req_mask_b;
+ /* [30] */
+ uint8_t reg_cg_check_vrf18_req_mask_b;
+ /* [31] */
+ uint8_t reg_cg_check_ddr_en_mask_b;
+
+ /* SPM_SRC4_MASK */
+ /* [8:0] */
+ uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+ /* [17:9] */
+ uint32_t reg_mcusys_merge_ddr_en_mask_b;
+ /* [19:18] */
+ uint8_t reg_dramc_md32_infra_req_mask_b;
+ /* [21:20] */
+ uint8_t reg_dramc_md32_vrf18_req_mask_b;
+ /* [23:22] */
+ uint8_t reg_dramc_md32_ddr_en_mask_b;
+ /* [24] */
+ uint8_t reg_dvfsrc_event_trigger_mask_b;
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ /* [3:0] */
+ uint8_t reg_sc_sw2spm_wakeup_mask_b;
+ /* [4] */
+ uint8_t reg_sc_adsp2spm_wakeup_mask_b;
+ /* [8:5] */
+ uint8_t reg_sc_sspm2spm_wakeup_mask_b;
+ /* [9] */
+ uint8_t reg_sc_scp2spm_wakeup_mask_b;
+ /* [10] */
+ uint8_t reg_csyspwrup_ack_mask;
+ /* [11] */
+ uint8_t reg_csyspwrup_req_mask;
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ /* [31:0] */
+ uint32_t reg_wakeup_event_mask;
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ /* [31:0] */
+ uint32_t reg_ext_wakeup_event_mask;
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+ PW_PCM_FLAGS,
+ PW_PCM_FLAGS_CUST,
+ PW_PCM_FLAGS_CUST_SET,
+ PW_PCM_FLAGS_CUST_CLR,
+ PW_PCM_FLAGS1,
+ PW_PCM_FLAGS1_CUST,
+ PW_PCM_FLAGS1_CUST_SET,
+ PW_PCM_FLAGS1_CUST_CLR,
+ PW_TIMER_VAL,
+ PW_TIMER_VAL_CUST,
+ PW_TIMER_VAL_RAMP_EN,
+ PW_TIMER_VAL_RAMP_EN_SEC,
+ PW_WAKE_SRC,
+ PW_WAKE_SRC_CUST,
+ PW_WDT_DISABLE,
+
+ /* SPM_AP_STANDBY_CON */
+ PW_REG_WFI_OP,
+ PW_REG_WFI_TYPE,
+ PW_REG_MP0_CPUTOP_IDLE_MASK,
+ PW_REG_MP1_CPUTOP_IDLE_MASK,
+ PW_REG_MCUSYS_IDLE_MASK,
+ PW_REG_MD_APSRC_1_SEL,
+ PW_REG_MD_APSRC_0_SEL,
+ PW_REG_CONN_APSRC_SEL,
+
+ /* SPM_SRC_REQ */
+ PW_REG_SPM_APSRC_REQ,
+ PW_REG_SPM_F26M_REQ,
+ PW_REG_SPM_INFRA_REQ,
+ PW_REG_SPM_VRF18_REQ,
+ PW_REG_SPM_DDR_EN_REQ,
+ PW_REG_SPM_DVFS_REQ,
+ PW_REG_SPM_SW_MAILBOX_REQ,
+ PW_REG_SPM_SSPM_MAILBOX_REQ,
+ PW_REG_SPM_ADSP_MAILBOX_REQ,
+ PW_REG_SPM_SCP_MAILBOX_REQ,
+
+ /* SPM_SRC_MASK */
+ PW_REG_SSPM_SRCCLKENA_0_MASK_B,
+ PW_REG_SSPM_INFRA_REQ_0_MASK_B,
+ PW_REG_SSPM_APSRC_REQ_0_MASK_B,
+ PW_REG_SSPM_VRF18_REQ_0_MASK_B,
+ PW_REG_SSPM_DDR_EN_0_MASK_B,
+ PW_REG_SCP_SRCCLKENA_MASK_B,
+ PW_REG_SCP_INFRA_REQ_MASK_B,
+ PW_REG_SCP_APSRC_REQ_MASK_B,
+ PW_REG_SCP_VRF18_REQ_MASK_B,
+ PW_REG_SCP_DDR_EN_MASK_B,
+ PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+ PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
+ PW_REG_APU_SRCCLKENA_MASK_B,
+ PW_REG_APU_INFRA_REQ_MASK_B,
+ PW_REG_APU_APSRC_REQ_MASK_B,
+ PW_REG_APU_VRF18_REQ_MASK_B,
+ PW_REG_APU_DDR_EN_MASK_B,
+ PW_REG_CPUEB_SRCCLKENA_MASK_B,
+ PW_REG_CPUEB_INFRA_REQ_MASK_B,
+ PW_REG_CPUEB_APSRC_REQ_MASK_B,
+ PW_REG_CPUEB_VRF18_REQ_MASK_B,
+ PW_REG_CPUEB_DDR_EN_MASK_B,
+ PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+ PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+ PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+ PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+ PW_REG_BAK_PSRI_DDR_EN_MASK_B,
+ PW_REG_CAM_DDREN_REQ_MASK_B,
+ PW_REG_IMG_DDREN_REQ_MASK_B,
+
+ /* SPM_SRC2_MASK */
+ PW_REG_MSDC0_SRCCLKENA_MASK_B,
+ PW_REG_MSDC0_INFRA_REQ_MASK_B,
+ PW_REG_MSDC0_APSRC_REQ_MASK_B,
+ PW_REG_MSDC0_VRF18_REQ_MASK_B,
+ PW_REG_MSDC0_DDR_EN_MASK_B,
+ PW_REG_MSDC1_SRCCLKENA_MASK_B,
+ PW_REG_MSDC1_INFRA_REQ_MASK_B,
+ PW_REG_MSDC1_APSRC_REQ_MASK_B,
+ PW_REG_MSDC1_VRF18_REQ_MASK_B,
+ PW_REG_MSDC1_DDR_EN_MASK_B,
+ PW_REG_MSDC2_SRCCLKENA_MASK_B,
+ PW_REG_MSDC2_INFRA_REQ_MASK_B,
+ PW_REG_MSDC2_APSRC_REQ_MASK_B,
+ PW_REG_MSDC2_VRF18_REQ_MASK_B,
+ PW_REG_MSDC2_DDR_EN_MASK_B,
+ PW_REG_UFS_SRCCLKENA_MASK_B,
+ PW_REG_UFS_INFRA_REQ_MASK_B,
+ PW_REG_UFS_APSRC_REQ_MASK_B,
+ PW_REG_UFS_VRF18_REQ_MASK_B,
+ PW_REG_UFS_DDR_EN_MASK_B,
+ PW_REG_USB_SRCCLKENA_MASK_B,
+ PW_REG_USB_INFRA_REQ_MASK_B,
+ PW_REG_USB_APSRC_REQ_MASK_B,
+ PW_REG_USB_VRF18_REQ_MASK_B,
+ PW_REG_USB_DDR_EN_MASK_B,
+ PW_REG_PEXTP_P0_SRCCLKENA_MASK_B,
+ PW_REG_PEXTP_P0_INFRA_REQ_MASK_B,
+ PW_REG_PEXTP_P0_APSRC_REQ_MASK_B,
+ PW_REG_PEXTP_P0_VRF18_REQ_MASK_B,
+ PW_REG_PEXTP_P0_DDR_EN_MASK_B,
+
+ /* SPM_SRC3_MASK */
+ PW_REG_PEXTP_P1_SRCCLKENA_MASK_B,
+ PW_REG_PEXTP_P1_INFRA_REQ_MASK_B,
+ PW_REG_PEXTP_P1_APSRC_REQ_MASK_B,
+ PW_REG_PEXTP_P1_VRF18_REQ_MASK_B,
+ PW_REG_PEXTP_P1_DDR_EN_MASK_B,
+ PW_REG_GCE0_INFRA_REQ_MASK_B,
+ PW_REG_GCE0_APSRC_REQ_MASK_B,
+ PW_REG_GCE0_VRF18_REQ_MASK_B,
+ PW_REG_GCE0_DDR_EN_MASK_B,
+ PW_REG_GCE1_INFRA_REQ_MASK_B,
+ PW_REG_GCE1_APSRC_REQ_MASK_B,
+ PW_REG_GCE1_VRF18_REQ_MASK_B,
+ PW_REG_GCE1_DDR_EN_MASK_B,
+ PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
+ PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
+ PW_REG_DISP0_APSRC_REQ_MASK_B,
+ PW_REG_DISP0_DDR_EN_MASK_B,
+ PW_REG_DISP1_APSRC_REQ_MASK_B,
+ PW_REG_DISP1_DDR_EN_MASK_B,
+ PW_REG_DISP2_APSRC_REQ_MASK_B,
+ PW_REG_DISP2_DDR_EN_MASK_B,
+ PW_REG_DISP3_APSRC_REQ_MASK_B,
+ PW_REG_DISP3_DDR_EN_MASK_B,
+ PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+ PW_REG_INFRASYS_DDR_EN_MASK_B,
+ PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+ PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+ PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+ PW_REG_CG_CHECK_DDR_EN_MASK_B,
+
+ /* SPM_SRC4_MASK */
+ PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+ PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
+ PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
+ PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
+ PW_REG_DRAMC_MD32_DDR_EN_MASK_B,
+ PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ PW_REG_SC_SW2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
+ PW_REG_CSYSPWRUP_ACK_MASK,
+ PW_REG_CSYSPWRUP_REQ_MASK,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ PW_REG_WAKEUP_EVENT_MASK,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ PW_REG_EXT_WAKEUP_EVENT_MASK,
+ PW_MAX_COUNT,
+};
+
+/* spm_internal.c internal status */
+#define SPM_INTERNAL_STATUS_HW_S1 BIT(0)
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG (0x800)
+/* BIT[0]: SW_EN, BIT[4]: STA_EN, BIT[8]: HW_EN */
+#define SPM_ACK_CHK_3_CON_EN (0x110)
+#define SPM_ACK_CHK_3_CON_CLR_ALL (0x2)
+/* BIT[15]: RESULT */
+#define SPM_ACK_CHK_3_CON_RESULT (0x8000)
+
+struct wake_status_trace_comm {
+ uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
+ uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
+ uint32_t timer_out; /* SPM_SW_RSV_6*/
+ uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
+ uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */
+ uint32_t r12; /* SPM_SW_RSV_0 */
+ uint32_t r13; /* PCM_REG13_DATA */
+ uint32_t req_sta0; /* SRC_REQ_STA_0 */
+ uint32_t req_sta1; /* SRC_REQ_STA_1 */
+ uint32_t req_sta2; /* SRC_REQ_STA_2 */
+ uint32_t req_sta3; /* SRC_REQ_STA_3 */
+ uint32_t req_sta4; /* SRC_REQ_STA_4 */
+ uint32_t raw_sta; /* SPM_WAKEUP_STA */
+ uint32_t times_h; /* timestamp high bits */
+ uint32_t times_l; /* timestamp low bits */
+ uint32_t resumetime; /* timestamp low bits */
+};
+
+struct wake_status_trace {
+ struct wake_status_trace_comm comm;
+};
+
+struct wake_status {
+ struct wake_status_trace tr;
+ uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */
+ uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */
+ uint32_t md32pcm_wakeup_sta; /* MD32PCM_WAKEUP_STA */
+ uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
+ uint32_t wake_misc; /* SPM_SW_RSV_5 */
+ uint32_t idle_sta; /* SUBSYS_IDLE_STA */
+ uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
+ uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
+ uint32_t isr; /* SPM_IRQ_STA */
+ uint32_t log_index;
+ uint32_t is_abort;
+};
+
+struct spm_lp_scen {
+ struct pcm_desc *pcmdesc;
+ struct pwr_ctrl *pwrctrl;
+};
+
+void __spm_set_cpu_status(unsigned int cpu);
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, unsigned int resource_usage);
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
+void __spm_send_cpu_wakeup_event(void);
+void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_status);
+void __spm_clean_after_wakeup(void);
+wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta);
+void __spm_set_pcm_wdt(int en);
+void __spm_ext_int_wakeup_req_clr(void);
+void __spm_hw_s1_state_monitor(int en, unsigned int *status);
+
+static inline void spm_hw_s1_state_monitor_resume(void)
+{
+ __spm_hw_s1_state_monitor(1, NULL);
+}
+
+static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
+{
+ __spm_hw_s1_state_monitor(0, status);
+}
+
+void __spm_clean_before_wfi(void);
+
+#endif /* MT_SPM_INTERNAL */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.c
new file mode 100644
index 0000000..97dedf9
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+
+#include <lib/pm/mtk_pm.h>
+#include "mt_spm.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_pmic_wrap.h"
+#include "mt_spm_reg.h"
+#include <platform_def.h>
+
+/* BIT operation */
+#define _BITS_(h, l, v) ((GENMASK(h, l) & ((v) << (l))))
+
+/* PMIC_WRAP */
+#define VCORE_BASE_UV (40000) /* PMIC MT6359 */
+#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
+
+#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
+#define SPM_DATA_SHIFT (16)
+
+#define BUCK_VGPU11_ELR0 (0x15B4)
+#define TOP_SPI_CON0 (0x0456)
+#define BUCK_TOP_CON1 (0x1443) /* PMIC MT6315 */
+#define TOP_CON (0x0013) /* PMIC MT6315 */
+#define TOP_DIG_WPK (0x03a9)
+#define TOP_CON_LOCK (0x03a8)
+#define TOP_CLK_CON0 (0x0134) /* PMIC MT6359*/
+
+struct pmic_wrap_cmd {
+ uint32_t cmd_addr;
+ uint32_t cmd_wdata;
+};
+
+struct pmic_wrap_setting {
+ enum pmic_wrap_phase_id phase;
+ struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
+ struct {
+ struct {
+ uint32_t cmd_addr;
+ uint32_t cmd_wdata;
+ } _[NR_PMIC_WRAP_CMD];
+ const int nr_idx;
+ } set[NR_PMIC_WRAP_PHASE];
+};
+
+static struct pmic_wrap_setting pw = {
+ .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
+ .addr = {{0, 0} },
+ .set[PMIC_WRAP_PHASE_ALLINONE] = {
+ ._[CMD_0] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(75000)),},
+ ._[CMD_1] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(65000)),},
+ ._[CMD_2] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(60000)),},
+ ._[CMD_3] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(55000)),},
+ ._[CMD_4] = {TOP_SPI_CON0, _BITS_(0, 0, 1),},
+ ._[CMD_5] = {TOP_SPI_CON0, _BITS_(0, 0, 0),},
+ ._[CMD_6] = {BUCK_TOP_CON1, 0x0,}, /* MT6315-3: VMD NO LP */
+ ._[CMD_7] = {BUCK_TOP_CON1, 0xF,}, /* MT6315-3: VMD LP */
+ ._[CMD_8] = {TOP_CON, 0x3,}, /* MT6315-3: PMIC NO LP */
+ ._[CMD_9] = {TOP_CON, 0x0,}, /* MT6315-3: PMIC LP */
+ ._[CMD_10] = {TOP_DIG_WPK, 0x63,}, /* MT6315-2: PMIC_CON_DIG_WPK */
+ ._[CMD_11] = {TOP_CON_LOCK, 0x15,}, /* MT6315-2: PMIC_CON_UNLOCK */
+ ._[CMD_12] = {TOP_DIG_WPK, 0x0,}, /* MT6315-2: PMIC_CON_DIG_WPK */
+ ._[CMD_13] = {TOP_CON_LOCK, 0x0,}, /* MT6315-2: PMIC_CON_LOCK */
+ ._[CMD_14] = {TOP_CLK_CON0, 0x0040,}, /* MT6359: 6359_LDO_SW_SEL_H */
+ ._[CMD_15] = {TOP_CLK_CON0, 0x0000,}, /* MT6359: 6359_LDO_SW_SEL_L */
+ .nr_idx = NR_IDX_ALL,
+ },
+};
+
+void _mt_spm_pmic_table_init(void)
+{
+ struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
+ { (uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0, },
+ { (uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1, },
+ { (uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2, },
+ { (uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3, },
+ { (uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4, },
+ { (uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5, },
+ { (uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6, },
+ { (uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7, },
+ { (uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8, },
+ { (uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9, },
+ { (uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10, },
+ { (uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11, },
+ { (uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12, },
+ { (uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13, },
+ { (uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14, },
+ { (uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15, },
+ };
+
+ memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
+}
+
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
+{
+ int idx;
+
+ if ((phase >= NR_PMIC_WRAP_PHASE) || (pw.phase == phase)) {
+ return;
+ }
+
+ if (pw.addr[0].cmd_addr == 0) {
+ _mt_spm_pmic_table_init();
+ }
+
+ pw.phase = phase;
+
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+ for (idx = 0; idx < pw.set[phase].nr_idx; idx++) {
+ mmio_write_32(pw.addr[idx].cmd_addr,
+ (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) |
+ (pw.set[phase]._[idx].cmd_wdata));
+ }
+}
+
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx,
+ unsigned int cmd_wdata)
+{
+ /* just set wdata value */
+ if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) {
+ return;
+ }
+
+ pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
+
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+ if (pw.phase == phase) {
+ mmio_write_32(pw.addr[idx].cmd_addr,
+ (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | cmd_wdata);
+ }
+}
+
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx)
+{
+ /* just get wdata value */
+ if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) {
+ return 0;
+ }
+
+ return pw.set[phase]._[idx].cmd_wdata;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.h
new file mode 100644
index 0000000..3043d36
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+
+#ifndef MT_SPM_PMIC_WRAP_H
+#define MT_SPM_PMIC_WRAP_H
+
+enum pmic_wrap_phase_id {
+ PMIC_WRAP_PHASE_ALLINONE = 0,
+ NR_PMIC_WRAP_PHASE,
+};
+
+/* IDX mapping */
+enum {
+ CMD_0 = 0, /* PMIC_WRAP_PHASE_ALLINONE */
+ CMD_1,
+ CMD_2,
+ CMD_3,
+ CMD_4,
+ CMD_5,
+ CMD_6,
+ CMD_7,
+ CMD_8,
+ CMD_9,
+ CMD_10,
+ CMD_11,
+ CMD_12,
+ CMD_13,
+ CMD_14,
+ CMD_15,
+ NR_IDX_ALL,
+};
+
+/* APIs */
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx,
+ unsigned int cmd_wdata);
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx);
+void mt_spm_dump_pmic_warp_reg(void);
+
+#endif /* MT_SPM_PMIC_WRAP_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_reg.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_reg.h
new file mode 100644
index 0000000..2c29f75
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_reg.h
@@ -0,0 +1,2249 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ ****************************************************************/
+
+#ifndef MT_SPM_REG_H
+#define MT_SPM_REG_H
+
+#include "pcm_def.h"
+#include "sleep_def.h"
+#include <spm_reg.h>
+
+/* Define and Declare */
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB (1U << 0) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */
+#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */
+#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */
+#define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */
+#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */
+#define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */
+#define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */
+#define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */
+#define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */
+#define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */
+#define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */
+#define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */
+#define SCP_DCM_EN_LSB (1U << 15) /* 1b */
+#define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */
+#define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */
+/* SPM_CLK_SETTLE (0x10006000+0x010) */
+#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */
+/* SPM_AP_STANDBY_CON (0x10006000+0x014) */
+#define REG_WFI_OP_LSB (1U << 0) /* 1b */
+#define REG_WFI_TYPE_LSB (1U << 1) /* 1b */
+#define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */
+#define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */
+#define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */
+#define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */
+#define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_CK_EN_LSB (1U << 2) /* 1b */
+#define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */
+#define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */
+#define PCM_SW_RESET_LSB (1U << 15) /* 1b */
+#define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* PCM_CON1 (0x10006000+0x01C) */
+#define RG_IM_SLAVE_LSB (1U << 0) /* 1b */
+#define RG_IM_SLEEP_LSB (1U << 1) /* 1b */
+#define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */
+#define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */
+#define RG_IM_PDN_LSB (1U << 4) /* 1b */
+#define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */
+#define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */
+#define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */
+#define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */
+#define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */
+#define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */
+#define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */
+#define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */
+#define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL2 (0x10006000+0x020) */
+#define POWER_ON_VAL2_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL3 (0x10006000+0x024) */
+#define POWER_ON_VAL3_LSB (1U << 0) /* 32b */
+/* PCM_REG_DATA_INI (0x10006000+0x028) */
+#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */
+/* PCM_PWR_IO_EN (0x10006000+0x02C) */
+#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */
+#define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */
+/* PCM_TIMER_VAL (0x10006000+0x030) */
+#define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */
+/* PCM_WDT_VAL (0x10006000+0x034) */
+#define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */
+/* SPM_SW_RST_CON (0x10006000+0x040) */
+#define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_SW_RST_CON_SET (0x10006000+0x044) */
+#define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_SW_RST_CON_CLR (0x10006000+0x048) */
+#define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* VS1_PSR_MASK_B (0x10006000+0x04C) */
+#define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
+#define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
+/* VS2_PSR_MASK_B (0x10006000+0x050) */
+#define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
+#define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
+#define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */
+/* MD32_CLK_CON (0x10006000+0x084) */
+#define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */
+#define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */
+/* SPM_SRAM_RSV_CON (0x10006000+0x088) */
+#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */
+/* SPM_SWINT (0x10006000+0x08C) */
+#define SPM_SWINT_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_SET (0x10006000+0x090) */
+#define SPM_SWINT_SET_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_CLR (0x10006000+0x094) */
+#define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */
+/* SPM_SCP_MAILBOX (0x10006000+0x098) */
+#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */
+/* SCP_SPM_MAILBOX (0x10006000+0x09C) */
+#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CON (0x10006000+0x0A0) */
+#define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */
+#define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */
+#define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */
+#define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */
+#define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */
+#define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */
+#define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */
+#define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */
+/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */
+#define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */
+#define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */
+#define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */
+#define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */
+#define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */
+/* SPM_SCP_IRQ (0x10006000+0x0AC) */
+#define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */
+#define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */
+/* SPM_IRQ_MASK (0x10006000+0x0B4) */
+#define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */
+/* DDR_EN_DBC (0x10006000+0x0B4) */
+#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 16) /* 1b */
+/* SPM_SRC_REQ (0x10006000+0x0B8) */
+#define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */
+#define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */
+#define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */
+#define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */
+#define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */
+#define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */
+#define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */
+#define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */
+#define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */
+#define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */
+/* SPM_SRC_MASK (0x10006000+0x0BC) */
+#define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC2_MASK (0x10006000+0x0C0) */
+#define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC3_MASK (0x10006000+0x0C4) */
+#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */
+#define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */
+#define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC4_MASK (0x10006000+0x0C8) */
+#define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */
+#define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */
+#define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */
+/* SPM_SRC5_MASK (0x10006000+0x0CC) */
+#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */
+#define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
+#define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */
+#define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */
+#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */
+/* SCP_CLK_CON (0x10006000+0x0DC) */
+#define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */
+#define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */
+#define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */
+#define SCP_SLP_REQ_LSB (1U << 3) /* 1b */
+#define SCP_SLP_ACK_LSB (1U << 4) /* 1b */
+/* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */
+#define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */
+#define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */
+#define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */
+#define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */
+#define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */
+#define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */
+#define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */
+#define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */
+#define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */
+#define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
+#define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */
+/* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */
+#define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */
+#define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */
+#define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */
+#define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */
+#define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */
+#define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */
+#define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */
+#define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */
+#define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */
+#define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */
+#define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */
+#define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */
+#define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
+/* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */
+#define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
+#define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */
+#define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */
+#define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */
+/* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */
+#define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
+#define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */
+#define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */
+#define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */
+/* PCM_REG0_DATA (0x10006000+0x100) */
+#define PCM_REG0_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG2_DATA (0x10006000+0x104) */
+#define PCM_REG2_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG6_DATA (0x10006000+0x108) */
+#define PCM_REG6_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG7_DATA (0x10006000+0x10C) */
+#define PCM_REG7_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG13_DATA (0x10006000+0x110) */
+#define PCM_REG13_RF_LSB (1U << 0) /* 32b */
+/* SRC_REQ_STA_0 (0x10006000+0x114) */
+#define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */
+#define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */
+#define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */
+#define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */
+#define MD_DDR_EN_0_LSB (1U << 5) /* 1b */
+#define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */
+#define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */
+#define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */
+#define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */
+#define MD_DDR_EN_1_LSB (1U << 11) /* 1b */
+#define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */
+#define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */
+#define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */
+#define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */
+#define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */
+#define CONN_DDR_EN_LSB (1U << 17) /* 1b */
+#define SRCCLKENI_LSB (1U << 18) /* 3b */
+#define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */
+#define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */
+#define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */
+#define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */
+#define MD32_DDR_EN_LSB (1U << 25) /* 1b */
+#define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */
+#define DISP0_DDR_EN_LSB (1U << 27) /* 1b */
+#define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define DISP1_DDR_EN_LSB (1U << 29) /* 1b */
+#define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */
+/* SRC_REQ_STA_1 (0x10006000+0x118) */
+#define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define SCP_DDR_EN_LSB (1U << 4) /* 1b */
+#define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */
+#define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */
+#define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */
+#define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */
+#define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */
+#define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */
+#define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */
+#define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */
+#define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */
+#define UFS_DDR_EN_LSB (1U << 14) /* 1b */
+#define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */
+#define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */
+#define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */
+#define GCE_DDR_EN_LSB (1U << 18) /* 1b */
+#define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */
+#define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */
+#define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */
+#define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */
+#define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */
+#define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */
+#define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */
+#define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */
+#define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */
+#define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */
+#define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */
+/* SRC_REQ_STA_2 (0x10006000+0x11C) */
+#define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */
+#define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */
+#define SW2SPM_INT_LSB (1U << 11) /* 4b */
+#define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */
+#define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */
+#define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */
+#define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */
+#define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */
+#define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */
+#define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */
+#define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */
+#define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */
+#define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */
+#define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */
+#define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */
+/* PCM_TIMER_OUT (0x10006000+0x120) */
+#define PCM_TIMER_LSB (1U << 0) /* 32b */
+/* PCM_WDT_OUT (0x10006000+0x124) */
+#define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */
+/* SPM_IRQ_STA (0x10006000+0x128) */
+#define TWAM_IRQ_LSB (1U << 2) /* 1b */
+#define PCM_IRQ_LSB (1U << 3) /* 1b */
+/* SRC_REQ_STA_4 (0x10006000+0x12C) */
+#define APU_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define APU_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define APU_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define APU_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define APU_DDR_EN_LSB (1U << 4) /* 1b */
+#define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */
+#define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */
+#define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */
+#define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */
+#define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */
+/* MD32PCM_WAKEUP_STA (0x10006000+0x130) */
+#define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */
+/* MD32PCM_EVENT_STA (0x10006000+0x134) */
+#define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_STA (0x10006000+0x138) */
+#define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */
+#define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */
+/* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */
+#define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_MISC (0x10006000+0x140) */
+#define GIC_WAKEUP_LSB (1U << 0) /* 10b */
+#define DVFSRC_IRQ_LSB (1U << 16) /* 1b */
+#define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */
+#define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */
+#define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */
+#define TWAM_IRQ_B_LSB (1U << 21) /* 1b */
+#define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */
+#define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */
+#define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */
+#define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */
+#define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */
+/* MM_DVFS_HALT (0x10006000+0x144) */
+#define MM_DVFS_HALT_LSB (1U << 0) /* 5b */
+/* BUS_PROTECT_RDY (0x10006000+0x150) */
+#define PROTECT_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT1_RDY (0x10006000+0x154) */
+#define PROTECT1_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT2_RDY (0x10006000+0x158) */
+#define PROTECT2_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT3_RDY (0x10006000+0x15C) */
+#define PROTECT3_READY_LSB (1U << 0) /* 32b */
+/* SUBSYS_IDLE_STA (0x10006000+0x160) */
+#define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */
+/* PCM_STA (0x10006000+0x164) */
+#define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */
+#define EXT_SRC_STA_LSB (1U << 4) /* 3b */
+/* SRC_REQ_STA_3 (0x10006000+0x168) */
+#define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */
+#define F26M_STATE_LSB (1U << 16) /* 1b */
+#define INFRA_STATE_LSB (1U << 17) /* 1b */
+#define APSRC_STATE_LSB (1U << 18) /* 1b */
+#define VRF18_STATE_LSB (1U << 19) /* 1b */
+#define DDR_EN_STATE_LSB (1U << 20) /* 1b */
+#define DVFS_STATE_LSB (1U << 21) /* 1b */
+#define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */
+#define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */
+#define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */
+#define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */
+/* PWR_STATUS (0x10006000+0x16C) */
+#define PWR_STATUS_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_2ND (0x10006000+0x170) */
+#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
+/* CPU_PWR_STATUS (0x10006000+0x174) */
+#define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */
+#define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */
+/* OTHER_PWR_STATUS (0x10006000+0x178) */
+#define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */
+/* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */
+#define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */
+#define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */
+#define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */
+#define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */
+#define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* MD32PCM_STA (0x10006000+0x190) */
+#define MD32PCM_HALT_LSB (1U << 0) /* 1b */
+#define MD32PCM_GATED_LSB (1U << 1) /* 1b */
+/* MD32PCM_PC (0x10006000+0x194) */
+#define MON_PC_LSB (1U << 0) /* 32b */
+/* DVFSRC_EVENT_STA (0x10006000+0x1A4) */
+#define DVFSRC_EVENT_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT4_RDY (0x10006000+0x1A8) */
+#define PROTECT4_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT5_RDY (0x10006000+0x1AC) */
+#define PROTECT5_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT6_RDY (0x10006000+0x1B0) */
+#define PROTECT6_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT7_RDY (0x10006000+0x1B4) */
+#define PROTECT7_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT8_RDY (0x10006000+0x1B8) */
+#define PROTECT8_READY_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */
+#define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */
+#define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */
+#define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */
+#define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */
+#define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */
+#define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */
+#define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */
+#define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */
+#define TWAM_TIMER_LSB (1U << 0) /* 32b */
+/* SPM_CG_CHECK_STA (0x10006000+0x1F4) */
+#define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */
+/* SPM_DVFS_STA (0x10006000+0x1F8) */
+#define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */
+#define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */
+#define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */
+#define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */
+/* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */
+#define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */
+#define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */
+#define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */
+#define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
+#define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */
+/* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */
+#define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */
+#define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */
+#define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
+#define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */
+#define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */
+/* SPM_CPU0_PWR_CON (0x10006000+0x208) */
+#define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */
+#define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */
+/* SPM_CPU1_PWR_CON (0x10006000+0x20C) */
+#define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */
+#define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */
+/* SPM_CPU2_PWR_CON (0x10006000+0x210) */
+#define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */
+#define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */
+/* SPM_CPU3_PWR_CON (0x10006000+0x214) */
+#define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */
+#define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */
+/* SPM_CPU4_PWR_CON (0x10006000+0x218) */
+#define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */
+#define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */
+/* SPM_CPU5_PWR_CON (0x10006000+0x21C) */
+#define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */
+#define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */
+/* SPM_CPU6_PWR_CON (0x10006000+0x220) */
+#define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */
+#define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */
+/* SPM_CPU7_PWR_CON (0x10006000+0x224) */
+#define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */
+#define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */
+/* ARMPLL_CLK_CON (0x10006000+0x22C) */
+#define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */
+#define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */
+#define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */
+#define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */
+#define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */
+#define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */
+#define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */
+#define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */
+#define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */
+#define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */
+#define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */
+#define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */
+#define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */
+#define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */
+#define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */
+#define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */
+#define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */
+#define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */
+#define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */
+#define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */
+/* MCUSYS_IDLE_STA (0x10006000+0x230) */
+#define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */
+#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */
+#define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */
+#define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */
+#define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */
+#define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */
+#define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */
+#define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */
+#define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */
+#define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */
+#define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */
+#define WFI_AF_SEL_LSB (1U << 24) /* 8b */
+/* GIC_WAKEUP_STA (0x10006000+0x234) */
+#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */
+/* CPU_SPARE_CON (0x10006000+0x238) */
+#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_SET (0x10006000+0x23C) */
+#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_CLR (0x10006000+0x240) */
+#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* ARMPLL_CLK_SEL (0x10006000+0x244) */
+#define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */
+/* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */
+#define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */
+#define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */
+#define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */
+/* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */
+#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */
+#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */
+#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */
+#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */
+#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */
+#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */
+#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */
+#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU0_WFI_EN (0x10006000+0x280) */
+#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU1_WFI_EN (0x10006000+0x284) */
+#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU2_WFI_EN (0x10006000+0x288) */
+#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU3_WFI_EN (0x10006000+0x28C) */
+#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU4_WFI_EN (0x10006000+0x290) */
+#define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU5_WFI_EN (0x10006000+0x294) */
+#define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU6_WFI_EN (0x10006000+0x298) */
+#define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU7_WFI_EN (0x10006000+0x29C) */
+#define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */
+/* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */
+#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */
+/* ROOT_CORE_ADDR (0x10006000+0x2A4) */
+#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */
+#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */
+#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */
+#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */
+#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_INT (0x10006000+0x2E0) */
+#define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_SET (0x10006000+0x2E4) */
+#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_CLR (0x10006000+0x2E8) */
+#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */
+/* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */
+#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */
+#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */
+#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */
+#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_CFG (0x10006000+0x2FC) */
+#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */
+/* MD1_PWR_CON (0x10006000+0x300) */
+#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MD1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CONN_PWR_CON (0x10006000+0x304) */
+#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CONN_PWR_ON_LSB (1U << 2) /* 1b */
+#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+/* MFG0_PWR_CON (0x10006000+0x308) */
+#define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG1_PWR_CON (0x10006000+0x30C) */
+#define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG2_PWR_CON (0x10006000+0x310) */
+#define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG2_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG3_PWR_CON (0x10006000+0x314) */
+#define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG3_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG4_PWR_CON (0x10006000+0x318) */
+#define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG4_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG5_PWR_CON (0x10006000+0x31C) */
+#define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG5_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG6_PWR_CON (0x10006000+0x320) */
+#define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG6_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IFR_PWR_CON (0x10006000+0x324) */
+#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IFR_SUB_PWR_CON (0x10006000+0x328) */
+#define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DPY_PWR_CON (0x10006000+0x32C) */
+#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ISP_PWR_CON (0x10006000+0x330) */
+#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ISP2_PWR_CON (0x10006000+0x334) */
+#define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP2_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IPE_PWR_CON (0x10006000+0x338) */
+#define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IPE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IPE_PWR_ON_LSB (1U << 2) /* 1b */
+#define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VDE_PWR_CON (0x10006000+0x33C) */
+#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VDE2_PWR_CON (0x10006000+0x340) */
+#define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE2_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VEN_PWR_CON (0x10006000+0x344) */
+#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VEN_CORE1_PWR_CON (0x10006000+0x348) */
+#define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MDP_PWR_CON (0x10006000+0x34C) */
+#define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MDP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MDP_PWR_ON_LSB (1U << 2) /* 1b */
+#define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DIS_PWR_CON (0x10006000+0x350) */
+#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DIS_PWR_ON_LSB (1U << 2) /* 1b */
+#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* AUDIO_PWR_CON (0x10006000+0x354) */
+#define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */
+#define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */
+#define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ADSP_PWR_CON (0x10006000+0x358) */
+#define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ADSP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */
+#define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+#define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */
+/* CAM_PWR_CON (0x10006000+0x35C) */
+#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWA_PWR_CON (0x10006000+0x360) */
+#define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWB_PWR_CON (0x10006000+0x364) */
+#define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWC_PWR_CON (0x10006000+0x368) */
+#define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* SYSRAM_CON (0x10006000+0x36C) */
+#define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */
+#define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */
+/* SYSROM_CON (0x10006000+0x370) */
+#define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */
+/* SSPM_SRAM_CON (0x10006000+0x374) */
+#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* SCP_SRAM_CON (0x10006000+0x378) */
+#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DPY_SHU_SRAM_CON (0x10006000+0x37C) */
+#define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */
+/* UFS_SRAM_CON (0x10006000+0x380) */
+#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */
+#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */
+/* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */
+#define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */
+#define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */
+#define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* USB_SRAM_CON (0x10006000+0x390) */
+#define USB_SRAM_PDN_LSB (1U << 0) /* 7b */
+/* DUMMY_SRAM_CON (0x10006000+0x394) */
+#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */
+#define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+/* EXT_BUCK_ISO (0x10006000+0x39C) */
+#define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+#define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */
+/* DXCC_SRAM_CON (0x10006000+0x3A0) */
+#define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* MSDC_SRAM_CON (0x10006000+0x3A4) */
+#define MSDC_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define MSDC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define MSDC_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */
+#define MSDC_SRAM_PDN_LSB (1U << 16) /* 5b */
+/* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */
+#define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */
+/* DP_TX_PWR_CON (0x10006000+0x3AC) */
+#define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */
+#define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DPMAIF_SRAM_CON (0x10006000+0x3B0) */
+#define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */
+#define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */
+/* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */
+#define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */
+#define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* MCUPM_SRAM_CON (0x10006000+0x3C0) */
+#define MCUPM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define MCUPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define MCUPM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define MCUPM_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* DPY2_PWR_CON (0x10006000+0x3C4) */
+#define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY2_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* SPM_MEM_CK_SEL (0x10006000+0x400) */
+#define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */
+#define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */
+/* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */
+#define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */
+#define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */
+#define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */
+#define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */
+#define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_EMI_BW_MODE (0x10006000+0x418) */
+#define EMI_BW_MODE_LSB (1U << 0) /* 1b */
+#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */
+#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */
+#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */
+/* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */
+#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */
+/* ULPOSC_CON (0x10006000+0x420) */
+#define ULPOSC_EN_LSB (1U << 0) /* 1b */
+#define ULPOSC_RST_LSB (1U << 1) /* 1b */
+#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */
+#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */
+/* SPM2MM_CON (0x10006000+0x424) */
+#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */
+#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */
+#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */
+#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */
+#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */
+#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */
+#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */
+#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */
+/* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */
+#define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM2MCUPM_CON (0x10006000+0x42C) */
+#define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */
+#define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */
+/* AP_MDSRC_REQ (0x10006000+0x430) */
+#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */
+#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */
+#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */
+#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */
+#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */
+#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */
+/* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */
+#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */
+/* SPM2MD_DVFS_CON (0x10006000+0x438) */
+#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */
+/* MD2SPM_DVFS_CON (0x10006000+0x43C) */
+#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */
+#define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */
+#define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */
+#define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PLL_CON (0x10006000+0x44C) */
+#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */
+#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */
+#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */
+#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */
+#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */
+#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */
+#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */
+#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */
+#define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */
+#define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */
+/* CPU_DVFS_REQ (0x10006000+0x450) */
+#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */
+#define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */
+#define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */
+/* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */
+#define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */
+#define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */
+#define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */
+#define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */
+#define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */
+#define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */
+/* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */
+#define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */
+#define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */
+#define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */
+#define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */
+#define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */
+#define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */
+#define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */
+#define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */
+/* RELAY_DVFS_LEVEL (0x10006000+0x478) */
+#define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */
+#define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */
+#define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */
+#define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */
+#define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */
+#define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */
+#define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */
+#define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */
+#define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */
+#define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */
+#define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */
+#define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */
+#define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */
+#define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */
+#define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */
+#define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */
+#define SW_DMYRD_EN_LSB (1U << 6) /* 2b */
+#define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */
+#define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */
+#define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */
+#define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */
+#define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */
+#define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */
+#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */
+#define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */
+#define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */
+#define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */
+#define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */
+#define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */
+#define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */
+#define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */
+#define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */
+#define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */
+#define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */
+#define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */
+#define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */
+#define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */
+#define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */
+#define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */
+#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */
+#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */
+#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */
+#define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */
+#define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */
+#define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */
+#define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */
+#define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */
+#define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */
+#define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */
+#define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */
+#define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */
+#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */
+#define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */
+#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */
+#define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */
+#define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */
+#define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */
+#define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */
+#define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */
+#define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */
+#define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */
+#define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */
+#define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */
+#define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */
+#define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */
+#define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */
+#define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */
+#define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */
+#define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */
+#define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */
+#define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */
+#define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */
+#define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */
+#define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */
+#define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */
+#define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */
+#define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */
+#define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */
+#define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */
+#define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */
+#define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */
+#define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */
+#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */
+/* SPM_DVFS_LEVEL (0x10006000+0x4A4) */
+#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_CIRQ_CON (0x10006000+0x4A8) */
+#define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */
+/* SPM_DVFS_MISC (0x10006000+0x4AC) */
+#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */
+#define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */
+#define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */
+#define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */
+#define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */
+#define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */
+#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */
+#define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */
+#define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */
+#define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */
+/* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */
+#define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */
+#define VS1_INIT_LSB (1U << 2) /* 1b */
+#define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */
+#define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */
+#define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */
+#define VS1_TRIGGER_LSB (1U << 9) /* 1b */
+#define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */
+#define VS2_INIT_LSB (1U << 13) /* 1b */
+#define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */
+#define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */
+#define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */
+#define VS2_TRIGGER_LSB (1U << 23) /* 1b */
+#define VS1_FORCE_LSB (1U << 24) /* 1b */
+#define VS2_FORCE_LSB (1U << 25) /* 1b */
+#define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */
+#define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */
+#define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */
+#define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */
+#define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* SPM_CG_CHECK_CON (0x10006000+0x4F0) */
+#define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */
+#define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */
+/* SPM_SRC_RDY_STA (0x10006000+0x4F4) */
+#define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */
+#define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */
+/* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */
+#define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */
+#define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */
+/* SPM_FORCE_DVFS (0x10006000+0x4FC) */
+#define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SRCLKEN_RC_CFG (0x10006000+0x500) */
+#define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG1 (0x10006000+0x504) */
+#define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG2 (0x10006000+0x508) */
+#define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */
+/* RC_CMD_ARB_CFG (0x10006000+0x50C) */
+#define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */
+/* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */
+#define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */
+/* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */
+#define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */
+/* RC_DCXO_FPM_CFG (0x10006000+0x518) */
+#define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG3 (0x10006000+0x51C) */
+#define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */
+/* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */
+#define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */
+#define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */
+#define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */
+#define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */
+#define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */
+#define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */
+#define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */
+#define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */
+#define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */
+#define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */
+#define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */
+#define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */
+#define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */
+#define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG4 (0x10006000+0x558) */
+#define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */
+/* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */
+#define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_CFG (0x10006000+0x564) */
+#define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */
+/* RC_MISC_0 (0x10006000+0x5B4) */
+#define SRCCLKENO_LSB (1U << 0) /* 2b */
+#define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */
+#define RC_VREQ_LSB (1U << 5) /* 1b */
+#define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */
+/* RC_SPM_CTRL (0x10006000+0x448) */
+#define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */
+#define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */
+#define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */
+/* SUBSYS_INTF_CFG (0x10006000+0x5BC) */
+#define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */
+#define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */
+/* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */
+#define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */
+#define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */
+#define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */
+#define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */
+#define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */
+#define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */
+#define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */
+#define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */
+#define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */
+#define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */
+#define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */
+#define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */
+#define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */
+#define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */
+#define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */
+/* SPM_SW_FLAG_0 (0x10006000+0x600) */
+#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */
+/* SPM_SW_DEBUG_0 (0x10006000+0x604) */
+#define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_FLAG_1 (0x10006000+0x608) */
+#define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_DEBUG_1 (0x10006000+0x60C) */
+#define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_0 (0x10006000+0x610) */
+#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_1 (0x10006000+0x614) */
+#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_2 (0x10006000+0x618) */
+#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_3 (0x10006000+0x61C) */
+#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_4 (0x10006000+0x620) */
+#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_5 (0x10006000+0x624) */
+#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_6 (0x10006000+0x628) */
+#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_7 (0x10006000+0x62C) */
+#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_8 (0x10006000+0x630) */
+#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */
+/* SPM_BK_WAKE_EVENT (0x10006000+0x634) */
+#define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */
+/* SPM_BK_VTCXO_DUR (0x10006000+0x638) */
+#define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */
+/* SPM_BK_WAKE_MISC (0x10006000+0x63C) */
+#define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */
+/* SPM_BK_PCM_TIMER (0x10006000+0x640) */
+#define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_0 (0x10006000+0x650) */
+#define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_1 (0x10006000+0x654) */
+#define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_0 (0x10006000+0x658) */
+#define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_1 (0x10006000+0x65C) */
+#define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON (0x10006000+0x660) */
+#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_SET (0x10006000+0x664) */
+#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_CLR (0x10006000+0x668) */
+#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */
+#define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 4) /* 4b */
+/* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */
+#define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 4) /* 4b */
+/* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */
+#define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 4) /* 4b */
+/* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */
+#define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 4) /* 4b */
+/* SCP_VCORE_LEVEL (0x10006000+0x67C) */
+#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */
+/* SC_MM_CK_SEL_CON (0x10006000+0x680) */
+#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */
+#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */
+/* SPARE_ACK_MASK (0x10006000+0x684) */
+#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_DV_CON_0 (0x10006000+0x68C) */
+#define SPM_DV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_DV_CON_1 (0x10006000+0x690) */
+#define SPM_DV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_DV_STA (0x10006000+0x694) */
+#define SPM_DV_STA_LSB (1U << 0) /* 32b */
+/* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */
+#define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */
+/* SPM_SEMA_M0 (0x10006000+0x69C) */
+#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M1 (0x10006000+0x6A0) */
+#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M2 (0x10006000+0x6A4) */
+#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M3 (0x10006000+0x6A8) */
+#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M4 (0x10006000+0x6AC) */
+#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M5 (0x10006000+0x6B0) */
+#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M6 (0x10006000+0x6B4) */
+#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M7 (0x10006000+0x6B8) */
+#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */
+/* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */
+#define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */
+/* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */
+#define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_ADSP_IRQ (0x10006000+0x6C4) */
+#define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+/* SPM_MD32_IRQ (0x10006000+0x6C8) */
+#define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */
+#define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */
+/* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */
+#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */
+#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */
+#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */
+#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */
+#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */
+#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */
+#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */
+#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* UFS_PSRI_SW (0x10006000+0x6EC) */
+#define UFS_PSRI_SW_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_SET (0x10006000+0x6F0) */
+#define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */
+#define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */
+/* SPM_AP_SEMA (0x10006000+0x6F8) */
+#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_SPM_SEMA (0x10006000+0x6FC) */
+#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_DVFS_CON (0x10006000+0x700) */
+#define SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CON_STA (0x10006000+0x704) */
+#define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */
+/* SPM_PMIC_SPMI_CON (0x10006000+0x708) */
+#define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */
+#define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */
+#define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */
+#define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */
+/* SPM_DVFS_CMD0 (0x10006000+0x710) */
+#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD1 (0x10006000+0x714) */
+#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD2 (0x10006000+0x718) */
+#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD3 (0x10006000+0x71C) */
+#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD4 (0x10006000+0x720) */
+#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD5 (0x10006000+0x724) */
+#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD6 (0x10006000+0x728) */
+#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD7 (0x10006000+0x72C) */
+#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD8 (0x10006000+0x730) */
+#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD9 (0x10006000+0x734) */
+#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD10 (0x10006000+0x738) */
+#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD11 (0x10006000+0x73C) */
+#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD12 (0x10006000+0x740) */
+#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD13 (0x10006000+0x744) */
+#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD14 (0x10006000+0x748) */
+#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD15 (0x10006000+0x74C) */
+#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD16 (0x10006000+0x750) */
+#define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD17 (0x10006000+0x754) */
+#define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD18 (0x10006000+0x758) */
+#define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD19 (0x10006000+0x75C) */
+#define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD20 (0x10006000+0x760) */
+#define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD21 (0x10006000+0x764) */
+#define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD22 (0x10006000+0x768) */
+#define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD23 (0x10006000+0x76C) */
+#define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_VALUE_L (0x10006000+0x770) */
+#define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_VALUE_H (0x10006000+0x774) */
+#define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_START_L (0x10006000+0x778) */
+#define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_START_H (0x10006000+0x77C) */
+#define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */
+#define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */
+#define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */
+#define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */
+#define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */
+#define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */
+#define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */
+#define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */
+#define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */
+#define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */
+#define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */
+#define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */
+#define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */
+#define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */
+#define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */
+#define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */
+#define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */
+#define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */
+#define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */
+#define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */
+#define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */
+#define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */
+#define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */
+#define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */
+#define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */
+#define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */
+#define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */
+#define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */
+#define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */
+#define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */
+#define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */
+#define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */
+#define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_0 (0x10006000+0x800) */
+#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_1 (0x10006000+0x804) */
+#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_2 (0x10006000+0x808) */
+#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */
+#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_4 (0x10006000+0x810) */
+#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_5 (0x10006000+0x814) */
+#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_6 (0x10006000+0x818) */
+#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */
+#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_8 (0x10006000+0x820) */
+#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_9 (0x10006000+0x824) */
+#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_10 (0x10006000+0x828) */
+#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_11 (0x10006000+0x82C) */
+#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_12 (0x10006000+0x830) */
+#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_13 (0x10006000+0x834) */
+#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_14 (0x10006000+0x838) */
+#define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_15 (0x10006000+0x83C) */
+#define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_16 (0x10006000+0x840) */
+#define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_17 (0x10006000+0x844) */
+#define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_18 (0x10006000+0x848) */
+#define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */
+#define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */
+#define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */
+#define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */
+#define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */
+#define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */
+#define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */
+#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */
+#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */
+#define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */
+#define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */
+#define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */
+#define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */
+#define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */
+#define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */
+#define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */
+#define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */
+#define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */
+#define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */
+#define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */
+#define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */
+#define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */
+#define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */
+#define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */
+#define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */
+/* SPM_COUNTER_0 (0x10006000+0x978) */
+#define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */
+/* SPM_COUNTER_1 (0x10006000+0x97C) */
+#define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */
+/* SPM_COUNTER_2 (0x10006000+0x980) */
+#define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */
+/* SYS_TIMER_CON (0x10006000+0x98C) */
+#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */
+#define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */
+#define SYS_TIMER_ID_LSB (1U << 8) /* 8b */
+#define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */
+/* RC_FSM_STA_0 (0x10006000+0xE00) */
+#define RC_FSM_STA_0_LSB (1U << 0) /* 32b */
+/* RC_CMD_STA_0 (0x10006000+0xE04) */
+#define RC_CMD_STA_0_LSB (1U << 0) /* 32b */
+/* RC_CMD_STA_1 (0x10006000+0xE08) */
+#define RC_CMD_STA_1_LSB (1U << 0) /* 32b */
+/* RC_SPI_STA_0 (0x10006000+0xE0C) */
+#define RC_SPI_STA_0_LSB (1U << 0) /* 32b */
+/* RC_PI_PO_STA_0 (0x10006000+0xE10) */
+#define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M00_REQ_STA_0 (0x10006000+0xE14) */
+#define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */
+#define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M02_REQ_STA_0 (0x10006000+0xE20) */
+#define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M03_REQ_STA_0 (0x10006000+0xE24) */
+#define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M04_REQ_STA_0 (0x10006000+0xE28) */
+#define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */
+#define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M06_REQ_STA_0 (0x10006000+0xE30) */
+#define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M07_REQ_STA_0 (0x10006000+0xE34) */
+#define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M08_REQ_STA_0 (0x10006000+0xE38) */
+#define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */
+#define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M10_REQ_STA_0 (0x10006000+0xE40) */
+#define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M11_REQ_STA_0 (0x10006000+0xE44) */
+#define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M12_REQ_STA_0 (0x10006000+0xE48) */
+#define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_STA_0 (0x10006000+0xE4C) */
+#define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */
+#define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */
+#define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */
+#define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */
+#define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */
+#define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */
+#define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */
+#define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */
+#define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */
+#define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */
+#define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */
+#define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */
+#define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */
+#define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */
+#define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */
+#define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */
+#define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */
+#define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */
+#define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */
+#define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */
+#define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */
+#define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */
+#define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */
+#define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */
+#define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */
+#define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */
+#define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */
+#define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */
+#define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */
+#define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */
+#define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */
+#define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */
+#define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_19 (0x10006000+0xED8) */
+#define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */
+#define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */
+#define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */
+#define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */
+#define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */
+#define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */
+/* PMSR_LAST_DAT (0x10006000+0xF00) */
+#define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */
+/* PMSR_LAST_CNT (0x10006000+0xF04) */
+#define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */
+#define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */
+/* PMSR_LAST_ACK (0x10006000+0xF08) */
+#define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */
+/* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */
+#define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */
+#define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */
+#define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */
+#define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */
+#define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */
+#define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */
+#define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */
+#define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */
+#define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */
+#define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */
+#define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */
+#define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */
+#define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */
+#define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */
+#define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */
+#define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */
+#define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */
+#define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */
+#define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */
+#define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */
+#define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */
+#define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */
+#define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */
+#define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */
+#define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */
+#define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */
+#define PMSR_MODE_LSB (1U << 20) /* 2b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */
+/* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */
+#define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */
+#define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */
+#define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */
+#define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */
+#define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */
+#define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */
+#define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */
+#define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */
+/* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */
+#define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */
+#define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */
+#define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */
+#define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */
+#define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */
+#define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */
+
+#define SPM_PROJECT_CODE (0xb16)
+#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
+
+#endif /* MT_SPM_REG_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.c
new file mode 100644
index 0000000..18047e6
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.c
@@ -0,0 +1,429 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
+#include <drivers/uart.h>
+#endif
+#include <lib/mmio.h>
+#ifndef MTK_PLAT_CIRQ_UNSUPPORT
+#include <mtk_cirq.h>
+#endif
+#include <constraints/mt_spm_rc_internal.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <pcm_def.h>
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+#define SPM_SUSPEND_PCM_FLAG \
+ (SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+/* Suspend spm power control */
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__ ( \
+ (R12_PCM_TIMER) | \
+ (R12_KP_IRQ_B) | \
+ (R12_APWDT_EVENT_B) | \
+ (R12_MSDC_WAKEUP_B) | \
+ (R12_EINT_EVENT_B) | \
+ (R12_SBD_INTR_WAKEUP_B) | \
+ (R12_SSPM2SPM_WAKEUP_B) | \
+ (R12_SCP2SPM_WAKEUP_B) | \
+ (R12_ADSP2SPM_WAKEUP_B) | \
+ (R12_USBX_CDSC_B) | \
+ (R12_USBX_POWERDWN_B) | \
+ (R12_SYS_TIMER_EVENT_B) | \
+ (R12_EINT_EVENT_SECURE_B) | \
+ (R12_ECE_INT_HDMI_B) | \
+ (R12_SYS_CIRQ_IRQ_B) | \
+ (R12_PCIE_WAKEUPEVENT_B) | \
+ (R12_SPM_CPU_WAKEUPEVENT_B) | \
+ (R12_APUSYS_WAKE_HOST_B))
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__ | R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl suspend_ctrl = {
+ .wake_src = WAKE_SRC_FOR_SUSPEND,
+
+ /* SPM_AP_STANDBY_CON */
+ /* [0] */
+ .reg_wfi_op = 0,
+ /* [1] */
+ .reg_wfi_type = 0,
+ /* [2] */
+ .reg_mp0_cputop_idle_mask = 0,
+ /* [3] */
+ .reg_mp1_cputop_idle_mask = 0,
+ /* [4] */
+ .reg_mcusys_idle_mask = 0,
+ /* [25] */
+ .reg_md_apsrc_1_sel = 0,
+ /* [26] */
+ .reg_md_apsrc_0_sel = 0,
+ /* [29] */
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC_REQ */
+ /* [0] */
+ .reg_spm_apsrc_req = 0,
+ /* [1] */
+ .reg_spm_f26m_req = 0,
+ /* [3] */
+ .reg_spm_infra_req = 0,
+ /* [4] */
+ .reg_spm_vrf18_req = 0,
+ /* [7] */
+ .reg_spm_ddr_en_req = 0,
+ /* [8] */
+ .reg_spm_dvfs_req = 0,
+ /* [9] */
+ .reg_spm_sw_mailbox_req = 0,
+ /* [10] */
+ .reg_spm_sspm_mailbox_req = 0,
+ /* [11] */
+ .reg_spm_adsp_mailbox_req = 0,
+ /* [12] */
+ .reg_spm_scp_mailbox_req = 0,
+
+ /* SPM_SRC_MASK */
+ /* [0] */
+ .reg_sspm_srcclkena_0_mask_b = 1,
+ /* [1] */
+ .reg_sspm_infra_req_0_mask_b = 1,
+ /* [2] */
+ .reg_sspm_apsrc_req_0_mask_b = 0,
+ /* [3] */
+ .reg_sspm_vrf18_req_0_mask_b = 0,
+ /* [4] */
+ .reg_sspm_ddr_en_0_mask_b = 0,
+ /* [5] */
+ .reg_scp_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_scp_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_scp_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_scp_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_scp_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_apu_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_apu_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_apu_apsrc_req_mask_b = 0,
+ /* [18] */
+ .reg_apu_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_apu_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_cpueb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_cpueb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_cpueb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_cpueb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_cpueb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ /* [26] */
+ .reg_bak_psri_infra_req_mask_b = 0,
+ /* [27] */
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ /* [28] */
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ /* [29] */
+ .reg_bak_psri_ddr_en_mask_b = 0,
+ /* [30] */
+ .reg_cam_ddren_req_mask_b = 0,
+ /* [31] */
+ .reg_img_ddren_req_mask_b = 0,
+
+ /* SPM_SRC2_MASK */
+ /* [0] */
+ .reg_msdc0_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_msdc0_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_msdc0_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_msdc1_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_msdc1_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_msdc1_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_msdc2_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_msdc2_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_msdc2_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_ufs_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_ufs_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_ufs_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_ufs_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_ufs_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_usb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_usb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_usb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_usb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_usb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_pextp_p0_srcclkena_mask_b = 1,
+ /* [26] */
+ .reg_pextp_p0_infra_req_mask_b = 1,
+ /* [27] */
+ .reg_pextp_p0_apsrc_req_mask_b = 1,
+ /* [28] */
+ .reg_pextp_p0_vrf18_req_mask_b = 1,
+ /* [29] */
+ .reg_pextp_p0_ddr_en_mask_b = 1,
+
+ /* SPM_SRC3_MASK */
+ /* [0] */
+ .reg_pextp_p1_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_pextp_p1_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_pextp_p1_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_pextp_p1_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_pextp_p1_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_gce0_infra_req_mask_b = 1,
+ /* [6] */
+ .reg_gce0_apsrc_req_mask_b = 1,
+ /* [7] */
+ .reg_gce0_vrf18_req_mask_b = 1,
+ /* [8] */
+ .reg_gce0_ddr_en_mask_b = 1,
+ /* [9] */
+ .reg_gce1_infra_req_mask_b = 1,
+ /* [10] */
+ .reg_gce1_apsrc_req_mask_b = 1,
+ /* [11] */
+ .reg_gce1_vrf18_req_mask_b = 1,
+ /* [12] */
+ .reg_gce1_ddr_en_mask_b = 1,
+ /* [13] */
+ .reg_spm_srcclkena_reserved_mask_b = 1,
+ /* [14] */
+ .reg_spm_infra_req_reserved_mask_b = 1,
+ /* [15] */
+ .reg_spm_apsrc_req_reserved_mask_b = 1,
+ /* [16] */
+ .reg_spm_vrf18_req_reserved_mask_b = 1,
+ /* [17] */
+ .reg_spm_ddr_en_reserved_mask_b = 1,
+ /* [18] */
+ .reg_disp0_apsrc_req_mask_b = 1,
+ /* [19] */
+ .reg_disp0_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_disp1_apsrc_req_mask_b = 1,
+ /* [21] */
+ .reg_disp1_ddr_en_mask_b = 1,
+ /* [22] */
+ .reg_disp2_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_disp2_ddr_en_mask_b = 1,
+ /* [24] */
+ .reg_disp3_apsrc_req_mask_b = 1,
+ /* [25] */
+ .reg_disp3_ddr_en_mask_b = 1,
+ /* [26] */
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ /* [27] */
+ .reg_infrasys_ddr_en_mask_b = 1,
+
+ /* [28] */
+ .reg_cg_check_srcclkena_mask_b = 1,
+ /* [29] */
+ .reg_cg_check_apsrc_req_mask_b = 1,
+ /* [30] */
+ .reg_cg_check_vrf18_req_mask_b = 1,
+ /* [31] */
+ .reg_cg_check_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ /* [8:0] */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0,
+ /* [17:9] */
+ .reg_mcusys_merge_ddr_en_mask_b = 0,
+ /* [19:18] */
+ .reg_dramc_md32_infra_req_mask_b = 3,
+ /* [21:20] */
+ .reg_dramc_md32_vrf18_req_mask_b = 3,
+ /* [23:22] */
+ .reg_dramc_md32_ddr_en_mask_b = 0,
+ /* [24] */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ /* [3:0] */
+ .reg_sc_sw2spm_wakeup_mask_b = 0,
+ /* [4] */
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ /* [8:5] */
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ /* [9] */
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ /* [10] */
+ .reg_csyspwrup_ack_mask = 0,
+ /* [11] */
+ .reg_csyspwrup_req_mask = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ /* [31:0] */
+ .reg_wakeup_event_mask = 0xC1382213,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ /* [31:0] */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+ /*sw flag setting */
+ .pcm_flags = SPM_SUSPEND_PCM_FLAG,
+ .pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
+};
+
+struct spm_lp_scen __spm_suspend = {
+ .pwrctrl = &suspend_ctrl,
+};
+
+int mt_spm_suspend_mode_set(int mode, void *prv)
+{
+ if (mode == MT_SPM_SUSPEND_SLEEP) {
+ suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
+ suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
+ } else {
+ suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
+ suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
+ }
+ return 0;
+}
+
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, unsigned int reosuce_req)
+{
+ int ret = 0;
+
+ /* if FMAudio, ADSP is active, change to sleep suspend mode */
+ if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+ mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP, NULL);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_PERI_ON) != 0U) {
+ suspend_ctrl.pcm_flags |= SPM_FLAG_PERI_ON_IN_SUSPEND;
+ } else {
+ suspend_ctrl.pcm_flags &= ~SPM_FLAG_PERI_ON_IN_SUSPEND;
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_INFRA_ON) != 0U) {
+ suspend_ctrl.pcm_flags |= SPM_FLAG_DISABLE_INFRA_PDN;
+ } else {
+ suspend_ctrl.pcm_flags &= ~SPM_FLAG_DISABLE_INFRA_PDN;
+ }
+
+#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
+ /* Notify UART to sleep */
+ mtk_uart_save();
+#endif
+
+ ret = spm_conservation(state_id, ext_opand, &__spm_suspend, reosuce_req);
+ if (ret == 0) {
+ struct mt_lp_publish_event event = {
+ .id = MT_LPM_PUBEVENTS_SYS_POWER_OFF,
+ .val.u32 = 0U,
+ };
+
+ MT_LP_SUSPEND_PUBLISH_EVENT(&event);
+ }
+ return ret;
+}
+
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, struct wake_status **status)
+{
+ struct mt_lp_publish_event event = {
+ .id = MT_LPM_PUBEVENTS_SYS_POWER_ON,
+ .val.u32 = 0U,
+ };
+
+ struct wake_status *st = NULL;
+
+ spm_conservation_finish(state_id, ext_opand, &__spm_suspend, &st);
+
+#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
+ /* Notify UART to wakeup */
+ mtk_uart_restore();
+#endif
+
+ /* If FMAudio, ADSP is active, change back to suspend mode and counting in resume */
+ if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+ mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN, NULL);
+ }
+
+ if (status != NULL) {
+ *status = st;
+ }
+ MT_LP_SUSPEND_PUBLISH_EVENT(&event);
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.h
new file mode 100644
index 0000000..37f621d
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SUSPEND_H
+#define MT_SPM_SUSPEND_H
+
+#include <mt_spm_internal.h>
+
+struct suspend_dbg_ctrl {
+ uint32_t sleep_suspend_cnt;
+};
+
+enum mt_spm_suspend_mode {
+ MT_SPM_SUSPEND_SYSTEM_PDN = 0,
+ MT_SPM_SUSPEND_SLEEP,
+};
+
+int mt_spm_suspend_mode_set(int mode, void *prv);
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, unsigned int reosuce_req);
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, struct wake_status **status);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/pcm_def.h b/plat/mediatek/drivers/spm/mt8188/pcm_def.h
new file mode 100644
index 0000000..976c167
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/pcm_def.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCM_DEF_H
+#define PCM_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN (1U << 1)
+#define R0_SC_MEM_CK_OFF (1U << 2)
+#define R0_SC_AXI_CK_OFF (1U << 3)
+#define R0_SC_DR_SRAM_LOAD (1U << 4)
+#define R0_SC_MD26M_CK_OFF (1U << 5)
+#define R0_SC_DPY_MODE_SW (1U << 6)
+#define R0_SC_DMSUS_OFF (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE (1U << 9)
+#define R0_SC_MPLLOUT_OFF (1U << 10)
+#define R0_SC_TX_TRACKING_DIS (1U << 11)
+#define R0_SC_DPY_DLL_EN (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN (1U << 13)
+#define R0_SC_DPY_VREF_EN (1U << 14)
+#define R0_SC_PHYPLL_EN (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
+#define R0_SC_MPLL_OFF (1U << 18)
+#define R0_SC_SHU_RESTORE (1U << 19)
+#define R0_SC_CKSQ0_OFF (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21)
+#define R0_SC_DR_SHU_EN (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP (1U << 23)
+#define R0_SC_MPLL_S_OFF (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0 (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1 (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ (1U << 0)
+#define R7_EMI_CLK_OFF_REQ (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ (1U << 2)
+#define R7_SPM_CK_UPDATE (1U << 3)
+#define R7_SPM_CK_SEL0 (1U << 4)
+#define R7_SPM_CK_SEL1 (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL (1U << 7)
+#define R7_SC_26M_CK_SEL (1U << 8)
+#define R7_PCM_TIMER_SET (1U << 9)
+#define R7_PCM_TIMER_CLR (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11)
+#define R7_CSYSPWRUPACK (1U << 12)
+#define R7_PCM_IM_SLP_EN (1U << 13)
+#define R7_SRCCLKENO0 (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
+#define R7_SC_AXI_DCM_DIS (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN (1U << 20)
+#define R7_SRCCLKENO1 (1U << 21)
+#define R7_PCM_WDT_KICK_P (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN (1U << 26)
+#define R7_FORCE_F26M_WAKE (1U << 27)
+#define R7_FORCE_APSRC_WAKE (1U << 28)
+#define R7_FORCE_INFRA_WAKE (1U << 29)
+#define R7_FORCE_VRF18_WAKE (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER (1U << 0)
+#define R12_TWAM_IRQ_B (1U << 1)
+#define R12_KP_IRQ_B (1U << 2)
+#define R12_APWDT_EVENT_B (1U << 3)
+#define R12_APXGPT1_EVENT_B (1U << 4)
+#define R12_MSDC_WAKEUP_B (1U << 5)
+#define R12_EINT_EVENT_B (1U << 6)
+#define R12_NOT_USED_7 (1U << 7)
+#define R12_SBD_INTR_WAKEUP_B (1U << 8)
+#define R12_LOWBATTERY_IRQ_B (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B (1U << 13)
+#define R12_USBX_CDSC_B (1U << 14)
+#define R12_USBX_POWERDWN_B (1U << 15)
+#define R12_SYS_TIMER_EVENT_B (1U << 16)
+#define R12_EINT_EVENT_SECURE_B (1U << 17)
+#define R12_ECE_INT_HDMI_B (1U << 18)
+#define R12_I2C_IRQ_B (1U << 19)
+#define R12_AFE_IRQ_MCU_B (1U << 20)
+#define R12_THERM_CTRL_EVENT_B (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B (1U << 22)
+#define R12_NOT_USED_23 (1U << 23)
+#define R12_CSYSPWREQ_B (1U << 24)
+#define R12_NOT_USED_25 (1U << 25)
+#define R12_PCIE_WAKEUPEVENT_B (1U << 26)
+#define R12_SEJ_EVENT_B (1U << 27)
+#define R12_SPM_CPU_WAKEUPEVENT_B (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B (1U << 29)
+#define R12_NOT_USED_30 (1U << 30)
+#define R12_NOT_USED_31 (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE (1U << 0)
+#define R12EXT_26M_SLEEP (1U << 1)
+#define R12EXT_INFRA_WAKE (1U << 2)
+#define R12EXT_INFRA_SLEEP (1U << 3)
+#define R12EXT_APSRC_WAKE (1U << 4)
+#define R12EXT_APSRC_SLEEP (1U << 5)
+#define R12EXT_VRF18_WAKE (1U << 6)
+#define R12EXT_VRF18_SLEEP (1U << 7)
+#define R12EXT_DVFS_WAKE (1U << 8)
+#define R12EXT_DDREN_WAKE (1U << 9)
+#define R12EXT_DDREN_SLEEP (1U << 10)
+#define R12EXT_MCU_PM_WFI (1U << 11)
+#define R12EXT_SSPM_IDLE (1U << 12)
+#define R12EXT_CONN_SRCCLKENB (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20)
+#define R12EXT_VS1_TRIGGER (1U << 21)
+#define R12EXT_VS2_TRIGGER (1U << 22)
+#define R12EXT_COROSS_REQ_APU (1U << 23)
+#define R12EXT_CROSS_REQ_L3 (1U << 24)
+#define R12EXT_DDR_PST_ACK (1U << 25)
+#define R12EXT_BIT26 (1U << 26)
+#define R12EXT_BIT27 (1U << 27)
+#define R12EXT_BIT28 (1U << 28)
+#define R12EXT_BIT29 (1U << 29)
+#define R12EXT_BIT30 (1U << 30)
+#define R12EXT_BIT31 (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0 (1U << 0)
+#define R13_SRCCLKENI1 (1U << 1)
+#define R13_MD_SRCCLKENA_0 (1U << 2)
+#define R13_MD_APSRC_REQ_0 (1U << 3)
+#define R13_CONN_DDR_EN (1U << 4)
+#define R13_MD_SRCCLKENA_1 (1U << 5)
+#define R13_SSPM_SRCCLKENA (1U << 6)
+#define R13_SSPM_APSRC_REQ (1U << 7)
+#define R13_MD1_STATE (1U << 8)
+#define R13_BIT9 (1U << 9)
+#define R13_MM_STATE (1U << 10)
+#define R13_SSPM_STATE (1U << 11)
+#define R13_MD_DDR_EN_0 (1U << 12)
+#define R13_CONN_STATE (1U << 13)
+#define R13_CONN_SRCCLKENA (1U << 14)
+#define R13_CONN_APSRC_REQ (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17)
+#define R13_SCP_STATE (1U << 18)
+#define R13_CSYSPWRUPREQ (1U << 19)
+#define R13_PWRAP_SLEEP_ACK (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21)
+#define R13_AUDIO_DSP_STATE (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23)
+#define R13_CONN_SRCCLKENB (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26)
+#define R13_DVFS_STATE (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29)
+#define R13_MD_VRF18_REQ_0 (1U << 30)
+#define R13_DDR_EN_STATE (1U << 31)
+
+#endif /* PCM_DEF_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/rules.mk b/plat/mediatek/drivers/spm/mt8188/rules.mk
new file mode 100644
index 0000000..a04e91f
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/rules.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+MODULE := spm_${MTK_SOC}
+
+define GET_UPPER_DIR
+$(shell dirname ${LOCAL_DIR})
+endef
+UPPER_DIR := $(call GET_UPPER_DIR)
+
+MT_SPM_FEATURE_SUPPORT := y
+MT_SPM_CIRQ_FEATURE_SUPPORT := n
+MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT := n
+MT_SPM_SSPM_NOTIFIER_SUPPORT := y
+MT_SPM_UART_SUSPEND_SUPPORT := n
+MT_SPM_RGU_SUPPORT := n
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/mt_spm.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mt_spm_conservation.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mt_spm_internal.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mt_spm_pmic_wrap.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/mt_spm_cond.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/mt_spm_idle.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/mt_spm_suspend.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_api.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_bus26m.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_cpu_buck_ldo.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_dram.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_syspll.c
+LOCAL_SRCS-${MT_SPM_SSPM_NOTIFIER_SUPPORT} += ${UPPER_DIR}/version/notifier/v1/mt_spm_sspm_notifier.c
+
+ifeq (${MT_SPM_FEATURE_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_UNSUPPORT))
+endif
+
+ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_CIRQ_UNSUPPORT))
+endif
+
+ifeq (${MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT))
+endif
+
+ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT))
+endif
+
+ifeq (${MT_SPM_UART_SUSPEND_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_UART_UNSUPPORT))
+endif
+
+ifeq ($(MTK_VOLTAGE_BIN_VCORE),y)
+$(eval $(call add_define,MTK_VOLTAGE_BIN_VCORE_SUPPORT))
+endif
+
+ifeq ($(MT_SPM_RGU_SUPPORT),n)
+$(eval $(call add_define,MTK_PLAT_SPM_RGU_UNSUPPORT))
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/spm/mt8188/sleep_def.h b/plat/mediatek/drivers/spm/mt8188/sleep_def.h
new file mode 100644
index 0000000..09a575b
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/sleep_def.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SLEEP_DEF_H
+#define SLEEP_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN (1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
+#define SPM_FLAG_PERI_ON_IN_SUSPEND (1U << 11)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12)
+#define SPM_FLAG_USE_SRCCLKENO2 (1U << 13)
+#define SPM_FLAG_ENABLE_6315_CTRL (1U << 14)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18)
+#define SPM_FLAG_DISABLE_DRAMC_ISSUE_CMD (1U << 19)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20)
+#define SPM_FLAG_RESERVED_BIT21 (1U << 21)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
+#define SPM_FLAG_DISABLE_DRAMC_MD32_BACKUP (1U << 23)
+#define SPM_FLAG_RESERVED_BIT24 (1U << 24)
+#define SPM_FLAG_RESERVED_BIT25 (1U << 25)
+#define SPM_FLAG_RESERVED_BIT26 (1U << 26)
+#define SPM_FLAG_VTCXO_STATE (1U << 27)
+#define SPM_FLAG_INFRA_STATE (1U << 28)
+#define SPM_FLAG_APSRC_STATE (1U << 29)
+#define SPM_FLAG_VRF18_STATE (1U << 30)
+#define SPM_FLAG_DDREN_STATE (1U << 31)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5 (1U << 5)
+#define SPM_FLAG1_ENABLE_REKICK (1U << 6)
+#define SPM_FLAG1_RESERVED_BIT7 (1U << 7)
+#define SPM_FLAG1_RESERVED_BIT8 (1U << 8)
+#define SPM_FLAG1_RESERVED_BIT9 (1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12 (1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13 (1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14 (1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15 (1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16 (1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17 (1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18 (1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19 (1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20)
+#define SPM_FLAG1_RESERVED_BIT21 (1U << 21)
+#define SPM_FLAG1_ENABLE_VS1_VOTER (1U << 22)
+#define SPM_FLAG1_ENABLE_VS2_VOTER (1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24)
+#define SPM_FLAG1_RESERVED_BIT25 (1U << 25)
+#define SPM_FLAG1_RESERVED_BIT26 (1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27 (1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28 (1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29 (1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30 (1U << 30)
+#define SPM_FLAG1_RESERVED_BIT31 (1U << 31)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V (1U << 23)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V (1U << 24)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V (1U << 25)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V (1U << 26)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29)
+#define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7)
+#define SPM_DBG1_RESERVED_BIT8 (1U << 8)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF (1U << 9)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON (1U << 10)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18)
+#define SPM_DBG1_RESERVED_BIT19 (1U << 19)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW (1U << 21)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH (1U << 22)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28)
+#define SPM_DBG1_RESERVED_BIT29 (1U << 29)
+#define SPM_DBG1_RESERVED_BIT30 (1U << 30)
+#define SPM_DBG1_RESERVED_BIT31 (1U << 31)
+
+/*
+ * Macro and Inline
+ */
+#define is_cpu_pdn(flags) ((flags) & SPM_FLAG_DIS_CPU_PDN == 0)
+#define is_infra_pdn(flags) ((flags) & SPM_FLAG_DIS_INFRA_PDN == 0)
+#define is_ddrphy_pdn(flags) ((flags) & SPM_FLAG_DIS_DDRPHY_PDN == 0)
+
+#endif /* SLEEP_DEF_H */
diff --git a/plat/mediatek/drivers/spm/rules.mk b/plat/mediatek/drivers/spm/rules.mk
new file mode 100644
index 0000000..b7128db
--- /dev/null
+++ b/plat/mediatek/drivers/spm/rules.mk
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+MODULE := spm
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
+
+ifneq ($(CONFIG_MTK_SPM_VERSION),)
+PLAT_INCLUDES += -I${LOCAL_DIR}/$(MTK_SOC)
+PLAT_INCLUDES += -I${LOCAL_DIR}/version/notifier/inc
+
+SUB_RULES-y += ${LOCAL_DIR}/$(CONFIG_MTK_SPM_VERSION)
+$(eval $(call add_define,SPM_PLAT_IMPL))
+endif
+
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))
diff --git a/plat/mediatek/drivers/spm/version/notifier/inc/mt_spm_notifier.h b/plat/mediatek/drivers/spm/version/notifier/inc/mt_spm_notifier.h
new file mode 100644
index 0000000..4d12624
--- /dev/null
+++ b/plat/mediatek/drivers/spm/version/notifier/inc/mt_spm_notifier.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_NOTIFIER_H
+#define MT_SPM_NOTIFIER_H
+
+enum mt_spm_sspm_notify_id {
+ MT_SPM_NOTIFY_LP_ENTER = 0,
+ MT_SPM_NOTIFY_LP_LEAVE,
+ MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE,
+};
+
+#ifdef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+static inline int mt_spm_sspm_notify_u32(int type, unsigned int val)
+{
+ (void)type;
+ (void)val;
+ return 0;
+}
+#else
+int mt_spm_sspm_notify_u32(int type, unsigned int val);
+#endif
+
+#endif /* MT_SPM_NOTIFIER_H */
diff --git a/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_intc.h b/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_intc.h
new file mode 100644
index 0000000..e57a966
--- /dev/null
+++ b/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_intc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_INTC_H
+#define MT_SPM_SSPM_INTC_H
+
+#include <mt_spm_reg.h>
+
+#define MT_SPM_SSPM_INTC_SEL_0 (0x10)
+#define MT_SPM_SSPM_INTC_SEL_1 (0x20)
+#define MT_SPM_SSPM_INTC_SEL_2 (0x40)
+#define MT_SPM_SSPM_INTC_SEL_3 (0x80)
+
+#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) (((0x10 << (id)) | (sg << (id))) & 0xFF)
+
+#define MT_SPM_SSPM_INTC0_HIGH MT_SPM_SSPM_INTC_TRIGGER(0, 1)
+#define MT_SPM_SSPM_INTC0_LOW MT_SPM_SSPM_INTC_TRIGGER(0, 0)
+
+#define MT_SPM_SSPM_INTC1_HIGH MT_SPM_SSPM_INTC_TRIGGER(1, 1)
+#define MT_SPM_SSPM_INTC1_LOW MT_SPM_SSPM_INTC_TRIGGER(1, 0)
+
+#define MT_SPM_SSPM_INTC2_HIGH MT_SPM_SSPM_INTC_TRIGGER(2, 1)
+#define MT_SPM_SSPM_INTC2_LOW MT_SPM_SSPM_INTC_TRIGGER(2, 0)
+
+#define MT_SPM_SSPM_INTC3_HIGH MT_SPM_SSPM_INTC_TRIGGER(3, 1)
+#define MT_SPM_SSPM_INTC3_LOW MT_SPM_SSPM_INTC_TRIGGER(3, 0)
+
+#define DO_SPM_SSPM_LP_SUSPEND() mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
+
+#define DO_SPM_SSPM_LP_RESUME() mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
+
+#endif /* MT_SPM_SSPM_INTC_H */
diff --git a/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_notifier.c b/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_notifier.c
new file mode 100644
index 0000000..081988f
--- /dev/null
+++ b/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_notifier.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include "mt_spm_notifier.h"
+#include "mt_spm_sspm_intc.h"
+#include <platform_def.h>
+
+#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_3_BASE + x)
+#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
+
+/* LOOKUP SSPM_MBOX_SPM_LP1 */
+#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)
+/* LOOKUP SSPM_MBOX_SPM_LP2 */
+#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1)
+
+#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2)
+#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3)
+
+int mt_spm_sspm_notify_u32(int type, unsigned int val)
+{
+ switch (type) {
+ case MT_SPM_NOTIFY_LP_ENTER:
+ mmio_write_32(SSPM_MBOX_SPM_LP1, val);
+ DO_SPM_SSPM_LP_SUSPEND();
+ break;
+ case MT_SPM_NOTIFY_LP_LEAVE:
+ mmio_write_32(SSPM_MBOX_SPM_LP1, val);
+ DO_SPM_SSPM_LP_RESUME();
+ break;
+ default:
+ panic();
+ break;
+ }
+ return 0;
+}
diff --git a/plat/mediatek/drivers/usb/mt8188/mt_usb.c b/plat/mediatek/drivers/usb/mt8188/mt_usb.c
new file mode 100644
index 0000000..c9e7a56
--- /dev/null
+++ b/plat/mediatek/drivers/usb/mt8188/mt_usb.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <lpm/mt_lp_api.h>
+#include <platform_def.h>
+
+int mt_usb_init(void)
+{
+ INFO("[%s] mt_usb initialization\n", __func__);
+
+ /* Keep infra and peri on to support wake-up from USB */
+ mtk_usb_update(LPM_USB_ENTER);
+
+ return 0;
+}
+MTK_PLAT_SETUP_0_INIT(mt_usb_init);
diff --git a/plat/mediatek/drivers/usb/rules.mk b/plat/mediatek/drivers/usb/rules.mk
new file mode 100644
index 0000000..f8c43f1
--- /dev/null
+++ b/plat/mediatek/drivers/usb/rules.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := usb
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/$(MTK_SOC)/mt_usb.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/include/drivers/spm/mt_spm_resource_req.h b/plat/mediatek/include/drivers/spm/mt_spm_resource_req.h
new file mode 100644
index 0000000..890bacc
--- /dev/null
+++ b/plat/mediatek/include/drivers/spm/mt_spm_resource_req.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM (0U)
+#define MT_SPM_BIT_26M (1U)
+#define MT_SPM_BIT_INFRA (2U)
+#define MT_SPM_BIT_SYSPLL (3U)
+#define MT_SPM_BIT_DRAM_S0 (4U)
+#define MT_SPM_BIT_DRAM_S1 (5U)
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1)
+
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/include/lpm/mt_lp_api.h b/plat/mediatek/include/lpm/mt_lp_api.h
new file mode 100644
index 0000000..00a2802
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lp_api.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_API_H
+#define MT_LP_API_H
+
+#include <lpm/mt_lp_rm.h>
+
+#if MTK_PUBEVENT_ENABLE
+#include <vendor_pubsub_events.h>
+#endif
+
+/* Ufs clk enum for PLAT_RC_CLKBUF_STATUS */
+enum rc_update_ex_ufs_ref_clk {
+ UFS_REF_CLK_OFF = 0,
+ UFS_REF_CLK_ON,
+};
+
+/* Enum for flight mode */
+enum rc_update_ex_flight_mode {
+ FLIGHT_MODE_OFF = 0,
+ FLIGHT_MODE_ON,
+};
+
+struct mt_lpm_pubevent_data {
+ unsigned int u32;
+};
+
+enum mt_lpm_pubevents_id {
+ MT_LPM_PUBEVENTS_BBLPM_ENTER,
+ MT_LPM_PUBEVENTS_BBLPM_LEAVE,
+ MT_LPM_PUBEVENTS_TARGET_CORE,
+ MT_LPM_PUBEVENTS_SYS_POWER_OFF,
+ MT_LPM_PUBEVENTS_SYS_POWER_ON,
+};
+
+struct mt_lp_publish_event {
+ unsigned int id;
+ struct mt_lpm_pubevent_data val;
+};
+
+#if MTK_PUBEVENT_ENABLE
+#define MT_LP_PUBLISH_EVENT(x) ({\
+ PUBLISH_EVENT_ARG(lpm_publish_event, (const void *)(x)); })
+#define MT_LP_SUSPEND_PUBLISH_EVENT(x) ({\
+ PUBLISH_EVENT_ARG(suspend_publish_event, (const void *)(x)); })
+
+#define MT_LP_SUBSCRIBE_SUSPEND(func) SUBSCRIBE_TO_EVENT(suspend_publish_event, func)
+#define MT_LP_SUBSCRIBE_LPM(func) SUBSCRIBE_TO_EVENT(lpm_publish_event, func)
+#else
+#define MT_LP_PUBLISH_EVENT(x) ({ (void)x; })
+#define MT_LP_SUSPEND_PUBLISH_EVENT(x) ({ (void)x; })
+#define MT_LP_SUBSCRIBE_SUSPEND(func)
+#define MT_LP_SUBSCRIBE_LPM(func)
+#endif
+
+/* MTK low power API types for audio */
+enum mt_lp_api_audio_type {
+ AUDIO_AFE_ENTER,
+ AUDIO_AFE_LEAVE,
+ AUDIO_DSP_ENTER,
+ AUDIO_DSP_LEAVE,
+};
+
+/* MTK low power API types for usb */
+enum mt_lp_api_usb_type {
+ LPM_USB_ENTER,
+ LPM_USB_LEAVE,
+};
+
+int mt_audio_update(int type);
+int mtk_usb_update(int type);
+
+#endif /* MT_LP_API_H */
diff --git a/plat/mediatek/include/lpm/mt_lp_rm.h b/plat/mediatek/include/lpm/mt_lp_rm.h
new file mode 100644
index 0000000..bf99489
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lp_rm.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RM_H
+#define MT_LP_RM_H
+
+#include <stdbool.h>
+
+#define MT_RM_STATUS_OK (0)
+#define MT_RM_STATUS_BAD (-1)
+#define MT_RM_STATUS_STOP (-2)
+
+enum PLAT_MT_LPM_RC_TYPE {
+ PLAT_RC_UPDATE_CONDITION,
+ PLAT_RC_STATUS,
+ PLAT_RC_UPDATE_REMAIN_IRQS,
+ PLAT_RC_IS_FMAUDIO,
+ PLAT_RC_IS_ADSP,
+ PLAT_RC_ENTER_CNT,
+ PLAT_RC_CLKBUF_STATUS,
+ PLAT_RC_UFS_STATUS,
+ PLAT_RC_IS_USB_PERI,
+ PLAT_RC_IS_USB_INFRA,
+ PLAT_RC_MAX,
+};
+
+enum plat_mt_lpm_hw_ctrl_type {
+ PLAT_AP_MDSRC_REQ,
+ PLAT_AP_MDSRC_ACK,
+ PLAT_AP_IS_MD_SLEEP,
+ PLAT_AP_MDSRC_SETTLE,
+ PLAT_AP_GPUEB_PLL_CONTROL,
+ PLAT_AP_GPUEB_GET_PWR_STATUS,
+ PLAT_AP_HW_CTRL_MAX,
+};
+
+struct mt_resource_constraint {
+ int level;
+ int (*init)(void);
+ bool (*is_valid)(unsigned int cpu, int stateid);
+ int (*update)(int stateid, int type, const void *p);
+ int (*run)(unsigned int cpu, int stateid);
+ int (*reset)(unsigned int cpu, int stateid);
+ int (*get_status)(unsigned int type, void *priv);
+ unsigned int (*allow)(int stateid);
+};
+
+struct mt_resource_manager {
+ int (*update)(struct mt_resource_constraint **con, unsigned int num,
+ int stateid, void *priv);
+ struct mt_resource_constraint **consts;
+};
+
+extern int mt_lp_rm_register(struct mt_resource_manager *rm);
+extern int mt_lp_rm_do_constraint(unsigned int constraint_id, unsigned int cpuid, int stateid);
+extern int mt_lp_rm_find_constraint(unsigned int idx, unsigned int cpuid,
+ int stateid, void *priv);
+extern int mt_lp_rm_find_and_run_constraint(unsigned int idx, unsigned int cpuid,
+ int stateid, void *priv);
+extern int mt_lp_rm_reset_constraint(unsigned int idx, unsigned int cpuid, int stateid);
+extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
+extern int mt_lp_rm_get_status(unsigned int type, void *priv);
+
+#endif /* MT_LP_RM_H */
diff --git a/plat/mediatek/include/lpm/mt_lp_rq.h b/plat/mediatek/include/lpm/mt_lp_rq.h
new file mode 100644
index 0000000..2c4908c
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lp_rq.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RQ_H
+#define MT_LP_RQ_H
+
+/* Determine the generic resource request public type */
+#define MT_LP_RQ_XO_FPM BIT(0)
+#define MT_LP_RQ_26M BIT(1)
+#define MT_LP_RQ_INFRA BIT(2)
+#define MT_LP_RQ_SYSPLL BIT(3)
+#define MT_LP_RQ_DRAM BIT(4)
+#define MT_LP_RQ_ALL (0xFFFFFFFF)
+
+struct mt_lp_resource_user {
+ /* Determine the resource user mask */
+ unsigned int umask;
+ /* Determine the resource request user identify */
+ unsigned int uid;
+ /* Request the resource */
+ int (*request)(struct mt_lp_resource_user *this, unsigned int resource);
+ /* Release the resource */
+ int (*release)(struct mt_lp_resource_user *this);
+};
+
+int mt_lp_resource_user_register(char *uname, struct mt_lp_resource_user *ru);
+
+#endif /* MT_LP_RQ_H */
diff --git a/plat/mediatek/include/lpm/mt_lp_rqm.h b/plat/mediatek/include/lpm/mt_lp_rqm.h
new file mode 100644
index 0000000..c30f762
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lp_rqm.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RQM_H
+#define MT_LP_RQM_H
+
+#include "mt_lp_rq.h"
+
+enum plat_mt_lpm_rq_update_type {
+ PLAT_RQ_USER_NUM,
+ PLAT_RQ_USER_VALID,
+ PLAT_RQ_USER_REQ,
+ PLAT_RQ_USER_REL,
+ PLAT_RQ_PER_USER_NAME,
+ PLAT_RQ_REQ_NUM,
+ PLAT_RQ_REQ_USAGE,
+};
+
+/* Determine the request valid */
+#define MT_LP_RQ_VALID (0x1)
+#define MT_LP_RQ_INVALID (0x0)
+
+/* Determine the request user opertions */
+#define MT_LP_RQ_USER_INVALID (-1)
+#define MT_LP_RQ_USER_MAX (32)
+#define MT_LP_RQ_USER_NAME_LEN (4)
+#define MT_LP_RQ_USER_CHAR_U (8)
+
+/* Determine the request update flag */
+#define MT_LP_RQ_FLAG_DONE (0)
+#define MT_LP_RQ_FLAG_NEED_UPDATE BIT(6)
+
+/* Determine the resource update id */
+#define MT_LP_RQ_ID_ALL_USAGE (-1)
+
+/* Determine the return status */
+#define MT_LP_RQ_STA_OK (0)
+#define MT_LP_RQ_STA_BAD (-1)
+
+struct mt_lp_res_req {
+ /* Determine the resource req public identify */
+ const unsigned int res_id;
+ /* Determine the resource bitwise internal control */
+ const unsigned int res_rq;
+ /* Determine the users per bit for current resource usage */
+ unsigned int res_usage;
+};
+
+struct mt_resource_req_manager {
+ /* Determine the set of resources */
+ struct mt_lp_res_req **res;
+};
+
+struct resource_req_status {
+ /* Determine the status id */
+ unsigned int id;
+ /* Determine the status value */
+ unsigned int val;
+};
+
+int mt_lp_resource_request_manager_register(struct mt_resource_req_manager *rqm);
+int mt_lp_rq_update_status(int type, void *p);
+int mt_lp_rq_get_status(int type, void *p);
+
+#endif /* MT_LP_RQM_H */
diff --git a/plat/mediatek/include/lpm/mt_lpm_smc.h b/plat/mediatek/include/lpm/mt_lpm_smc.h
new file mode 100644
index 0000000..0117ca9
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lpm_smc.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LPM_SMC_H
+#define MT_LPM_SMC_H
+
+/*
+ * MTK LPM smc user format:
+ * bit[31:24]: magic number
+ * bit[23:16]: user number
+ * bit[15:00]: user id
+ */
+
+#define MT_LPM_SMC_MAGIC (0xDA000000)
+#define MT_LPM_SMC_MAGIC_MASK (0xFF000000)
+#define MT_LPM_SMC_USER_MASK (0xFF)
+#define MT_LPM_SMC_USER_SHIFT (16)
+
+#define MT_LPM_SMC_USER_ID_MASK (0x0000FFFF)
+
+/*
+ * cpu_pm is used for MCDI to read/write CPC information
+ * spm_dbg is used for spm related debug information
+ * spm is used for spm related settings
+ * cpu_pm_lp is used for MCDI setting irq_remain
+ */
+enum mt_lpm_smc_user_id {
+ MT_LPM_SMC_USER_CPU_PM = 0,
+ MT_LPM_SMC_USER_SPM_DBG,
+ MT_LPM_SMC_USER_SPM,
+ MT_LPM_SMC_USER_CPU_PM_LP,
+ MT_LPM_SMC_USER_SECURE_CPU_PM,
+ MT_LPM_SMC_USER_SECURE_SPM_DBG,
+ MT_LPM_SMC_USER_SECURE_SPM,
+ MT_LPM_SMC_USER_MAX,
+};
+
+#define IS_MT_LPM_SMC(smcid) ((smcid & MT_LPM_SMC_MAGIC_MASK) == MT_LPM_SMC_MAGIC)
+
+/* get real user id */
+#define MT_LPM_SMC_USER(id) ((id >> MT_LPM_SMC_USER_SHIFT) & MT_LPM_SMC_USER_MASK)
+#define MT_LPM_SMC_USER_ID(uid) (uid & MT_LPM_SMC_USER_ID_MASK)
+
+/* sink user id to smc's user id */
+#define MT_LPM_SMC_USER_SINK(user, uid) (((uid & MT_LPM_SMC_USER_ID_MASK) |\
+ ((user & MT_LPM_SMC_USER_MASK) << MT_LPM_SMC_USER_SHIFT)) |\
+ MT_LPM_SMC_MAGIC)
+
+/* sink cpu pm's smc id */
+#define MT_LPM_SMC_USER_ID_CPU_PM(uid) MT_LPM_SMC_USER_SINK(MT_LPM_SMC_USER_CPU_PM, uid)
+/* sink spm's smc id */
+#define MT_LPM_SMC_USER_ID_SPM(uid) MT_LPM_SMC_USER_SINK(MT_LPM_SMC_USER_SPM, uid)
+
+/* sink cpu pm's user id */
+#define MT_LPM_SMC_USER_CPU_PM(uid) MT_LPM_SMC_USER_ID_CPU_PM(uid)
+
+/* sink spm's user id */
+#define MT_LPM_SMC_USER_SPM(uid) MT_LPM_SMC_USER_ID_SPM(uid)
+
+/* behavior */
+#define MT_LPM_SMC_ACT_SET BIT(0)
+#define MT_LPM_SMC_ACT_CLR BIT(1)
+#define MT_LPM_SMC_ACT_GET BIT(2)
+#define MT_LPM_SMC_ACT_PUSH BIT(3)
+#define MT_LPM_SMC_ACT_POP BIT(4)
+#define MT_LPM_SMC_ACT_SUBMIT BIT(5)
+
+/* compatible action for legacy smc from lk */
+#define MT_LPM_SMC_ACT_COMPAT BIT(31)
+
+enum mt_lpm_spmc_compat_id {
+ MT_LPM_SPMC_COMPAT_LK_FW_INIT,
+ MT_LPM_SPMC_COMPAT_LK_MCDI_WDT_DUMP,
+};
+
+#endif /* MT_LPM_SMC_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
index a420e16..14a84b2 100644
--- a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -148,7 +148,8 @@
(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
-int mt_spm_cond_update(struct mt_resource_constraint **con, int stateid, void *priv)
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
+ int stateid, void *priv)
{
int res;
uint32_t i;
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
index 24c39ba..28a3020 100644
--- a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,7 +54,7 @@
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
-extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv);
#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8186/platform.mk b/plat/mediatek/mt8186/platform.mk
index 68f4a1f..2bd2fb4 100644
--- a/plat/mediatek/mt8186/platform.mk
+++ b/plat/mediatek/mt8186/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,7 +8,6 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
- -I${MTK_PLAT}/common/lpm \
-I${MTK_PLAT}/drivers/cirq/ \
-I${MTK_PLAT}/drivers/gic600/ \
-I${MTK_PLAT}/drivers/gpio/ \
@@ -18,6 +17,7 @@
-I${MTK_PLAT}/drivers/timer/ \
-I${MTK_PLAT}/drivers/uart/ \
-I${MTK_PLAT}/include/ \
+ -I${MTK_PLAT}/include/lpm \
-I${MTK_PLAT_SOC}/drivers/spm/ \
-I${MTK_PLAT_SOC}/drivers/dcm/ \
-I${MTK_PLAT_SOC}/drivers/dfd/ \
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 156a7e2..34d4637 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,8 @@
#define MTK_DEV_RNG1_BASE (IO_PHYS)
#define MTK_DEV_RNG1_SIZE (0x10000000)
+#define TOPCKGEN_BASE (IO_PHYS)
+
/*******************************************************************************
* AUDIO related constants
******************************************************************************/
@@ -57,6 +59,8 @@
/*******************************************************************************
* Infra IOMMU related constants
******************************************************************************/
+#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
+#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00002000)
#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
#define PERICFG_AO_REG_SIZE (0x1000)
@@ -108,6 +112,33 @@
#define SMI_LARB_REG_RNG_SIZE (0x1000)
/*******************************************************************************
+ * SPM related constants
+ ******************************************************************************/
+#define SPM_BASE (IO_PHYS + 0x00006000)
+
+/*******************************************************************************
+ * APMIXEDSYS related constants
+ ******************************************************************************/
+#define APMIXEDSYS (IO_PHYS + 0x0000C000)
+
+/*******************************************************************************
+ * VPPSYS related constants
+ ******************************************************************************/
+#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
+#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
+
+/*******************************************************************************
+ * VDOSYS related constants
+ ******************************************************************************/
+#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
+#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
+
+/*******************************************************************************
+ * SSPM_MBOX_3 related constants
+ ******************************************************************************/
+#define SSPM_MBOX_3_BASE (IO_PHYS + 0x00480000)
+
+/*******************************************************************************
* DP related constants
******************************************************************************/
#define EDP_SEC_BASE (IO_PHYS + 0x0C504000)
diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk
index 137318e..2e3392f 100644
--- a/plat/mediatek/mt8188/plat_config.mk
+++ b/plat/mediatek/mt8188/plat_config.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -41,6 +41,8 @@
CONFIG_MTK_CPU_PM_ARCH := 3_2
CONFIG_MTK_SMP_EN := y
CONFIG_MTK_CPU_SUSPEND_EN := y
+CONFIG_MTK_SPM_VERSION := mt8188
+CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND := y
CPU_PM_TINYSYS_SUPPORT := y
MTK_PUBEVENT_ENABLE := y
diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk
index b6a17aa..85ceeb9 100644
--- a/plat/mediatek/mt8188/platform.mk
+++ b/plat/mediatek/mt8188/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -39,7 +39,9 @@
MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
MODULES-y += $(MTK_PLAT)/drivers/ptp3
MODULES-y += $(MTK_PLAT)/drivers/rtc
+MODULES-y += $(MTK_PLAT)/drivers/spm
MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-y += $(MTK_PLAT)/drivers/usb
MODULES-y += $(MTK_PLAT)/helpers
MODULES-y += $(MTK_PLAT)/topology
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
index 2d67fdf..4332b70 100644
--- a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -155,7 +155,7 @@
(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
-int mt_spm_cond_update(struct mt_resource_constraint **con,
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv)
{
int res;
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
index 91ebdd9..ffd5f3f 100644
--- a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -51,6 +51,6 @@
const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
-extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv);
#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index a19fc45..4afd157 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,7 +8,6 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
- -I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT}/drivers/cirq/ \
-I${MTK_PLAT}/drivers/gic600/ \
-I${MTK_PLAT}/drivers/gpio/ \
@@ -18,6 +17,7 @@
-I${MTK_PLAT}/drivers/timer/ \
-I${MTK_PLAT}/drivers/uart/ \
-I${MTK_PLAT}/include/ \
+ -I${MTK_PLAT}/include/lpm/ \
-I${MTK_PLAT_SOC}/include/ \
-I${MTK_PLAT_SOC}/drivers/ \
-I${MTK_PLAT_SOC}/drivers/apusys/ \
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
index c80faf5..0ca0e1d 100644
--- a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -171,7 +171,7 @@
(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
-int mt_spm_cond_update(struct mt_resource_constraint **con,
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv)
{
int res;
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
index e471b55..83007af 100644
--- a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -68,6 +68,6 @@
const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
-extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv);
#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
index 07d39cb..48dafa3 100644
--- a/plat/mediatek/mt8195/platform.mk
+++ b/plat/mediatek/mt8195/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,7 +8,6 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
- -I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT}/drivers/cirq/ \
-I${MTK_PLAT}/drivers/dp/ \
-I${MTK_PLAT}/drivers/gic600/ \
@@ -20,6 +19,7 @@
-I${MTK_PLAT}/drivers/timer/ \
-I${MTK_PLAT}/drivers/uart/ \
-I${MTK_PLAT}/include/ \
+ -I${MTK_PLAT}/include/lpm/ \
-I${MTK_PLAT_SOC}/drivers/apusys/ \
-I${MTK_PLAT_SOC}/drivers/dcm \
-I${MTK_PLAT_SOC}/drivers/dfd \
diff --git a/plat/qti/common/src/qti_pm.c b/plat/qti/common/src/qti_pm.c
index 5f1b7aa..ae361e9 100644
--- a/plat/qti/common/src/qti_pm.c
+++ b/plat/qti/common/src/qti_pm.c
@@ -47,8 +47,7 @@
#define QTI_CORE_PWRDN_EN_MASK 1
/* cpu power control happens to be same across all CPUs */
-_DEFINE_SYSREG_WRITE_FUNC(cpu_pwrctrl_val, S3_0_C15_C2_7)
-_DEFINE_SYSREG_READ_FUNC(cpu_pwrctrl_val, S3_0_C15_C2_7)
+DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7)
const unsigned int qti_pm_idle_states[] = {
qti_make_pwrstate_lvl0(QTI_LOCAL_STATE_OFF,
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 3946e9b..7bdd5bd 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -215,7 +215,7 @@
#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
-#define SILICON_ID_XCK24 0x4714093U
+#define SILICON_ID_XCK24 0x4712093U
#define SILICON_ID_XCK26 0x4724093U
static char *zynqmp_get_silicon_idcode_name(void)
diff --git a/tools/fiptool/fiptool.c b/tools/fiptool/fiptool.c
index 5c240b5..fadf319 100644
--- a/tools/fiptool/fiptool.c
+++ b/tools/fiptool/fiptool.c
@@ -1,9 +1,12 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#ifndef _MSC_VER
+#include <sys/mount.h>
+#endif
#include <sys/types.h>
#include <sys/stat.h>
@@ -298,6 +301,7 @@
fip_toc_header_t *toc_header;
fip_toc_entry_t *toc_entry;
int terminated = 0;
+ size_t st_size;
fp = fopen(filename, "rb");
if (fp == NULL)
@@ -306,13 +310,21 @@
if (fstat(fileno(fp), &st) == -1)
log_err("fstat %s", filename);
+ st_size = st.st_size;
+
- buf = xmalloc(st.st_size, "failed to load file into memory");
- if (fread(buf, 1, st.st_size, fp) != st.st_size)
+#ifdef BLKGETSIZE64
+ if ((st.st_mode & S_IFBLK) != 0)
+ if (ioctl(fileno(fp), BLKGETSIZE64, &st_size) == -1)
+ log_err("ioctl %s", filename);
+#endif
+
+ buf = xmalloc(st_size, "failed to load file into memory");
+ if (fread(buf, 1, st_size, fp) != st_size)
log_errx("Failed to read %s", filename);
- bufend = buf + st.st_size;
+ bufend = buf + st_size;
fclose(fp);
- if (st.st_size < sizeof(fip_toc_header_t))
+ if (st_size < sizeof(fip_toc_header_t))
log_errx("FIP %s is truncated", filename);
toc_header = (fip_toc_header_t *)buf;
@@ -347,9 +359,11 @@
"failed to allocate image buffer, is FIP file corrupted?");
/* Overflow checks before memory copy. */
if (toc_entry->size > (uint64_t)-1 - toc_entry->offset_address)
- log_errx("FIP %s is corrupted", filename);
- if (toc_entry->size + toc_entry->offset_address > st.st_size)
- log_errx("FIP %s is corrupted", filename);
+ log_errx("FIP %s is corrupted: entry size exceeds 64 bit address space",
+ filename);
+ if (toc_entry->size + toc_entry->offset_address > st_size)
+ log_errx("FIP %s is corrupted: entry size exceeds FIP file size",
+ filename);
memcpy(image->buffer, buf + toc_entry->offset_address,
toc_entry->size);