feat(plat/qti): fix to support cpu errata
fix to support ARM CPU errata based on core used.
Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf14164db37e
diff --git a/plat/qti/common/inc/qti_plat.h b/plat/qti/common/inc/qti_plat.h
index 4d9d320..d616efe 100644
--- a/plat/qti/common/inc/qti_plat.h
+++ b/plat/qti/common/inc/qti_plat.h
@@ -25,13 +25,14 @@
/*
* Utility functions common to ARM standard platforms
*/
-void qti_setup_page_tables(uintptr_t total_base,
+void qti_setup_page_tables(
+ uintptr_t total_base,
size_t total_size,
uintptr_t code_start,
uintptr_t code_limit,
uintptr_t rodata_start,
- uintptr_t rodata_limit,
- uintptr_t coh_start, uintptr_t coh_limit);
+ uintptr_t rodata_limit
+ );
/*
* Mandatory functions required in ARM standard platforms
diff --git a/plat/qti/common/src/aarch64/qti_helpers.S b/plat/qti/common/src/aarch64/qti_helpers.S
index c1ea7b3..d34b530 100644
--- a/plat/qti/common/src/aarch64/qti_helpers.S
+++ b/plat/qti/common/src/aarch64/qti_helpers.S
@@ -72,17 +72,10 @@
/* save the lr */
mov x18, x30
- /* Serialize CPUSS boot setup. Multi core enter simultaneously. */
- ldr x0, =g_qti_cpuss_boot_lock
- bl spin_lock
-
/* pass cold boot status. */
ldr w0, g_qti_bl31_cold_booted
/* Execuete CPUSS boot set up on every core. */
bl qtiseclib_cpuss_reset_asm
- ldr x0, =g_qti_cpuss_boot_lock
- bl spin_unlock
-
ret x18
endfunc plat_reset_handler
diff --git a/plat/qti/common/src/aarch64/qti_kryo4_gold.S b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
index a1b40c8..9bcdf54 100644
--- a/plat/qti/common/src/aarch64/qti_kryo4_gold.S
+++ b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
@@ -28,19 +28,11 @@
mov x19, x30
bl qtiseclib_kryo4_gold_reset_asm
-
- ret x19
+ mov x30, x19
+ b cortex_a76_reset_func
endfunc qti_kryo4_gold_reset_func
-/* ----------------------------------------------------
- * The CPU Ops core power down function for Kryo-3 Gold
- * ----------------------------------------------------
- */
-func qti_kryo4_gold_core_pwr_dwn
- ret
-endfunc qti_kryo4_gold_core_pwr_dwn
-
/* -------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Gold
* -------------------------------------------------------
@@ -77,7 +69,9 @@
ret
endfunc qti_kryo4_gold_cpu_reg_dump
-declare_cpu_ops qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
+declare_cpu_ops_wa qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
qti_kryo4_gold_reset_func, \
- qti_kryo4_gold_core_pwr_dwn, \
+ CPU_NO_EXTRA1_FUNC, \
+ cortex_a76_disable_wa_cve_2018_3639, \
+ cortex_a76_core_pwr_dwn, \
qti_kryo4_gold_cluster_pwr_dwn
diff --git a/plat/qti/common/src/aarch64/qti_kryo4_silver.S b/plat/qti/common/src/aarch64/qti_kryo4_silver.S
index 183eeb0..36374b7 100644
--- a/plat/qti/common/src/aarch64/qti_kryo4_silver.S
+++ b/plat/qti/common/src/aarch64/qti_kryo4_silver.S
@@ -22,19 +22,11 @@
mov x19, x30
bl qtiseclib_kryo4_silver_reset_asm
-
- ret x19
+ mov x30, x19
+ b cortex_a55_reset_func
endfunc qti_kryo4_silver_reset_func
-/* ------------------------------------------------------
- * The CPU Ops core power down function for Kryo-3 Silver
- * ------------------------------------------------------
- */
-func qti_kryo4_silver_core_pwr_dwn
- ret
-endfunc qti_kryo4_silver_core_pwr_dwn
-
/* ---------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Silver
* ---------------------------------------------------------
@@ -75,5 +67,5 @@
declare_cpu_ops qti_kryo4_silver, QTI_KRYO4_SILVER_MIDR, \
qti_kryo4_silver_reset_func, \
- qti_kryo4_silver_core_pwr_dwn, \
+ cortex_a55_core_pwr_dwn, \
qti_kryo4_silver_cluster_pwr_dwn
diff --git a/plat/qti/common/src/aarch64/qti_kryo6_gold.S b/plat/qti/common/src/aarch64/qti_kryo6_gold.S
index db1a304..577e7ff 100644
--- a/plat/qti/common/src/aarch64/qti_kryo6_gold.S
+++ b/plat/qti/common/src/aarch64/qti_kryo6_gold.S
@@ -28,19 +28,11 @@
mov x19, x30
bl qtiseclib_kryo6_gold_reset_asm
-
- ret x19
+ mov x30, x19
+ b cortex_a78_reset_func
endfunc qti_kryo6_gold_reset_func
-/* ----------------------------------------------------
- * The CPU Ops core power down function for Kryo-3 Gold
- * ----------------------------------------------------
- */
-func qti_kryo6_gold_core_pwr_dwn
- ret
-endfunc qti_kryo6_gold_core_pwr_dwn
-
/* -------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Gold
* -------------------------------------------------------
@@ -79,5 +71,5 @@
declare_cpu_ops qti_kryo6_gold, QTI_KRYO6_GOLD_MIDR, \
qti_kryo6_gold_reset_func, \
- qti_kryo6_gold_core_pwr_dwn, \
+ cortex_a78_core_pwr_dwn, \
qti_kryo6_gold_cluster_pwr_dwn
diff --git a/plat/qti/common/src/aarch64/qti_kryo6_silver.S b/plat/qti/common/src/aarch64/qti_kryo6_silver.S
index 2d189f2..6ad0bca 100644
--- a/plat/qti/common/src/aarch64/qti_kryo6_silver.S
+++ b/plat/qti/common/src/aarch64/qti_kryo6_silver.S
@@ -22,19 +22,11 @@
mov x19, x30
bl qtiseclib_kryo6_silver_reset_asm
-
- ret x19
+ mov x30, x19
+ b cortex_a55_reset_func
endfunc qti_kryo6_silver_reset_func
-/* ------------------------------------------------------
- * The CPU Ops core power down function for Kryo-3 Silver
- * ------------------------------------------------------
- */
-func qti_kryo6_silver_core_pwr_dwn
- ret
-endfunc qti_kryo6_silver_core_pwr_dwn
-
/* ---------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Silver
* ---------------------------------------------------------
@@ -75,5 +67,5 @@
declare_cpu_ops qti_kryo6_silver, QTI_KRYO6_SILVER_MIDR, \
qti_kryo6_silver_reset_func, \
- qti_kryo6_silver_core_pwr_dwn, \
+ cortex_a55_core_pwr_dwn, \
qti_kryo6_silver_cluster_pwr_dwn
diff --git a/plat/qti/common/src/qti_bl31_setup.c b/plat/qti/common/src/qti_bl31_setup.c
index b2bc543..dac0253 100644
--- a/plat/qti/common/src/qti_bl31_setup.c
+++ b/plat/qti/common/src/qti_bl31_setup.c
@@ -36,16 +36,10 @@
static uint64_t g_qti_cpu_cntfrq;
/*
- * Lock variable to serialize cpuss reset execution.
- */
-spinlock_t g_qti_cpuss_boot_lock __attribute__ ((section("tzfw_coherent_mem"),
- aligned(CACHE_WRITEBACK_GRANULE))) = {0x0};
-
-/*
* Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot.
* Any other value means cold booted.
*/
-uint32_t g_qti_bl31_cold_booted __attribute__ ((section("tzfw_coherent_mem"))) = 0x0;
+uint32_t g_qti_bl31_cold_booted;
/*******************************************************************************
* Perform any BL31 early platform setup common to ARM standard platforms.
@@ -91,13 +85,14 @@
******************************************************************************/
void bl31_plat_arch_setup(void)
{
- qti_setup_page_tables(BL_CODE_BASE,
- BL_COHERENT_RAM_END - BL_CODE_BASE,
+ qti_setup_page_tables(
+ BL31_START,
+ BL31_END-BL31_START,
BL_CODE_BASE,
BL_CODE_END,
BL_RO_DATA_BASE,
- BL_RO_DATA_END,
- BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
+ BL_RO_DATA_END
+ );
enable_mmu_el3(0);
}
diff --git a/plat/qti/common/src/qti_common.c b/plat/qti/common/src/qti_common.c
index da0eaec..8821731 100644
--- a/plat/qti/common/src/qti_common.c
+++ b/plat/qti/common/src/qti_common.c
@@ -77,13 +77,14 @@
* - Read-only data section;
* - Coherent memory region, if applicable.
*/
-void qti_setup_page_tables(uintptr_t total_base,
+void qti_setup_page_tables(
+ uintptr_t total_base,
size_t total_size,
uintptr_t code_start,
uintptr_t code_limit,
uintptr_t rodata_start,
- uintptr_t rodata_limit,
- uintptr_t coh_start, uintptr_t coh_limit)
+ uintptr_t rodata_limit
+ )
{
/*
* Map the Trusted SRAM with appropriate memory attributes.
@@ -106,12 +107,6 @@
mmap_add_region(rodata_start, rodata_start,
rodata_limit - rodata_start, MT_RO_DATA | MT_SECURE);
- /* Re-map the coherent memory region */
- VERBOSE("Coherent region: %p - %p\n",
- (void *)coh_start, (void *)coh_limit);
- mmap_add_region(coh_start, coh_start,
- coh_limit - coh_start, MT_DEVICE | MT_RW | MT_SECURE);
-
/* Now (re-)map the platform-specific memory regions */
mmap_add(plat_qti_mmap);